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Intel Pentium

X86 OPCODES


Intel Pentium Instruction Set Re

Intel Pentium Instruction Set Reference
Produced by mindweaver@technologist.com

This is a complete reference of all Intel Pentium instructions, with the exception of MMX and FPU instructions.

This document has been painstakingly rendered into a nice searchable Windows help file for you to enjoy. Various source documents have been used to produce this. The official Intel Pentium Instruction Set Reference Manual for the mnenonics, opcodes, descriptions and flags; and Quantasm's instruction set reference for the opcode timing, size, and pairing data.

You can also check out the document conventionsJEUQFG and instruction page descriptionJEUQFD.

Not part of the instruction set information, but useful nonetheless is the basic architecture overviewJEUQFC.

Version History
1.0 15-04-99 First Version.

Basic Architecture Overview

The following diagram shows the general purpose registers:

EAX Accumulator for operands and results data.
EBX Pointer to data in the DS segment.
ECX Counter for string and loop operations.
EDX I/O pointer.
EBP Pointer to data on the stack (in the SS segment).
ESI Pointer to data in the segment pointed to by the DS register; source pointer
for string operations.
EDI Pointer to data (or destination) in the segment pointed to by the ES register;
destination pointer for string operations.
ESP Stack pointer (in the SS segment).

The 16-Bit Segment Registers are: -

CS Code Segment
DS Data Segment
SS Stack Segment
ES Data Segment
FS Data Segment
GS Data Segment

The format of the EFLAGS register: -

Mnemonic - Description
Opcodes Official Operands Description

Description
Long description.

Operands Bytes Clocks
Generalised operands Size Clock cycles Pairing info

Flags
Affected Flags
___________________________________________________
Opcodes are in Hex.

Conventions

The following conventions are used throughout this document.

Offical Operands

rel8 A relative address in the range from 128 bytes
before the end of the instruction to 127 bytes after
the end of the instruction.
rel16 and rel32 A relative address within the same code segment
as the instruction assembled. The rel16 symbol
applies to instructions with an operand-size attribute
of 16 bits; the rel32 symbol applies to instructions
with an operand-size attribute of 32 bits.
ptr16:16 and ptr16:32 A far pointer, typically in a code segment different
from that of the instruction. The notation 16:16
indicates that the value of the pointer has two parts.
The value to the left of the colon is a 16-bit selector
or value destined for the code segment register. The
value to the right corresponds to the offset within the
destination segment. The ptr16:16 symbol is used
when the instruction's operand-size attribute is 16
bits; the ptr16:32 symbol is used when the
operand-size attribute is 32 bits.
r8 One of the byte general-purpose registers
AL, CL, DL, BL, AH, CH, DH, or BH.
r16 One of the word general-purpose registers
AX, CX, DX, BX, SP, BP, SI, or DI.
r32 One of the doubleword general-purpose registers
EAX, ECX, EDX, EBX, ESP, EBP, ESI, or EDI.
imm8 An immediate byte value. The imm8 symbol is a
signed number between -128 and +127 inclusive.
For instructions in which imm8 is combined with
a word or doubleword operand, the immediate value
is sign-extended to form a word or doubleword.
The upper byte of the word is filled with the topmost
bit of the immediate value.
imm16 An immediate word value used for instructions whose
operand-size attribute is 16 bits. This is a number
between -32,768 and +32,767 inclusive.
imm32 An immediate doubleword value used for instructions
whose operand-size attribute is 32 bits. It allows the
use of a number between +2,147,483,647 and
-2,147,483,648 inclusive.
r/m8 A byte operand that is either the contents of a byte
general-purpose register (AL, BL, CL, DL, AH, BH, CH,
and DH), or a byte from memory.
r/m16 A word general-purpose register or memory operand
used for instructions whose operand-size attribute is
16 bits. The word general-purpose registers are:
AX, BX, CX, DX, SP, BP, SI, and DI. The contents
of memory are found at the address provided by the
effective address computation.
r/m32 A doubleword general-purpose register or memory
operand used for instructions whose operand-size
attribute is 32 bits. The doubleword general-purpose
registers are: EAX, EBX, ECX, EDX, ESP, EBP,
ESI, and EDI. The contents of memory are found
at the address provided by the effective address
computation.
m A 16- or 32-bit operand in memory.
m8 A byte operand in memory, usually expressed as a
variable or array name, but pointed to by the DS:(E)SI
or ES:(E)DI registers. This nomenclature is used only
with the string instructions and the XLAT instruction.
m16 A word operand in memory, usually expressed as a
variable or array name, but pointed to by the DS:(E)SI
or ES:(E)DI registers. This nomenclature is used only
with the string instructions.
m32 A doubleword operand in memory, usually expressed
as a variable or array name, but pointed to by the
DS:(E)SI or ES:(E)DI registers. This nomenclature is
used only with the string instructions.
m64 A memory quadword operand in memory. This
nomenclature is used only with the CMPXCHG8B
instruction.
m16:16, m16:32 A memory operand containing a far pointer composed
of two numbers. The number to the left of the colon
corresponds to the pointer's segment selector. The
number to the right corresponds to its offset.
m16&32, m16&16, m32&32 A memory operand consisting of data item
pairs whose sizes are indicated on the left and the right
side of the ampersand. All memory addressing modes are
allowed. The m16&16 and m32&32 operands are used by the
BOUND instruction to provide an operand containing
an upper and lower bounds for array indices. The m16&32
operand is used by LIDT and LGDT to provide a word with
which to load the limit field, and a doubleword with which
to load the base field of the corresponding GDTR and
IDTR registers.
moffs8, moffs16, moffs32 A simple memory variable (memory offset)
of type byte, word, or doubleword used by some variants
of the MOV instruction. The actual address is given by
a simple offset relative to the segment base. No
ModR/M byte is used in the instruction. The number
shown with moffs indicates its size, which is determined
by the address-size attribute of the instruction.
Sreg A segment register. The segment register bit assignments
are ES=0, CS=1, SS=2, DS=3, FS=4, and GS=5.
m32real, m64real, m80real A single-, double-, and extended-real
(respectively) floating-point operand in memory.
m16int, m32int, m64int A word-, short-, and long-integer (respectively) floating-point
operand in memory.
ST or ST(0) The top element of the FPU register stack.
ST(i) The i th element from the top of the FPU register
stack. (i = 0 through 7)
mm An MMX™ register. The 64-bit MMX registers are: MM0
through MM7.
mm/m32 The low order 32 bits of an MMX register or a 32-bit
memory operand. The 64-bit MMX registers are: MM0
through MM7. The contents of memory are found at
the address provided by the effective address computation.
mm/m64 An MMX register or a 64-bit memory operand. The 64-bit
MMX registers are: MM0 through MM7. The contents of
memory are found at the address provided by the effective
address computation.

Generalised Operands
acc AL, AX or EAX unless specified otherwise
reg any general register
r8 any 8-bit register
r16 any general purpose 16-bit register
r32 any general purpose 32-bit register
imm immediate data
imm8 8-bit immediate data
imm16 16-bit immediate data
mem memory address
mem8 address of 8-bit data item
mem16 address of 16-bit data item
mem32 address of 32-bit data item
mem48 address of 48-bit data item
dest 16/32-bit destination
short 8-bit destination

Instruction Size
The byte count includes the opcode length and length of any required displacement or immediate data. If the displacement is optional, it is shown as d() with the possible lengths in parentheses. If the immediate data is optional, it is shown as i() with the possible lengths in parentheses.

Pairing Categories
 NP = not pairable
UV = pairable in the U pipe or V pipe
PU = pairable in the U pipe only
PV = pairable in the V pipe only

Pentium Optimisations
By mindweaver@technologist.com

Instruction Timing
To time the number of clock cycles that a block of code takes you can use the rdtscMM84RZ instruction. See it's entry for full information.

The following code ultimately sets eax to the number of clock cycles taken by the usercode: -

rdtsc // get CPU clocks
mov clocks,eax // save clock counter

 [usercode]

rdtsc // get CPU clocks
mov ecx, clocks // get the old clock counter
sub eax, ecx // calc clock cycles taken
sub eax, $0E // subtract clocks wasted on rdtsc's

Where clocks is a 32-Bit variable.

If you are using assembly embedded in a high level language your assembler might not support the rdtsc mnemonic, as Borland Delphi 3 doesn't. In this case you can use the following construct in place of the rdtsc instruction: -

dw $310F // two bytes in hex

Note that if the code being timed is quite long, the time value might not be acurate due to interupts occuring during your code execution.


AAA - Ascii Adjust for Addition
37 AAA ASCII adjust AL after addition

Description
Adjusts the sum of two unpacked BCD values to create an unpacked BCD result. The AL register is the implied source and destination operand for this instruction. The AAA instruction is only useful when it follows an ADD instruction that adds (binary addition) two unpacked BCD values and stores a byte result in the AL register. The AAA instruction then adjusts the contents of the AL register to contain the correct 1-digit unpacked BCD result.

If the addition produces a decimal carry, the AH register is incremented by 1, and the CF and AF flags are set. If there was no decimal carry, the CF and AF flags are cleared and the AH register is unchanged. In either case, bits 4 through 7 of the AL register are cleared to 0.

Operands Bytes Clocks
 1 3 NP

Flags
The AF and CF flags are set to 1 if the adjustment results in a decimal carry; otherwise they are cleared to 0. The OF, SF, ZF, and PF flags are undefined.


AAD - Ascii Adjust AX Before Div

AAD - Ascii Adjust AX Before Division
D5 0A AAD ASCII adjust AX before division
D5 ib (No mnemonic) Adjust AX before division to number base imm8

Description
Adjusts two unpacked BCD digits (the least-significant digit in the AL register and the most-significant digit in the AH register) so that a division operation performed on the result will yield a correct unpacked BCD value. The AAD instruction is only useful when it precedes a DIV instruction that divides (binary division) the adjusted value in the AX register by an unpacked BCD value.

The AAD instruction sets the value in the AL register to (AL + (10 * AH)), and then clears the AH register to 00H. The value in the AX register is then equal to the binary equivalent of the original unpacked two-digit (base 10) number in registers AH and AL.

The generalized version of this instruction allows adjustment of two unpacked digits of any number base (see the "Operation" section below), by setting the imm8 byte to the selected number base (for example, 08H for octal, 0AH for decimal, or 0CH for base 12 numbers). The AAD mnemonic is interpreted by all assemblers to mean adjust ASCII (base 10) values. To adjust values in another number base, the instruction must be hand coded in machine code (D5 imm8).

Operands Bytes Clocks
 2 10 NP

Flags
The SF, ZF, and PF flags are set according to the result; the OF, AF, and CF flags are undefined.


AAM - Ascii Adjust AX After Mult

AAM - Ascii Adjust AX After Multiply
D4 0A AAM ASCII adjust AX after multiply
D4 ib (No mnemonic) Adjust AX after multiply to number base imm8

Description
Adjusts the result of the multiplication of two unpacked BCD values to create a pair of unpacked (base 10) BCD values. The AX register is the implied source and destination operand for this instruction. The AAM instruction is only useful when it follows an MUL instruction that multi-plies (binary multiplication) two unpacked BCD values and stores a word result in the AX register. The AAM instruction then adjusts the contents of the AX register to contain the correct 2-digit unpacked (base 10) BCD result.

The generalized version of this instruction allows adjustment of the contents of the AX to create two unpacked digits of any number base (see the "Operation" section below). Here, the imm8 byte is set to the selected number base (for example, 08H for octal, 0AH for decimal, or 0CH for base 12 numbers). The AAM mnemonic is interpreted by all assemblers to mean adjust to ASCII (base 10) values. To adjust to values in another number base, the instruction must be hand coded in machine code (D4 imm8).

Operands Bytes Clocks
2 18 NP

Flags
The SF, ZF, and PF flags are set according to the result. The OF, AF, and CF flags are undefined.


AAS - ASCII Adjust AL After Subt

AAS - ASCII Adjust AL After Subtraction
3F AAS ASCII adjust AL after subtraction

Description
Adjusts the result of the subtraction of two unpacked BCD values to create a unpacked BCD result. The AL register is the implied source and destination operand for this instruction. The AAS instruction is only useful when it follows a SUB instruction that subtracts (binary subtraction) one unpacked BCD value from another and stores a byte result in the AL register. The AAA instruction then adjusts the contents of the AL register to contain the correct 1-digit unpacked BCD result.

If the subtraction produced a decimal carry, the AH register is decremented by 1, and the CF and AF flags are set. If no decimal carry occurred, the CF and AF flags are cleared, and the AH register is unchanged. In either case, the AL register is left with its top nibble set to 0.

Operands Bytes Clocks
1 3 NP

Flags
The AF and CF flags are set to 1 if there is a decimal borrow; otherwise, they are cleared to 0.
The OF, SF, ZF, and PF flags are undefined.


ADC - Add with Carry 14 ib ADC A

ADC - Add with Carry
14 ib ADC AL, imm8 Add with carry imm8 to AL
15 iw ADC AX, imm16 Add with carry imm16 to AX
15 id ADC EAX, imm32 Add with carry imm32 to EAX
80 /2 ib ADC r/m8, imm8 Add with carry imm8 to r/m8
81 /2 iw ADC r/m16,imm16 Add with carry imm16 to r/m16
81 /2 id ADC r/m32,imm32 Add with CF imm32 to r/m32
83 /2 ib ADC r/m16,imm8 Add with CF sign-extended imm8 to r/m16
83 /2 ib ADC r/m32,imm8 Add with CF sign-extended imm8 into r/m32
10 / r ADC r/m8,r8 Add with carry byte register to r/m8
11 / r ADC r/m16,r16 Add with carry r16 to r/m16
11 / r ADC r/m32,r32 Add with CF r32 to r/m32
12 / r ADC r8,r/m8 Add with carry r/m8 to byte register
13 / r ADC r16,r/m16 Add with carry r/m16 to r16
13 / r ADC r32,r/m32 Add with CF r/m32 to r32

Description
Adds the destination operand (first operand), the source operand (second operand), and the carry (CF) flag and stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) The state of the CF flag represents a carry from a previous addition. When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.

The ADC instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates the result for both data types and sets the OF and CF flags to indicate a carry in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result.

The ADC instruction is usually executed as part of a multibyte or multiword addition in which an ADD instruction is followed by an ADC instruction.

Operands Bytes Clocks
reg, reg 2 1 PU
mem, reg 2+d(0,2) 3 PU
reg, mem 2+d(0,2) 2 PU
reg, imm 2+i(1,2) 1 PU
mem, imm 2+d(0,2)+i(1,2) 3 PU*
acc, imm 1+i(1,2) 1 PU

* = not pairable if there is a displacement and immediate

Flags
The OF, SF, ZF, AF, CF, and PF flags are set according to the result.


ADD - Add 04 ib ADD AL

ADD - Add
04 ib ADD AL, imm8 Add imm8 to AL
05 iw ADD AX, imm16 Add imm16 to AX
05 id ADD EAX, imm32 Add imm32 to EAX
80 /0 ib ADD r/m8,imm8 Add imm8 to r/m8
81 /0 iw ADD r/m16,imm16 Add imm16 to r/m16
81 /0 id ADD r/m32,imm32 Add imm32 to r/m32
83 /0 ib ADD r/m16,imm8 Add sign-extended imm8 to r/m16
83 /0 ib ADD r/m32,imm8 Add sign-extended imm8 to r/m32
00 / r ADD r/m8,r8 Add r8 to r/m8
01 / r ADD r/m16,r16 Add r16 to r/m16
01 / r ADD r/m32,r32 Add r32 to r/m32
02 / r ADD r8,r/m8 Add r/m8 to r8
03 / r ADD r16,r/m16 Add r/m16 to r16
03 / r ADD r32,r/m32 Add r/m32 to r32

Description
Adds the first operand (destination operand) and the second operand (source operand) and stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.

The ADD instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates the result for both data types and sets the OF and CF flags to indicate a carry in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result.

Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2+d(0,2) 3 UV
reg, mem 2+d(0,2) 2 UV
reg, imm 2+i(1,2) 1 UV
mem, imm 2+d(0,2)+i(1,2) 3 UV*
acc, imm 1+i(1,2) 1 UV

* = not pairable if there is a displacement and immediate

Flags
The OF, SF, ZF, AF, CF, and PF flags are set according to the result.


AND - Logical AND 24 ib AND AL

AND - Logical AND
24 ib AND AL, imm8 AL AND imm8
25 iw AND AX, imm16 AX AND i mm16
25 id AND EAX, imm32 EAX AND imm32
80 /4 ib AND r/m8,imm8 r/m8 AND imm8
81 /4 iw AND r/m16,imm16 r/m16 AND imm16
81 /4 id AND r/m32,imm32 r/m32 AND imm32
83 /4 ib AND r/m16,imm8 r/m16 AND imm8 (sign-extended)
83 /4 ib AND r/m32,imm8 r/m32 AND imm8 (sign-extended)
20 /r AND r/m8,r8 r/m8 AND r8
21 / r AND r/m16,r16 r/m16 AND r16
21 / r AND r/m32,r32 r/m32 AND r32
22 / r AND r8,r/m8 r8 AND r/m8
23 / r AND r16,r/m16 r16 AND r/m16
23 / r AND r32,r/m32 r32 AND r/m32

Description
Performs a bitwise AND operation on the destination (first) and source (second) operands and stores the result in the destination operand location. The source operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location. (However, two memory operands cannot be used in one instruction.) Each bit of the result of the AND instruction is a 1 if both corresponding bits of the operands are 1; otherwise, it becomes a 0.

Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2+d(0,2) 3 UV
reg, mem 2+d(0,2) 2 UV
reg, imm 2+i(1,2) 1 UV
mem, imm 2+d(0,2)+i(1,2) 3 UV*
acc, imm 1+i(1,2) 1 UV

* = not pairable if there is a displacement and immediate

Flags
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is undefined.


ARPL - Adjust RPL Field of Segme

ARPL - Adjust RPL Field of Segment Selector
63 / r ARPL r/m16,r16 Adjust RPL of r/m16 to not less than RPL of r16

Description
Compares the RPL fields of two segment selectors. The first operand (the destination operand) contains one segment selector and the second operand (source operand) contains the other. (The RPL field is located in bits 0 and 1 of each operand.) If the RPL field of the destination operand is less than the RPL field of the source operand, the ZF flag is set and the RPL field of the desti-nation operand is increased to match that of the source operand. Otherwise, the ZF flag is cleared and no change is made to the destination operand. (The destination operand can be a word register or a memory location; the source operand must be a word register.)

The ARPL instruction is provided for use by operating-system procedures (however, it can also be used by applications). It is generally used to adjust the RPL of a segment selector that has been passed to the operating system by an application program to match the privilege level of the application program. Here the segment selector passed to the operating system is placed in the destination operand and segment selector for the application program's code segment is placed in the source operand. (The RPL field in the source operand represents the privilege level of the application program.) Execution of the ARPL instruction then insures that the RPL of the segment selector received by the operating system is no lower (does not have a higher privilege) than the privilege level of the application program. (The segment selector for the application program's code segment can be read from the stack following a procedure call.)

Operands Bytes Clocks
reg, reg 2 7 NP
mem, reg 2+d(0-2) 7 NP

Flags
The ZF flag is set to 1 if the RPL field of the destination operand is less than that of the source operand; otherwise, is cleared to 0.


BOUND - Check Array Index Agains

BOUND - Check Array Index Against Bounds
62 / r BOUND r16,m16&16 Check if r16 (array index) is within bounds specified by m16&16
62 / r BOUND r32,m32&32 Check if r32 (array index) is within bounds specified by m16&16

Description
Determines if the first operand (array index) is within the bounds of an array specified the second operand (bounds operand). The array index is a signed integer located in a register. The bounds operand is a memory location that contains a pair of signed doubleword-integers (when the operand-size attribute is 32) or a pair of signed word-integers (when the operand-size attribute is 16). The first doubleword (or word) is the lower bound of the array and the second doubleword (or word) is the upper bound of the array. The array index must be greater than or equal to the lower bound and less than or equal to the upper bound plus the operand size in bytes. If the index is not within bounds, a BOUND range exceeded exception (#BR) is signaled. (When a this exception is generated, the saved return instruction pointer points to the BOUND instruction.)

The bounds limit data structure (two words or doublewords containing the lower and upper limits of the array) is usually placed just before the array itself, making the limits addressable via a constant offset from the beginning of the array. Because the address of the array already will be present in a register, this practice avoids extra bus cycles to obtain the effective address of the array bounds.

Operands Bytes Clocks
reg, mem 4 8 NP

Flags
None.


BSF - Bit Scan Forward 0F BC BSF

BSF - Bit Scan Forward
0F BC BSF r16,r/m16 Bit scan forward on r/m16
0F BC BSF r32,r/m32 Bit scan forward on r/m32

Description
Searches the source operand (second operand) for the least significant set bit (1 bit). If a least significant 1 bit is found, its bit index is stored in the destination operand (first operand). The source operand can be a register or a memory location; the destination operand is a register. The bit index is an unsigned offset from bit 0 of the source operand. If the contents source operand are 0, the contents of the destination operand is undefined.

Operands Bytes Clocks
r16, r16 3 6-34 NP
r32, r32 3 6-42 NP
r16, m16 3+d(0,1,2) 6-35 NP
r32, m32 3+d(0,1,2,4) 6-43 NP

Flags
The ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag is cleared. The CF, OF, SF, AF, and PF, flags are undefined.


BSR - Bit Scan Reverse 0F BD BSR

BSR - Bit Scan Reverse
0F BD BSR r16,r/m16 Bit scan reverse on r/m16
0F BD BSR r32,r/m32 Bit scan reverse on r/m32

Description
Searches the source operand (second operand) for the most significant set bit (1 bit). If a most significant 1 bit is found, its bit index is stored in the destination operand (first operand). The source operand can be a register or a memory location; the destination operand is a register. The bit index is an unsigned offset from bit 0 of the source operand. If the contents source operand are 0, the contents of the destination operand is undefined.

Operands Bytes Clocks
r16, r16 3 7-39 NP
r32, r32 3 7-71 NP
r16, m16 3+d(0,1,2) 7-40 NP
r32, m32 3+d(0,1,2,4) 7-72 NP

Flags
The ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag is cleared. The CF, OF, SF, AF, and PF, flags are undefined.


BSWAP - Byte Swap 0F C8+ rd BSWA

BSWAP - Byte Swap
0F C8+ rd BSWAP r32 Reverses the byte order of a 32-bit register.

Description
Reverses the byte order of a 32-bit (destination) register: bits 0 through 7 are swapped with bits 24 through 31, and bits 8 through 15 are swapped with bits 16 through 23. This instruction is provided for converting little-endian values to big-endian format and vice versa.

To swap bytes in a word value (16-bit register), use the XCHG instruction. When the BSWAP instruction references a 16-bit register, the result is undefined.

Operands Bytes Clocks
r32 2 1 NP

Flags
None.


BT - Bit Test 0F A3 BT r/m16

BT - Bit Test
0F A3 BT r/m16,r16 Store selected bit in CF flag
0F A3 BT r/m32,r32 Store selected bit in CF flag
0F BA /4 ib BT r/m16,imm8 Store selected bit in CF flag
0F BA /4 ib BT r/m32,imm8 Store selected bit in CF flag

Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by the bit offset operand (second operand) and stores the value of the bit in the CF flag. The bit base operand can be a register or a memory location; the bit offset operand can be a register or an immediate value. If the bit base operand specifies a register, the instruction takes the modulo 16 or 32 (depending on the register size) of the bit offset operand, allowing any bit position to be selected in a 16- or 32-bit register, respectively (see Figure 3-1). If the bit base operand specifies a memory location, it represents the address of the byte in memory that
contains the bit base (bit 0 of the specified byte) of the bit string (see Figure 3-2). The offset operand then selects a bit position within the range -2^31 to 2^31 - 1 for a register offset and 0 to 31 for an immediate offset.

Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand. In this case, the low-order 3 or 5 bits (3 for 16-bit operands, 5 for 32-bit operands) of the immediate bit offset are stored in the immediate bit offset field, and the high-order bits are shifted and combined with the byte displacement in the addressing mode by the assembler. The processor will ignore the high order bits if they are not zero.

When accessing a bit in memory, the processor may access 4 bytes starting from the memory address for a 32-bit operand size, using by the following relationship:

Effective Address + (4 * (BitOffset DIV 32))

Or, it may access 2 bytes starting from the memory address for a 16-bit operand, using this relationship:

Effective Address + (2 * (BitOffset DIV 16))

It may do so even when only a single byte needs to be accessed to reach the given bit. When using this bit addressing mechanism, software should avoid referencing areas of memory close to address space holes. In particular, it should avoid references to memory-mapped I/O registers. Instead, software should use the MOV instructions to load from or store to these addresses, and use the register form of these instructions to manipulate the data.

Operands Bytes Clocks
reg, reg 3 4 NP
mem, reg 3+d(0,1,2,4) 9 NP
reg, imm8 3+i(1) 4 NP
mem, imm8 3+d(0,1,2,4)+i(1) 4 NP

Flags
The CF flag contains the value of the selected bit. The OF, SF, ZF, AF, and PF flags are undefined.


BTC - Bit Test and Compliment 0F

BTC - Bit Test and Compliment
0F BB BTC r/m16,r16 Store selected bit in CF flag and complement
0F BB BTC r/m32,r32 Store selected bit in CF flag and complement
0F BA /7 ib BTC r/m16,imm8 Store selected bit in CF flag and complement
0F BA /7 ib BTC r/m32,imm8 Store selected bit in CF flag and complement

Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by the bit offset operand (second operand), stores the value of the bit in the CF flag, and complements the selected bit in the bit string. The bit base operand can be a register or a memory location; the bit offset operand can be a register or an immediate value. If the bit base operand specifies a register, the instruction takes the modulo 16 or 32 (depending on the register size) of the bit offset operand, allowing any bit position to be selected in a 16- or 32-bit register, respectively (see Figure 3-1). If the bit base operand specifies a memory location, it represents the address of the byte in memory that contains the bit base (bit 0 of the specified byte) of the bit string (see Figure 3-2). The offset operand then selects a bit position within the range -2^31 to 2^31 - 1 for a register offset and 0 to 31 for an immediate offset.

Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand. See "BT-Bit TestCVX_O" for more information on this addressing mechanism.

Operands Bytes Clocks
reg, reg 3 7 NP
mem, reg 3+d(0,1,2,4) 13 NP
reg, imm8 3+i(1) 7 NP
mem, imm8 3+d(0,1,2,4)+i(1) 8 NP

Flags
The CF flag contains the value of the selected bit before it is complemented. The OF, SF, ZF, AF, and PF flags are undefined.


BTR - Bit Test and Reset 0F B3 B

BTR - Bit Test and Reset
0F B3 BTR r/m16,r16 Store selected bit in CF flag and clear
0F B3 BTR r/m32,r32 Store selected bit in CF flag and clear
0F BA /6 ib BTR r/m16,imm8 Store selected bit in CF flag and clear
0F BA /6 ib BTR r/m32,imm8 Store selected bit in CF flag and clear

Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by the bit offset operand (second operand), stores the value of the bit in the CF flag, and clears the selected bit in the bit string to 0. The bit base operand can be a register or a memory location; the bit offset operand can be a register or an immediate value. If the bit base operand specifies a register, the instruction takes the modulo 16 or 32 (depending on the register size) of the bit offset operand, allowing any bit position to be selected in a 16- or 32-bit register, respectively (see Figure 3-1). If the bit base operand specifies a memory location, it represents the address of the byte in memory that contains the bit base (bit 0 of the specified byte) of the bit string (see Figure 3-2). The offset operand then selects a bit position within the range -2^31 to 2^31 - 1 for a register offset and 0 to 31 for an immediate offset.

Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand. See "BT-Bit TestCVX_O" in this chapter for more information on this addressing mechanism.

Operands Bytes Clocks
reg, reg 3 7 NP
mem, reg 3+d(0,1,2,4) 13 NP
reg, imm8 3+i(1) 7 NP
mem, imm8 3+d(0,1,2,4)+i(1) 8 NP

Flags
The CF flag contains the value of the selected bit before it is cleared. The OF, SF, ZF, AF, and PF flags are undefined.


BTS - Bit Test and Set 0F AB BTS

BTS - Bit Test and Set
0F AB BTS r/m16,r16 Store selected bit in CF flag and set
0F AB BTS r/m32,r32 Store selected bit in CF flag and set
0F BA /5 ib BTS r/m16,imm8 Store selected bit in CF flag and set
0F BA /5 ib BTS r/m32,imm8 Store selected bit in CF flag and set

Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by the bit offset operand (second operand), stores the value of the bit in theCF flag, and sets the selected bit in the bit string to 1. The bit base operand can be a register or a memory location; the bit offset operand can be a register or an immediate value. If the bit base operand specifies a register, the instruction takes the modulo 16 or 32 (depending on the register size) of the bit offset operand, allowing any bit position to be selected in a 16- or 32-bit register, respectively (see Figure 3-1). If the bit base operand specifies a memory location, it represents the address of the byte in memory that contains the bit base (bit 0 of the specified byte) of the bit string (see Figure 3-2). The offset operand then selects a bit position within the range -2^31 to 2^31 - 1 for a register offset and 0 to 31 for an immediate offset.

Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand. See "BT-Bit TestCVX_O" for more information on this addressing mechanism.

Operands Bytes Clocks
reg, reg 3 7 NP
mem, reg 3+d(0,1,2,4) 13 NP
reg, imm8 3+i(1) 7 NP
mem, imm8 3+d(0,1,2,4)+i(1) 8 NP

Flags
The CF flag contains the value of the selected bit before it is set. The OF, SF, ZF, AF, and PF flags are undefined.


CALL - Call Procedure E8 cw CALL

CALL - Call Procedure
E8 cw CALL rel16 Call near, relative, displacement relative to next instruction
E8 cd CALL rel32 Call near, relative, displacement relative to next instruction
FF /2 CALL r/m16 Call near, absolute indirect, address given in r/m16
FF /2 CALL r/m32 Call near, absolute indirect, address given in r/m32
9A cd CALL ptr16:16 Call far, absolute, address given in operand
9A cp CALL ptr16:32 Call far, absolute, address given in operand
FF /3 CALL m16:16 Call far, absolute indirect, address given in m16:16
FF /3 CALL m16:32 Call far, absolute indirect, address given in m16:32

Description
Saves procedure linking information on the stack and branches to the procedure (called proce-dure) specified with the destination (target) operand. The target operand specifies the address of the first instruction in the called procedure. This operand can be an immediate value, a general-purpose register, or a memory location.

This instruction can be used to execute four different types of calls:

· Near call-A call to a procedure within the current code segment (the segment currently pointed to by the CS register), sometimes referred to as an intrasegment call.
· Far call-A call to a procedure located in a different segment than the current code segment, sometimes referred to as an intersegment call.
· Inter-privilege-level far call-A far call to a procedure in a segment at a different privilege level than that of the currently executing program or procedure.
· Task switch-A call to a procedure located in a different task.

The latter two call types (inter-privilege-level call and task switch) can only be executed in protected mode. See the section titled "Calling Procedures Using Call and RET" in Chapter 4 of the Intel Architecture Software Developer's Manual, Volume 1, for additional information on near, far, and inter-privilege-level calls. See Chapter 6, Task Management, in the Intel Architecture Software Developer's Manual, Volume 3, for information on performing task switches with the CALL instruction.

Near Call. When executing a near call, the processor pushes the value of the EIP register (which contains the offset of the instruction following the CALL instruction) onto the stack (for use later as a return-instruction pointer). The processor then branches to the address in the current code segment specified with the target operand. The target operand specifies either an absolute offset in the code segment (that is an offset from the base of the code segment) or a relative offset (a signed displacement relative to the current value of the instruction pointer in the EIP register, which points to the instruction following the CALL instruction). The CS register is not changed on near calls.

For a near call, an absolute offset is specified indirectly in a general-purpose register or a memory location (r/m16 or r/m32). The operand-size attribute determines the size of the target operand (16 or 32 bits). Absolute offsets are loaded directly into the EIP register. If the operand-size attribute is 16, the upper two bytes of the EIP register are cleared to 0s, resulting in a maximum instruction pointer size of 16 bits. (When accessing an absolute offset indirectly using the stack pointer [ESP] as a base register, the base value used is the value of the ESP before the instruction executes.)

A relative offset (rel16 or rel32) is generally specified as a label in assembly code, but at the machine code level, it is encoded as a signed, 16- or 32-bit immediate value. This value is added to the value in the EIP register. As with absolute offsets, the operand-size attribute determines the size of the target operand (16 or 32 bits).

Far Calls in Real-Address or Virtual-8086 Mode. When executing a far call in real-address or virtual-8086 mode, the processor pushes the current value of both the CS and EIP registers onto the stack for use as a return-instruction pointer. The processor then performs a "far branch" to the code segment and offset specified with the target operand for the called procedure. Here the target operand specifies an absolute far address either directly with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). With the pointer method, the segment and offset of the called procedure is encoded in the instruction, using a 4-byte (16-bit operand size) or 6-byte (32-bit operand size) far address immediate. With the indirect method, the target operand specifies a memory location that contains a 4-byte (16-bit operand size) or 6-byte (32-bit operand size) far address. The operand-size attribute determines the size of the offset (16 or 32 bits) in the far address. The far address is loaded directly into the CS and EIP registers. If the operand-size attribute is 16, the upper two bytes of the EIP register
are cleared to 0s.

Far Calls in Protected Mode. When the processor is operating in protected mode, the CALL instruction can be used to perform the following three types of far calls:

· Far call to the same privilege level.
· Far call to a different privilege level (inter-privilege level call).
· Task switch (far call to another task).

In protected mode, the processor always uses the segment selector part of the far address to access the corresponding descriptor in the GDT or LDT. The descriptor type (code segment, call gate, task gate, or TSS) and access rights determine the type of call operation to be performed.

If the selected descriptor is for a code segment, a far call to a code segment at the same privilege level is performed. (If the selected code segment is at a different privilege level and the code segment is non-conforming, a general-protection exception is generated.) A far call to the same privilege level in protected mode is very similar to one carried out in real-address or virtual-8086 mode. The target operand specifies an absolute far address either directly with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). The operand-size attribute determines the size of the offset (16 or 32 bits) in the far address. The new code segment selector and its descriptor are loaded into CS register, and the offset from the instruction is loaded into the EIP register.

Note that a call gate (described in the next paragraph) can also be used to perform far call to a code segment at the same privilege level. Using this mechanism provides an extra level of indi-rection and is the preferred method of making calls between 16-bit and 32-bit code segments.

When executing an inter-privilege-level far call, the code segment for the procedure being called must be accessed through a call gate. The segment selector specified by the target operand identifies the call gate. Here again, the target operand can specify the call gate segment selector either directly with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). The processor obtains the segment selector for the new code segment and the new instruction pointer (offset) from the call gate descriptor. (The offset from the target operand is ignored when a call gate is used.) On inter-privilege-level calls, the processor switches to the stack for the privilege level of the called procedure. The segment selector for the new stack segment is specified in the TSS for the currently running task. The branch to the new code segment occurs after the stack switch. (Note that when using a call gate to perform a far call to a segment at the same privilege level, no stack switch occurs.) On the new stack, the processor pushes the segment selector and stack pointer for the calling procedure's stack, an (optional) set of parameters from the calling procedures stack, and the segment selector and instruction pointer for the calling procedure's code segment. (A value in the call gate descriptor determines how many parameters to copy to the new stack.) Finally, the processor branches to the address of the procedure being called within the new code segment.

Executing a task switch with the CALL instruction, is somewhat similar to executing a call through a call gate. Here the target operand specifies the segment selector of the task gate for the task being switched to (and the offset in the target operand is ignored.) The task gate in turn points to the TSS for the task, which contains the segment selectors for the task's code and stack segments. The TSS also contains the EIP value for the next instruction that was to be executed before the task was suspended. This instruction pointer value is loaded into EIP register so that the task begins executing again at this next instruction.

The CALL instruction can also specify the segment selector of the TSS directly, which elimi-nates the indirection of the task gate. See Chapter 6, Task Management, in the Intel Architecture Software Developer's Manual, Volume 3, for detailed information on the mechanics of a task switch.

Note that when you execute at task switch with a CALL instruction, the nested task flag (NT) is set in the EFLAGS register and the new TSS's previous task link field is loaded with the old tasks TSS selector. Code is expected to suspend this nested task by executing an IRET instruction, which, because the NT flag is set, will automatically use the previous task link to return to the calling task. (See "Task Linking" in Chapter 6 of the Intel Architecture Software Developer's Manual, Volume 3, for more information on nested tasks.) Switching tasks with the CALL instruction differs in this regard from the JMP instruction which does not set the NT flag and therefore does not expect an IRET instruction to suspend the task.

Mixing 16-Bit and 32-Bit Calls. When making far calls between 16-bit and 32-bit code segments, the calls should be made through a call gate. If the far call is from a 32-bit code segment to a 16-bit code segment, the call should be made from the first 64 KBytes of the 32-bit code segment. This is because the operand-size attribute of the instruction is set to 16, so only a 16-bit return address offset is saved. Also, the call should be made using a 16-bit call gate so that 16-bit values will be pushed on the stack. See Chapter 16, Mixing 16-Bit and 32-Bit Code, in the Intel Architecture Software Developer's Manual, Volume 3, for more information on making calls between 16-bit and 32-bit code segments.

Operands Bytes Clocks
near 3 1 PV
reg 2 2 NP
mem16 2+d(0-2) 2 NP
far 5 4 NP
mem32 2+d(0-2) 4 NP

Protected Mode
far 5 4-13 NP
mem32 2+d(0-2) 5-14 NP

Cycles not shown for calls through call and task gates

Flags
All flags are affected if a task switch occurs; no flags are affected if a task switch does not occur.


CBW - Convert Byte to Word 98 CB

CBW - Convert Byte to Word
98 CBW AX ¬ sign-extend of AL
98 CWDE EAX ¬ sign-extend of AX

Description
Double the size of the source operand by means of sign extension (see Figure 6-5 in the Intel Architecture Software Developer's Manual, Volume 1). The CBW (convert byte to word) instruction copies the sign (bit 7) in the source operand into every bit in the AH register. The CWDE (convert word to doubleword) instruction copies the sign (bit 15) of the word in the AX register into the higher 16 bits of the EAX register.

The CBW and CWDE mnemonics reference the same opcode. The CBW instruction is intended for use when the operand-size attribute is 16 and the CWDE instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when CBW is used and to 32 when CWDE is used. Others may treat these mnemonics as synonyms (CBW/CWDE) and use the current setting of the operand-size attribute to determine the size of values to be converted, regardless of the mnemonic used.

The CWDE instruction is different from the CWD (convert word to double) instruction. The CWD instruction uses the DX:AX register pair as a destination operand; whereas, the CWDE instruction uses the EAX register as a destination.

Operands Bytes Clocks
1 3 NP

Flags
None.


CDQ - Convert Double to Quad 99

CDQ - Convert Double to Quad
99 CWD DX:AX ¬ sign-extend of AX
99 CDQ EDX:EAX ¬ sign-extend of EAX

Description
Doubles the size of the operand in register AX or EAX (depending on the operand size) by means of sign extension and stores the result in registers DX:AX or EDX:EAX, respectively. The CWD instruction copies the sign (bit 15) of the value in the AX register into every bit position in the DX register (see Figure 6-5 in the Intel Architecture Software Developer's Manual, Vo l u me 1 ). The CDQ instruction copies the sign (bit 31) of the value in the EAX register into every bit position in the EDX register.

The CWD instruction can be used to produce a doubleword dividend from a word before a word division, and the CDQ instruction can be used to produce a quadword dividend from a double-word before doubleword division.

The CWD and CDQ mnemonics reference the same opcode. The CWD instruction is intended for use when the operand-size attribute is 16 and the CDQ instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when CWD is used and to 32 when CDQ is used. Others may treat these mnemonics as synonyms (CWD/CDQ) and use the current setting of the operand-size attribute to determine the size of values to be converted, regardless of the mnemonic used.

Operands Bytes Clocks
1 2 NP

Flags
None.


CLC - Clear Carry Flag F8 CLC Cl

CLC - Clear Carry Flag
F8 CLC Clear CF flag

Description
Clears the CF flag in the EFLAGS register.

Operands Bytes Clocks
1 2 NP

Flags
The CF flag is cleared to 0. The OF, ZF, SF, AF, and PF flags are unaffected.


CLD - Clear Direction Flag FC CL

CLD - Clear Direction Flag
FC CLD Clear DF flag

Description
Clears the DF flag in the EFLAGS register. When the DF flag is set to 0, string operations increment the index registers (ESI and/or EDI).

Operands Bytes Clocks
1 2 NP

Flags
The DF flag is cleared to 0. The CF, OF, ZF, SF, AF, and PF flags are unaffected.


CLI - Clear Interrupt Flag FA CL

CLI - Clear Interrupt Flag
FA CLI Clear interrupt flag; interrupts disabled when interrupt flag cleared

Description
Clears the IF flag in the EFLAGS register. No other flags are affected. Clearing the IF flag causes the processor to ignore maskable external interrupts. The IF flag and the CLI and STI instruction have no affect on the generation of exceptions and NMI interrupts.

Operands Bytes Clocks
1 7 NP

Flags
The IF is cleared to 0 if the CPL is equal to or less than the IOPL; otherwise, it is not affected. The other flags in the EFLAGS register are unaffected.


CLTS - Clear Task-Switched Flag

CLTS - Clear Task-Switched Flag in CR0
0F 06 CLTS Clears TS flag in CR0

Description
Clears the task-switched (TS) flag in the CR0 register. This instruction is intended for use in operating-system procedures. It is a privileged instruction that can only be executed at a CPL of 0. It is allowed to be executed in real-address mode to allow initialization for protected mode.

The processor sets the TS flag every time a task switch occurs. The flag is used to synchronize the saving of FPU context in multitasking applications. See the description of the TS flag in the section titled "Control Registers" in Chapter 2 of the Intel Architecture Software Developer's Manual, Volume 3, for more information about this flag.

Operands Bytes Clocks
2 10 NP

Flags
The TS flag in CR0 register is cleared.


CMC - Complement Carry Flag F5 C

CMC - Complement Carry Flag
F5 CMC Complement CF flag

Description
Complements the CF flag in the EFLAGS register.

Operands Bytes Clocks
1 2 NP

Flags
The CF flag contains the complement of its original value. The OF, ZF, SF, AF, and PF flags are unaffected.


CMP - Compare Two Operands 3C i

CMP - Compare Two Operands
3C ib CMP AL, imm8 Compare imm8 with AL
3D iw CMP AX, imm16 Compare imm16 with AX
3D id CMP EAX, imm32 Compare imm32 with EAX
80 /7 ib CMP r/m8, imm8 Compare imm8 with r/m8
81 /7 iw CMP r/m16, imm16 Compare imm16 with r/m16
81 /7 id CMP r/m32,imm32 Compare imm32 with r/m32
83 /7 ib CMP r/m16,imm8 Compare imm8 with r/m16
83 /7 ib CMP r/m32,imm8 Compare imm8 with r/m32
38 / r CMP r/m8,r8 Compare r8 with r/m8
39 / r CMP r/m16,r16 Compare r16 with r/m16
39 / r CMP r/m32,r32 Compare r32 with r/m32
3A / r CMP r8,r/m8 Compare r/m8 with r8
3B / r CMP r16,r/m16 Compare r/m16 with r16
3B / r CMP r32,r/m32 Compare r/m32 with r32

Description
Compares the first source operand with the second source operand and sets the status flags in the EFLAGS register according to the results. The comparison is performed by subtracting the second operand from the first operand and then setting the status flags in the same manner as the SUB instruction. When an immediate value is used as an operand, it is sign-extended to the length of the first operand.

The CMP instruction is typically used in conjunction with a conditional jump (Jcc), condition move (CMOVcc), or SETcc instruction. The condition codes used by the Jcc, CMOVcc, and SETcc instructions are based on the results of a CMP instruction. Appendix B, EFLAGS Condi-tion Codes, in the Intel Architecture Software Developer's Manual, Volume 1, shows the rela-tionship of the status flags and the condition codes.

Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2+d(0,2) 2 UV
reg, mem 2+d(0,2) 2 UV
reg, imm 2+i(1,2) 1 UV
mem, imm 2+d(0,2)+i(1,2) 2 UV*
acc, imm 1+i(1,2) 1 UV

* = not pairable if there is a displacement and immediate

Flags
The CF, OF, SF, ZF, AF, and PF flags are set according to the result.


CMPS/CMPSB/CMPSW/CMPSD - Compare

CMPS/CMPSB/CMPSW/CMPSD - Compare String Operands
A6 CMPS m8, m8 Compares byte at address DS:(E)SI with byte at address
ES:(E)DI and sets the status flags accordingly
A7 CMPS m16, m16 Compares word at address DS:(E)SI with word at address
ES:(E)DI and sets the status flags accordingly
A7 CMPS m32, m32 Compares doubleword at address DS:(E)SI with doubleword
at address ES:(E)DI and sets the status flags accordingly
A6 CMPSB Compares byte at address DS:(E)SI with byte at address
ES:(E)DI and sets the status flags accordingly
A7 CMPSW Compares word at address DS:(E)SI with word at address
ES:(E)DI and sets the status flags accordingly
A7 CMPSD Compares doubleword at address DS:(E)SI with doubleword
at address ES:(E)DI and sets the status flags accordingly

Description
Compares the byte, word, or double word specified with the first source operand with the byte, word, or double word specified with the second source operand and sets the status flags in the EFLAGS register according to the results. Both the source operands are located in memory. The address of the first source operand is read from either the DS:ESI or the DS:SI registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). The address of the second source operand is read from either the ES:EDI or the ES:DI registers (again depending on the address-size attribute of the instruction). The DS segment may be overridden with a segment override prefix, but the ES segment cannot be overridden.

At the assembly-code level, two forms of this instruction are allowed: the "explicit-operands" form and the "no-operands" form. The explicit-operands form (specified with the CMPS mnemonic) allows the two source operands to be specified explicitly. Here, the source operands should be symbols that indicate the size and location of the source values. This explicit-operands form is provided to allow documentation; however, note that the documentation provided by this form can be misleading. That is, the source operand symbols must specify the correct type (size) of the operands (bytes, words, or doublewords), but they do not have to specify the correct location. The locations of the source operands are always specified by the DS:(E)SI and ES:(E)DI registers, which must be loaded correctly before the compare string instruction is executed.

The no-operands form provides "short forms" of the byte, word, and doubleword versions of the CMPS instructions. Here also the DS:(E)SI and ES:(E)DI registers are assumed by the processor to specify the location of the source operands. The size of the source operands is selected with the mnemonic: CMPSB (byte comparison), CMPSW (word comparison), or CMPSD (double-word comparison).

After the comparison, the (E)SI and (E)DI registers are incremented or decremented automati-cally according to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)SI and (E)DI register are incremented; if the DF flag is 1, the (E)SI and (E)DI registers are decremented.) The registers are incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword operations.

The CMPS, CMPSB, CMPSW, and CMPSD instructions can be preceded by the REP prefix for block comparisons of ECX bytes, words, or doublewords. More often, however, these instructions will be used in a LOOP construct that takes some action based on the setting of the status flags before the next comparison is made. See "REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix" in this chapter for a description of the REP prefix.

Variations Bytes Clocks
cmpsb 1 5 NP
cmpsw 1 5 NP
cmpsd 1 5 NP
repX cmpsb 2 9+4n NP
repX cmpsw 2 9+4n NP
repX cmpsd 2 9+4n NP

Flags
The CF, OF, SF, ZF, AF, and PF flags are set according to the temporary result of the comparison.


CMPXCHG - Compare and Exchange 0

CMPXCHG - Compare and Exchange
0F B0/ r CMPXCHG r/m8,r8 Compare AL with r/m8. If equal, ZF is set and r8 is loaded
into r/m8. Else, clear ZF and load r/m8 into AL.
0F B1/ r CMPXCHG r/m16,r16 Compare AX with r/m16. If equal, ZF is set and r16 is
loaded into r/m16. Else, clear ZF and load r/m16 into AL
0F B1/ r CMPXCHG r/m32,r32 Compare EAX with r/m32. If equal, ZF is set and r32 is
loaded into r/m32. Else, clear ZF and load r/m32 into AL

Description
Compares the value in the AL, AX, or EAX register (depending on the size of the operand) with the first operand (destination operand). If the two values are equal, the second operand (source operand) is loaded into the destination operand. Otherwise, the destination operand is loaded into the AL, AX, or EAX register.

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomi-cally. To simplify the interface to the processor's bus, the destination operand receives a write cycle without regard to the result of the comparison. The destination operand is written back if the comparison fails; otherwise, the source operand is written into the destination. (The processor never produces a locked read without also producing a locked write.)

Operands Bytes Clocks
reg, reg 3 5 NP
mem, reg 3+d(0-2) 6 NP

Flags
The ZF flag is set if the values in the destination operand and register AL, AX, or EAX are equal; otherwise it is cleared. The CF, PF, AF, SF, and OF flags are set according to the results of the comparison operation.


CMPXCHG8B - Compare and Exchange

CMPXCHG8B - Compare and Exchange 8 Bytes
0F C7 /1 m64 CMPXCHG8B m64 Compare EDX:EAX with m64. If equal, set ZF and load
ECX:EBX into m64. Else, clear ZF and load m64 into
EDX:EAX.

Description
Compares the 64-bit value in EDX:EAX with the operand (destination operand). If the values are equal, the 64-bit value in ECX:EBX is stored in the destination operand. Otherwise, the value in the destination operand is loaded into EDX:EAX. The destination operand is an 8-byte memory location. For the EDX:EAX and ECX:EBX register pairs, EDX and ECX contain the high-order 32 bits and EAX and EBX contain the low-order 32 bits of a 64-bit value.

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomi-cally. To simplify the interface to the processor's bus, the destination operand receives a write cycle without regard to the result of the comparison. The destination operand is written back if the comparison fails; otherwise, the source operand is written into the destination. (The processor never produces a locked read without also producing a locked write.)

Operands Bytes Clocks
mem, reg 3+d(0-2) 10 NP

Flags
The ZF flag is set if the destination operand and EDX:EAX are equal; otherwise it is cleared. The CF, PF, AF, SF, and OF flags are unaffected.


CPUID - CPU Identification 0F A2

CPUID - CPU Identification
0F A2 CPUID EAX ¬ Processor identification information

Description
Provides processor identification information in registers EAX, EBX, ECX, and EDX. This information identifies Intel as the vendor, gives the family, model, and stepping of processor, feature information, and cache information. An input value loaded into the EAX register determines what information is returned.

Information Returned by CPUID Instruction

Initial EAX Value Information Provided about the Processor
0 EAX Maximum CPUID Input Value (2 for the Pentium ® Pro processor and 1 for
the Pentium processor and the later versions of Intel486™ processor that
support the CPUID instruction).
EBX "Genu"
ECX "ntel"
EDX "ineI"
1 EAX Version Information (Type, Family, Model, and Stepping ID)
EBX Reserved
ECX Reserved
EDX Feature Information
2 EAX Cache and TLB Information
EBX Cache and TLB Information
ECX Cache and TLB Information
EDX Cache and TLB Information

The CPUID instruction can be executed at any privilege level to serialize instruction execution. Serializing instruction execution guarantees that any modifications to flags, registers, and memory for previous instructions are completed before the next instruction is fetched and executed (see "Serializing Instructions" in Chapter 7 of the Intel Architecture Software Developer's Manual, Volume 3).

When the input value in register EAX is 0, the processor returns the highest value the CPUID instruction recognizes in the EAX register (see Table 3-4). A vendor identification string is returned in the EBX, EDX, and ECX registers. For Intel processors, the vendor identification string is "GenuineIntel" as follows:

EBX ¬ 756e6547h (* "Genu", with G in the low nibble of BL *)
EDX ¬ 49656e69h (* "ineI", with i in the low nibble of DL *)
ECX ¬ 6c65746eh (* "ntel", with n in the low nibble of CL *)

When the input value is 1, the processor returns version information in the EAX register and feature information in the EDX register (see Figure 3-3).

{bmc bm2.BMP}

The version information consists of an Intel Architecture family identifier, a model identifier, a stepping ID, and a processor type. The model, family, and processor type for the first processor in the Intel Pentium Pro family is as follows:

· Model-0001B
· Family-0110B
· Processor Type-00B

See AP-485, Intel Processor Identification and the CPUID Instruction (Order Number 241618), the Intel Pentium ® Pro Processor Specification Update (Order Number 242689), and the Intel Pe n t i u m ® Processor Specification Update (Order Number 242480) for more information on identifying earlier Intel Architecture processors.

The available processor types are given in Table 3-5. Intel releases information on stepping IDs as needed.

Type Encoding
Original OEM Processor 00B
Intel OverDrive ® Processor 01B
Dual processor *10B
Intel reserved. 11B

Table 3-6 shows the encoding of the feature flags in the EDX register. A feature flag set to 1 indicates the corresponding feature is supported. Software should identify Intel as the vendor to properly interpret the feature flags.

BiT Feature Description
0 FPU-Floating-Point Unit Processor contains an FPU and executes the Intel 387
on Chip instruction set.
1 VME-Virtual-8086 Processor supports the following virtual-8086 mode
Mode Enhancements enhancements:
• CR4.VME bit enables virtual-8086 mode extensions.
• CR4.PVI bit enables protected-mode virtual interrupts.
• Expansion of the TSS with the software indirection bitmap.
• EFLAGS.VIF bit (virtual interrupt flag).
• EFLAGS.VIP bit (virtual interrupt pending flag).
2 DE-Debugging Processor supports I/O breakpoints, including the CR4.DE bit
Extensions for enabling debug extensions and optional trapping of access
to the DR4 and DR5 registers.
3 PSE-Page Size Processor supports 4-Mbyte pages, including the CR4.PSE bit
Extensions for enabling page size extensions, the modified bit in page
directory entries (PDEs), page directory entries, and page table
entries (PTEs).
4 TSC-Time Stamp Processor supports the RDTSC (read time stamp counter)
Counter instruction, including the CR4.TSD bit that, along with the CPL,
controls whether the time stamp counter can be read.
5 MSR-Model Specific Processor supports the RDMSR (read model-specific register)
Registers and WRMSR (write model-specific register) instructions.
6 PAE-Physical Address Processor supports physical addresses greater than 32 bits, the
Extension extended page-table-entry format, an extra level in the page
translation tables, and 2-MByte pages. The CR4.PAE bit enables
this feature. The number of address bits is implementation specific.
The Pentium ® Pro processor supports 36 bits of addressing when
the PAE bit is set.
7 MCE-Machine Check Processor supports the CR4.MCE bit, enabling machine check
Exception exceptions. However, this feature does not define the model-specific
implementations of machine-check error logging, reporting,
or processor shutdowns. Machine-check exception handlers might
have to check the processor version to do model-specific
processing of the exception or check for the presence of the
standard machine-check feature.
8 CX8-CMPXCHG8B Processor supports the CMPXCHG8B (compare and exchange 8
Instruction bytes) instruction.
9 APIC Processor contains an on-chip Advanced Programmable Interrupt
Controller (APIC) and it has been enabled and is available for use.
10,11 Reserved
12 MTRR-Memory Type Processor supports machine-specific memory-type range registers
Range Registers (MTRRs). The MTRRs contains bit fields that indicate the
processor's MTRR capabilities, including which memory types the
processor supports, the number of variable MTRRs the processor
supports, and whether the processor supports fixed MTRRs.
13 PGE-PTE Global Flag Processor supports the CR4.PGE flag enabling the global bit in
both PTDEs and PTEs. These bits are used to indicate translation
lookaside buffer (TLB) entries that are common to different tasks
and need not be flushed when control register CR3 is written.
14 MCA-Machine Check Processor supports the MCG_CAP (machine check global
Architecture capability) MSR. The MCG_CAP register indicates how many
banks of error reporting MSRs the processor supports.
15 CMOV-Conditional Processor supports the CMOV cc instruction and, if the FPU feature
Move and Compare flag (bit 0) is also set, supports the FCMOV cc and FCOMI
Instructions instructions.
16-22 Reserved
23 MMX™ Technology Processor supports the MMX instruction set. These instructions
operate in parallel on multiple data elements (8 bytes, 4 words, or 2
doublewords) packed into quadword registers or memory locations.
24-31 Reserved

When the input value is 2, the processor returns information about the processor's internal caches and TLBs in the EAX, EBX, ECX, and EDX registers. The encoding of these registers is as follows:

· The least-significant byte in register EAX (register AL) indicates the number of times the CPUID instruction must be executed with an input value of 2 to get a complete description of the processor's caches and TLBs. The Pentium ® Pro family of processors will return a 1.
· The most significant bit (bit 31) of each register indicates whether the register contains valid information (cleared to 0) or is reserved (set to 1).
· If a register contains valid information, the information is contained in 1 byte descriptors. Table 3-7 shows the encoding of these descriptors.

Descriptor Value Cache or TLB Description
00H Null descriptor
01H Instruction TLB: 4K-Byte Pages, 4-way set associative, 32 entries
02H Instruction TLB: 4M-Byte Pages, 4-way set associative, 4 entries
03H Data TLB: 4K-Byte Pages, 4-way set associative, 64 entries
04H Data TLB: 4M-Byte Pages, 4-way set associative, 8 entries
06H Instruction cache: 8K Bytes, 4-way set associative, 32 byte line size
08H Instruction cache: 16K Bytes, 4-way set associative, 32 byte line size
0AH Data cache: 8K Bytes, 2-way set associative, 32 byte line size
0CH Data cache: 16K Bytes, 2-way set associative, 32 byte line size
41H Unified cache: 128K Bytes, 4-way set associative, 32 byte line size
42H Unified cache: 256K Bytes, 4-way set associative, 32 byte line size
43H Unified cache: 512K Bytes, 4-way set associative, 32 byte line size
44H Unified cache: 1M Byte, 4-way set associative, 32 byte line size

The first member of the Pentium Pro processor family will return the following information about caches and TLBs when the CPUID instruction is executed with an input value of 2:

EAX 03 02 01 01H
EBX 0H
ECX 0H
EDX 06 04 0A 42H

These values are interpreted as follows:

· The least-significant byte (byte 0) of register EAX is set to 01H, indicating that the CPUID instruction needs to be executed only once with an input value of 2 to retrieve complete information about the processor's caches and TLBs.
· The most-significant bit of all four registers (EAX, EBX, ECX, and EDX) is set to 0, indicating that each register contains valid 1-byte descriptors.
· Bytes 1, 2, and 3 of register EAX indicate that the processor contains the following:
- 01H-A 32-entry instruction TLB (4-way set associative) for mapping 4-KByte pages.
- 02H-A 4-entry instruction TLB (4-way set associative) for mapping 4-MByte pages.
- 03H-A 64-entry data TLB (4-way set associative) for mapping 4-KByte pages.
· The descriptors in registers EBX and ECX are valid, but contain null descriptors.
· Bytes 0, 1, 2, and 3 of register EDX indicate that the processor contains the following:
- 42H-A 256-KByte unified cache (the L2 cache), 4-way set associative,
with a 32-byte cache line size.
- 0AH-An 8-KByte data cache (the L1 data cache), 2-way set associative, with a
32-byte cache line size.
- 04H-An 8-entry data TLB (4-way set associative) for mapping 4M-byte pages.
- 06H-An 8-KByte instruction cache (the L1 instruction cache), 4-way set associative,
with a 32-byte cache line size.

Operands Bytes Clocks
2 14 NP

Flags
None.


CWD - Convert Word to Doubleword
99 CWD DX:AX ¬ sign-extend of AX
99 CDQ EDX:EAX ¬ sign-extend of EAX

Description
Doubles the size of the operand in register AX or EAX (depending on the operand size) by means of sign extension and stores the result in registers DX:AX or EDX:EAX, respectively. The CWD instruction copies the sign (bit 15) of the value in the AX register into every bit position in the DX register (see Figure 6-5 in the Intel Architecture Software Developer's Manual, Vo l u me 1 ). The CDQ instruction copies the sign (bit 31) of the value in the EAX register into every bit position in the EDX register.

The CWD instruction can be used to produce a doubleword dividend from a word before a word division, and the CDQ instruction can be used to produce a quadword dividend from a double-word before doubleword division.

The CWD and CDQ mnemonics reference the same opcode. The CWD instruction is intended for use when the operand-size attribute is 16 and the CDQ instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when CWD is used and to 32 when CDQ is used. Others may treat these mnemonics as synonyms (CWD/CDQ) and use the current setting of the operand-size attribute to determine the size of values to be converted, regardless of the mnemonic used.

Operands Bytes Clocks
1 2 NP

Flags
None.


CWDE - Convert Word to Doublewor

CWDE - Convert Word to Doubleword
98 CBW AX ¬ sign-extend of AL
98 CWDE EAX ¬ sign-extend of AX

Description
Double the size of the source operand by means of sign extension (see Figure 6-5 in the Intel Architecture Software Developer's Manual, Volume 1). The CBW (convert byte to word) instruction copies the sign (bit 7) in the source operand into every bit in the AH register. The CWDE (convert word to doubleword) instruction copies the sign (bit 15) of the word in the AX register into the higher 16 bits of the EAX register.

The CBW and CWDE mnemonics reference the same opcode. The CBW instruction is intended for use when the operand-size attribute is 16 and the CWDE instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when CBW is used and to 32 when CWDE is used. Others may treat these mnemonics as synonyms (CBW/CWDE) and use the current setting of the operand-size attribute to determine the size of values to be converted, regardless of the mnemonic used.

The CWDE instruction is different from the CWD (convert word to double) instruction. The CWD instruction uses the DX:AX register pair as a destination operand; whereas, the CWDE instruction uses the EAX register as a destination.

Operands Bytes Clocks
1 3 NP

Flags
None.


DAA - Decimal Adjust AL after Ad

DAA - Decimal Adjust AL after Addition
27 DAA Decimal adjust AL after addition

Description
Adjusts the sum of two packed BCD values to create a packed BCD result. The AL register is the implied source and destination operand. The DAA instruction is only useful when it follows an ADD instruction that adds (binary addition) two 2-digit, packed BCD values and stores a byte result in the AL register. The DAA instruction then adjusts the contents of the AL register to contain the correct 2-digit, packed BCD result. If a decimal carry is detected, the CF and AF flags are set accordingly.

Operands Bytes Clocks
1 3 NP

Flags
The CF and AF flags are set if the adjustment of the value results in a decimal carry in either digit of the result (see the "Operation" section above). The SF, ZF, and PF flags are set according to the result. The OF flag is undefined.


DAS - Decimal Adjust AL after Su

DAS - Decimal Adjust AL after Subtraction
2F DAS Decimal adjust AL after subtraction

Description
Adjusts the result of the subtraction of two packed BCD values to create a packed BCD result. The AL register is the implied source and destination operand. The DAS instruction is only useful when it follows a SUB instruction that subtracts (binary subtraction) one 2-digit, packed BCD value from another and stores a byte result in the AL register. The DAS instruction then adjusts the contents of the AL register to contain the correct 2-digit, packed BCD result. If a decimal borrow is detected, the CF and AF flags are set accordingly.

Operands Bytes Clocks
1 3 NP

Flags
The CF and AF flags are set if the adjustment of the value results in a decimal borrow in either digit of the result (see the "Operation" section above). The SF, ZF, and PF flags are set according to the result. The OF flag is undefined.
+$#KDEC - Decrement by 1
FE /1 DEC r/m8 Decrement r/m8 by 1
FF /1 DEC r/m16 Decrement r/m16 by 1
FF /1 DEC r/m32 Decrement r/m32 by 1
48+rw DEC r16 Decrement r16 by 1
48+rd DEC r32 Decrement r32 by 1

Description
Subtracts 1 from the destination operand, while preserving the state of the CF flag. The destination operand can be a register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag. (To perform a decrement operation that updates the CF flag, use a SUB instruction with an immediate operand of 1.)

Operands Bytes Clocks
r8 2 1 UV
r16 1 1 UV
r32 1 1 UV
mem 2+d(0,2) 3 UV

Flags
The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.


DEC - Decrement by 1 FE /1 DEC r

DEC - Decrement by 1
FE /1 DEC r/m8 Decrement r/m8 by 1
FF /1 DEC r/m16 Decrement r/m16 by 1
FF /1 DEC r/m32 Decrement r/m32 by 1
48+rw DEC r16 Decrement r16 by 1
48+rd DEC r32 Decrement r32 by 1

Description
Subtracts 1 from the destination operand, while preserving the state of the CF flag. The destination operand can be a register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag. (To perform a decrement operation that updates the CF flag, use a SUB instruction with an immediate operand of 1.)

Operands Bytes Clocks
r8 2 1 UV
r16 1 1 UV
r32 1 1 UV
mem 2+d(0,2) 3 UV

Flags
The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.


DIV - Unsigned Divide F6 /6 DIV

DIV - Unsigned Divide
F6 /6 DIV r/m8 Unsigned divide AX by r/m8; AL ¬ Quotient,
AH ¬ Remainder
F7 /6 DIV r/m16 Unsigned divide DX:AX by r/m16; AX ¬ Quotient,
DX ¬ Remainder
F7 /6 DIV r/m32 Unsigned divide EDX:EAX by r/m32 doubleword;
EAX ¬ Quotient, EDX ¬ Remainder

Description
Divides (unsigned) the value in the AX register, DX:AX register pair, or EDX:EAX register pair (dividend) by the source operand (divisor) and stores the result in the AX (AH:AL), DX:AX, or EDX:EAX registers. The source operand can be a general-purpose register or a memory loca-tion. The action of this instruction depends on the operand size, as shown in the following table:

Operand Size Dividend Divisor Quotient Remainder Maximum
Quotient
Word/byte AX r/m8 AL AH 255
Doubleword/word DX:AX r/m16 AX DX 65,535
Quadword/
doubleword EDX:EAX r/m32 EAX EDX 2^32 - 1

Non-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magnitude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag.

Operands Bytes Clocks
r8 2 17 NP
r16 2 25 NP
r32 2 41 NP
mem8 2+d(0-2) 17 NP
mem16 2+d(0-2) 25 NP
mem32 2+d(0-2) 41 NP

implied operand quotient remainder
dividend
AX / byte = AL AH
DX:AX / word = AX DX
EDX:EAX / dword = EAX EDX

Flags
The CF, OF, SF, ZF, AF, and PF flags are undefined.


ENTER - Make Stack Frame for Pro

ENTER - Make Stack Frame for Procedure Parameters
C8 iw 00 ENTER imm16,0 Create a stack frame for a procedure
C8 iw 01 ENTER imm16,1 Create a nested stack frame for a procedure
C8 iw ib ENTER imm16,imm8 Create a nested stack frame for a procedure

Description
Creates a stack frame for a procedure. The first operand (size operand) specifies the size of the stack frame (that is, the number of bytes of dynamic storage allocated on the stack for the procedure). The second operand (nesting level operand) gives the lexical nesting level (0 to 31) of the procedure. The nesting level determines the number of stack frame pointers that are copied into the "display area" of the new stack frame from the preceding frame. Both of these operands are immediate values.

The stack-size attribute determines whether the BP (16 bits) or EBP (32 bits) register specifies the current frame pointer and whether SP (16 bits) or ESP (32 bits) specifies the stack pointer.

The ENTER and companion LEAVE instructions are provided to support block structured languages. The ENTER instruction (when used) is typically the first instruction in a procedure and is used to set up a new stack frame for a procedure. The LEAVE instruction is then used at the end of the procedure (just before the RET instruction) to release the stack frame.

If the nesting level is 0, the processor pushes the frame pointer from the EBP register onto the stack, copies the current stack pointer from the ESP register into the EBP register, and loads the ESP register with the current stack-pointer value minus the value in the size operand. For nesting levels of 1 or greater, the processor pushes additional frame pointers on the stack before adjusting the stack pointer. These additional frame pointers provide the called procedure with access points to other nested frames on the stack. See "Procedure Calls for Block-Structured Languages" in Chapter 4 of the Intel Architecture Software Developer's Manual, Volume 1, for more information about the actions of the ENTER instruction.

Operands Bytes Clocks
imm16, 0 3 11 NP
imm16, 1 4 15 NP
imm16, imm8 4 15+2i NP

i = imm8

Flags
None.

HLT - Halt
F4 HLT Halt

Description
Stops instruction execution and places the processor in a HALT state. An enabled interrupt, NMI, or a reset will resume execution. If an interrupt (including NMI) is used to resume execution after a HLT instruction, the saved instruction pointer (CS:EIP) points to the instruction following the HLT instruction.

The HLT instruction is a privileged instruction. When the processor is running in protected or virtual-8086 mode, the privilege level of a program or procedure must be 0 to execute the HLT instruction.

Operands Bytes Clocks
1 4 NP

Flags
None.


IDIV - Signed Divide F6 /7 IDIV

IDIV - Signed Divide
F6 /7 IDIV r/m8 Signed divide AX (where AH must contain sign-extension
of AL) by r/m byte. (Results: AL=Quotient,
AH=Remainder)
F7 /7 IDIV r/m16 Signed divide DX:AX (where DX must contain sign-extension
of AX) by r/m word. (Results: AX=Quotient,
DX=Remainder)
F7 /7 IDIV r/m32 Signed divide EDX:EAX (where EDX must contain
sign-extension of EAX) by r/m doubleword. (Results:
EAX=Quotient, EDX=Remainder)

Description
Divides (signed) the value in the AL, AX, or EAX register by the source operand and stores the result in the AX, DX:AX, or EDX:EAX registers. The source operand can be a general-purpose register or a memory location. The action of this instruction depends on the operand size, as shown in the following table:

Operand Size Dividend Divisor Quotient Remainder Quotient Range
Word/byte AX r/m8 AL AH -128 to +127
Doubleword/word DX:AX r/m16 AX DX -32,768 to +32,767
Quadword/
doubleword EDX:EAX r/m32 EAX EDX -2 31 to 2 32 - 1

Non-integral results are truncated (chopped) towards 0. The sign of the remainder is always the same as the sign of the dividend. The absolute value of the remainder is always less than the absolute value of the divisor. Overflow is indicated with the #DE (divide error) exception rather than with the OF (overflow) flag.

Operands Bytes Clocks
r8 2 22 NP
r16 2 30 NP
r32 2 46 NP
mem8 2+d(0-2) 22 NP
mem16 2+d(0-2) 30 NP
mem32 2+d(0-2) 46 NP

implied operand quotient remainder
dividend
AX / byte = AL AH
DX:AX / word = AX DX
EDX:EAX / dword = EAX EDX

Flags
The CF, OF, SF, ZF, AF, and PF flags are undefined.


IMUL - Signed Multiply F6 /5 IMU

IMUL - Signed Multiply
F6 /5 IMUL r/m8 AX¬ AL * r/m byte
F7 /5 IMUL r/m16 DX:AX ¬ AX * r/m word
F7 /5 IMUL r/m32 EDX:EAX ¬ EAX * r/m doubleword
0F AF / r IMUL r16,r/m16 word register ¬ word register * r/m word
0F AF / r IMUL r32,r/m32 doubleword register ¬ doubleword register * r/m
doubleword
6B / r ib IMUL r16,r/m16,imm8 word register ¬ r/m16 * sign-extended immediate byte
6B / r ib IMUL r32,r/m32,imm8 doubleword register ¬ r/m32 * sign-extended immediate
byte
6B / r ib IMUL r16,imm8 word register ¬ word register * sign-extended immediate
byte
6B / r ib IMUL r32,imm8 doubleword register ¬ doubleword register * sign-extended
immediate byte
69 / r iw IMUL r16,r/m16,imm16 word register ¬ r/m16 * immediate word
69 / r id IMUL r32,r/m32,imm32 doubleword register ¬ r/m32 * immediate doubleword
69 / r iw IMUL r16,imm16 word register ¬ r/m16 * immediate word
69 / r id IMUL r32,imm32 doubleword register ¬ r/m32 * immediate doubleword

Description
Performs a signed multiplication of two operands. This instruction has three forms, depending on the number of operands.

One-operand form. This form is identical to that used by the MUL instruction. Here, the source operand (in a general-purpose register or memory location) is multiplied by the value in the AL, AX, or EAX register (depending on the operand size) and the product is stored in the AX, DX:AX, or EDX:EAX registers, respectively.

Two-operand form. With this form the destination operand (the first operand) is multiplied by the source operand (second operand). The destination operand is a general-purpose register and the source operand is an immediate value, a general-purpose register, or a memory location. The product is then stored in the destination operand location.

Three-operand form. This form requires a destination operand (the first operand) and two source operands (the second and the third operands). Here, the first source operand (which can be a general-purpose register or a memory location) is multiplied by the second source operand (an immediate value). The product is then stored in the destination operand (a general-purpose register).

When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.

The CF and OF flags are set when significant bits are carried into the upper half of the result. The CF and OF flags are cleared when the result fits exactly in the lower half of the result.

The three forms of the IMUL instruction are similar in that the length of the product is calculated to twice the length of the operands. With the one-operand form, the product is stored exactly in the destination. With the two- and three- operand forms, however, result is truncated to the length of the destination before it is stored in the destination register. Because of this truncation, the CF or OF flag should be tested to ensure that no significant bits are lost.

The two- and three-operand forms may also be used with unsigned operands because the lower half of the product is the same regardless if the operands are signed or unsigned. The CF and OF flags, however, cannot be used to determine if the upper half of the result is non-zero.

Accumulator Multiplies
Operands Bytes Clocks
r8 2 11 NP
r16 2 11 NP
r32 2 10 NP
mem8 2+d(0-2) 11 NP
mem16 2+d(0-2) 11 NP
mem32 2+d(0-2) 10 NP

implied operand result
multiplicand (multiplier)
AL * byte = AX
AX * word = DX:AX
EAX * dword = EDX:EAX

2 and 3 operand Multiplies
Operands Bytes Clocks
r16, imm 2+i(1,2) 10 NP
r32, imm 2+i(1,2) 10 NP
r16,r16,imm 2+i(1,2) 10 NP
r32,r32,imm 2+i(1,2) 10 NP
r16,m16,imm 2+d(0-2)+i(1,2) 10 NP
r32,m32,imm 2+d(0-2)+i(1,2) 10 NP
r16, r16 2+i(1,2) 10 NP
r32, r32 2+i(1,2) 10 NP
r16, m16 2+d(0-2)+i(1,2) 10 NP
r32, m32 2+d(0-2)+i(1,2) 10 NP

Flags
For the one operand form of the instruction, the CF and OF flags are set when significant bits are carried into the upper half of the result and cleared when the result fits exactly in the lower half of the result. For the two- and three-operand forms of the instruction, the CF and OF flags are set when the result must be truncated to fit in the destination operand size and cleared when the result fits exactly in the destination operand size. The SF, ZF, AF, and PF flags are undefined.


IN - Input from Port E4 ib IN A

IN - Input from Port
E4 ib IN AL, imm8 Input byte from imm8 I/O port address into AL
E5 ib IN AX, imm8 Input byte from imm8 I/O port address into AX
E5 ib IN EAX, imm8 Input byte from imm8 I/O port address into EAX
EC IN AL,DX Input byte from I/O port in DX into AL
ED IN AX,DX Input word from I/O port in DX into AX
ED IN EAX,DX Input doubleword from I/O port in DX into EAX

Description
Copies the value from the I/O port specified with the second operand (source operand) to the destination operand (first operand). The source operand can be a byte-immediate or the DX register; the destination operand can be register AL, AX, or EAX, depending on the size of the port being accessed (8, 16, or 32 bits, respectively). Using the DX register as a source operand allows I/O port addresses from 0 to 65,535 to be accessed; using a byte immediate allows I/O port addresses 0 to 255 to be accessed.

When accessing an 8-bit I/O port, the opcode determines the port size; when accessing a 16- and 32-bit I/O port, the operand-size attribute determines the port size.

At the machine code level, I/O instructions are shorter when accessing 8-bit I/O ports. Here, the upper eight bits of the port address will be 0.

This instruction is only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 9, Input/Output, in the Intel Architecture Software Developer's Manual, Vo l u me 1 , for more information on accessing I/O ports in the I/O address space.

Operands Bytes Clocks
al, imm8 2 7 NP
ax, imm8 2 7 NP
eax, imm8 2 7 NP
al, dx 1 7 NP
ax, dx 1 7 NP
eax, dx 1 7 NP

Protected mode
acc, imm 2 4/21/19 NP
acc, dx 1 4/21/19 NP

cycles for: CPL <= IOPL / CPL > IOPL / V86

Flags
None.


INS/INSB/INSW/INSD - Input from

INS/INSB/INSW/INSD - Input from Port to String
6C INS m8, DX Input byte from I/O port specified in DX into memory
location specified in ES:(E)DI
6D INS m16, DX Input word from I/O port specified in DX into memory
location specified in ES:(E)DI
6D INS m32, DX Input doubleword from I/O port specified in DX into
memory location specified in ES:(E)DI
6C INSB Input byte from I/O port specified in DX into memory
location specified with ES:(E)DI
6D INSW Input word from I/O port specified in DX into memory
location specified in ES:(E)DI
6D INSD Input doubleword from I/O port specified in DX into
memory location specified in ES:(E)DI

Description
Copies the data from the I/O port specified with the source operand (second operand) to the destination operand (first operand). The source operand is an I/O port address (from 0 to 65,535) that is read from the DX register. The destination operand is a memory location, the address of which is read from either the ES:EDI or the ES:DI registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). (The ES segment cannot be overridden with a segment override prefix.) The size of the I/O port being accessed (that is, the size of the source and destination operands) is determined by the opcode for an 8-bit I/O port or by the operand-size attribute of the instruction for a 16- or 32-bit I/O port.

At the assembly-code level, two forms of this instruction are allowed: the "explicit-operands" form and the "no-operands" form. The explicit-operands form (specified with the INS mnemonic) allows the source and destination operands to be specified explicitly. Here, the source operand must be "DX," and the destination operand should be a symbol that indicates the size of the I/O port and the destination address. This explicit-operands form is provided to allow documentation; however, note that the documentation provided by this form can be misleading. That is, the destination operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does not have to specify the correct location. The location is always specified by the ES:(E)DI registers, which must be loaded correctly before the INS instruction is executed.

The no-operands form provides "short forms" of the byte, word, and doubleword versions of the INS instructions. Here also DX is assumed by the processor to be the source operand and ES:(E)DI is assumed to be the destination operand. The size of the I/O port is specified with the choice of mnemonic: INSB (byte), INSW (word), or INSD (doubleword).

After the byte, word, or doubleword is transfer from the I/O port to the memory location, the (E)DI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)DI register is incremented; if the DF flag is 1, the (E)DI register is decremented.) The (E)DI register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword operations.

The INS, INSB, INSW, and INSD instructions can be preceded by the REP prefix for block input of ECX bytes, words, or doublewords. See "REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix" in this chapter for a description of the REP prefix.

These instructions are only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 9, Input/Output, in the Intel Architecture Software Developer's Manual, Vo l u me 1 , for more information on accessing I/O ports in the I/O address space.

Operands Bytes Clocks
insb 1 9 NP
insw 1 9 NP
insd 1 9 NP

Protected Mode
1 6/24/22 NP

cycles for: CPL <= IOPL / CPL > IOPL / V86

Flags
None.


INT n/INTO/INT 3 - Call to Inter

INT n/INTO/INT 3 - Call to Interrupt Procedure
CC INT 3 Interrupt 3-trap to debugger
CD ib INT imm8 Interrupt vector number specified by immediate byte
CE INTO Interrupt 4-if overflow flag is 1

Description
The INT n instruction generates a call to the interrupt or exception handler specified with the destination operand (see the section titled "Interrupts and Exceptions" in Chapter 4 of the Intel Architecture Software Developer's Manual, Volume 1). The destination operand specifies an interrupt vector number from 0 to 255, encoded as an 8-bit unsigned intermediate value. Each interrupt vector number provides an index to a gate descriptor in the IDT. The first 32 interrupt vector numbers are reserved by Intel for system use. Some of these interrupts are used for inter-nally generated exceptions.

The INT n instruction is the general mnemonic for executing a software-generated call to an interrupt handler. The INTO instruction is a special mnemonic for calling overflow exception (#OF), interrupt vector number 4. The overflow interrupt checks the OF flag in the EFLAGS register and calls the overflow interrupt handler if the OF flag is set to 1.

The INT 3 instruction generates a special one byte opcode (CC) that is intended for calling the debug exception handler. (This one byte form is valuable because it can be used to replace the first byte of any instruction with a breakpoint, including other one byte instructions, without over-writing other code). To further support its function as a debug breakpoint, the interrupt generated with the CC opcode also differs from the regular software interrupts as follows:

· Interrupt redirection does not happen when in VME mode; the interrupt is handled by a protected-mode handler.
· The virtual-8086 mode IOPL checks do not occur. The interrupt is taken without faulting at any IOPL level.

Note that the "normal" 2-byte opcode for INT 3 (CD03) does not have these special features. Intel and Microsoft assemblers will not generate the CD03 opcode from any mnemonic, but this opcode can be created by direct numeric code definition or by self-modifying code.

The action of the INT n instruction (including the INTO and INT 3 instructions) is similar to that of a far call made with the CALL instruction. The primary difference is that with the INT n instruction, the EFLAGS register is pushed onto the stack before the return address. (The return address is a far address consisting of the current values of the CS and EIP registers.) Returns from interrupt procedures are handled with the IRET instruction, which pops the EFLAGS information and return address from the stack.

The interrupt vector number specifies an interrupt descriptor in the interrupt descriptor table (IDT); that is, it provides index into the IDT. The selected interrupt descriptor in turn contains a pointer to an interrupt or exception handler procedure. In protected mode, the IDT contains an array of 8-byte descriptors, each of which is an interrupt gate, trap gate, or task gate. In real-address mode, the IDT is an array of 4-byte far pointers (2-byte code segment selector and a 2-byte instruction pointer), each of which point directly to a procedure in the selected segment. (Note that in real-address mode, the IDT is called the interrupt vector table, and it's pointers are called interrupt vectors.)

When the processor is executing in virtual-8086 mode, the IOPL determines the action of the INT n instruction. If the IOPL is less than 3, the processor generates a general protection exception (#GP); if the IOPL is 3, the processor executes a protected mode interrupt to privilege level 0. The interrupt gate's DPL must be set to three and the target CPL of the interrupt handler procedure must be 0 to execute the protected mode interrupt to privilege level 0.

The interrupt descriptor table register (IDTR) specifies the base linear address and limit of the IDT. The initial base address value of the IDTR after the processor is powered up or reset is 0.

Operands Bytes Clocks
3 (const) 1 13 NP
imm8 2 16 NP

Protected mode
1 27-82 NP

Flags
The EFLAGS register is pushed onto the stack. The IF, TF, NT, AC, RF, and VM flags may be cleared, depending on the mode of operation of the processor when the INT instruction is executed (see the "Operation" section). If the interrupt uses a task gate, any flags may be set or cleared, controlled by the EFLAGS image in the new task's TSS.

INVD - Invalidate Internal Caches
0F 08 INVD Flush internal caches; initiate flushing of external caches.

Description
Invalidates (flushes) the processor's internal caches and issues a special-function bus cycle that directs external caches to also flush themselves. Data held in internal caches is not written back to main memory.

After executing this instruction, the processor does not wait for the external caches to complete their flushing operation before proceeding with instruction execution. It is the responsibility of hardware to respond to the cache flush signal.

The INVD instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a program or procedure must be 0 to execute this instruction.

Use this instruction with care. Data cached internally and not written back to main memory will be lost. Unless there is a specific requirement or benefit to flushing caches without writing back modified cache lines (for example, testing or fault recovery where cache coherency with main memory is not a concern), software should use the WBINVD instruction.

Operands Bytes Clocks
2 15 NP

Flags
None.


INVLPG - Invalidate TLB Entry 0

INVLPG - Invalidate TLB Entry
0F 01/7 INVLPG m Invalidate TLB Entry for page that contains m

Description
Invalidates (flushes) the translation lookaside buffer (TLB) entry specified with the source operand. The source operand is a memory address. The processor determines the page that contains that address and flushes the TLB entry for that page.

The INVLPG instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a program or procedure must be 0 to execute this instruction.

The INVLPG instruction normally flushes the TLB entry only for the specified page; however, in some cases, it flushes the entire TLB. See "MOV-Move to/from Control Registers" in this chapter for further information on operations that flush the TLB.

Operands Bytes Clocks
mem32 5 25 NP

Flags
None.


IRET/IRETD - Interrupt Return CF

IRET/IRETD - Interrupt Return
CF IRET Interrupt return (16-bit operand size)
CF IRETD Interrupt return (32-bit operand size)

Description
Returns program control from an exception or interrupt handler to a program or procedure that was interrupted by an exception, an external interrupt, or a software-generated interrupt. These instructions are also used to perform a return from a nested task. (A nested task is created when a CALL instruction is used to initiate a task switch or when an interrupt or exception causes a task switch to an interrupt or exception handler.) See the section titled "Task Linking" in Chapter 6 of the Intel Architecture Software Developer's Manual, Volume 1.

IRET and IRETD are mnemonics for the same opcode. The IRETD mnemonic (interrupt return double) is intended for use when returning from an interrupt when using the 32-bit operand size; however, most assemblers use the IRET mnemonic interchangeably for both operand sizes.

In Real-Address Mode, the IRET instruction preforms a far return to the interrupted program or procedure. During this operation, the processor pops the return instruction pointer, return code segment selector, and EFLAGS image from the stack to the EIP, CS, and EFLAGS registers, respectively, and then resumes execution of the interrupted program or procedure.

In Protected Mode, the action of the IRET instruction depends on the settings of the NT (nested task) and VM flags in the EFLAGS register and the VM flag in the EFLAGS image stored on the current stack. Depending on the setting of these flags, the processor performs the following types of interrupt returns:

· Return from virtual-8086 mode.
· Return to virtual-8086 mode.
· Intra-privilege level return.
· Inter-privilege level return.
· Return from nested task (task switch).

If the NT flag (EFLAGS register) is cleared, the IRET instruction performs a far return from the interrupt procedure, without a task switch. The code segment being returned to must be equally or less privileged than the interrupt handler routine (as indicated by the RPL field of the code segment selector popped from the stack). As with a real-address mode interrupt return, the IRET instruction pops the return instruction pointer, return code segment selector, and EFLAGS image from the stack to the EIP, CS, and EFLAGS registers, respectively, and then resumes execution of the interrupted program or procedure. If the return is to another privilege level, the IRET instruction also pops the stack pointer and SS from the stack, before resuming program execution. If the return is to virtual-8086 mode, the processor also pops the data segment registers from the stack.

If the NT flag is set, the IRET instruction performs a task switch (return) from a nested task (a task called with a CALL instruction, an interrupt, or an exception) back to the calling or interrupted task. The updated state of the task executing the IRET instruction is saved in its TSS. If the task is reentered later, the code that follows the IRET instruction is executed.

Operands Bytes Clocks
IRET 1 8-27 NP
IRETD 1 10-27 NP

Flags
All the flags and fields in the EFLAGS register are potentially modified, depending on the mode of operation of the processor. If performing a return from a nested task to a previous task, the EFLAGS register will be modified according to the EFLAGS image stored in the previous task's TSS.


Jcc - Jump if Condition Is Met 7

Jcc - Jump if Condition Is Met
77 cb JA rel8 Jump short if above (CF=0 and ZF=0)
73 cb JAE rel8 Jump short if above or equal (CF=0)
72 cb JB rel8 Jump short if below (CF=1)
76 cb JBE rel8 Jump short if below or equal (CF=1 or ZF=1)
72 cb JC rel8 Jump short if carry (CF=1)
E3 cb JCXZ rel8 Jump short if CX register is 0
E3 cb JECXZ rel8 Jump short if ECX register is 0
74 cb JE rel8 Jump short if equal (ZF=1)
7F cb JG rel8 Jump short if greater (ZF=0 and SF=OF)
7D cb JGE rel8 Jump short if greater or equal (SF=OF)
7C cb JL rel8 Jump short if less (SF<>OF)
7E cb JLE rel8 Jump short if less or equal (ZF=1 or SF<>OF)
76 cb JNA rel8 Jump short if not above (CF=1 or ZF=1)
72 cb JNAE rel8 Jump short if not above or equal (CF=1)
73 cb JNB rel8 Jump short if not below (CF=0)
77 cb JNBE rel8 Jump short if not below or equal (CF=0 and ZF=0)
73 cb JNC rel8 Jump short if not carry (CF=0)
75 cb JNE rel8 Jump short if not equal (ZF=0)
7E cb JNG rel8 Jump short if not greater (ZF=1 or SF<>OF)
7C cb JNGE rel8 Jump short if not greater or equal (SF<>OF)
7D cb JNL rel8 Jump short if not less (SF=OF)
7F cb JNLE rel8 Jump short if not less or equal (ZF=0 and SF=OF)
71 cb JNO rel8 Jump short if not overflow (OF=0)
7B cb JNP rel8 Jump short if not parity (PF=0)
79 cb JNS rel8 Jump short if not sign (SF=0)
75 cb JNZ rel8 Jump short if not zero (ZF=0)
70 cb JO rel8 Jump short if overflow (OF=1)
7A cb JP rel8 Jump short if parity (PF=1)
7A cb JPE rel8 Jump short if parity even (PF=1)
7B cb JPO rel8 Jump short if parity odd (PF=0)
78 cb JS rel8 Jump short if sign (SF=1)
74 cb JZ rel8 Jump short if zero (ZF = 1)
0F 87 cw/cd JA rel16/32 Jump near if above (CF=0 and ZF=0)
0F 83 cw/cd JAE rel16/32 Jump near if above or equal (CF=0)
0F 82 cw/cd JB rel16/32 Jump near if below (CF=1)
0F 86 cw/cd JBE rel16/32 Jump near if below or equal (CF=1 or ZF=1)
0F 82 cw/cd JC rel16/32 Jump near if carry (CF=1)
0F 84 cw/cd JE rel16/32 Jump near if equal (ZF=1)
0F 84 cw/cd JZ rel16/32 Jump near if 0 (ZF=1)
0F 8F cw/cd JG rel16/32 Jump near if greater (ZF=0 and SF=OF)
0F 8D cw/cd JGE rel16/32 Jump near if greater or equal (SF=OF)
0F 8C cw/cd JL rel16/32 Jump near if less (SF<>OF)
0F 8E cw/cd JLE rel16/32 Jump near if less or equal (ZF=1 or SF<>OF)
0F 86 cw/cd JNA rel16/32 Jump near if not above (CF=1 or ZF=1)
0F 82 cw/cd JNAE rel16/32 Jump near if not above or equal (CF=1)
0F 83 cw/cd JNB rel16/32 Jump near if not below (CF=0)
0F 87 cw/cd JNBE rel16/32 Jump near if not below or equal (CF=0 and ZF=0)
0F 83 cw/cd JNC rel16/32 Jump near if not carry (CF=0)
0F 85 cw/cd JNE rel16/32 Jump near if not equal (ZF=0)
0F 8E cw/cd JNG rel16/32 Jump near if not greater (ZF=1 or SF<>OF)
0F 8C cw/cd JNGE rel16/32 Jump near if not greater or equal (SF<>OF)
0F 8D cw/cd JNL rel16/32 Jump near if not less (SF=OF)
0F 8F cw/cd JNLE rel16/32 Jump near if not less or equal (ZF=0 and SF=OF)
0F 81 cw/cd JNO rel16/32 Jump near if not overflow (OF=0)
0F 8B cw/cd JNP rel16/32 Jump near if not parity (PF=0)
0F 89 cw/cd JNS rel16/32 Jump near if not sign (SF=0)
0F 85 cw/cd JNZ rel16/32 Jump near if not zero (ZF=0)
0F 80 cw/cd JO rel16/32 Jump near if overflow (OF=1)
0F 8A cw/cd JP rel16/32 Jump near if parity (PF=1)
0F 8A cw/cd JPE rel16/32 Jump near if parity even (PF=1)
0F 8B cw/cd JPO rel16/32 Jump near if parity odd (PF=0)
0F 88 cw/cd JS rel16/32 Jump near if sign (SF=1)
0F 84 cw/cd JZ rel16/32 Jump near if 0 (ZF=1)

Description
Checks the state of one or more of the status flags in the EFLAGS register (CF, OF, PF, SF, and ZF) and, if the flags are in the specified state (condition), performs a jump to the target instruction specified by the destination operand. A condition code (cc) is associated with each instruction to indicate the condition being tested for. If the condition is not satisfied, the jump is not performed and execution continues with the instruction following the Jcc instruction.

The target instruction is specified with a relative offset (a signed offset relative to the current value of the instruction pointer in the EIP register). A relative offset (rel8, rel16, or rel32) is generally specified as a label in assembly code, but at the machine code level, it is encoded as a signed, 8-bit or 32-bit immediate value, which is added to the instruction pointer. Instruction coding is most efficient for offsets of -128 to +127. If the operand-size attribute is 16, the upper two bytes of the EIP register are cleared to 0s, resulting in a maximum instruction pointer size of 16 bits.

The conditions for each Jcc mnemonic are given in the "Description" column of the table on the preceding page. The terms "less" and "greater" are used for comparisons of signed integers and the terms "above" and "below" are used for unsigned integers.

Because a particular state of the status flags can sometimes be interpreted in two ways, two mnemonics are defined for some opcodes. For example, the JA (jump if above) instruction and the JNBE (jump if not below or equal) instruction are alternate mnemonics for the opcode 77H.

The Jcc instruction does not support far jumps (jumps to other code segments). When the target for the conditional jump is in a different segment, use the opposite condition from the condition being tested for the Jcc instruction, and then access the target with an unconditional far jump (JMP instruction) to the other segment. For example, the following conditional far jump is illegal:

JZ FARLABEL;

To accomplish this far jump, use the following two instructions:

JNZ BEYOND;
JMP FARLABEL;
BEYOND:

The JECXZ and JCXZ instructions differs from the other Jcc instructions because they do not check the status flags. Instead they check the contents of the ECX and CX registers, respectively, for 0. Either the CX or ECX register is chosen according to the address-size attribute. These instructions are useful at the beginning of a conditional loop that terminates with a conditional loop instruction (such as LOOPNE). They prevent entering the loop when the ECX or CX register is equal to 0, which would cause the loop to execute 2 32 or 64K times, respectively, instead of zero times.

All conditional jumps are converted to code fetches of one or two cache lines, regardless of jump address or cacheability.

Operands Bytes Clocks
near8 2 1 PV
near16 3 1 PV
cycles apply to jump and no jump

Flags
None.


LAHF - Load Status Flags into AH

LAHF - Load Status Flags into AH Register
9F LAHF Load: AH = EFLAGS(SF:ZF:0:AF:0:PF:1:CF)

Description
Moves the low byte of the EFLAGS register (which includes status flags SF, ZF, AF, PF, and CF) to the AH register. Reserved bits 1, 3, and 5 of the EFLAGS register are set in the AH register as shown in the "Operation" section below.

Operands Bytes Clocks
1 2 NP

Flags
None (that is, the state of the flags in the EFLAGS register are not affected).


LAR - Load Access Rights Byte 0F

LAR - Load Access Rights Byte
0F 02 / r LAR r16,r/m16 r16 ¬ r/m16 masked by FF00H
0F 02 / r LAR r32,r/m32 r32 ¬ r/m32 masked by 00FxFF00H

Description
Loads the access rights from the segment descriptor specified by the second operand (source operand) into the first operand (destination operand) and sets the ZF flag in the EFLAGS register. The source operand (which can be a register or a memory location) contains the segment selector for the segment descriptor being accessed. The destination operand is a general-purpose register.

The processor performs access checks as part of the loading process. Once loaded in the desti-nation register, software can perform additional checks on the access rights information.

When the operand size is 32 bits, the access rights for a segment descriptor include the type and DPL fields and the S, P, AVL, D/B, and G flags, all of which are located in the second double-word (bytes 4 through 7) of the segment descriptor. The doubleword is masked by 00FXFF00H before it is loaded into the destination operand. When the operand size is 16 bits, the access rights include the type and DPL fields. Here, the two lower-order bytes of the doubleword are masked by FF00H before being loaded into the destination operand.

This instruction performs the following checks before it loads the access rights in the destination register:

· Checks that the segment selector is not null.
· Checks that the segment selector points to a descriptor that is within the limits of the GDT or LDT being accessed
· Checks that the descriptor type is valid for this instruction. All code and data segment descriptors are valid for (can be accessed with) the LAR instruction. The valid system segment and gate descriptor types are given in the following table.
· If the segment is not a conforming code segment, it checks that the specified segment descriptor is visible at the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to the DPL of the segment selector).

If the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no access rights are loaded in the destination operand.

The LAR instruction can only be executed in protected mode.

Operands Bytes Clocks
r16, r16 3 8 NP
r32, r32 3 8 NP
r16, m16 3 8 NP
r32, m32 3 8 NP

Flags
The ZF flag is set to 1 if the access rights are loaded successfully; otherwise, it is cleared to 0.


LDS - Load Far Pointer C5 / r LD

LDS - Load Far Pointer
C5 / r LDS r16,m16:16 Load DS: r16 with far pointer from memory
C5 / r LDS r32,m16:32 Load DS: r32 with far pointer from memory
0F B2 / r LSS r16,m16:16 Load SS: r16 with far pointer from memory
0F B2 / r LSS r32,m16:32 Load SS: r32 with far pointer from memory
C4 / r LES r16,m16:16 Load ES: r16 with far pointer from memory
C4 / r LES r32,m16:32 Load ES: r32 with far pointer from memory
0F B4 / r LFS r16,m16:16 Load FS: r16 with far pointer from memory
0F B4 / r LFS r32,m16:32 Load FS: r32 with far pointer from memory
0F B5 / r LGS r16,m16:16 Load GS: r16 with far pointer from memory
0F B5 / r LGS r32,m16:32 Load GS: r32 with far pointer from memory

Description
Loads a far pointer (segment selector and offset) from the second operand (source operand) into a segment register and the first operand (destination operand). The source operand specifies a 48-bit or a 32-bit pointer in memory depending on the current setting of the operand-size attribute (32 bits or 16 bits, respectively). The instruction opcode and the destination operand specify a segment register/general-purpose register pair. The 16-bit segment selector from the source operand is loaded into the segment register specified with the opcode (DS, SS, ES, FS, or GS). The 32-bit or 16-bit offset is loaded into the register specified with the destination operand.

If one of these instructions is executed in protected mode, additional information from the segment descriptor pointed to by the segment selector in the source operand is loaded in the hidden part of the selected segment register.

Also in protected mode, a null selector (values 0000 through 0003) can be loaded into DS, ES, FS, or GS registers without causing a protection exception. (Any subsequent reference to a segment whose corresponding segment register is loaded with a null selector, causes a general-protection exception (#GP) and no memory reference to the segment occurs.)

Operands Bytes Clocks
reg, mem 2+d(2) 4 NP

Flags
None.


LEA - Load Effective Address 8D

LEA - Load Effective Address
8D / r LEA r16,m Store effective address for m in register r16
8D / r LEA r32,m Store effective address for m in register r32

Description
Computes the effective address of the second operand (the source operand) and stores it in the first operand (destination operand). The source operand is a memory address (offset part) specified with one of the processors addressing modes; the destination operand is a general-purpose register. The address-size and operand-size attributes affect the action performed by this instruction, as shown in the following table. The operand-size attribute of the instruction is determined by the chosen register; the address-size attribute is determined by the attribute of the codesegment.

Operand Size Address Size Action Performed
16 16 16-bit effective address is calculated and stored in requested
16-bit register destination.
16 32 32-bit effective address is calculated. The lower 16 bits of the
address are stored in the requested 16-bit register destination.
32 16 16-bit effective address is calculated. The 16-bit address is zero-extended
and stored in the requested 32-bit register destination.
32 32 32-bit effective address is calculated and stored in the requested
32-bit register destination.

Different assemblers may use different algorithms based on the size attribute and symbolic reference of the source operand.

Operands Bytes Clocks
r16, mem 2+d(2) 1 UV
r32, mem 2+d(2) 1 UV

Flags
None.


LEAVE - High Level Procedure Exi

LEAVE - High Level Procedure Exit
C9 LEAVE Set SP to BP, then pop BP
C9 LEAVE Set ESP to EBP, then pop EBP

Description
Releases the stack frame set up by an earlier ENTER instruction. The LEAVE instruction copies the frame pointer (in the EBP register) into the stack pointer register (ESP), which releases the stack space allocated to the stack frame. The old frame pointer (the frame pointer for the calling procedure that was saved by the ENTER instruction) is then popped from the stack into the EBP register, restoring the calling procedure's stack frame.

A RET instruction is commonly executed following a LEAVE instruction to return program control to the calling procedure.

See "Procedure Calls for Block-Structured Languages" in Chapter 6 of the Intel Architecture Software Developer's Manual, Volume 1, for detailed information on the use of the ENTER and LEAVE instructions.

Operands Bytes Clocks
1 3 NP

Flags
None.


LES - Load Far Pointer Usage

LES - Load Far Pointer

Usage: LES dest,src

Description
See LDSCW1.O

Operands Bytes Clocks
reg, mem 2+d(2) 4 NP


LFS - Load Far Pointer Usage

LFS - Load Far Pointer

Usage: LFS dest,src

Description
See LDSCW1.O

Operands Bytes Clocks
reg, mem 3+d(2,4) 4 NP

LGS - Load Far Pointer

Usage: LGS dest,src

Description
See LDSCW1.O

Operands Bytes Clocks
reg, mem 3+d(2,4) 4 NP


LGDT/LIDT - Load Global/Interrup

LGDT/LIDT - Load Global/Interrupt Descriptor Table Register
0F 01 /2 LGDT m16&32 Load m into GDTR
0F 01 /3 LIDT m16&32 Load m into IDTR

Description
Loads the values in the source operand into the global descriptor table register (GDTR) or the interrupt descriptor table register (IDTR). The source operand specifies a 6-byte memory location that contains the base address (a linear address) and the limit (size of table in bytes) of the global descriptor table (GDT) or the interrupt descriptor table (IDT). If operand-size attribute is 32 bits, a 16-bit limit (lower 2 bytes of the 6-byte data operand) and a 32-bit base address (upper 4 bytes of the data operand) are loaded into the register. If the operand-size attribute is 16 bits, a 16-bit limit (lower 2 bytes) and a 24-bit base address (third, fourth, and fifth byte) are loaded. Here, the high-order byte of the operand is not used and the high-order byte of the base address in the GDTR or IDTR is filled with zeros.

The LGDT and LIDT instructions are used only in operating-system software; they are not used in application programs. They are the only instructions that directly load a linear address (that is, not a segment-relative address) and a limit in protected mode. They are commonly executed in real-address mode to allow processor initialization prior to switching to protected mode.

See "SGDT/SIDT-Store Global/Interrupt Descriptor Table Register" in this chapter for information on storing the contents of the GDTR and IDTR.

Operands Bytes Clocks
mem48 5 6 NP

Flags
None.


LLDT - Load Local Descriptor Tab

LLDT - Load Local Descriptor Table Register
0F 00 /2 LLDT r/m16 Load segment selector r/m16 into LDTR

Description
Loads the source operand into the segment selector field of the local descriptor table register (LDTR). The source operand (a general-purpose register or a memory location) contains a segment selector that points to a local descriptor table (LDT). After the segment selector is loaded in the LDTR, the processor uses to segment selector to locate the segment descriptor for the LDT in the global descriptor table (GDT). It then loads the segment limit and base address for the LDT from the segment descriptor into the LDTR. The segment registers DS, ES, SS, FS, GS, and CS are not affected by this instruction, nor is the LDTR field in the task state segment (TSS) for the current task.

If the source operand is 0, the LDTR is marked invalid and all references to descriptors in the LDT (except by the LAR, VERR, VERW or LSL instructions) cause a general protection excep-tion (#GP).

The operand-size attribute has no effect on this instruction.

The LLDT instruction is provided for use in operating-system software; it should not be used in application programs. Also, this instruction can only be executed in protected mode.

Operands Bytes Clocks
r16 3 9 NP
mem16 3+d(0-2) 9 NP

Flags
None.

LIDT - Load Interrupt Descriptor Table Register

See LGDT/LIDTC W2CO


LMSW - Load Machine Status Word
0F 01 /6 LMSW r/m16 Loads r/m16 in machine status word of CR0

Description
Loads the source operand into the machine status word, bits 0 through 15 of register CR0. The source operand can be a 16-bit general-purpose register or a memory location. Only the low-order 4 bits of the source operand (which contains the PE, MP, EM, and TS flags) are loaded into CR0. The PG, CD, NW, AM, WP, NE, and ET flags of CR0 are not affected. The operand-size attribute has no effect on this instruction.

If the PE flag of the source operand (bit 0) is set to 1, the instruction causes the processor to switch to protected mode. While in protected mode, the LMSW instruction cannot be used clear the PE flag and force a switch back to real-address mode.

The LMSW instruction is provided for use in operating-system software; it should not be used in application programs. In protected or virtual-8086 mode, it can only be executed at CPL 0.

This instruction is provided for compatibility with the Intel 286 processor; programs and procedures intended to run on the Pentium Pro, Pentium, Intel486, and Intel386 processors should use the MOV (control registers) instruction to load the whole CR0 register. The MOV CR0 instruction can be used to set and clear the PE flag in CR0, allowing a procedure or program to switch between protected and real-address modes.

This instruction is a serializing instruction.

Operands Bytes Clocks
r16 3 8 NP
mem16 3+d(0-2) 8 NP

Flags
None.


LOCK - Assert LOCK# Signal Prefi

LOCK - Assert LOCK# Signal Prefix
F0 LOCK Asserts LOCK# signal for duration of the accompanying
 instruction

Description
Causes the processor's LOCK# signal to be asserted during execution of the accompanying instruction (turns the instruction into an atomic instruction). In a multiprocessor environment, the LOCK# signal insures that the processor has exclusive use of any shared memory while the signal is asserted.

Note that in later Intel Architecture processors (such as the Pentium Pro processor), locking may occur without the LOCK# signal being asserted. See Intel Architecture Compatibility below.

The LOCK prefix can be prepended only to the following instructions and to those forms of the instructions that use a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. An undefined opcode exception will be generated if the LOCK prefix is used with any other instruction. The XCHG instruction always asserts the LOCK# signal regardless of the presence or absence of the LOCK prefix.

The LOCK prefix is typically used with the BTS instruction to perform a read-modify-write operation on a memory location in shared memory environment.

The integrity of the LOCK prefix is not affected by the alignment of the memory field. Memory locking is observed for arbitrarily misaligned fields.

Operands Bytes Clocks
1 1 NP

Flags
None.


LODS/LODSB/LODSW/LODSD - Load St

LODS/LODSB/LODSW/LODSD - Load String
AC LODS m8 Load byte at address DS:(E)SI into AL
AD LODS m16 Load word at address DS:(E)SI into AX
AD LODS m32 Load doubleword at address DS:(E)SI into EAX
AC LODSB Load byte at address DS:(E)SI into AL
AD LODSW Load word at address DS:(E)SI into AX
AD LODSD Load doubleword at address DS:(E)SI into EAX

Description
Loads a byte, word, or doubleword from the source operand into the AL, AX, or EAX register, respectively. The source operand is a memory location, the address of which is read from the DS:EDI or the DS:SI registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). The DS segment may be overridden with a segment override prefix.

At the assembly-code level, two forms of this instruction are allowed: the "explicit-operands" form and the "no-operands" form. The explicit-operands form (specified with the LODS mnemonic) allows the source operand to be specified explicitly. Here, the source operand should be a symbol that indicates the size and location of the source value. The destination operand is then automatically selected to match the size of the source operand (the AL register for byte operands, AX for word operands, and EAX for doubleword operands). This explicit-operands form is provided to allow documentation; however, note that the documentation provided by this form can be misleading. That is, the source operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does not have to specify the correct location. The location is always specified by the DS:(E)SI registers, which must be loaded correctly before the load string instruction is executed.

The no-operands form provides "short forms" of the byte, word, and doubleword versions of the LODS instructions. Here also DS:(E)SI is assumed to be the source operand and the AL, AX, or EAX register is assumed to be the destination operand. The size of the source and destination operands is selected with the mnemonic: LODSB (byte loaded into register AL), LODSW (word loaded into AX), or LODSD (doubleword loaded into EAX).

After the byte, word, or doubleword is transferred from the memory location into the AL, AX, or EAX register, the (E)SI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)SI register is incremented; if the DF flag is 1, the ESI register is decremented.) The (E)SI register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword operations.

The LODS, LODSB, LODSW, and LODSD instructions can be preceded by the REP prefix for block loads of ECX bytes, words, or doublewords. More often, however, these instructions are used within a LOOP construct because further processing of the data moved into the register is usually necessary before the next transfer can be made. See "REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix" in this chapter for a description of the REP prefix.

Operands Bytes Clocks
all variants 1 2 NP

Flags
None.


LOOP - Loop According to ECX Cou

LOOP - Loop According to ECX Counter
E2 cb LOOP rel8 Decrement count; jump short if count ¹ 0
E1 cb LOOPE rel8 Decrement count; jump short if count ¹ 0 and ZF=1
E1 cb LOOPZ rel8 Decrement count; jump short if count ¹ 0 and ZF=1
E0 cb LOOPNE rel8 Decrement count; jump short if count ¹ 0 and ZF=0
E0 cb LOOPNZ rel8 Decrement count; jump short if count ¹ 0 and ZF=0

Description
Performs a loop operation using the ECX or CX register as a counter. Each time the LOOP instruction is executed, the count register is decremented, then checked for 0. If the count is 0, the loop is terminated and program execution continues with the instruction following the LOOP instruction. If the count is not zero, a near jump is performed to the destination (target) operand, which is presumably the instruction at the beginning of the loop. If the address-size attribute is 32 bits, the ECX register is used as the count register; otherwise the CX register is used.

The target instruction is specified with a relative offset (a signed offset relative to the current value of the instruction pointer in the EIP register). This offset is generally specified as a label in assembly code, but at the machine code level, it is encoded as a signed, 8-bit immediate value, which is added to the instruction pointer. Offsets of -128 to +127 are allowed with this instruction.

Some forms of the loop instruction (LOOPcc) also accept the ZF flag as a condition for terminating the loop before the count reaches zero. With these forms of the instruction, a condition code (cc) is associated with each instruction to indicate the condition being tested for. Here, the LOOPcc instruction itself does not affect the state of the ZF flag; the ZF flag is changed by other instructions in the loop.

Operands Bytes Clocks
short 2 5/6 NP

Flags
None.


LOOPcc - Loop According to ECX C

LOOPcc - Loop According to ECX Counter

Usage: LOOPcc label

Description
See LOOPMM81W4

Operands Bytes Clocks
2 7/8 NP


LSL - Load Segment Limit 0F 03 /

LSL - Load Segment Limit
0F 03 / r LSL r16,r/m16 Load: r16 ¬ segment limit, selector r/m16
0F 03 / r LSL r32,r/m32 Load: r32 ¬ segment limit, selector r/m32)

Description
Loads the unscrambled segment limit from the segment descriptor specified with the second operand (source operand) into the first operand (destination operand) and sets the ZF flag in the EFLAGS register. The source operand (which can be a register or a memory location) contains the segment selector for the segment descriptor being accessed. The destination operand is a general-purpose register.

The processor performs access checks as part of the loading process. Once loaded in the destination register, software can compare the segment limit with the offset of a pointer.

The segment limit is a 20-bit value contained in bytes 0 and 1 and in the first 4 bits of byte 6 of the segment descriptor. If the descriptor has a byte granular segment limit (the granularity flag is set to 0), the destination operand is loaded with a byte granular value (byte limit). If the descriptor has a page granular segment limit (the granularity flag is set to 1), the LSL instruction will translate the page granular limit (page limit) into a byte limit before loading it into the desti-nation operand. The translation is performed by shifting the 20-bit "raw" limit left 12 bits and filling the low-order 12 bits with 1s.

When the operand size is 32 bits, the 32-bit byte limit is stored in the destination operand. When the operand size is 16 bits, a valid 32-bit limit is computed; however, the upper 16 bits are trun-cated and only the low-order 16 bits are loaded into the destination operand.

This instruction performs the following checks before it loads the segment limit into the desti-nation register:

· Checks that the segment selector is not null.
· Checks that the segment selector points to a descriptor that is within the limits of the GDT or LDT being accessed
· Checks that the descriptor type is valid for this instruction. All code and data segment descriptors are valid for (can be accessed with) the LSL instruction. The valid special segment and gate descriptor types are given in the following table.
· If the segment is not a conforming code segment, the instruction checks that the specified segment descriptor is visible at the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to the DPL of the segment selector).

If the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no value is loaded in the destination operand.

Type Name Valid
0 Reserved No
1 Available 16-bit TSS Yes
2 LDT Yes
3 Busy 16-bit TSS Yes
4 16-bit call gate No
5 16-bit/32-bit task gate No
6 16-bit interrupt gate No
7 16-bit trap gate No
8 Reserved No
9 Available 32-bit TSS Yes
A Reserved No
B Busy 32-bit TSS Yes
C 32-bit call gate No
D Reserved No
E 32-bit interrupt gate No
F 32-bit trap gate No

Operands Bytes Clocks
r16, r16 3 8 NP
r32, r32 3 8 NP
r16, m16 3+d(0,2) 8 NP
r32, m32 3+d(0,2) 8 NP

Flags
The ZF flag is set to 1 if the segment limit is loaded successfully; otherwise, it is cleared to 0.

LTR - Load Task Register
0F 00 /3 LTR r/m16 Load r/m16 into task register

Description
Loads the source operand into the segment selector field of the task register. The source operand (a general-purpose register or a memory location) contains a segment selector that points to a task state segment (TSS). After the segment selector is loaded in the task register, the processor uses the segment selector to locate the segment descriptor for the TSS in the global descriptor table (GDT). It then loads the segment limit and base address for the TSS from the segment descriptor into the task register. The task pointed to by the task register is marked busy, but a switch to the task does not occur.

The LTR instruction is provided for use in operating-system software; it should not be used in application programs. It can only be executed in protected mode when the CPL is 0. It is commonly used in initialization code to establish the first task to be executed.

The operand-size attribute has no effect on this instruction.

Operands Bytes Clocks
r16 3 10 NP
mem16 3+d(0,2) 10 NP

 Flags
None.


LSS - Load Far Pointer Usage

LSS - Load Far Pointer

Usage: LSS dest,src

Description
See LDSCW1.O

Operands Bytes Clocks
reg, mem 3+d(2,4) 4 N P


MOV - Move to/from Debug Registe

MOV - Move to/from Debug Registers
0F 21/ r MOV r32, DR0-DR7 Move debug register to r32
0F 23 / r MOV DR0-DR7, r32 Move r32 to debug register

Description
Moves the contents of a debug register (DR0, DR1, DR2, DR3, DR4, DR5, DR6, or DR7) to a general-purpose register or vice versa. The operand size for these instructions is always 32 bits, regardless of the operand-size attribute. (See Chapter 14, Debugging and Performance Monitoring, of the Intel Architecture Software Developer's Manual, Volume 3, for a detailed description of the flags and fields in the debug registers.)

The instructions must be executed at privilege level 0 or in real-address mode.

When the debug extension (DE) flag in register CR4 is clear, these instructions operate on debug registers in a manner that is compatible with Intel386 and Intel486 processors. In this mode, references to DR4 and DR5 refer to DR6 and DR7, respectively. When the DE set in CR4 is set, attempts to reference DR4 and DR5 result in an undefined opcode (#UD) exception. (The CR4 register was added to the Intel Architecture beginning with the Pentium processor.)

At the opcode level, the reg field within the ModR/M byte specifies which of the debug registers is loaded or read. The two bits in the mod field are always 11. The r/m field specifies the general-purpose register loaded or read.

Operands Bytes Clocks
See MOVCW3CO

Flags
The OF, SF, ZF, AF, PF, and CF flags are undefined.


MOV - Move to/from Control Regis

MOV - Move to/from Control Registers
0F 22 / r MOV CR0, r32 Move r32 to CR0
0F 22 / r MOV CR2, r32 Move r32 to CR2
0F 22 / r MOV CR3, r32 Move r32 to CR3
0F 22 / r MOV CR4, r32 Move r32 to CR4
0F 20 / r MOV r32,CR0 Move CR0 to r32
0F 20 / r MOV r32,CR2 Move CR2 to r32
0F 20 / r MOV r32,CR3 Move CR3 to r32
0F 20 / r MOV r32,CR4 Move CR4 to r32

Description
Moves the contents of a control register (CR0, CR2, CR3, or CR4) to a general-purpose register or vice versa. The operand size for these instructions is always 32 bits, regardless of the operand-size attribute. (See "Control Registers" in Chapter 2 of the Intel Architecture Software Devel-oper's Manual, Volume 3, for a detailed description of the flags and fields in the control regis-ters.)

When loading a control register, a program should not attempt to change any of the reserved bits; that is, always set reserved bits to the value previously read.

At the opcode level, the reg field within the ModR/M byte specifies which of the control registers is loaded or read. The 2 bits in the mod field are always 11B. The r/m field specifies the general-purpose register loaded or read.

These instructions have the following side effects:

· When writing to control register CR3, all non-global TLB entries are flushed (see "Translation Lookaside Buffers (TLBs)" in Chapter 3 of the Intel Architecture Software Developer's Manual, Volume 3).

Operands Bytes Clocks
See MOVCW30O

Flags
The OF, SF, ZF, AF, PF, and CF flags are undefined.


MOV - Move 88 / r MOV r/m8

MOV - Move
88 / r MOV r/m8,r8 Move r8 to r/m8
89 / r MOV r/m16,r16 Move r16 to r/m16
89 / r MOV r/m32,r32 Move r32 to r/m32
8A / r MOV r8,r/m8 Move r/m8 to r8
8B / r MOV r16,r/m16 Move r/m16 to r16
8B / r MOV r32,r/m32 Move r/m32 to r32
8C / r MOV r/m16,Sreg** Move segment register to r/m16
8E / r MOV Sreg,r/m16** Move r/m16 to segment register
A0 MOV AL, moffs8* Move byte at ( seg:offset) to AL
A1 MOV AX, moffs16* Move word at ( seg:offset) to AX
A1 MOV EAX, moffs32* Move doubleword at ( seg:offset) to EAX
A2 MOV moffs8*,AL Move AL to ( seg:offset)
A3 MOV moffs16*,AX Move AX to ( seg:offset)
A3 MOV moffs32*,EAX Move EAX to ( seg:offset)
B0+ rb MOV r8,imm8 Move imm8 to r8
B8+ rw MOV r16,imm16 Move imm16 to r16
B8+ rd MOV r32,imm32 Move imm32 to r32
C6 / 0 MOV r/m8,imm8 Move imm8 to r/m8
C7 / 0 MOV r/m16,imm16 Move imm16 to r/m16
C7 / 0 MOV r/m32,imm32 Move imm32 to r/m32
NOTES:
*The moffs8, moffs16, and moffs32 operands specify a simple offset relative to the segment base, where 8, 16, and 32 refer to the size of the data. The address-size attribute of the instruction determines the size of the offset, either 16 or 32 bits.
** In 32-bit mode, the assembler may insert the 16-bit operand-size prefix with this instruction (see the following “Description” section for further information).

Description
Copies the second operand (source operand) to the first operand (destination operand). The source operand can be an immediate value, general-purpose register, segment register, or memory location; the destination register can be a general-purpose register, segment register, or memory location. Both operands must be the same size, which can be a byte, a word, or a doubleword.

The MOV instruction cannot be used to load the CS register. Attempting to do so results in an invalid opcode exception (#UD). To load the CS register, use the far JMP, CALL, or RET instruction.

If the destination operand is a segment register (DS, ES, FS, GS, or SS), the source operand must be a valid segment selector. In protected mode, moving a segment selector into a segment register automatically causes the segment descriptor information associated with that segment selector to be loaded into the hidden (shadow) part of the segment register. While loading this information, the segment selector and segment descriptor information is validated (see the "Operation" algorithm below). The segment descriptor data is obtained from the GDT or LDT entry for the specified segment selector.

A null segment selector (values 0000-0003) can be loaded into the DS, ES, FS, and GS registers without causing a protection exception. However, any subsequent attempt to reference a segment whose corresponding segment register is loaded with a null value causes a general protection exception (#GP) and no memory reference occurs.

Loading the SS register with a MOV instruction inhibits all interrupts until after the execution of the next instruction. This operation allows a stack pointer to be loaded into the ESP register with the next instruction (MOV ESP, stack-pointer value) before an interrupt occurs 1 . The LSS instruction offers a more efficient method of loading the SS and ESP registers.

When operating in 32-bit mode and moving data between a segment register and a general-purpose register, the Intel Architecture 32-bit processors do not require the use of the 16-bit operand-size prefix (a byte with the value 66H) with this instruction, but most assemblers will insert it if the standard form of the instruction is used (for example, MOV DS, AX). The processor will execute this instruction correctly, but it will usually require an extra clock. With most assemblers, using the instruction form MOV DS, EAX will avoid this unneeded 66H prefix. When the processor executes the instruction with a 32-bit general-purpose register, it assumes that the 16 least-significant bits of the general-purpose register are the destination or source operand. If the register is a destination operand, the resulting value in the two high-order bytes of the register is implementation dependent. For the Pentium Pro processor, the two high-order bytes are filled with zeros; for earlier 32-bit Intel Architecture processors, the two high order bytes are undefined.

Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2+d(0-2) 1 UV
reg, mem 2+d(0-2) 1 UV
mem, imm 2+d(0-2)+i(1,2) 1 UV*
reg, imm 2+i(1,2) 1 UV
acc, mem 3 1 UV
mem, acc 3 1 UV

* = not pairable if there is a displacement and immediate

Segment Register Moves

Real Mode
seg, r16 2 2-11 NP
seg, m16 2+d(0,2) 3-12 NP
r16, seg 2 1 NP
m16, seg 2+d(0,2) 1 NP

Protected Mode Differences
seg, r16 2 2-11* NP
seg, m16 2+d(0,2) 3-12* NP
* = add 8 if new descriptor; add 6 if SS

MOVE to/from special registers
r32, cr32 3 4 NP
cr32, r32 3 12/22* NP

r32, dr32 3 2/12* NP
dr32, r32 3 11/12* NP

r32, tr32 3 - NP
tr32, r32 3 - NP

* = cycles depend on which special register

Flags
None.


MOVS/MOVSB/MOVSW/MOVSD - Move Da

MOVS/MOVSB/MOVSW/MOVSD - Move Data from String to String
A4 MOVS m8, m8 Move byte at address DS:(E)SI to address ES:(E)DI
A5 MOVS m16, m16 Move word at address DS:(E)SI to address ES:(E)DI
A5 MOVS m32, m32 Move doubleword at address DS:(E)SI to address
ES:(E)DI
A4 MOVSB Move byte at address DS:(E)SI to address ES:(E)DI
A5 MOVSW Move word at address DS:(E)SI to address ES:(E)DI
A5 MOVSD Move doubleword at address DS:(E)SI to address
ES:(E)DI

Description
Moves the byte, word, or doubleword specified with the second operand (source operand) to the location specified with the first operand (destination operand). Both the source and destination operands are located in memory. The address of the source operand is read from the DS:ESI or the DS:SI registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). The address of the destination operand is read from the ES:EDI or the ES:DI registers (again depending on the address-size attribute of the instruction). The DS segment may be over-ridden with a segment override prefix, but the ES segment cannot be overridden.

At the assembly-code level, two forms of this instruction are allowed: the "explicit-operands" form and the "no-operands" form. The explicit-operands form (specified with the MOVS mnemonic) allows the source and destination operands to be specified explicitly. Here, the source and destination operands should be symbols that indicate the size and location of the source value and the destination, respectively. This explicit-operands form is provided to allow documentation; however, note that the documentation provided by this form can be misleading. That is, the source and destination operand symbols must specify the correct type (size) of the operands (bytes, words, or doublewords), but they do not have to specify the correct location. The locations of the source and destination operands are always specified by the DS:(E)SI and ES:(E)DI registers, which must be loaded correctly before the move string instruction is executed.

The no-operands form provides "short forms" of the byte, word, and doubleword versions of the MOVS instructions. Here also DS:(E)SI and ES:(E)DI are assumed to be the source and destination operands, respectively. The size of the source and destination operands is selected with the mnemonic: MOVSB (byte move), MOVSW (word move), or MOVSD (doubleword move).

After the move operation, the (E)SI and (E)DI registers are incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)SI and (E)DI register are incremented; if the DF flag is 1, the (E)SI and (E)DI registers are decremented.) The registers are incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword operations.

The MOVS, MOVSB, MOVSW, and MOVSD instructions can be preceded by the REP prefix (see "REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix" in this chapter) for block moves of ECX bytes, words, or doublewords.

Variations Bytes Clocks
movsb 1 4 NP
movsw 1 4 NP
movsd 1 4 NP
rep movsb 2 3+n NP
rep movsw 2 3+n NP
rep movsd 2 3+n NP

(n = count of bytes, words or dwords)

Flags
None.


MOVSX - Move with Sign-Extension
0F BE / r MOVSX r16,r/m8 Move byte to word with sign-extension
0F BE / r MOVSX r32,r/m8 Move byte to doubleword, sign-extension
0F BF / r MOVSX r32,r/m16 Move word to doubleword, sign-extension

Description
Copies the contents of the source operand (register or memory location) to the destination operand (register) and sign extends the value to 16 or 32 bits (see Figure 6-5 in the Intel Architecture Software Developer's Manual, Volume 1). The size of the converted value depends on the operand-size attribute.

Operands Bytes Clocks
reg, reg 3 3 NP
reg, mem 3+d(0,1,2,4) 3 NP
(Note: destination reg is 16 or 32-bits; source is 8 or 16 bits)

Flags
None.


MOVZX - Move with Zero-Extend 0F

MOVZX - Move with Zero-Extend
0F B6 / r MOVZX r16,r/m8 Move byte to word with zero-extension
0F B6 / r MOVZX r32,r/m8 Move byte to doubleword, zero-extension
0F B7 / r MOVZX r32,r/m16 Move word to doubleword, zero-extension

Description
Copies the contents of the source operand (register or memory location) to the destination operand (register) and zero extends the value to 16 or 32 bits. The size of the converted value depends on the operand-size attribute.

Operands Bytes Clocks
reg, reg 3 3 NP
reg, mem 3+d(0,1,2,4) 3 NP
(Note: destination reg is 16 or 32-bits; source is 8 or 16 bits)

Flags
None.


MUL - Unsigned Multiply F6 /4 M

MUL - Unsigned Multiply
F6 /4 MUL r/m8 Unsigned multiply (AX ¬ AL * r/m8)
F7 /4 MUL r/m16 Unsigned multiply (DX:AX ¬ AX * r/m16)
F7 /4 MUL r/m32 Unsigned multiply (EDX:EAX ¬ EAX * r/m32)

Description
Performs an unsigned multiplication of the first operand (destination operand) and the second operand (source operand) and stores the result in the destination operand. The destination operand is an implied operand located in register AL, AX or EAX (depending on the size of the operand); the source operand is located in a general-purpose register or a memory location. The action of this instruction and the location of the result depends on the opcode and the operand size as shown in the following table.

Operand Size Source 1 Source 2 Destination
Byte AL r/m8 AX
Word AX r/m16 DX:AX
Doubleword EAX r/m32 EDX:EAX

The result is stored in register AX, register pair DX:AX, or register pair EDX:EAX (depending on the operand size), with the high-order bits of the product contained in register AH, DX, or EDX, respectively. If the high-order bits of the product are 0, the CF and OF flags are cleared; otherwise, the flags are set.

Operands Bytes Clocks
r8 2 11 NP
r16 2 11 NP
r32 2 10 NP
mem8 2+d(0-2) 11 NP
mem16 2+d(0-2) 11 NP
mem32 2+d(0-2) 10 NP

implied operand result
multiplicand (multiplier)
AL * byte = AX
AX * word = DX:AX
EAX * dword = EDX:EAX

Flags
The OF and CF flags are cleared to 0 if the upper half of the result is 0; otherwise, they are set to 1. The SF, ZF, AF, and PF flags are undefined.


NEG - Two

NEG - Two's Complement Negation
F6 /3 NEG r/m8 Two's complement negate r/m8
F7 /3 NEG r/m16 Two's complement negate r/m16
F7 /3 NEG r/m32 Two's complement negate r/m32

Description
Replaces the value of operand (the destination operand) with its two's complement. (This operation is equivalent to subtracting the operand from 0.) The destination operand is located in a general-purpose register or a memory location.

Operands Bytes Clocks
reg 2 1 NP
mem 2+d(0-2) 3 NP

Flags
The CF flag cleared to 0 if the source operand is 0; otherwise it is set to 1. The OF, SF, ZF, AF, and PF flags are set according to the result.


NOP - No Operation 90 NOP No op

NOP - No Operation
90 NOP No operation

Description
Performs no operation. This instruction is a one-byte instruction that takes up space in the instruction stream but does not affect the machine context, except the EIP register.

The NOP instruction is an alias mnemonic for the XCHG (E)AX, (E)AX instruction.

Operands Bytes Clocks
1 1 UV

Flags
None.


NOT - One

NOT - One's Complement Negation
F6 /2 NOT r/m8 Reverse each bit of r/m8
F7 /2 NOT r/m16 Reverse each bit of r/m16
F7 /2 NOT r/m32 Reverse each bit of r/m32

Description
Performs a bitwise NOT operation (each 1 is cleared to 0, and each 0 is set to 1) on the destination operand and stores the result in the destination operand location. The destination operand can be a register or a memory location.

Operands Bytes Clocks
reg 2 1 NP
mem 2+d(0-2) 3 NP

Flags
None.


OR - Logical Inclusive OR 0C ib

OR - Logical Inclusive OR
0C ib OR AL, imm8 AL OR imm8
0D iw OR AX, imm16 AX OR imm16
0D id OR EAX, imm32 EAX OR imm32
80 /1 ib OR r/m8,imm8 r/m8 OR imm8
81 /1 iw OR r/m16,imm16 r/m16 OR imm16
81 /1 id OR r/m32,imm32 r/m32 OR imm32
83 /1 ib OR r/m16,imm8 r/m16 OR imm8 (sign-extended)
83 /1 ib OR r/m32,imm8 r/m32 OR imm8 (sign-extended)
08 / r OR r/m8,r8 r/m8 OR r8
09 / r OR r/m16,r16 r/m16 OR r16
09 / r OR r/m32,r32 r/m32 OR r32
0A / r OR r8,r/m8 r8 OR r/m8
0B / r OR r16,r/m16 r16 OR r/m16
0B / r OR r32,r/m32 r32 OR r/m32

Description
Performs a bitwise inclusive OR operation between the destination (first) and source (second) operands and stores the result in the destination operand location. The source operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location. (However, two memory operands cannot be used in one instruction.) Each bit of the result of the OR instruction is 0 if both corresponding bits of the operands are 0; otherwise, each bit is 1.

Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2+d(0,2) 3 UV
reg, mem 2+d(0,2) 2 UV
reg, imm 2+i(1,2) 1 UV
mem, imm 2+d(0,2)+i(1,2) 3 UV*
acc, imm 1+i(1,2) 1 UV

* = not pairable if there is a displacement and immediate

Flags
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is undefined.


OUT - Output to Port E6 ib OUT

OUT - Output to Port
E6 ib OUT imm8, AL Output byte in AL to I/O port address imm8
E7 ib OUT imm8, AX Output word in AX to I/O port address imm8
E7 ib OUT imm8, EAX Output doubleword in EAX to I/O port address imm8
EE OUT DX, AL Output byte in AL to I/O port address in DX
EF OUT DX, AX Output word in AX to I/O port address in DX
EF OUT DX, EAX Output doubleword in EAX to I/O port address in DX

Description
Copies the value from the second operand (source operand) to the I/O port specified with the destination operand (first operand). The source operand can be register AL, AX, or EAX, depending on the size of the port being accessed (8, 16, or 32 bits, respectively); the destination operand can be a byte-immediate or the DX register. Using a byte immediate allows I/O port addresses 0 to 255 to be accessed; using the DX register as a source operand allows I/O ports from 0 to 65,535 to be accessed.

The size of the I/O port being accessed is determined by the opcode for an 8-bit I/O port or by the operand-size attribute of the instruction for a 16- or 32-bit I/O port.

At the machine code level, I/O instructions are shorter when accessing 8-bit I/O ports. Here, the upper eight bits of the port address will be 0.

This instruction is only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 9, Input/Output, in the Intel Architecture Software Developer's Manual, Vo l u me 1 , for more information on accessing I/O ports in the I/O address space.

Operands Bytes Clocks
imm8, al 2 12 NP
imm8, ax 2 12 NP
imm8, eax 2 12 NP
dx, al 1 12 NP
dx, ax 1 12 NP
dx, eax 1 12 NP

Protected Mode
imm8, acc 2 9/26/24 NP
dx, acc 1 9/26/24 NP

cycles for: CPL <= IOPL / CPL > IOPL / V86

Flags
None.


OUTS/OUTSB/OUTSW/OUTSD - Output

OUTS/OUTSB/OUTSW/OUTSD - Output String to Port
6E OUTS DX, m8 Output byte from memory location specified in DS:(E)SI to
I/O port specified in DX
6F OUTS DX, m16 Output word from memory location specified in DS:(E)SI
to I/O port specified in DX
6F OUTS DX, m32 Output doubleword from memory location specified in
DS:(E)SI to I/O port specified in DX
6E OUTSB Output byte from memory location specified in DS:(E)SI to
I/O port specified in DX
6F OUTSW Output word from memory location specified in DS:(E)SI
to I/O port specified in DX
6F OUTSD Output doubleword from memory location specified in
DS:(E)SI to I/O port specified in DX

Description
Copies data from the source operand (second operand) to the I/O port specified with the destination operand (first operand). The source operand is a memory location, the address of which is read from either the DS:EDI or the DS:DI registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). (The DS segment may be overridden with a segment override prefix.) The destination operand is an I/O port address (from 0 to 65,535) that is read from the DX register. The size of the I/O port being accessed (that is, the size of the source and destination operands) is determined by the opcode for an 8-bit I/O port or by the operand-size attribute of the instruction for a 16- or 32-bit I/O port.

At the assembly-code level, two forms of this instruction are allowed: the "explicit-operands" form and the "no-operands" form. The explicit-operands form (specified with the OUTS mnemonic) allows the source and destination operands to be specified explicitly. Here, the source operand should be a symbol that indicates the size of the I/O port and the source address, and the destination operand must be DX. This explicit-operands form is provided to allow docu-mentation; however, note that the documentation provided by this form can be misleading. That is, the source operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does not have to specify the correct location. The location is always spec-ified by the DS:(E)SI registers, which must be loaded correctly before the OUTS instruction is executed.

The no-operands form provides "short forms" of the byte, word, and doubleword versions of the OUTS instructions. Here also DS:(E)SI is assumed to be the source operand and DX is assumed to be the destination operand. The size of the I/O port is specified with the choice of mnemonic: OUTSB (byte), OUTSW (word), or OUTSD (doubleword).

After the byte, word, or doubleword is transferred from the memory location to the I/O port, the (E)SI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)SI register is incremented; if the DF flag is 1, the (E)SI register is decremented.) The (E)SI register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword operations.

The OUTS, OUTSB, OUTSW, and OUTSD instructions can be preceded by the REP prefix for block input of ECX bytes, words, or doublewords. See "REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix" in this chapter for a description of the REP prefix.

This instruction is only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 9, Input/Output, in the Intel Architecture Software Developer's Manual, Vo l u me 1 , for more information on accessing I/O ports in the I/O address space.

Variations Bytes Clocks
outsb 1 13 NP
outsw 1 13 NP
outsd 1 13 NP

Protected Mode
1 10/27/25 NP

cycles for: CPL <= IOPL / CPL > IOPL / V86

Flags
None.


POP - Pop a Value from the Stack
8F /0 POP m16 Pop top of stack into m16; increment stack pointer
8F /0 POP m32 Pop top of stack into m32; increment stack pointer
58+ rw POP r16 Pop top of stack into r16; increment stack pointer
58+ rd POP r32 Pop top of stack into r32; increment stack pointer
1F POP DS Pop top of stack into DS; increment stack pointer
07 POP ES Pop top of stack into ES; increment stack pointer
17 POP SS Pop top of stack into SS; increment stack pointer
0F A1 POP FS Pop top of stack into FS; increment stack pointer
0F A9 POP GS Pop top of stack into GS; increment stack pointer

Description
Loads the value from the top of the stack to the location specified with the destination operand and then increments the stack pointer. The destination operand can be a general-purpose register, memory location, or segment register.

The address-size attribute of the stack segment determines the stack pointer size (16 bits or 32 bits-the source address size), and the operand-size attribute of the current code segment deter-mines the amount the stack pointer is incremented (2 bytes or 4 bytes). For example, if these address- and operand-size attributes are 32, the 32-bit ESP register (stack pointer) is incre-mented by 4 and, if they are 16, the 16-bit SP register is incremented by 2. (The B flag in the stack segment's segment descriptor determines the stack's address-size attribute, and the D flag in the current code segment's segment descriptor, along with prefixes, determines the operand-size attribute and also the address-size attribute of the destination operand.)

If the destination operand is one of the segment registers DS, ES, FS, GS, or SS, the value loaded into the register must be a valid segment selector. In protected mode, popping a segment selector into a segment register automatically causes the descriptor information associated with that segment selector to be loaded into the hidden (shadow) part of the segment register and causes the selector and the descriptor information to be validated (see the "Operation" section below).

A null value (0000-0003) may be popped into the DS, ES, FS, or GS register without causing a general protection fault. However, any subsequent attempt to reference a segment whose corre-sponding segment register is loaded with a null value causes a general protection exception (#GP). In this situation, no memory reference occurs and the saved value of the segment register is null.

The POP instruction cannot pop a value into the CS register. To load the CS register from the stack, use the RET instruction.

If the ESP register is used as a base register for addressing a destination operand in memory, the POP instruction computes the effective address of the operand after it increments the ESP register.

The POP ESP instruction increments the stack pointer (ESP) before data at the old top of stack is written into the destination.

A POP SS instruction inhibits all interrupts, including the NMI interrupt, until after execution of the next instruction. This action allows sequential execution of POP SS and MOV ESP, EBP instructions without the danger of having an invalid stack during an interrupt 1 . However, use of the LSS instruction is the preferred method of loading the SS and ESP registers.

Operands Bytes Clocks
reg 1 1 UV
mem 2+d(0-2) 3 NP
seg 1 3 NP
FS/GS 2 3 NP

Protected Mode
CS/DS/ES 1 3-12 NP
SS 1 8-17 NP
FS/GS 2 3-12 NP

Flags
None.


POPA/POPAD - Pop All General-Pur

POPA/POPAD - Pop All General-Purpose Registers
61 POPA Pop DI, SI, BP, BX, DX, CX, and AX
61 POPAD Pop EDI, ESI, EBP, EBX, EDX, ECX, and EAX

Description
Pops doublewords (POPAD) or words (POPA) from the stack into the general-purpose registers. The registers are loaded in the following order: EDI, ESI, EBP, EBX, EDX, ECX, and EAX (if the operand-size attribute is 32) and DI, SI, BP, BX, DX, CX, and AX (if the operand-size attribute is 16). (These instructions reverse the operation of the PUSHA/PUSHAD instructions.) The value on the stack for the ESP or SP register is ignored. Instead, the ESP or SP register is incremented after each register is loaded.

The POPA (pop all) and POPAD (pop all double) mnemonics reference the same opcode. The POPA instruction is intended for use when the operand-size attribute is 16 and the POPAD instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when POPA is used and to 32 when POPAD is used (using the operand-size override prefix [66H] if necessary). Others may treat these mnemonics as synonyms (POPA/POPAD) and use the current setting of the operand-size attribute to determine the size of values to be popped from the stack, regardless of the mnemonic used. (The D flag in the current code segment's segment descriptor determines the operand-size attribute.)

Variations Bytes Clocks
popa 1 5 NP
popad 1 5 NP

popa = pop di, si, bp, sp, bx, dx, cx, ax
popad = pop edi, esi, ebp, esp, ebx, edx, ecx, eax
(sp and esp are discarded)

Flags
None.


POPF/POPFD - Pop Stack into EFLA

POPF/POPFD - Pop Stack into EFLAGS Register
9D POPF Pop top of stack into lower 16 bits of EFLAGS
9D POPFD Pop top of stack into EFLAGS

Description
Pops a doubleword (POPFD) from the top of the stack (if the current operand-size attribute is 32) and stores the value in the EFLAGS register or pops a word from the top of the stack (if the operand-size attribute is 16) and stores it in the lower 16 bits of the EFLAGS register (that is, the FLAGS register). (These instructions reverse the operation of the PUSHF/PUSHFD instructions.)

The POPF (pop flags) and POPFD (pop flags double) mnemonics reference the same opcode. The POPF instruction is intended for use when the operand-size attribute is 16 and the POPFD instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when POPF is used and to 32 when POPFD is used. Others may treat these mnemonics as synonyms (POPF/POPFD) and use the current setting of the operand-size attribute to determine the size of values to be popped from the stack, regardless of the mnemonic used.

The effect of the POPF/POPFD instructions on the EFLAGS register changes slightly, depending on the mode of operation of the processor. When the processor is operating in protected mode at privilege level 0 (or in real-address mode, which is equivalent to privilege level 0), all the non-reserved flags in the EFLAGS register except the VIP, VIF, and VM flags can be modified. The VIP and VIF flags are cleared, and the VM flag is unaffected.

When operating in protected mode, with a privilege level greater than 0, but less than or equal to IOPL, all the flags can be modified except the IOPL field and the VIP, VIF, and VM flags. Here, the IOPL flags are unaffected, the VIP and VIF flags are cleared, and the VM flag is unaffected. The interrupt flag (IF) is altered only when executing at a level at least as privileged as the IOPL. If a POPF/POPFD instruction is executed with insufficient privilege, an exception does not occur, but the privileged bits do not change.

When operating in virtual-8086 mode, the I/O privilege level (IOPL) must be equal to 3 to use POPF/POPFD instructions and the VM, RF, IOPL, VIP, and VIF flags are unaffected. If the IOPL is less than 3, the POPF/POPFD instructions cause a general-protection exception (#GP).

See the section titled "EFLAGS Register" in Chapter 3 of the Intel Architecture Software Developer's Manual, Volume 1, for information about the EFLAGS registers.

Variations Bytes Clocks
popf 1 6 NP
popfd 1 6 NP

Protected Mode
popf 1 4 NP
popfd 1 4 NP

Flags
All flags except the reserved bits and the VM bit.


PUSH - Push Word or Doubleword O

PUSH - Push Word or Doubleword Onto the Stack
FF /6 PUSH r/m16 Push r/m16
FF /6 PUSH r/m32 Push r/m32
50+ rw PUSH r16 Push r16
50+ rd PUSH r32 Push r32
6A PUSH imm8 Push imm8
68 PUSH imm16 Push imm16
68 PUSH imm32 Push imm32
0E PUSH CS Push CS
16 PUSH SS Push SS
1E PUSH DS Push DS
06 PUSH ES Push ES
0F A0 PUSH FS Push FS
0F A8 PUSH GS Push GS

Description
Decrements the stack pointer and then stores the source operand on the top of the stack. The address-size attribute of the stack segment determines the stack pointer size (16 bits or 32 bits), and the operand-size attribute of the current code segment determines the amount the stack pointer is decremented (2 bytes or 4 bytes). For example, if these address- and operand-size attributes are 32, the 32-bit ESP register (stack pointer) is decremented by 4 and, if they are 16, the 16-bit SP register is decremented by 2.(The B flag in the stack segment's segment descriptor determines the stack's address-size attribute, and the D flag in the current code segment's segment descriptor, along with prefixes, determines the operand-size attribute and also the address-size attribute of the source operand.) Pushing a 16-bit operand when the stack address-size attribute is 32 can result in a misaligned the stack pointer (that is, the stack pointer is not aligned on a doubleword boundary).

The PUSH ESP instruction pushes the value of the ESP register as it existed before the instruction was executed. Thus, if a PUSH instruction uses a memory operand in which the ESP register is used as a base register for computing the operand address, the effective address of the operand is computed before the ESP register is decremented.

In the real-address mode, if the ESP or SP register is 1 when the PUSH instruction is executed, the processor shuts down due to a lack of stack space. No exception is generated to indicate this condition.

Operands Bytes Clocks
reg 1 1 UV
mem 2+d(0-2) 2 NP
seg 1 1 NP
imm 1+i(1,2) 1 NP
FS/GS 2 1 NP

Flags
None.


PUSHA/PUSHAD - Push All General-

PUSHA/PUSHAD - Push All General-Purpose Registers
60 PUSHA Push AX, CX, DX, BX, original SP, BP, SI, and DI
60 PUSHAD Push EAX, ECX, EDX, EBX, original ESP, EBP, ESI, and EDI

Description
Pushes the contents of the general-purpose registers onto the stack. The registers are stored on the stack in the following order: EAX, ECX, EDX, EBX, EBP, ESP (original value), EBP, ESI, and EDI (if the current operand-size attribute is 32) and AX, CX, DX, BX, SP (original value), BP, SI, and DI (if the operand-size attribute is 16). (These instructions perform the reverse operation of the POPA/POPAD instructions.) The value pushed for the ESP or SP register is its value before prior to pushing the first register (see the "Operation" section below).

The PUSHA (push all) and PUSHAD (push all double) mnemonics reference the same opcode. The PUSHA instruction is intended for use when the operand-size attribute is 16 and the PUSHAD instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when PUSHA is used and to 32 when PUSHAD is used. Others may treat these mnemonics as synonyms (PUSHA/PUSHAD) and use the current setting of the operand-size attribute to determine the size of values to be pushed from the stack, regardless of the mnemonic used.

In the real-address mode, if the ESP or SP register is 1, 3, or 5 when the PUSHA/PUSHAD instruction is executed, the processor shuts down due to a lack of stack space. No exception is generated to indicate this condition.

Variations Bytes Clocks
pusha 1 5 NP
pushad 1 5 NP

pusha = push ax, cx, dx, bx, sp, bp, si, di,
pushad = push eax, ecx, edx, ebx, esp, ebp, esi, edi

Flags
None.


RCL - Rotate Bits Left with CF D

RCL - Rotate Bits Left with CF
D0 /2 RCL r/m8,1 Rotate 9 bits (CF, r/m8) left once
D2 /2 RCL r/m8,CL Rotate 9 bits (CF, r/m8) left CL times
C0 /2 ib RCL r/m8,imm8 Rotate 9 bits (CF, r/m8) left imm8 times
D1 /2 RCL r/m16,1 Rotate 17 bits (CF, r/m16) left once
D3 /2 RCL r/m16,CL Rotate 17 bits (CF, r/m16) left CL times
C1 /2 ib RCL r/m16,imm8 Rotate 17 bits (CF, r/m16) left imm8 times
D1 /2 RCL r/m32,1 Rotate 33 bits (CF, r/m32) left once
D3 /2 RCL r/m32,CL Rotate 33 bits (CF, r/m32) left CL times
C1 /2 ib RCL r/m32,imm8 Rotate 33 bits (CF, r/m32) left imm8 times
D0 /3 RCR r/m8,1 Rotate 9 bits (CF, r/m8) right once
D2 /3 RCR r/m8,CL Rotate 9 bits (CF, r/m8) right CL times
C0 /3 ib RCR r/m8,imm8 Rotate 9 bits (CF, r/m8) right imm8 times
D1 /3 RCR r/m16,1 Rotate 17 bits (CF, r/m16) right once
D3 /3 RCR r/m16,CL Rotate 17 bits (CF, r/m16) right CL times
C1 /3 ib RCR r/m16,imm8 Rotate 17 bits (CF, r/m16) right imm8 times
D1 /3 RCR r/m32,1 Rotate 33 bits (CF, r/m32) right once
D3 /3 RCR r/m32,CL Rotate 33 bits (CF, r/m32) right CL times
C1 /3 ib RCR r/m32,imm8 Rotate 33 bits (CF, r/m32) right imm8 times
D0 /0 ROL r/m8,1 Rotate 8 bits r/m8 left once
D2 /0 ROL r/m8,CL Rotate 8 bits r/m8 left CL times
C0 /0 ib ROL r/m8,imm8 Rotate 8 bits r/m8 left imm8 times
D1 /0 ROL r/m16,1 Rotate 16 bits r/m16 left once
D3 /0 ROL r/m16,CL Rotate 16 bits r/m16 left CL times
C1 /0 ib ROL r/m16,imm8 Rotate 16 bits r/m16 left imm8 times
D1 /0 ROL r/m32,1 Rotate 32 bits r/m32 left once
D3 /0 ROL r/m32,CL Rotate 32 bits r/m32 left CL times
C1 /0 ib ROL r/m32,imm8 Rotate 32 bits r/m32 left imm8 times
D0 /1 ROR r/m8,1 Rotate 8 bits r/m8 right once
D2 /1 ROR r/m8,CL Rotate 8 bits r/m8 right CL times
C0 /1 ib ROR r/m8,imm8 Rotate 8 bits r/m16 right imm8 times
D1 /1 ROR r/m16,1 Rotate 16 bits r/m16 right once
D3 /1 ROR r/m16,CL Rotate 16 bits r/m16 right CL times
C1 /1 ib ROR r/m16,imm8 Rotate 16 bits r/m16 right imm8 times
D1 /1 ROR r/m32,1 Rotate 32 bits r/m32 right once
D3 /1 ROR r/m32,CL Rotate 32 bits r/m32 right CL times
C1 /1 ib ROR r/m32,imm8 Rotate 32 bits r/m32 right imm8 times

Description
Shifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the second operand (count operand) and stores the result in the destination operand. The destination operand can be a register or a memory location; the count operand is an unsigned integer that can be an immediate or a value in the CL register. The processor restricts the count to a number between 0 and 31 by masking all the bits in the count operand except the 5 least-significant bits.

The rotate left (ROL) and rotate through carry left (RCL) instructions shift all the bits toward more-significant bit positions, except for the most-significant bit, which is rotated to the least-significant bit location (see Figure 6-10 in the Intel Architecture Software Developer's Manual, Vo l u me 1 ). The rotate right (ROR) and rotate through carry right (RCR) instructions shift all the bits toward less significant bit positions, except for the least-significant bit, which is rotated to the most-significant bit location (see Figure 6-10 in the Intel Architecture Software Developer's Manual, Volume 1).

The RCL and RCR instructions include the CF flag in the rotation. The RCL instruction shifts the CF flag into the least-significant bit and shifts the most-significant bit into the CF flag (see Figure 6-10 in the Intel Architecture Software Developer's Manual, Volume 1). The RCR instruction shifts the CF flag into the most-significant bit and shifts the least-significant bit into the CF flag (see Figure 6-10 in the Intel Architecture Software Developer's Manual, Volume 1). For the ROL and ROR instructions, the original value of the CF flag is not a part of the result, but the CF flag receives a copy of the bit that was shifted from one end to the other.

The OF flag is defined only for the 1-bit rotates; it is undefined in all other cases (except that a zero-bit rotate does nothing, that is affects no flags). For left rotates, the OF flag is set to the exclusive OR of the CF bit (after the rotate) and the most-significant bit of the result. For right rotates, the OF flag is set to the exclusive OR of the two most-significant bits of the result.

Operands Bytes Clocks
reg, 1 2 1 PU
mem, 1 2+d(0,2) 3 PU
reg, cl 2 7-24 NP
mem, cl 2+d(0,2) 9-26 NP
reg, imm 3 8-25 NP
mem, imm 3+d(0,2) 10-27 NP

Flags
The CF flag contains the value of the bit shifted into it. The OF flag is affected only for single-bit rotates (see "Description" above); it is undefined for multi-bit rotates. The SF, ZF, AF, and PF flags are not affected.


RCR - Rotate Bits Right with CF

Usage: RCR dest, count

Description
See RCLCW50O

Operands Bytes Clocks
reg, 1 2 1 PU
mem, 1 2+d(0,2) 3 PU
reg, cl 2 7-24 NP
mem, cl 2+d(0,2) 9-26 NP
reg, imm 3 8-25 NP
mem, imm 3+d(0,2) 10-27 NP


RDTSC - Read Time-Stamp Counter
0F 31 RDTSC Read time-stamp counter into EDX:EAX

Description
Loads the current value of the processor's time-stamp counter into the EDX:EAX registers. The time-stamp counter is contained in a 64-bit MSR. The high-order 32 bits of the MSR are loaded into the EDX register, and the low-order 32 bits are loaded into the EAX register. The processor increments the time-stamp counter MSR every clock cycle and resets it to 0 whenever the processor is reset.

The time stamp disable (TSD) flag in register CR4 restricts the use of the RDTSC instruction. When the TSD flag is clear, the RDTSC instruction can be executed at any privilege level; when the flag is set, the instruction can only be executed at privilege level 0. The time-stamp counter can also be read with the RDMSR instruction, when executing at privilege level 0.

The RDTSC instruction is not a serializing instruction. Thus, it does not necessarily wait until all previous instructions have been executed before reading the counter. Similarly, subsequent instructions may begin execution before the read operation is performed.

This instruction was introduced into the Intel Architecture in the Pentium processor.

Operands Bytes Clocks
2 6-7 NP

Flags
None.


REP/REPE/REPZ/REPNE/REPNZ - Repe

REP/REPE/REPZ/REPNE/REPNZ - Repeat String Operation Prefix
F3 6C REP INS r/m8, DX Input (E)CX bytes from port DX into ES:[(E)DI]
F3 6D REP INS r/m16,DX Input (E)CX words from port DX into ES:[(E)DI]
F3 6D REP INS r/m32,DX Input (E)CX doublewords from port DX into ES:[(E)DI]
F3 A4 REP MOVS m8,m8 Move (E)CX bytes from DS:[(E)SI] to ES:[(E)DI]
F3 A5 REP MOVS m16,m16 Move (E)CX words from DS:[(E)SI] to ES:[(E)DI]
F3 A5 REP MOVS m32,m32 Move (E)CX doublewords from DS:[(E)SI] to ES:[(E)DI]
F3 6E REP OUTS DX, r/m8 Output (E)CX bytes from DS:[(E)SI] to port DX
F3 6F REP OUTS DX, r/m16 Output (E)CX words from DS:[(E)SI] to port DX
F3 6F REP OUTS DX, r/m32 Output (E)CX doublewords from DS:[(E)SI] to port DX
F3 AC REP LODS AL Load (E)CX bytes from DS:[(E)SI] to AL
F3 AD REP LODS AX Load (E)CX words from DS:[(E)SI] to AX
F3 AD REP LODS EAX Load (E)CX doublewords from DS:[(E)SI] to EAX
F3 AA REP STOS m8 Fill (E)CX bytes at ES:[(E)DI] with AL
F3 AB REP STOS m16 Fill (E)CX words at ES:[(E)DI] with AX
F3 AB REP STOS m32 Fill (E)CX doublewords at ES:[(E)DI] with EAX
F3 A6 REPE CMPS m8,m8 Find nonmatching bytes in ES:[(E)DI] and DS:[(E)SI]
F3 A7 REPE CMPS m16,m16 Find nonmatching words in ES:[(E)DI] and DS:[(E)SI]
F3 A7 REPE CMPS m32,m32 Find nonmatching doublewords in ES:[(E)DI] and DS:[(E)SI]
F3 AE REPE SCAS m8 Find non-AL byte starting at ES:[(E)DI]
F3 AF REPE SCAS m16 Find non-AX word starting at ES:[(E)DI]
F3 AF REPE SCAS m32 Find non-EAX doubleword starting at ES:[(E)DI]
F2 A6 REPNE CMPS m8,m8 Find matching bytes in ES:[(E)DI] and DS:[(E)SI]
F2 A7 REPNE CMPS m16,m16 Find matching words in ES:[(E)DI] and DS:[(E)SI]
F2 A7 REPNE CMPS m32,m32 Find matching doublewords in ES:[(E)DI] and DS:[(E)SI]
F2 AE REPNE SCAS m8 Find AL, starting at ES:[(E)DI]
F2 AF REPNE SCAS m16 Find AX, starting at ES:[(E)DI]
F2 AF REPNE SCAS m32 Find EAX, starting at ES:[(E)DI]

Description
Repeats a string instruction the number of times specified in the count register ((E)CX) or until the indicated condition of the ZF flag is no longer met. The REP (repeat), REPE (repeat while equal), REPNE (repeat while not equal), REPZ (repeat while zero), and REPNZ (repeat while not zero) mnemonics are prefixes that can be added to one of the string instructions. The REP prefix can be added to the INS, OUTS, MOVS, LODS, and STOS instructions, and the REPE, REPNE, REPZ, and REPNZ prefixes can be added to the CMPS and SCAS instructions. (The REPZ and REPNZ prefixes are synonymous forms of the REPE and REPNE prefixes, respectively.) The behavior of the REP prefix is undefined when used with non-string instructions.

The REP prefixes apply only to one string instruction at a time. To repeat a block of instructions, use the LOOP instruction or another looping construct.

All of these repeat prefixes cause the associated instruction to be repeated until the count in register (E)CX is decremented to 0 (see the following table). (If the current address-size attribute is 32, register ECX is used as a counter, and if the address-size attribute is 16, the CX register is used.) The REPE, REPNE, REPZ, and REPNZ prefixes also check the state of the ZF flag after each iteration and terminate the repeat loop if the ZF flag is not in the specified state. When both termination conditions are tested, the cause of a repeat termination can be determined either by testing the (E)CX register with a JECXZ instruction or by testing the ZF flag with a JZ, JNZ, and JNE instruction.

Repeat Prefix Termination Condition 1 Termination Condition 2
REP ECX=0 None
REPE/REPZ ECX=0 ZF=0
REPNE/REPNZ ECX=0 ZF=1

When the REPE/REPZ and REPNE/REPNZ prefixes are used, the ZF flag does not require initialization because both the CMPS and SCAS instructions affect the ZF flag according to the results of the comparisons they make.

A repeating string operation can be suspended by an exception or interrupt. When this happens, the state of the registers is preserved to allow the string operation to be resumed upon a return from the exception or interrupt handler. The source and destination registers point to the next string elements to be operated on, the EIP register points to the string instruction, and the ECX register has the value it held following the last successful iteration of the instruction. This mechanism allows long string operations to proceed without affecting the interrupt response time of the system.

When a fault occurs during the execution of a CMPS or SCAS instruction that is prefixed with REPE or REPNE, the EFLAGS value is restored to the state prior to the execution of the instruction. Since the SCAS and CMPS instructions do not use EFLAGS as an input, the processor can resume the instruction after the page fault handler.

Use the REP INS and REP OUTS instructions with caution. Not all I/O ports can handle the rate at which these instructions execute.

A REP STOS instruction is the fastest way to initialize a large block of memory.

Operands Bytes Clocks
See MOVSMM82V4 (rep movs) move block
See STOSCVX0O0 (rep stos) fill block
See CMPSCVYBO (repe cmps) find non-matching memory items
See CMPSCVYBO (repe scas) find non-acc matching byte in memory

Flags
None; however, the CMPS and SCAS instructions do set the status flags in the EFLAGS register.


RET - Return from Procedure C3 R

RET - Return from Procedure
C3 RET Near return to calling procedure
CB RET Far return to calling procedure
C2 iw RET imm16 Near return to calling procedure and pop imm16 bytes
from stack
CA iw RET imm16 Far return to calling procedure and pop imm16 bytes from
stack

Description
Transfers program control to a return address located on the top of the stack. The address is usually placed on the stack by a CALL instruction, and the return is made to the instruction that follows the CALL instruction.

The optional source operand specifies the number of stack bytes to be released after the return address is popped; the default is none. This operand can be used to release parameters from the stack that were passed to the called procedure and are no longer needed. It must be used when the CALL instruction used to switch to a new procedure uses a call gate with a non-zero word count to access the new procedure. Here, the source operand for the RET instruction must specify the same number of bytes as is specified in the word count field of the call gate.

The RET instruction can be used to execute three different types of returns:

· Near return-A return to a calling procedure within the current code segment (the segment currently pointed to by the CS register), sometimes referred to as an intrasegment return.
· Far return-A return to a calling procedure located in a different segment than the current code segment, sometimes referred to as an intersegment return.
· Inter-privilege-level far return-A far return to a different privilege level than that of the currently executing program or procedure.

The inter-privilege-level return type can only be executed in protected mode. See the section titled "Calling Procedures Using Call and RET" in Chapter 4 of the Intel Architecture Software Developer's Manual, Volume 1, for detailed information on near, far, and inter-privilege-level returns.

When executing a near return, the processor pops the return instruction pointer (offset) from the top of the stack into the EIP register and begins program execution at the new instruction pointer. The CS register is unchanged.

When executing a far return, the processor pops the return instruction pointer from the top of the stack into the EIP register, then pops the segment selector from the top of the stack into the CS register. The processor then begins program execution in the new code segment at the new instruction pointer.

The mechanics of an inter-privilege-level far return are similar to an intersegment return, except that the processor examines the privilege levels and access rights of the code and stack segments being returned to determine if the control transfer is allowed to be made. The DS, ES, FS, and GS segment registers are cleared by the RET instruction during an inter-privilege-level return if they refer to segments that are not allowed to be accessed at the new privilege level. Since a stack switch also occurs on an inter-privilege level return, the ESP and SS registers are loaded from the stack.

If parameters are passed to the called procedure during an inter-privilege level call, the optional source operand must be used with the RET instruction to release the parameters on the return. Here, the parameters are released both from the called procedure's stack and the calling procedure's stack (that is, the stack being returned to).

Varations Bytes Clocks
retn 1 2 NP
retn imm16 1+d(2) 3 NP
retf 1 4 NP
retf imm16 1+d(2) 4 NP

Flags
None.


ROL - Rotate Bits Left Usage

ROL - Rotate Bits Left

Usage: ROL dest, count

Description
See RCLCW50O

Operands Bytes Clocks
reg, 1 2 1 PU
mem, 1 2+d(0,2) 3 PU
reg, cl 2 4 NP
mem, cl 2+d(0,2) 4 NP
reg, imm 3 1 PU
mem, imm 3+d(0,2) 3 PU*

* = not pairable if there is a displacement and immediate


RSM - Resume from System Managem

RSM - Resume from System Management Mode
0F AA RSM Resume operation of interrupted program

Description
Returns program control from system management mode (SMM) to the application program or operating-system procedure that was interrupted when the processor received an SSM interrupt. The processor's state is restored from the dump created upon entering SMM. If the processor detects invalid state information during state restoration, it enters the shutdown state. The following invalid information can cause a shutdown:

· Any reserved bit of CR4 is set to 1.
· Any illegal combination of bits in CR0, such as (PG=1 and PE=0) or (NW=1 and CD=0).
· (Intel Pentium ® and Intel486™ processors only.) The value stored in the state dump base field is not a 32-KByte aligned address.

The contents of the model-specific registers are not affected by a return from SMM.

See Chapter 11, System Management Mode (SMM), in the Intel Architecture Software Developer's Manual, Volume 3, for more information about SMM and the behavior of the RSM instruction.

Operands Bytes Clocks
2 83 NP

Flags
All.


SAHF - Store AH into Flags 9E SA

SAHF - Store AH into Flags
9E SAHF Loads SF, ZF, AF, PF, and CF from AH into
EFLAGS register

Description
Loads the SF, ZF, AF, PF, and CF flags of the EFLAGS register with values from the corresponding bits in the AH register (bits 7, 6, 4, 2, and 0, respectively). Bits 1, 3, and 5 of register AH are ignored; the corresponding reserved bits (1, 3, and 5) in the EFLAGS register remain as shown in the "Operation" section below.

Operands Bytes Clocks
1 2 NP

Flags
The SF, ZF, AF, PF, and CF flags are loaded with values from the AH register. Bits 1, 3, and 5 of the EFLAGS register are unaffected, with the values remaining 1, 0, and 0, respectively.


SAL - Shift Arithmetic Left D0 /

SAL - Shift Arithmetic Left
D0 /4 SAL r/m8,1 Multiply r/m8 by 2, once
D2 /4 SAL r/m8,CL Multiply r/m8 by 2, CL times
C0 /4 ib SAL r/m8,imm8 Multiply r/m8 by 2, imm8 times
D1 /4 SAL r/m16,1 Multiply r/m16 by 2, once
D3 /4 SAL r/m16,CL Multiply r/m16 by 2, CL times
C1 /4 ib SAL r/m16,imm8 Multiply r/m16 by 2, imm8 times
D1 /4 SAL r/m32,1 Multiply r/m32 by 2, once
D3 /4 SAL r/m32,CL Multiply r/m32 by 2, CL times
C1 /4 ib SAL r/m32,imm8 Multiply r/m32 by 2, imm8 times
D0 /7 SAR r/m8,1 Signed divide* r/m8 by 2, once
D2 /7 SAR r/m8,CL Signed divide* r/m8 by 2, CL times
C0 /7 ib SAR r/m8,imm8 Signed divide* r/m8 by 2, imm8 times
D1 /7 SAR r/m16,1 Signed divide* r/m16 by 2, once
D3 /7 SAR r/m16,CL Signed divide* r/m16 by 2, CL times
C1 /7 ib SAR r/m16,imm8 Signed divide* r/m16 by 2, imm8 times
D1 /7 SAR r/m32,1 Signed divide* r/m32 by 2, once
D3 /7 SAR r/m32,CL Signed divide* r/m32 by 2, CL times
C1 /7 ib SAR r/m32,imm8 Signed divide* r/m32 by 2, imm8 times
D0 /4 SHL r/m8,1 Multiply r/m8 by 2, once
D2 /4 SHL r/m8,CL Multiply r/m8 by 2, CL times
C0 /4 ib SHL r/m8,imm8 Multiply r/m8 by 2, imm8 times
D1 /4 SHL r/m16,1 Multiply r/m16 by 2, once
D3 /4 SHL r/m16,CL Multiply r/m16 by 2, CL times
C1 /4 ib SHL r/m16,imm8 Multiply r/m16 by 2, imm8 times
D1 /4 SHL r/m32,1 Multiply r/m32 by 2, once
D3 /4 SHL r/m32,CL Multiply r/m32 by 2, CL times
C1 /4 ib SHL r/m32,imm8 Multiply r/m32 by 2, imm8 times
D0 /5 SHR r/m8,1 Unsigned divide r/m8 by 2, once
D2 /5 SHR r/m8,CL Unsigned divide r/m8 by 2, CL times
C0 /5 ib SHR r/m8,imm8 Unsigned divide r/m8 by 2, imm8 times
D1 /5 SHR r/m16,1 Unsigned divide r/m16 by 2, once
D3 /5 SHR r/m16,CL Unsigned divide r/m16 by 2, CL times
C1 /5 ib SHR r/m16,imm8 Unsigned divide r/m16 by 2, imm8 times
D1 /5 SHR r/m32,1 Unsigned divide r/m32 by 2, once
D3 /5 SHR r/m32,CL Unsigned divide r/m32 by 2, CL times
C1 /5 ib SHR r/m32,imm8 Unsigned divide r/m32 by 2, imm8 times

Description
Shifts the bits in the first operand (destination operand) to the left or right by the number of bits specified in the second operand (count operand). Bits shifted beyond the destination operand boundary are first shifted into the CF flag, then discarded. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.

The destination operand can be a register or a memory location. The count operand can be an immediate value or register CL. The count is masked to 5 bits, which limits the count range to 0 to 31. A special opcode encoding is provided for a count of 1.

The shift arithmetic left (SAL) and shift logical left (SHL) instructions perform the same operation; they shift the bits in the destination operand to the left (toward more significant bit loca-tions). For each shift count, the most significant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared (see Figure 6-6 in the Intel Architecture Software Developer's Manual, Volume 1).

The shift arithmetic right (SAR) and shift logical right (SHR) instructions shift the bits of the destination operand to the right (toward less significant bit locations). For each shift count, the least significant bit of the destination operand is shifted into the CF flag, and the most significant bit is either set or cleared depending on the instruction type. The SHR instruction clears the most significant bit (see Figure 6-7 in the Intel Architecture Software Developer's Manual, Volume 1); the SAR instruction sets or clears the most significant bit to correspond to the sign (most signif-icant bit) of the original value in the destination operand. In effect, the SAR instruction fills the empty bit position's shifted value with the sign of the unshifted value (see Figure 6-8 in the Intel Architecture Software Developer's Manual, Volume 1).

The SAR and SHR instructions can be used to perform signed or unsigned division, respectively, of the destination operand by powers of 2. For example, using the SAR instruction to shift a signed integer 1 bit to the right divides the value by 2.

Using the SAR instruction to perform a division operation does not produce the same result as the IDIV instruction. The quotient from the IDIV instruction is rounded toward zero, whereas the "quotient" of the SAR instruction is rounded toward negative infinity. This difference is apparent only for negative numbers. For example, when the IDIV instruction is used to divide -9 by 4, the result is -2 with a remainder of -1. If the SAR instruction is used to shift -9 right by two bits, the result is -3 and the "remainder" is +3; however, the SAR instruction stores only the most significant bit of the remainder (in the CF flag).

The OF flag is affected only on 1-bit shifts. For left shifts, the OF flag is cleared to 0 if the most-significant bit of the result is the same as the CF flag (that is, the top two bits of the original operand were the same); otherwise, it is set to 1. For the SAR instruction, the OF flag is cleared for all 1-bit shifts. For the SHR instruction, the OF flag is set to the most-significant bit of the original operand.

Operands Bytes Clocks
reg, 1 2 1 PU
mem, 1 2+d(0,2) 3 PU
reg, cl 2 4 NP
mem, cl 2+d(0,2) 4 NP
reg, imm 3 1 PU
mem, imm 3+d(0,2) 3 PU*

* = not pairable if there is a displacement and immediate

sal = shift arithmetic left sar = shift arithmetic right
shl = shift left (same as sal) shr = shift right

Flags
The CF flag contains the value of the last bit shifted out of the destination operand; it is undefined for SHL and SHR instructions where the count is greater than or equal to the size (in bits) of the destination operand. The OF flag is affected only for 1-bit shifts (see "Description" above); otherwise, it is undefined. The SF, ZF, and PF flags are set according to the result. If the count is 0, the flags are not affected. For a non-zero count, the AF flag is undefined.


SAR - Shift Arithmetic Right Se

SAR - Shift Arithmetic Right

See SALMM84X4


SBB - Integer Subtraction with B

SBB - Integer Subtraction with Borrow
1C ib SBB AL, imm8 Subtract with borrow imm8 from AL
1D iw SBB AX, imm16 Subtract with borrow imm16 from AX
1D id SBB EAX, imm32 Subtract with borrow imm32 from EAX
80 /3 ib SBB r/m8,imm8 Subtract with borrow imm8 from r/m8
81 /3 iw SBB r/m16,imm16 Subtract with borrow imm16 from r/m16
81 /3 id SBB r/m32,imm32 Subtract with borrow imm32 from r/m32
83 /3 ib SBB r/m16,imm8 Subtract with borrow sign-extended imm8 from r/m16
83 /3 ib SBB r/m32,imm8 Subtract with borrow sign-extended imm8 from r/m32
18 / r SBB r/m8,r8 Subtract with borrow r8 from r/m8
19 / r SBB r/m16,r16 Subtract with borrow r16 from r/m16
19 / r SBB r/m32,r32 Subtract with borrow r32 from r/m32
1A / r SBB r8,r/m8 Subtract with borrow r/m8 from r8
1B / r SBB r16,r/m16 Subtract with borrow r/m16 from r16
1B / r SBB r32,r/m32 Subtract with borrow r/m32 from r32

Description
Adds the source operand (second operand) and the carry (CF) flag, and subtracts the result from the destination operand (first operand). The result of the subtraction is stored in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) The state of the CF flag represents a borrow from a previous subtraction.

When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.

The SBB instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates the result for both data types and sets the OF and CF flags to indicate a borrow in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result.

The SBB instruction is usually executed as part of a multibyte or multiword subtraction in which a SUB instruction is followed by a SBB instruction.

Operands Bytes Clocks
reg, reg 2 1 PU
mem, reg 2+d(0,2) 3 PU
reg, mem 2+d(0,2) 2 PU
reg, imm 2+i(1,2) 1 PU
mem, imm 2+d(0,2)+i(1,2) 3 PU*
acc, imm 1+i(1,2) 1 PU

* = not pairable if there is a displacement and immediate

Flags
The OF, SF, ZF, AF, PF, and CF flags are set according to the result.


SCAS/SCASB/SCASW/SCASD - Scan St

SCAS/SCASB/SCASW/SCASD - Scan String
AE SCAS m8 Compare AL with byte at ES:(E)DI and set status flags
AF SCAS m16 Compare AX with word at ES:(E)DI and set status flags
AF SCAS m32 Compare EAX with doubleword at ES(E)DI and set status flags
AE SCASB Compare AL with byte at ES:(E)DI and set status flags
AF SCASW Compare AX with word at ES:(E)DI and set status flags
AF SCASD Compare EAX with doubleword at ES:(E)DI and set status flags

Description
Compares the byte, word, or double word specified with the memory operand with the value in the AL, AX, or EAX register, and sets the status flags in the EFLAGS register according to the results. The memory operand address is read from either the ES:EDI or the ES:DI registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). The ES segment cannot be overridden with a segment override prefix.

At the assembly-code level, two forms of this instruction are allowed: the "explicit-operands" form and the "no-operands" form. The explicit-operand form (specified with the SCAS mnemonic) allows the memory operand to be specified explicitly. Here, the memory operand should be a symbol that indicates the size and location of the operand value. The register operand is then automatically selected to match the size of the memory operand (the AL register for byte comparisons, AX for word comparisons, and EAX for doubleword comparisons). This explicit-operand form is provided to allow documentation; however, note that the documentation provided by this form can be misleading. That is, the memory operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does not have to specify the correct location. The location is always specified by the ES:(E)DI registers, which must be loaded correctly before the compare string instruction is executed.

The no-operands form provides "short forms" of the byte, word, and doubleword versions of the SCAS instructions. Here also ES:(E)DI is assumed to be the memory operand and the AL, AX, or EAX register is assumed to be the register operand. The size of the two operands is selected with the mnemonic: SCASB (byte comparison), SCASW (word comparison), or SCASD (doubleword comparison).

After the comparison, the (E)DI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)DI register is incremented; if the DF flag is 1, the (E)DI register is decremented.) The (E)DI register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for double-word operations.

The SCAS, SCASB, SCASW, and SCASD instructions can be preceded by the REP prefix for block comparisons of ECX bytes, words, or doublewords. More often, however, these instructions will be used in a LOOP construct that takes some action based on the setting of the status flags before the next comparison is made. See "REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix" in this chapter for a description of the REP prefix.

Variations Bytes Clocks
scasb 1 4 NP
scasw 1 4 NP
scasd 1 4 NP
repX scasb 2 8+4n NP
repX scasw 2 8+4n NP
repX scasd 2 8+4n NP

repX = repe or repz or repne or repnz
(n = count of bytes, words or dwords)

Flags
The OF, SF, ZF, AF, PF, and CF flags are set according to the temporary result of the comparison.


SETcc - Set Byte on Condition 0F

SETcc - Set Byte on Condition
0F 97 SETA r/m8 Set byte if above (CF=0 and ZF=0)
0F 93 SETAE r/m8 Set byte if above or equal (CF=0)
0F 92 SETB r/m8 Set byte if below (CF=1)
0F 96 SETBE r/m8 Set byte if below or equal (CF=1 or ZF=1)
0F 92 SETC r/m8 Set if carry (CF=1)
0F 94 SETE r/m8 Set byte if equal (ZF=1)
0F 9F SETG r/m8 Set byte if greater (ZF=0 and SF=OF)
0F 9D SETGE r/m8 Set byte if greater or equal (SF=OF)
0F 9C SETL r/m8 Set byte if less (SF<>OF)
0F 9E SETLE r/m8 Set byte if less or equal (ZF=1 or SF<>OF)
0F 96 SETNA r/m8 Set byte if not above (CF=1 or ZF=1)
0F 92 SETNAE r/m8 Set byte if not above or equal (CF=1)
0F 93 SETNB r/m8 Set byte if not below (CF=0)
0F 97 SETNBE r/m8 Set byte if not below or equal (CF=0 and ZF=0)
0F 93 SETNC r/m8 Set byte if not carry (CF=0)
0F 95 SETNE r/m8 Set byte if not equal (ZF=0)
0F 9E SETNG r/m8 Set byte if not greater (ZF=1 or SF<>OF)
0F 9C SETNGE r/m8 Set if not greater or equal (SF<>OF)
0F 9D SETNL r/m8 Set byte if not less (SF=OF)
0F 9F SETNLE r/m8 Set byte if not less or equal (ZF=0 and SF=OF)
0F 91 SETNO r/m8 Set byte if not overflow (OF=0)
0F 9B SETNP r/m8 Set byte if not parity (PF=0)
0F 99 SETNS r/m8 Set byte if not sign (SF=0)
0F 95 SETNZ r/m8 Set byte if not zero (ZF=0)
0F 90 SETO r/m8 Set byte if overflow (OF=1)
0F 9A SETP r/m8 Set byte if parity (PF=1)
0F 9A SETPE r/m8 Set byte if parity even (PF=1)
0F 9B SETPO r/m8 Set byte if parity odd (PF=0)
0F 98 SETS r/m8 Set byte if sign (SF=1)
0F 94 SETZ r/m8 Set byte if zero (ZF=1)

Description
Set the destination operand to 0 or 1 depending on the settings of the status flags (CF, SF, OF, ZF, and PF) in the EFLAGS register. The destination operand points to a byte register or a byte in memory. The condition code suffix (cc) indicates the condition being tested for.

The terms "above" and "below" are associated with the CF flag and refer to the relationship between two unsigned integer values. The terms "greater" and "less" are associated with the SF and OF flags and refer to the relationship between two signed integer values.

Many of the SETcc instruction opcodes have alternate mnemonics. For example, the SETG (set byte if greater) and SETNLE (set if not less or equal) both have the same opcode and test for the same condition: ZF equals 0 and SF equals OF. These alternate mnemonics are provided to make code more intelligible. Appendix B, EFLAGS Condition Codes, in the Intel Architecture Software Developer's Manual, Volume 1, shows the alternate mnemonics for various test conditions.

Some languages represent a logical one as an integer with all bits set. This representation can be obtained by choosing the logically opposite condition for the SETcc instruction, then decrementing the result. For example, to test for overflow, use the SETNO instruction, then decrement the result.

Operands Bytes Clocks
r8 3 1/2 NP
mem8 3+d(0-2) 1/2 NP

Cycles are for: true/false

setCC = one of:
seta setae setb setbe setc sete
setg setge setl setle setna setnae
setnb setnbe setnc setne setng setnge
setnl setnle setno setnp setns setnz
seto setp setpe setpo sets setz

Flags
None.


SGDT/SIDT - Store Global/Interru

SGDT/SIDT - Store Global/Interrupt Descriptor Table Register
0F 01 /0 SGDT m Store GDTR to m
0F 01 /1 SIDT m Store IDTR to m

Description
Stores the contents of the global descriptor table register (GDTR) or the interrupt descriptor table register (IDTR) in the destination operand. The destination operand specifies a 6-byte memory location. If the operand-size attribute is 32 bits, the 16-bit limit field of the register is stored in the lower 2 bytes of the memory location and the 32-bit base address is stored in the upper 4 bytes. If the operand-size attribute is 16 bits, the limit is stored in the lower 2 bytes and the 24-bit base address is stored in the third, fourth, and fifth byte, with the sixth byte filled with 0s.

The SGDT and SIDT instructions are only useful in operating-system software; however, they can be used in application programs without causing an exception to be generated.

See "LGDT/LIDT-Load Global/Interrupt Descriptor Table Register" in this chapter for information on loading the GDTR and IDTR.

Operands Bytes Clocks
mem48 5 4 NP

Flags
None.


SHL - Shift Left See SALMM84X4

SHL - Shift Left

See SALMM84X4


SHLD - Double Precision Shift Le

SHLD - Double Precision Shift Left
0F A4 SHLD r/m16,r16,imm8 Shift r/m16 to left imm8 places while shifting bits from r16
in from the right
0F A5 SHLD r/m16,r16,CL Shift r/m16 to left CL places while shifting bits from r16 in
from the right
0F A4 SHLD r/m32,r32,imm8 Shift r/m32 to left imm8 places while shifting bits from r32
in from the right
0F A5 SHLD r/m32,r32,CL Shift r/m32 to left CL places while shifting bits from r32 in
from the right

Description
Shifts the first operand (destination operand) to the left the number of bits specified by the third operand (count operand). The second operand (source operand) provides bits to shift in from the right (starting with bit 0 of the destination operand). The destination operand can be a register or a memory location; the source operand is a register. The count operand is an unsigned integer that can be an immediate byte or the contents of the CL register. Only bits 0 through 4 of the count are used, which masks the count to a value between 0 and 31. If the count is greater than the operand size, the result in the destination operand is undefined.

If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. If the count operand is 0, the flags are not affected.

The SHLD instruction is useful for multiprecision shifts of 64 bits or more.

Operands Bytes Clocks
reg, reg, imm 4 4 NP
mem, reg, imm 4+d(0-2) 4 NP
reg, reg, cl 4 4 NP
mem, reg, cl 4+d(0-2) 5 NP

Flags
If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand and the SF, ZF, and PF flags are set according to the value of the result. For a 1-bit shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. For shifts greater than 1 bit, the OF flag is undefined. If a shift occurs, the AF flag is undefined. If the count operand is 0, the flags are not affected. If the count is greater than the operand size, the flags are undefined.

SHRD - Double Precision Shift Right
0F AC SHRD r/m16,r16,imm8 Shift r/m16 to right imm8 places while shifting bits from
r16 in from the left
0F AD SHRD r/m16,r16,CL Shift r/m16 to right CL places while shifting bits from r16
in from the left
0F AC SHRD r/m32,r32,imm8 Shift r/m32 to right imm8 places while shifting bits from
r32 in from the left
0F AD SHRD r/m32,r32,CL Shift r/m32 to right CL places while shifting bits from r32
in from the left

Description
Shifts the first operand (destination operand) to the right the number of bits specified by the third operand (count operand). The second operand (source operand) provides bits to shift in from the left (starting with the most significant bit of the destination operand). The destination operand can be a register or a memory location; the source operand is a register. The count operand is an unsigned integer that can be an immediate byte or the contents of the CL register. Only bits 0 through 4 of the count are used, which masks the count to a value between 0 and 31. If the count is greater than the operand size, the result in the destination operand is undefined.

If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. If the count operand is 0, the flags are not affected.

The SHRD instruction is useful for multiprecision shifts of 64 bits or more.

Operands Bytes Clocks
reg, reg, imm 4 4 NP
mem, reg, imm 4+d(0-2) 4 NP
reg, reg, cl 4 4 NP
mem, reg, cl 4+d(0-2) 5 NP

Flags
If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand and the SF, ZF, and PF flags are set according to the value of the result. For a 1-bit shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. For shifts greater than 1 bit, the OF flag is undefined. If a shift occurs, the AF flag is undefined. If the count operand is 0, the flags are not affected. If the count is greater than the operand size, the flags are undefined.

SIDT - Store Interrupt Descriptor Table Register

See SGDT/SIDTCVXCF0


SLDT - Store Local Descriptor Ta

SLDT - Store Local Descriptor Table Register
0F 00 /0 SLDT r/m16 Stores segment selector from LDTR in r/m16
0F 00 /0 SLDT r/m32 Store segment selector from LDTR in low-order 16 bits of
r/m32

Description
Stores the segment selector from the local descriptor table register (LDTR) in the destination operand. The destination operand can be a general-purpose register or a memory location. The segment selector stored with this instruction points to the segment descriptor (located in the GDT) for the current LDT. This instruction can only be executed in protected mode.

When the destination operand is a 32-bit register, the 16-bit segment selector is copied into the lower-order 16 bits of the register. The high-order 16 bits of the register are cleared to 0s for the Pentium Pro processor and are undefined for Pentium, Intel486, and Intel386 processors. When the destination operand is a memory location, the segment selector is written to memory as a 16-bit quantity, regardless of the operand size.

The SLDT instruction is only useful in operating-system software; however, it can be used in application programs.

Operands Bytes Clocks
r16 3 2 NP
mem16 3+d(0-2) 2 NP

Flags
None.


SMSW - Store Machine Status Word
0F 01 /4 SMSW r/m16 Store machine status word to r/m16
0F 01 /4 SMSW r32/m16 Store machine status word in low-order 16 bits of r32/m16;
high-order 16 bits of r32 are undefined

Description
Stores the machine status word (bits 0 through 15 of control register CR0) into the destination operand. The destination operand can be a 16-bit general-purpose register or a memory location.

When the destination operand is a 32-bit register, the low-order 16 bits of register CR0 are copied into the low-order 16 bits of the register and the upper 16 bits of the register are undefined. When the destination operand is a memory location, the low-order 16 bits of register CR0 are written to memory as a 16-bit quantity, regardless of the operand size.

The SMSW instruction is only useful in operating-system software; however, it is not a privileged instruction and can be used in application programs.

This instruction is provided for compatibility with the Intel 286 processor. Programs and procedures intended to run on the Pentium Pro, Pentium, Intel486, and Intel386 processors should use the MOV (control registers) instruction to load the machine status word.

Operands Bytes Clocks
r16 3 4 NP
mem16 3+d(0-2) 4 NP

Flags
None.


STC - Set Carry Flag F9 STC Set

STC - Set Carry Flag
F9 STC Set CF flag

Description
Sets the CF flag in the EFLAGS register.

Operands Bytes Clocks
 1 2 NP

Flags
The CF flag is set. The OF, ZF, SF, AF, and PF flags are unaffected.


STD - Set Direction Flag FD STD

STD - Set Direction Flag
FD STD Set DF flag

Description
Sets the DF flag in the EFLAGS register. When the DF flag is set to 1, string operations decrement the index registers (ESI and/or EDI).

Operands Bytes Clocks
1 2 NP

Flags
The DF flag is set. The CF, OF, ZF, SF, AF, and PF flags are unaffected.


STI - Set Interrupt Flag FB STI

STI - Set Interrupt Flag
FB STI Set interrupt flag; external, maskable interrupts enabled
at the end of the next instruction

Description
Sets the interrupt flag (IF) in the EFLAGS register. After the IF flag is set, the processor begins responding to external, maskable interrupts after the next instruction is executed. The delayed effect of this instruction is provided to allow interrupts to be enabled just before returning from a procedure (or subroutine). For instance, if an STI instruction is followed by an RET instruction, the RET instruction is allowed to execute before external interrupts are recognized 1 . This behavior allows external interrupts to be disabled at the beginning of a procedure and enabled again at the end of the procedure. If the STI instruction is followed by a CLI instruction (which clears the IF flag), the effect of the STI instruction is negated.

The IF flag and the STI and CLI instructions have no affect on the generation of exceptions and NMI interrupts.

The following decision table indicates the action of the STI instruction (bottom of the table) depending on the processor's mode of operation and the CPL and IOPL of the currently running program or procedure (top of the table).

PE = 0 1 1 1
VM = X 0 0 1
CPL X £ IOPL > IOPL =3
IOPL X X X =3
IF ¬ 1 Y Y N Y
#GP(0) N N Y N
NOTES:
X Don't care.
N Action in Column 1 not taken.
Y Action in Column 1 taken.

Operands Bytes Clocks
1 7 NP

Flags
The IF flag is set to 1.


STOS/STOSB/STOSW/STOSD - Store S

STOS/STOSB/STOSW/STOSD - Store String
AA STOS m8 Store AL at address ES:(E)DI
AB STOS m16 Store AX at address ES:(E)DI
AB STOS m32 Store EAX at address ES:(E)DI
AA STOSB Store AL at address ES:(E)DI
AB STOSW Store AX at address ES:(E)DI
AB STOSD Store EAX at address ES:(E)DI

Description
Stores a byte, word, or doubleword from the AL, AX, or EAX register, respectively, into the destination operand. The destination operand is a memory location, the address of which is read from either the ES:EDI or the ES:DI registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). The ES segment cannot be overridden with a segment override prefix.

At the assembly-code level, two forms of this instruction are allowed: the "explicit-operands" form and the "no-operands" form. The explicit-operands form (specified with the STOS mnemonic) allows the destination operand to be specified explicitly. Here, the destination operand should be a symbol that indicates the size and location of the destination value. The source operand is then automatically selected to match the size of the destination operand (the AL register for byte operands, AX for word operands, and EAX for doubleword operands). This explicit-operands form is provided to allow documentation; however, note that the documentation provided by this form can be misleading. That is, the destination operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does not have to specify the correct location. The location is always specified by the ES:(E)DI registers, which must be loaded correctly before the store string instruction is executed.

The no-operands form provides "short forms" of the byte, word, and doubleword versions of the STOS instructions. Here also ES:(E)DI is assumed to be the destination operand and the AL, AX, or EAX register is assumed to be the source operand. The size of the destination and source operands is selected with the mnemonic: STOSB (byte read from register AL), STOSW (word from AX), or STOSD (doubleword from EAX).

After the byte, word, or doubleword is transferred from the AL, AX, or EAX register to the memory location, the (E)DI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)DI register is incremented; if the DF flag is 1, the (E)DI register is decremented.) The (E)DI register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword operations.

The STOS, STOSB, STOSW, and STOSD instructions can be preceded by the REP prefix for block loads of ECX bytes, words, or doublewords. More often, however, these instructions are used within a LOOP construct because data needs to be moved into the AL, AX, or EAX register before it can be stored. See "REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix" in this chapter for a description of the REP prefix.

Variations Bytes Clocks
stosb 1 3 NP
stosw 1 3 NP
stosd 1 3 NP
rep stosb 2 3+n NP
rep stosw 2 3+n NP
rep stosd 2 3+n NP
(n = count of bytes, words or dwords)

Flags
None.


STR - Store Task Register 0F 00

STR - Store Task Register
0F 00 /1 STR r/m16 Stores segment selector from TR in r/m16

Description
Stores the segment selector from the task register (TR) in the destination operand. The destination operand can be a general-purpose register or a memory location. The segment selector stored with this instruction points to the task state segment (TSS) for the currently running task.

When the destination operand is a 32-bit register, the 16-bit segment selector is copied into the lower 16 bits of the register and the upper 16 bits of the register are cleared to 0s. When the destination operand is a memory location, the segment selector is written to memory as a 16-bit quantity, regardless of operand size.

The STR instruction is useful only in operating-system software. It can only be executed in protected mode.

Operands Bytes Clocks
r16 3 2 NP
mem16 3+d(0-2) 2 NP

Flags
None.


SUB - Subtract 2C ib SUB AL

SUB - Subtract
2C ib SUB AL, imm8 Subtract imm8 from AL
2D iw SUB AX, imm16 Subtract imm16 from AX
2D id SUB EAX, imm32 Subtract imm32 from EAX
80 /5 ib SUB r/m8,imm8 Subtract imm8 from r/m8
81 /5 iw SUB r/m16,imm16 Subtract imm16 from r/m16
81 /5 id SUB r/m32,imm32 Subtract imm32 from r/m32
83 /5 ib SUB r/m16,imm8 Subtract sign-extended imm8 from r/m16
83 /5 ib SUB r/m32,imm8 Subtract sign-extended imm8 from r/m32
28 / r SUB r/m8,r8 Subtract r8 from r/m8
29 / r SUB r/m16,r16 Subtract r16 from r/m16
29 / r SUB r/m32,r32 Subtract r32 from r/m32
2A / r SUB r8,r/m8 Subtract r/m8 from r8
2B / r SUB r16,r/m16 Subtract r/m16 from r16
2B / r SUB r32,r/m32 Subtract r/m32 from r32

Description
Subtracts the second operand (source operand) from the first operand (destination operand) and stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, register, or memory location. (However, two memory operands cannot be used in one instruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.

The SUB instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates the result for both data types and sets the OF and CF flags to indicate a borrow in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result.

Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2+d(0,2) 3 UV
reg, mem 2+d(0,2) 2 UV
reg, imm 2+i(1,2) 1 UV
mem, imm 2+d(0,2)+i(1,2) 3 UV*
acc, imm 1+i(1,2) 1 UV

* = not pairable if there is a displacement and immediate

Flags
The OF, SF, ZF, AF, PF, and CF flags are set according to the result.

TEST - Logical Compare
A8 ib TEST AL, imm8 AND imm8 with AL; set SF, ZF, PF according to result
A9 iw TEST AX, imm16 AND imm16 with AX; set SF, ZF, PF according to result
A9 id TEST EAX, imm32 AND imm32 with EAX; set SF, ZF, PF according to result
F6 /0 ib TEST r/m8,imm8 AND imm8 with r/m8; set SF, ZF, PF according to result
F7 /0 iw TEST r/m16,imm16 AND imm16 with r/m16; set SF, ZF, PF according to result
F7 /0 id TEST r/m32,imm32 AND imm32 with r/m32; set SF, ZF, PF according to result
84 / r TEST r/m8,r8 AND r8 with r/m8; set SF, ZF, PF according to result
85 / r TEST r/m16,r16 AND r16 with r/m16; set SF, ZF, PF according to result
85 / r TEST r/m32,r32 AND r32 with r/m32; set SF, ZF, PF according to result

Description
Computes the bit-wise logical AND of first operand (source 1 operand) and the second operand (source 2 operand) and sets the SF, ZF, and PF status flags according to the result. The result is then discarded.

Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2+d(0,2) 2 UV
reg, mem 2+d(0,2) 2 UV
reg, imm 2+i(1,2) 1 UV
mem, imm 2+d(0,2)+i(1,2) 2 UV*
acc, imm 1+i(1,2) 1 UV

* = not pairable if there is a displacement and immediate

Flags
The OF and CF flags are cleared to 0. The SF, ZF, and PF flags are set according to the result (see the "Operation" section above). The state of the AF flag is undefined.


VERR/VERW - Verify a Segment for

VERR/VERW - Verify a Segment for Reading or Writing
0F 00 /4 VERR r/m16 Set ZF=1 if segment specified with r/m16 can be read
0F 00 /5 VERW r/m16 Set ZF=1 if segment specified with r/m16 can be written

Description
Verifies whether the code or data segment specified with the source operand is readable (VERR) or writable (VERW) from the current privilege level (CPL). The source operand is a 16-bit register or a memory location that contains the segment selector for the segment to be verified. If the segment is accessible and readable (VERR) or writable (VERW), the ZF flag is set; otherwise, the ZF flag is cleared. Code segments are never verified as writable. This check cannot be performed on system segments.

To set the ZF flag, the following conditions must be met:

· The segment selector is not null.
· The selector must denote a descriptor within the bounds of the descriptor table (GDT or LDT).
· The selector must denote the descriptor of a code or data segment (not that of a system segment or gate).
· For the VERR instruction, the segment must be readable.
· For the VERW instruction, the segment must be a writable data segment.
· If the segment is not a conforming code segment, the segment's DPL must be greater than or equal to (have less or the same privilege as) both the CPL and the segment selector's RPL.

The validation performed is the same as is performed when a segment selector is loaded into the DS, ES, FS, or GS register, and the indicated access (read or write) is performed. The segment selector's value cannot result in a protection exception, enabling the software to anticipate possible segment access problems.

Operands Bytes Clocks
r16 3 7 NP
mem16 3+d(0,2) 7 NP

Flags
The ZF flag is set to 1 if the segment is accessible and readable (VERR) or writable (VERW); otherwise, it is cleared to 0.


WAIT - Wait 9B WAIT Check pendin

WAIT - Wait
9B WAIT Check pending unmasked floating-point exceptions.
9B FWAIT Check pending unmasked floating-point exceptions.

Description
Causes the processor to check for and handle pending, unmasked, floating-point exceptions before proceeding. (FWAIT is an alternate mnemonic for the WAIT).

This instruction is useful for synchronizing exceptions in critical sections of code. Coding a WAIT instruction after a floating-point instruction insures that any unmasked floating-point exceptions the instruction may raise are handled before the processor can modify the instruction's results. See the section titled "Floating-Point Exception Synchronization" in Chapter 7 of the Intel Architecture Software Developer's Manual, Volume 1, for more information on using the WAIT/FWAIT instruction.

Operands Bytes Clocks
1 1 NP

FPU Flags
The C0, C1, C2, and C3 flags are undefined.


WBINVD - Write Back and Invalida

WBINVD - Write Back and Invalidate Cache
0F 09 WBINVD Write back and flush Internal caches; initiate writing-back
and flushing of external caches.

Description
Writes back all modified cache lines in the processor's internal cache to main memory and invalidates (flushes) the internal caches. The instruction then issues a special-function bus cycle that directs external caches to also write back modified data and another bus cycle to indicate that the external caches should be invalidated.

After executing this instruction, the processor does not wait for the external caches to complete their write-back and flushing operations before proceeding with instruction execution. It is the responsibility of hardware to respond to the cache write-back and flush signals.

The WDINVD instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a program or procedure must be 0 to execute this instruction. This instruction is also a serializing instruction (see "Serializing Instructions" in Chapter 7 of the Intel Architecture Software Developer's Manual, Volume 3).

In situations where cache coherency with main memory is not a concern, software can use the INVD instruction.

Operands Bytes Clocks
2 2000+ NP

Flags
None.


WRMSR - Write to Model Specific

WRMSR - Write to Model Specific Register
0F 30 WRMSR Write the value in EDX:EAX to MSR specified by ECX

Description
Writes the contents of registers EDX:EAX into the 64-bit model specific register (MSR) specified in the ECX register. The high-order 32 bits are copied from EDX and the low-order 32 bits are copied from EAX. Always set the undefined or reserved bits in an MSR to the values previously read.

This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) will be generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a general protection exception.

When the WRMSR instruction is used to write to an MTRR, the TLBs are invalidated, including the global entries (see "Translation Lookaside Buffers (TLBs)" in Chapter 3 of the Intel Architecture Software Developer's Manual, Volume 3). (MTRRs are an implementation-specific feature of the Pentium Pro processor.)

The MSRs control functions for testability, execution tracing, performance monitoring and machine check errors. Appendix B, Model-Specific Registers (MSRs), in the Intel Architecture Software Developer's Manual, Volume 3, lists all the MSRs that can be written to with this instruction and their addresses.

The WRMSR instruction is a serializing instruction (see "Serializing Instructions" in Chapter 7 of the Intel Architecture Software Developer's Manual, Volume 3).

The CPUID instruction should be used to determine whether MSRs are supported (EDX[5]=1) before using this instruction.

Operands Bytes Clocks
2 30-45 NP

Flags
None.


XADD - Exchange and Add 0F C0/r

XADD - Exchange and Add
0F C0/r XADD r/m8,r8 Exchange r8 and r/m8; load sum into r/m8.
0F C1/r XADD r/m16,r16 Exchange r16 and r/m16; load sum into r/m16.
0F C1/r XADD r/m32,r32 Exchange r32 and r/m32; load sum into r/m32.

Description
Exchanges the first operand (destination operand) with the second operand (source operand), then loads the sum of the two values into the destination operand. The destination operand can be a register or a memory location; the source operand is a register.

This instruction can be used with a LOCK prefix.

Operands Bytes Clocks
reg, reg 3 3 NP
mem, reg 3+d(0-2) 4 NP

Flags
The CF, PF, AF, SF, ZF, and OF flags are set according to the result of the addition, which is stored in the destination operand.


XCHG - Exchange Register/Memory

XCHG - Exchange Register/Memory with Register
90+ rw XCHG AX, r16 Exchange r16 with AX
90+ rw XCHG r16,AX Exchange AX with r16
90+ rd XCHG EAX, r32 Exchange r32 with EAX
90+ rd XCHG r32,EAX Exchange EAX with r32
86 / r XCHG r/m8,r8 Exchange r8 (byte register) with byte from r/m8
86 / r XCHG r8,r/m8 Exchange byte from r/m8 with r8 (byte register)
87 / r XCHG r/m16,r16 Exchange r16 with word from r/m16
87 / r XCHG r16,r/m16 Exchange word from r/m16 with r16
87 / r XCHG r/m32,r32 Exchange r32 with doubleword from r/m32
87 / r XCHG r32,r/m32 Exchange doubleword from r/m32 with r32

Description
Exchanges the contents of the destination (first) and source (second) operands. The operands can be two general-purpose registers or a register and a memory location. If a memory operand is referenced, the processor's locking protocol is automatically implemented for the duration of the exchange operation, regardless of the presence or absence of the LOCK prefix or of the value of the IOPL. (See the LOCK prefix description in this chapter for more information on the locking protocol.)

This instruction is useful for implementing semaphores or similar data structures for process synchronization. (See "Bus Locking" in Chapter 7 of the Intel Architecture Software Developer's Manual, Volume 3, for more information on bus locking.)

The XCHG instruction can also be used instead of the BSWAP instruction for 16-bit operands.

Operands Bytes Clocks
reg, reg 2 3 NP
reg, mem 2+d(0-2) 3 NP
mem, reg 2+d(0-2) 3 NP

acc, reg 1 2 NP
reg, acc 1 2 NP
in above: acc = AX or EAX only

Flags
None.


XLAT/XLATB - Table Look-up Trans

XLAT/XLATB - Table Look-up Translation
D7 XLAT m8 Set AL to memory byte DS:[(E)BX + unsigned AL]
D7 XLATB Set AL to memory byte DS:[(E)BX + unsigned AL]

Description
Locates a byte entry in a table in memory, using the contents of the AL register as a table index, then copies the contents of the table entry back into the AL register. The index in the AL register is treated as an unsigned integer. The XLAT and XLATB instructions get the base address of the table in memory from either the DS:EBX or the DS:BX registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). (The DS segment may be overridden with a segment override prefix.)

At the assembly-code level, two forms of this instruction are allowed: the "explicit-operand" form and the "no-operand" form. The explicit-operand form (specified with the XLAT mnemonic) allows the base address of the table to be specified explicitly with a symbol. This explicit-operands form is provided to allow documentation; however, note that the documentation provided by this form can be misleading. That is, the symbol does not have to specify the correct base address. The base address is always specified by the DS:(E)BX registers, which must be loaded correctly before the XLAT instruction is executed.

The no-operands form (XLATB) provides a "short form" of the XLAT instructions. Here also the processor assumes that the DS:(E)BX registers contain the base address of the table.

Operands Bytes Clocks
1 4 NP

Flags
None.


XOR - Logical Exclusive OR 34 ib

XOR - Logical Exclusive OR
34 ib XOR AL, imm8 AL XOR imm8
35 iw XOR AX, imm16 AX XOR imm16
35 id XOR EAX, imm32 EAX XOR imm32
80 /6 ib XOR r/m8,imm8 r/m8 XOR imm8
81 /6 iw XOR r/m16,imm16 r/m16 XOR imm16
81 /6 id XOR r/m32,imm32 r/m32 XOR imm32
83 /6 ib XOR r/m16,imm8 r/m16 XOR imm8 (sign-extended)
83 /6 ib XOR r/m32,imm8 r/m32 XOR imm8 (sign-extended)
30 / r XOR r/m8,r8 r/m8 XOR r8
31 / r XOR r/m16,r16 r/m16 XOR r16
31 / r XOR r/m32,r32 r/m32 XOR r32
32 / r XOR r8,r/m8 r8 XOR r/m8
33 / r XOR r16,r/m16 r8 XOR r/m8
33 / r XOR r32,r/m32 r8 XOR r/m8

Description
Performs a bitwise exclusive OR (XOR) operation on the destination (first) and source (second) operands and stores the result in the destination operand location. The source operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location. (However, two memory operands cannot be used in one instruction.) Each bit of the result is 1 if the corresponding bits of the operands are different; each bit is 0 if the corresponding bits are the same.

Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2+d(0,2) 3 UV
reg, mem 2+d(0,2) 2 UV
reg, imm 2+i(1,2) 1 UV
mem, imm 2+d(0,2)+i(1,2) 3 UV*
acc, imm 1+i(1,2) 1 UV

* = not pairable if there is a displacement and immediate

Flags
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is undefined.


MASM_PASCAL

Les instructions du FPU

The Pascal language type does not cause names to be mapped to uppercase.

F2XM1 Instruction
----------------------------------------------------------------------------

  Title:    Calculate 2(^X)-1

  Syntax:   F2XM1

  See also: FYL2X, FYL2XP1

  Description:

     Calculates Y = 2(^X) - 1 where X is taken from ST. The result, Y,
     is returned in ST. X must be in the range 0 <= X <= 0.5 on the
     8087/287, or in the range -1.0 <= X <= +1.0 on the 80387/486.

-----------------+------------------------+---------------------------------
 F2XM1           | f2xm1                  |  87 310-630
                 |                        | 287 310-630
                 |                        | 387 211-476
                 |                        | 486 140-279
-----------------+------------------------+---------------------------------

FABS Instruction
----------------------------------------------------------------------------

  Title:    Absolute Value

  Syntax:   FABS

  See also: FCHS, FRNDINT

  Description:

     Converts the element in ST to its absolute value.

-----------------+------------------------+---------------------------------
 FABS            | fabs                   |  87 10-17
                 |                        | 287 10-17
                 |                        | 387 22
                 |                        | 486 3
-----------------+------------------------+---------------------------------

FADD Instruction
----------------------------------------------------------------------------

  Title:    Add

  Syntax:   FADD [dest,src]
            FADDP dest,ST
            FADD src
            FIADD src

  See also: FSUB, FSUBR

  Description:

     Adds the source to the destination and returns the sum in the
     destination. If two register operands are specified, one must be
     ST. If a memory operand is specified, the sum replaces the value
     in ST. Memory operands can be 32- or 64-bit real numbers or 16-
     or 32-bit integers.

     If no operand is specified, ST is added to ST(1) and the stack is
     popped; the sum is returned in ST. For FADDP, the source must be
     ST; the sum is returned in the destination and ST is popped.

----------------+-------------------------+---------------------------------
 FADD [reg,reg] | fadd   st,st(2)         |  87 70-100
                | fadd   st(5),st         | 287 70-100
                | fadd                    | 387 to=23-31,fr=26-34
                |                         | 486 8-20
----------------+-------------------------+---------------------------------
 FADDP reg,ST   | faddp  st(6),st         |  87 75-105
                |                         | 287 75-105
                |                         | 387 23-31
                |                         | 486 8-20
----------------+-------------------------+---------------------------------
 FADD memreal   | fadd   QWORD PTR [bx]   |  87 (s=90-120,s=95-125)+EA
                | fadd   shortreal        | 287 s=90-120,l=95-125
                |                         | 387 s=24-32,l=29-37
                |                         | 486 8-20
----------------+-------------------------+---------------------------------
 FIADD memint   | fiadd  int16            |  87 (w=102-137,d=108-143)+EA
                | fiadd  warray[di]       | 287 w=102-137,d=108-143
                | fiadd  double           | 387 w=71-85,d=57-72
                |                         | 486 w=20-35,d=19-32
----------------+-------------------------+---------------------------------

FCHS Instruction

----------------------------------------------------------------------------

  Title:    Change Sign

  Syntax:   FCHS

  See also: FABS

  Description:

     Reverses the sign of the value in ST.

-----------------+------------------------+---------------------------------
 FCHS            | fchs                   |  87 10-17
                 |                        | 287 10-17
                 |                        | 387 24-25
                 |                        | 486 6
-----------------+------------------------+---------------------------------

FCLEX Instruction

----------------------------------------------------------------------------

  Title:    Clear Exceptions

  Syntax:   FCLEX
            FNCLEX

  See also: Status Word

  Description:

     Clears all exception flags, the busy flag, and bit 7 in the status
     word. Bit 7 is the interrupt-request flag on the 8087 and the
     error-status flag on the 80287, 80387, and 80486.

     This instruction has wait and no-wait versions. The wait version
     (FCLEX) checks for unmasked numeric errors. The no-wait version
     (FNCLEX) does not. When the .8087 directive is used, the assembler
     puts the WAIT instruction before the wait versions and the NOP
     instruction before the no-wait versions.

-----------------+------------------------+---------------------------------
 FCLEX           | fclex                  |  87 2-8
 FNCLEX          |                        | 287 2-8
                 |                        | 387 11
                 |                        | 486 7
-----------------+------------------------+---------------------------------

  NOTE: The timings reflect the no-wait version of the instruction.
        The wait version may take additional clock cycles.

FCOM Instruction
----------------------------------------------------------------------------

  Title:    Compare

  Syntax:   FCOM [src]
            FCOMP [src]
            FCOMPP
            FICOM src
            FICOMP src

  See also: FTST, FUCOM, FSTSW, SAHF, FXAM, Status Word

  Description:

     Compares the specified source operand to ST and sets the condition
     codes of the status word according to the result. The instruction
     subtracts the source operand from ST without changing either
     operand. Memory operands can be 32- or 64-bit real numbers or 16-
     or 32-bit integers.

     If no operand is specified or if two pops are specified, ST is
     compared to ST(1) and the stack is popped. If one pop is specified
     with an operand, the operand is compared to ST. If one of the
     operands is a NAN, an invalid-operation exception occurs.
     See: FUCOM

     The condition codes for FCOM are as follows:

     C3     C2     C1     C0     Meaning

     0      0      ?      0      ST > source
     0      0      ?      1      ST < source
     1      0      ?      0      ST = source
     1      1      ?      1      ST not comparable to source

----------------+-------------------------+---------------------------------
 FCOM [reg]     | fcom   st(2)            |  87 40-50
                | fcom                    | 287 40-50
                |                         | 387 24
                |                         | 486 4
----------------+-------------------------+---------------------------------
 FCOMP [reg]    | fcomp  st(7)            |  87 42-52
                | fcomp                   | 287 42-52
                |                         | 387 26
                |                         | 486 4
----------------+-------------------------+---------------------------------
 FCOMPP         | fcompp                  |  87 45-55
                |                         | 287 45-55
                |                         | 387 26
                |                         | 486 5
----------------+-------------------------+---------------------------------
 FCOM memreal   | fcom   shortreals[di]   |  87 (s=60-70,l=65-75)+EA
                | fcom   longreal         | 287 s=60-70,l=65-75
                |                         | 387 s=26,l=31
                |                         | 486 4
----------------+-------------------------+---------------------------------
 FCOMP memreal  | fcomp  longreal         |  87 (s=63-73,l=67-77)+EA
                | fcomp  shorts[di]       | 287 s=63-73,l=67-77
                |                         | 387 s=26,l=31
                |                         | 486 4
----------------+-------------------------+---------------------------------
 FICOM memint   | ficom  double           |  87 (w=72-86,d=78-91)+EA
                | ficom  warray[di]       | 287 w=72-86,d=78-91
                |                         | 387 w=71-75,d=56-63
                |                         | 486 w=16-20,d=15-17
----------------+-------------------------+---------------------------------
 FICOMP memint  | ficomp WORD PTR [bp+6]  |  87 (w=74-88,d=80-93)+EA
                | ficomp darray[di]       | 287 w=74-88,d=80-93
                |                         | 387 w=71-75,d=56-63
                |                         | 486 w=16-20,d=15-17
----------------+-------------------------+---------------------------------

FSIN/FCOS/FSINCOS Instructions

----------------------------------------------------------------------------

  Title:    Sine/Cosine
            80387/486 Only

  Syntax:   FSIN
            FCOS
            FSINCOS

  See also: .387, .486, FPREM, FPREM1, FPTAN

  Description:

     FSIN replaces a value in radians in ST with its sine. FCOS
     replaces a value in radians in ST with its cosine. FSINCOS
     calculates the sine and cosine of a radian value in ST. The sine
     replaces the value in ST, and then the cosine is pushed onto the
     stack.

     If |ST| < 2^63, the C2 bit of the status word is cleared and the
     sine and/or cosine is calculated. Otherwise, C2 is set and no
     calculation is performed. ST can be reduced to the required range
     with FPREM or FPREM1.

----------------+-------------------------+---------------------------------
 FSIN           | fsin                    |  87 --
                |                         | 287 --
                |                         | 387 122-771*
                |                         | 486 257-354œ
----------------+-------------------------+---------------------------------
 FCOS           | fcos                    |  87 --
                |                         | 287 --
                |                         | 387 123-772*
                |                         | 486 257-354œ
----------------+-------------------------+---------------------------------
 FSINCOS        | fsincos                 |  87 --
                |                         | 287 --
                |                         | 387 194-809*
                |                         | 486 292-365œ
----------------+-------------------------+---------------------------------
  * For operands with an absolute value greater than pi/4, up to 76
    additional clocks may be required.

  œ For operands with an absolute value greater than pi/4, add n clocks
    where n = operand / (pi/4).

FINCSTP/FDECSTP Instructions

----------------------------------------------------------------------------

  Title:    Increment or Decrement Stack Pointer

  Syntax:   FINCSTP
            FDECSTP

  Description:

     Increments or decrements the stack-top pointer in the status word.
     No tags or registers are changed, and no data is transferred. If
     the stack pointer is 7, FINCSTP changes it to 0. If the stack
     pointer is 0, FDECSTP changes it to 7.

----------------+-------------------------+---------------------------------
 FINCSTP        | fincstp                 |  87 6-12
                |                         | 287 6-12
                |                         | 387 21
                |                         | 486 3
----------------+-------------------------+---------------------------------
 FDECSTP        | fdecstp                 |  87 6-12
                |                         | 287 6-12
                |                         | 387 22
                |                         | 486 3
----------------+-------------------------+---------------------------------

FDISI/FENI Instructions

----------------------------------------------------------------------------

  Title:    Enable or Disable Interrupts
            8087 Only

  Syntax:   FDISI
            FNDISI
            FENI
            FNENI

  See also: .8087

  Description:

     FDISI disables interrupts by setting the interrupt-enable mask in
     the control word; FENI enables them by clearing the interrupt-
     enable mask. Since the 80287, 80387, and 80486 do not have an
     interrupt-enable mask, FDISI and FENI are recognized but ignored
     on these coprocessors.

     These instructions have wait and no-wait versions. The wait
     versions (FDISI and FENI) check for unmasked numeric errors; the
     no-wait versions (FNDISI and FNENI) do not. When the .8087
     directive is used, the assembler puts the WAIT instruction before
     the wait versions and the NOP instruction before the no-wait
     versions.

----------------+-------------------------+---------------------------------
 FDISI          | fdisi                   |  87 2-8
 FNDISI         |                         | 287 2
                |                         | 387 2
                |                         | 486 3
----------------+-------------------------+---------------------------------
 FENI           | feni                    |  87 2-8
 FNENI          |                         | 287 2
                |                         | 387 2
                |                         | 486 3
----------------+-------------------------+---------------------------------

  NOTE: The timings reflect the no-wait version of the instructions.
        The wait versions may take additional clock cycles.

FDIV Instructions

----------------------------------------------------------------------------

  Title:    Divide

  Syntax:   FDIV [dest,src]
            FDIVP dest,ST
            FDIV src
            FIDIV src

  See also: FDIVR, FMUL

  Description:

     Divides the destination by the source and returns the quotient in
     the destination. If two register operands are specified, one must
     be ST. If a memory operand is specified, the quotient replaces the
     value in ST. Memory operands can be 32- or 64-bit real numbers or
     16- or 32-bit integers.

     If no operand is specified, ST(1) is divided by ST and the stack
     is popped; the result is returned in ST. For FDIVP, the source
     must be ST; the quotient is returned in the destination register
     and ST is popped.

----------------+-------------------------+---------------------------------
 FDIV [reg,reg] | fdiv   st,st(2)         |  87 193-203
                | fdiv   st(5),st         | 287 193-203
                | fdiv                    | 387 to=88,fr=91
                |                         | 486 73
----------------+-------------------------+---------------------------------
 FDIVP reg,ST   | fdivp  st(6),st         |  87 197-207
                |                         | 287 197-207
                |                         | 387 91
                |                         | 486 73
----------------+-------------------------+---------------------------------
 FDIV memreal   | fdiv   DWORD PTR [bx]   |  87 (s=215-225,l=220-230)+EA
                | fdiv   shortreal[di]    | 287 s=215-225,l=220-230
                | fdiv   longreal         | 387 s=89,l=94
                |                         | 486 73
----------------+-------------------------+---------------------------------
 FIDIV memint   | fidiv  int16            |  87 (w=224-238,d=230-243)+EA
                | fidiv  warray[di]       | 287 w=224-238,d=230-243
                | fidiv  double           | 387 w=136-140,d=120-127
                |                         | 486 w=85-89,d=84-86
----------------+-------------------------+---------------------------------

FDIVR Instructions

----------------------------------------------------------------------------

  Title:    Divide Reversed

  Syntax:   FDIVR [dest,src]
            FDIVRP dest,ST
            FDIVR src
            FIDIVR src

  See also: FDIV, FMUL

  Description:

     Divides the source by the destination and returns the quotient in
     the destination. If two register operands are specified, one must
     be ST. If a memory operand is specified, the quotient replaces the
     value in ST. Memory operands can be 32- or 64-bit real numbers or
     16- or 32-bit integers.

     If no operand is specified, ST is divided by ST(1) and the stack
     is popped; the result is returned in ST. For FDIVRP, the source
     must be ST; the quotient is returned in the destination register
     and ST is popped.

----------------+-------------------------+---------------------------------
 FDIVR [reg,reg]| fdivr  st,st(2)         |  87 194-204
                | fdivr  st(5),st         | 287 194-204
                | fdivr                   | 387 to=88,fr=91
                |                         | 486 73
----------------+-------------------------+---------------------------------
 FDIVRP reg,ST  | fdivrp st(6),st         |  87 198-208
                |                         | 287 198-208
                |                         | 387 91
                |                         | 486 73
----------------+-------------------------+---------------------------------
 FDIVR memreal  | fdivr  longreal         |  87 (s=216-226,l=221-231)+EA
                | fdivr  shortreal[di]    | 287 s=216-226,l=221-231
                |                         | 387 s=89,l=94
                |                         | 486 73
----------------+-------------------------+---------------------------------
 FIDIVR memint  | fidivr double           |  87 (w=225-239,d=231-245)+EA
                | fidivr warray[di]       | 287 w=225-239,d=231-245
                |                         | 387 w=135-141,d=121-128
                |                         | 486 w=85-89,d=84-86
----------------+-------------------------+---------------------------------

FFREE Instruction
----------------------------------------------------------------------------

  Title:    Free Register

  Syntax:   FFREE dest

  See also: Coprocessor Environment

  Description:

     Changes the specified register's tag to empty without changing the
     contents of the register.

----------------+-------------------------+---------------------------------
 FFREE ST(i)    | ffree  st(3)            |  87 9-16
                |                         | 287 9-16
                |                         | 387 18
                |                         | 486 3
----------------+-------------------------+---------------------------------

FINIT Instruction

----------------------------------------------------------------------------

  Title:    Initialize Coprocessor

  Syntax:    FINIT
             FNINIT

  Description:

     Initializes the coprocessor and resets all the registers and flags
     to their default values. On the 80387/486, the condition codes of
     the status word are cleared. On the 8087/287, they are unchanged.

     This instruction has wait and no-wait versions. The wait version
     (FINIT) checks for unmasked numeric errors; the no-wait version
     (FNINIT) does not. When the .8087 directive is used, the assembler
     puts the WAIT instruction before the wait versions and the NOP
     instruction before the no-wait versions.

----------------+-------------------------+---------------------------------
 FINIT          | finit                   |  87 2-8
 FNINIT         |                         | 287 2-8
                |                         | 387 33
                |                         | 486 17
----------------+-------------------------+---------------------------------

  NOTE: The timings reflect the no-wait version of the instruction.
        The wait version may take additional clock cycles.

FLD Instruction
----------------------------------------------------------------------------

  Title:    Load

  Syntax:   FLD src
            FILD src
            FBLD src

  See also: FLDconst, FST, FXCH

  Description:

     Pushes the specified operand onto the stack. All memory operands
     are automatically converted to temporary-real numbers before being
     loaded.

     Memory operands can be 32-, 64-, or 80-bit real numbers or 16-,
     32-, or 64-bit integers.

--------------+------------------------+-----------------------------------
 FLD reg      | fld   st(3)            |  87 17-22
              |                        | 287 17-22
              |                        | 387 14
              |                        | 486  4
--------------+------------------------+-----------------------------------
 FLD memreal  | fld   longreal         |  87 (s=38-56,l=40-60,t=53-65)+EA
              | fld   shortarray[bx+di]| 287 s=38-56,l=40-60,t=53-65
              | fld   tempreal         | 387 s=20,l=25,t=44
              |                        | 486 s=3,l=3,t=6
--------------+------------------------+-----------------------------------
 FILD memint  | fild  mem16            |  87 (w=46-54,d=52-60,q=60-68)+EA
              | fild  DWORD PTR [bx]   | 287 w=46-54,d=52-60,q=60-68
              | fild  quads[si]        | 387 w=61-65,d=45-52,q=56-67
              |                        | 486 w=13-16,d=9-12,q=10-18
--------------+------------------------+-----------------------------------
 FBLD membcd  | fbld  packbcd          |  87 (290-310)+EA
              |                        | 287 290-310
              |                        | 387 266-275
              |                        | 486 70-103
--------------+------------------------+-----------------------------------

FLDconst Instruction
----------------------------------------------------------------------------

  Title:    Load Constant

  Syntax:   FLDconst

  See also: FLD

  Description:

     Pushes a constant onto the stack. The following constants can be
     loaded:

     Instruction     Constant

     FLD1            +1.0

     FLDZ            +0.0

     FLDPI           pi

     FLDL2E          Log (e)
                        2

     FLDL2T          Log (10)
                        2

     FLDLG2          Log  (2)
                        10

     FLDLN2          Log (2)
                        e
----------------+-------------------------+---------------------------------
 FLD1           | fld1                    |  87 15-21
                |                         | 287 15-21
                |                         | 387 24
                |                         | 486 4
----------------+-------------------------+---------------------------------
 FLDZ           | fldz                    |  87 11-17
                |                         | 287 11-17
                |                         | 387 20
                |                         | 486 4
----------------+-------------------------+---------------------------------
 FLDPI          | fldpi                   |  87 16-22
                |                         | 287 16-22
                |                         | 387 40
                |                         | 486 8
----------------+-------------------------+---------------------------------
 FLDL2E         | fldl2e                  |  87 15-21
                |                         | 287 15-21
                |                         | 387 40
                |                         | 486 8
----------------+-------------------------+---------------------------------
 FLDL2T         | fldl2t                  |  87 16-22
                |                         | 287 16-22
                |                         | 387 40
                |                         | 486 8
----------------+-------------------------+---------------------------------
 FLDLG2         | fldlg2                  |  87 18-24
                |                         | 287 18-24
                |                         | 387 41
                |                         | 486 8
----------------+-------------------------+---------------------------------
 FLDLN2         | fldln2                  |  87 17-23
                |                         | 287 17-23
                |                         | 387 41
                |                         | 486 8
----------------+-------------------------+---------------------------------

FLDCW/FSTCW Instructions

----------------------------------------------------------------------------

  Title:    Load or Store Control Word

  Syntax:   FLDCW src
            FSTCW dest
            FNSTCW dest

  See also: FSTSW, FSTENV, FSAVE, Control Word

  Description:

     FLDCW loads the specified word into the coprocessor control word.
     FSTCW stores the control word to a specified 16-bit memory
     operand.

     FSTCW has wait and no-wait versions. The wait version (FSTCW)
     checks for unmasked numeric errors; the no-wait version (FNSTCW)
     does not. When the .8087 directive is used, the assembler puts the
     WAIT instruction before the wait version and the NOP instruction
     before the no-wait version.

----------------+-------------------------+---------------------------------
 FLDCW mem16    | fldcw  ctrlword         |  87 (7-14)+EA
                |                         | 287 7-14
                |                         | 387 19
                |                         | 486 4
----------------+-------------------------+---------------------------------
 FSTCW mem16    | fstcw  ctrlword         |  87 12-18
 FNSTCW mem16   |                         | 287 12-18
                |                         | 387 15
                |                         | 486 3
----------------+-------------------------+---------------------------------

  NOTE: The timings reflect the no-wait version of the FSTCW. The wait
        version may take additional clock cycles.

FSTENV/FLDENV Instructions
----------------------------------------------------------------------------

  Title:    Load or Store Environment State

  Syntax:   FSTENV dest
            FNSTENV dest
            FLDENV mem

  See also: FSAVE, FSTCW, FSTSW, Coprocessor Environment

  Description:

     FSTENV stores the 14-byte coprocessor environment state to a
     specified memory location. FLDENV loads it from a specified memory
     location.

     The environment state includes the control word, status word, tag
     word, instruction pointer, and operand pointer. On the 80387/486
     in 32-bit mode, the environment state is 28 bytes.

     The FSTENV instruction has wait and no-wait versions. The wait
     version (FSTENV) checks for unmasked numeric errors; the no-wait
     version (FNSTENV) does not. When the .8087 directive is used, the
     assembler puts the WAIT instruction before the wait version and
     the NOP instruction before the no-wait version.

----------------+-------------------------+---------------------------------
 FLDENV mem     | fldenv [bp+10]          |  87 (35-45)+EA
 FLDENVW mem*   |                         | 287 35-45
 FLDENVD mem*   |                         | 387 71
                |                         | 486 44,pm=34
----------------+-------------------------+---------------------------------
 FSTENV mem     | fstenv [bp-14]          |  87 (40-50)+EA
 FSTENVW mem*   |                         | 287 40-50
 FSTENVD mem*   |                         | 387 103-104
 FNSTENV mem    |                         | 486 67,pm=56
 FNSTENVW mem*  |                         |
 FNSTENVD mem*  |                         |
----------------+-------------------------+---------------------------------
  * 80387/486 only.

  NOTE: The timings reflect the no-wait versions of FSTENV. The wait
        versions may take additional clock cycles.

FMUL Instruction
----------------------------------------------------------------------------

  Title:    Multiply

  Syntax:   FMUL [dest,src]
            FMULP dest,ST
            FMUL src
            FIMUL src

  See also: FDIV, FDIVR

  Description:

     Multiplies the source by the destination and returns the product
     in the destination. If two register operands are specified, one
     must be ST. If a memory operand is specified, the product replaces
     the value in ST. Memory operands can be 32- or 64-bit real numbers
     or 16- or 32-bit integers.

     If no operand is specified, ST(1) is multiplied by ST and the
     stack is popped; the product is returned in ST. For FMULP, the
     source must be ST; the product is returned in the destination
     register and ST is popped.

----------------+------------------------+----------------------------------
 FMUL [reg,reg] | fmul   st,st(2)        |  87 130-145 (90-105)*
                | fmul   st(5),st        | 287 130-145 (90-105)*
                | fmul                   | 387 to=46-54 (49),fr=29-57 (52)œ
                |                        | 486 16
----------------+------------------------+----------------------------------
 FMULP reg,ST   | fmulp  st(6),st        |  87 134-148 (94-108)*
                |                        | 287 134-148 (94-108)*
                |                        | 387 29-57 (52)œ
                |                        | 486 16
----------------+------------------------+----------------------------------
 FMUL memreal   | fmul   DWORD PTR [bx]  |  87 (s=110-125,l=154-168)+EA
                | fmul   shortreal[di+3] | 287 s=110-125,l=154-168
                | fmul   longreal        | 387 s=27-35,l=32-57
                |                        | 486 s=11,l=14
----------------+------------------------+----------------------------------
 FIMUL memint   | fimul  int16           |  87 (w=124-138,d=130-144)+EA
                | fimul  warray[di]      | 287 w=124-138,d=130-144
                | fimul  double          | 387 w=76-87,d=61-82
                |                        | 486 w=23-27,d=22-24
----------------+------------------------+----------------------------------
  * The clocks in parentheses show times for short values--those with 40
    trailing zeros in their fraction because they were loaded from a
    short-real memory operand.

  œ The clocks in parentheses show typical speeds.

   If the register operand is a short value--having 40 trailing zeros
    in its fraction because it was loaded from a short-real memory
    operand--then the timing is (112-126)+EA on the 8087 or 112-126 on
    the 80287.

FNOP Instruction
----------------------------------------------------------------------------

  Title:    No Operation

  Syntax:   FNOP

  See also: NOP

  Description:

     Performs no operation. FNOP can be used for timing delays or
     alignment.

----------------+-------------------------+---------------------------------
 FNOP           | fnop                    |  87 10-16
                |                         | 287 10-16
                |                         | 387 12
                |                         | 486 3
----------------+-------------------------+---------------------------------

FPATAN/FPTAN Instructions
----------------------------------------------------------------------------

  Title:    Partial Arctangent and Tangent

  Syntax:   FPATAN
            FPTAN

  See also: FSIN

  Description:

     FPATAN finds the partial tangent by calculating Z = ARCTAN(Y / X)
     where X is taken from ST and Y from ST(1). On the 8087/287, Y and
     X must be in the range 0 <= Y < X < infinity. On the 80387/486,
     there is no restriction on X and Y. X is popped from the stack and
     Z replaces Y in ST.

     FPTAN finds the partial tangent by calculating Y / X = TAN(Z). Z
     is taken from ST. Z must be in the range 0 <= Z <= pi/4 on the
     8087/287. On the 80387/486, |Z| must be less than 2^63. The result
     is the ratio Y / X. Y replaces Z, and X is pushed into ST. Thus, Y
     is returned in ST(1) and X in ST.

----------------+-------------------------+---------------------------------
 FPATAN         | fpatan                  |  87 250-800
                |                         | 287 250-800
                |                         | 387 314-487
                |                         | 486 218-303
----------------+-------------------------+---------------------------------
 FPTAN          | fptan                   |  87 30-540
                |                         | 287 30-540
                |                         | 387 191-497*
                |                         | 486 200-273œ
----------------+-------------------------+---------------------------------
  * For operands with an absolute value greater than pi/4, up to 76
    additional clocks may be required.

  œ For operands with an absolute value greater than pi/4, add n clocks
    where n = operand / (pi/4).

FPREM/FPREM1 Instructions
----------------------------------------------------------------------------

  Title:    Partial Remainder

  Syntax:   FPREM
            FPREM1 (80387/487 only)

  Description:

     Calculates the remainder of ST divided by ST(1); the result is
     returned in ST. The remainder retains the same sign as the original
     dividend. The calculation uses the following formula:

          remainder = ST - ST(1) * quotient

     For FPREM, the quotient is the exact value obtained by chopping
     ST / ST(1) toward 0. For FPREM1, the quotient is the integer
     nearest to the exact value of ST / ST(1). When two integers are
     equally close to the given value, the even integer is used. FPREM1
     conforms to the IEEE standard.

     These instructions are normally used in a loop that repeats until
     the reduction is complete, as indicated by the condition codes of
     the status word.

     The condition codes for FPREM and FPREM1 are as follows:

     C3     C2     C1     C0     Meaning

     ?      1      ?      ?      Incomplete reduction
     0      0      0      0      Quotient MOD 8 = 0
     0      0      0      1      Quotient MOD 8 = 4
     0      0      1      0      Quotient MOD 8 = 1
     0      0      1      1      Quotient MOD 8 = 5
     1      0      0      0      Quotient MOD 8 = 2
     1      0      0      1      Quotient MOD 8 = 6
     1      0      1      0      Quotient MOD 8 = 3
     1      0      1      1      Quotient MOD 8 = 7

----------------+-------------------------+---------------------------------
 FPREM          | fprem                   |  87 15-190
                |                         | 287 15-190
                |                         | 387 74-155
                |                         | 486 70-138
----------------+-------------------------+---------------------------------
 FPREM1         | fprem1                  |  87 --
                |                         | 287 --
                |                         | 387 95-185
                |                         | 486 72-167
----------------+-------------------------+---------------------------------

FRNDINT Instruction
----------------------------------------------------------------------------

  Title:    Round to Integer

  Syntax:   FRNDINT

  See also: FABS

  Description:

     Rounds ST from a real number to an integer. The rounding control
     (RC) field of the control word specifies the rounding method.

----------------+-------------------------+---------------------------------
 FRNDINT        | frndint                 |  87 16-50
                |                         | 287 16-50
                |                         | 387 66-80
                |                         | 486 21-30
----------------+-------------------------+---------------------------------

FSAVE/FRSTOR Instructions
----------------------------------------------------------------------------

  Title:    Save or Restore Coprocessor State

  Syntax:   FSAVE dest
            FNSAVE dest
            FRSTOR src

  See also: FSTENV, FSTSW, FSTCW, Coprocessor Environment

  Description:

     FSAVE stores the 94-byte coprocessor state to a specified memory
     location; FRSTOR restores it from a specified memory location.

     In 32-bit mode on the 80387/486, the environment state takes 108
     bytes.

     FSAVE has wait and no-wait versions. The wait version (FSAVE)
     checks for unmasked numeric errors; the no-wait version (FNSAVE)
     does not. After saving the state, the coprocessor is initialized
     as if FINIT had been executed.

     When the .8087 directive is used, the assembler puts the WAIT
     instruction before the wait version and the NOP instruction before
     the no-wait version.

----------------+-------------------------+---------------------------------
 FSAVE mem      | fsave  [bp-94]          |  87 (197-207)+EA
 FSAVEW mem*    | fsave  cobuffer         | 287 œ
 FSAVED mem*    |                         | 387 375-376
 FNSAVE mem     |                         | 486 154,pm=143
 FNSAVEW mem*   |                         |
 FNSAVED mem*   |                         |
----------------+-------------------------+---------------------------------
 FRSTOR mem     | frstor [bp-94]          |  87 (197-207)+EA
 FRSTORW mem*   |                         | 287 œ
 FRSTORD mem*   |                         | 387 308
                |                         | 486 131,pm=120
----------------+-------------------------+---------------------------------
  * 80387/486 only.

  œ Clock counts are not meaningful in determining overall execution
    time of this instruction. Timing is determined by operand
    transfers.

  NOTE: The timings reflect the no-wait versions of FSAVE. The wait
        versions may take additional clock cycles.

FSCALE Instruction
----------------------------------------------------------------------------

  Title:    Scale

  Syntax:   FSCALE

  See also: FSQRT

  Description:

     Scales by powers of 2 by calculating the function Y = Y * 2^X. X
     is the scaling factor taken from ST(1), and Y is the value to be
     scaled from ST. The scaled result replaces the value in ST; the
     scaling factor remains in ST(1). If the scaling factor is not an
     integer, it will be truncated toward zero before the scaling.

     On the 8087/287 processors, if X is not in the range -2^15 <= X < 2^15
     or if X is in the range 0 < X < 1, the result will be undefined. The
     80387/486 processors have no restrictions on the range of operands.

----------------+-------------------------+---------------------------------
 FSCALE         | fscale                  |  87 32-38
                |                         | 287 32-38
                |                         | 387 67-86
                |                         | 486 30-32
----------------+-------------------------+---------------------------------

FSETPM Instruction
----------------------------------------------------------------------------

  Title:    Set Protected Mode
            80287 Only

  Syntax:   FSETPM

  See also: .287

  Description:

     Sets the 80287 to protected mode. The instruction and operand
     pointers are in the protected-mode format after this instruction.
     On the 80387/486, FSETPM is recognized but interpreted as the FNOP
     instruction, since the 80386/486 processors handle addressing
     identically in real and protected modes.

----------------+-------------------------+---------------------------------
 FSETPM         | fsetpm                  |  87 --
                |                         | 287 2-8
                |                         | 387 12
                |                         | 486 3
----------------+-------------------------+---------------------------------

FSQRT Instruction
----------------------------------------------------------------------------

  Title:    Square Root

  Syntax:   FSQRT

  See also: FSCALE

  Description:

     Replaces the value of ST with its square root. The square root
     of -0 is -0.

----------------+-------------------------+---------------------------------
 FSQRT          | fsqrt                   |  87 180-186
                |                         | 287 180-186
                |                         | 387 122-129
                |                         | 486 83-87
----------------+-------------------------+---------------------------------

FST Instruction
----------------------------------------------------------------------------

  Title:    Store

  Syntax:   FST dest
            FSTP dest
            FIST dest
            FISTP dest
            FBSTP dest

  Description:

     Stores the value in ST to the specified memory location or
     register. Temporary-real values in registers are converted to the
     appropriate integer, BCD, or floating-point format as they are
     stored. With FSTP, FISTP, and FBSTP, the ST register value is
     popped off the stack.

     Memory operands can be 32-, 64-, or 80-bit real numbers for FSTP,
     or 16-, 32-, or 64-bit integers for FISTP.

---------------+-----------------------+------------------------------------
 FST reg       | fst    st(6)          |  87 15-22
               | fst    st             | 287 15-22
               |                       | 387 11
               |                       | 486 3
---------------+-----------------------+------------------------------------
 FSTP reg      | fstp   st             |  87 17-24
               | fstp   st(3)          | 287 17-24
               |                       | 387 12
               |                       | 486 3
---------------+-----------------------+------------------------------------
 FST memreal   | fst    shortreal      |  87 (s=84-90,l=96-104)+EA
               | fst    longs[bx]      | 287 s=84-90,l=96-104
               |                       | 387 s=44,l=45
               |                       | 486 s=7,l=8
---------------+-----------------------+------------------------------------
 FSTP memreal  | fstp   longreal       |  87 (s=86-92,l=98-106,t=52-58)+EA
               | fstp   tempreals[bx]  | 287 s=86-92,l=98-106,t=52-58
               |                       | 387 s=44,l=45,t=53
               |                       | 486 s=7,l=8,t=6
---------------+-----------------------+------------------------------------
 FIST memint   | fist   int16          |  87 (w=80-90,d=82-92)+EA
               | fist   doubles[8]     | 287 w=80-90,d=82-92
               |                       | 387 w=82-95,d=79-93
               |                       | 486 w=29-34,d=28-34
---------------+-----------------------+------------------------------------
 FISTP memint  | fistp  longint        |  87 (w=82-92,d=84-94,q=94-105)+EA
               | fistp  doubles[bx]    | 287 w=82-92,d=84-94,q=94-105
               |                       | 387 w=82-95,d=79-93,q=80-97
               |                       | 486 29-34
---------------+-----------------------+------------------------------------
 FBSTP membcd  | fbstp  bcds[bx]       |  87 (520-540)+EA
               |                       | 287 520-540
               |                       | 387 512-534
               |                       | 486 172-176
---------------+-----------------------+------------------------------------

FSTSW Instruction
----------------------------------------------------------------------------

  Title:    Store Status Word

  Syntax:   FSTSW dest
            FNSTSW dest

  Description:

     Stores the status word to a specified 16-bit memory operand. On
     the 80287, 80387, and 80486, the status word can also be stored to
     the processor's AX register.

     FSTSW has wait and no-wait versions. The wait version (FSTSW)
     checks for unmasked numeric errors; the no-wait version (FNSTSW)
     does not. When the .8087 directive is used, the assembler puts the
     WAIT instruction before the wait version and the NOP instruction
     before the no-wait version.

----------------+-------------------------+---------------------------------
 FSTSW mem16    | fstsw  statword         |  87 12-18
 FNSTSW mem16   |                         | 287 12-18
                |                         | 387 15
                |                         | 486 3
----------------+-------------------------+---------------------------------
 FSTSW AX       | fstsw  ax               |  87 --
 FNSTSW AX      |                         | 287 10-16
                |                         | 387 13
                |                         | 486 3
----------------+-------------------------+---------------------------------

  NOTE: The timings reflect the no-wait version of the instruction.
        The wait version may take additional clock cycles.

FSUB Instruction

----------------------------------------------------------------------------

  Title:    Subtract

  Syntax:   FSUB [dest,src]
            FSUBP dest,ST
            FSUB src
            FISUB src

  See also: FSUBR, FADD

  Description:

     Subtracts the source from the destination and returns the
     difference in the destination. If two register operands are
     specified, one must be ST. If a memory operand is specified, the
     result replaces the value in ST. Memory operands can be 32- or
     64-bit real numbers or 16- or 32-bit integers.

     If no operand is specified, ST is subtracted from ST(1) and the
     stack is popped; the difference is returned in ST. For FSUBP, the
     source must be ST; the difference (destination minus source) is
     returned in the destination register and ST is popped.

----------------+-------------------------+---------------------------------
 FSUB [reg,reg] | fsub   st,st(2)         |  87 70-100
                | fsub   st(5),st         | 287 70-100
                | fsub                    | 387 to=29-37,fr=26-34
                |                         | 486 8-20
----------------+-------------------------+---------------------------------
 FSUBP reg,ST   | fsubp  st(6),st         |  87 75-105
                |                         | 287 75-105
                |                         | 387 26-34
                |                         | 486 8-20
----------------+-------------------------+---------------------------------
 FSUB memreal   | fsub   longreal         |  87 (s=90-120,s=95-125)+EA
                | fsub   shortreals[di]   | 287 s=90-120,l=95-125
                |                         | 387 s=24-32,l=28-36
                |                         | 486 8-20
----------------+-------------------------+---------------------------------
 FISUB memint   | fisub  double           |  87 (w=102-137,d=108-143)+EA
                | fisub  warray[di]       | 287 w=102-137,d=108-143
                |                         | 387 w=71-83,d=57-82
                |                         | 486 w=20-35,d=19-32
----------------+-------------------------+---------------------------------

FSUBR Instruction
----------------------------------------------------------------------------

  Title:    Subtract Reversed

  Syntax:   FSUBR [dest,src]
            FSUBRP dest,ST
            FSUBR src
            FISUBR src

  See also: FSUB, FADD

  Description:

     Subtracts the destination operand from the source operand and
     returns the result in the destination operand. If two register
     operands are specified, one must be ST. If a memory operand is
     specified, the result replaces the value in ST. Memory operands
     can be 32- or 64-bit real numbers or 16- or 32-bit integers.

     If no operand is specified, ST(1) is subtracted from ST and the
     stack is popped; the difference is returned in ST. For FSUBRP, the
     source must be ST; the difference (source minus destination) is
     returned in the destination register and ST is popped.

----------------+-------------------------+---------------------------------
 FSUBR [reg,reg]| fsubr  st,st(2)         |  87 70-100
                | fsubr  st(5),st         | 287 70-100
                | fsubr                   | 387 to=29-37,fr=26-34
                |                         | 486 8-20
----------------+-------------------------+---------------------------------
 FSUBRP reg,ST  | fsubrp st(6),st         |  87 75-105
                |                         | 287 75-105
                |                         | 387 26-34
                |                         | 486 8-20
----------------+-------------------------+---------------------------------
 FSUBR memreal  | fsubr  QWORD PTR [bx]   |  87 (s=90-120,s=95-125)+EA
                | fsubr  shortreal[di]    | 287 s=90-120,l=95-125
                | fsubr  longreal         | 387 s=25-33,l=29-37
                |                         | 486 8-20
----------------+-------------------------+---------------------------------
 FISUBR memint  | fisubr int16            |  87 (w=103-139,d=109-144)+EA
                | fisubr warray[di]       | 287 w=103-139,d=109-144
                | fisubr double           | 387 w=72-84,d=58-83
                |                         | 486 w=20-35,d=19-32
----------------+-------------------------+---------------------------------

FTST Instruction
----------------------------------------------------------------------------

  Title:    Test for Zero

  Syntax:   FTST

  See also: FCOM, Status Word

  Description:

     Compares ST with +0.0 and sets the condition of the status word
     according to the result.

     The condition codes for FTST are as follows:

     C3     C2     C1     C0     Meaning

     0      0      ?      0      ST is positive
     0      0      ?      1      ST is negative
     1      0      ?      0      ST is 0
     1      1      ?      1      ST is not comparable (NAN or
                                 projective infinity)
----------------+-------------------------+---------------------------------
 FTST           | ftst                    |  87 38-48
                |                         | 287 38-48
                |                         | 387 28
                |                         | 486 4
----------------+-------------------------+---------------------------------

FUCOM Instruction
----------------------------------------------------------------------------

  Title:    Unordered Compare
            80387/486 Only

  Syntax:   FUCOM [src]
            FUCOMP [src]
            FUCOMPP

  See also: FCOM, FTST, Status Word

  Description:

     Compares the specified source to ST and sets the condition codes
     of the status word according to the result. The instruction
     subtracts the source operand from ST without changing either
     operand. Memory operands are not allowed.

     If no operand is specified or if two pops are specified, ST is
     compared to ST(1). If one pop is specified with an operand, the
     given register is compared to ST.

     Unlike FCOM, FUCOM does not cause an invalid-operation exception
     if one of the operands is a NAN. Instead, the condition codes are
     set to unordered.

     The condition codes for FUCOM are as follows:

     C3     C2     C1     C0     Meaning

     0      0      ?      0      ST > source
     0      0      ?      1      ST < source
     1      0      ?      0      ST = source
     1      1      ?      1      Unordered

----------------+-------------------------+---------------------------------
 FUCOM [reg]    | fucom  st(2)            |  87 --
                | fucom                   | 287 --
                |                         | 387 24
                |                         | 486 4
----------------+-------------------------+---------------------------------
 FUCOMP [reg]   | fucomp st(7)            |  87 --
                | fucomp                  | 287 --
                |                         | 387 26
                |                         | 486 4
----------------+-------------------------+---------------------------------
 FUCOMPP        | fucompp                 |  87 --
                |                         | 287 --
                |                         | 387 26
                |                         | 486 5
----------------+-------------------------+---------------------------------

FWAIT Instruction
----------------------------------------------------------------------------

  Title:    Wait

  Syntax:   FWAIT

  See also: WAIT

  Description:

     Suspends execution of the processor until the coprocessor is
     finished executing. This is an alternate mnemonic for the
     processor WAIT instruction.

----------------+-------------------------+---------------------------------
 FWAIT          | fwait                   |  87 4
                |                         | 287 3
                |                         | 387 6
                |                         | 486 1-3
----------------+-------------------------+---------------------------------

FXAM Instruction
----------------------------------------------------------------------------

  Title:    Examine

  Syntax:   FXAM

  See also: Status Word

  Description:

     Reports the contents of ST in the condition flags of the status
     word.

     The condition codes for FXAM are as follows:

     C3     C2     C1     C0     Meaning

     0      0      0      0      + Unnormal*
     0      0      0      1      + NAN
     0      0      1      0      - Unnormal*
     0      0      1      1      - NAN
     0      1      0      0      + Normal
     0      1      0      1      + Infinity
     0      1      1      0      - Normal
     0      1      1      1      - Infinity
     1      0      0      0      + 0
     1      0      0      1      Empty
     1      0      1      0      - 0
     1      0      1      1      Empty
     1      1      0      0      + Denormal
     1      1      0      1      Empty*
     1      1      1      0      - Denormal
     1      1      1      1      Empty*

     * Not used on the 80387/486 processors. Unnormals are not supported by
       the 80387/486. Also, the 80387/486 processors use two codes instead
       of four to identify empty registers.

----------------+-------------------------+---------------------------------
 FXAM           | fxam                    |  87 12-23
                |                         | 287 12-23
                |                         | 387 30-38
                |                         | 486 8
----------------+-------------------------+---------------------------------

FXCH Instruction
----------------------------------------------------------------------------

  Title:    Exchange Registers

  Syntax:   FXCH [dest]

  See also: FLD

  Description:

     Exchanges the specified (destination) register and ST. If no
     operand is specified, ST and ST(1) are exchanged.

----------------+-------------------------+---------------------------------
 FXCH [reg]     | fxch   st(3)            |  87 10-15
                | fxch                    | 287 10-15
                |                         | 387 18
                |                         | 486 4
----------------+-------------------------+---------------------------------

FXTRACT Instruction
----------------------------------------------------------------------------

  Title:    Extract Exponent and Significand

  Syntax:   FXTRACT

  Description:

     Extracts the exponent and significand (mantissa) fields of ST. The
     exponent replaces the value in ST, and then the significand is
     pushed onto the stack.

----------------+-------------------------+---------------------------------
 FXTRACT        | fxtract                 |  87 27-55
                |                         | 287 27-55
                |                         | 387 70-76
                |                         | 486 16-20
----------------+-------------------------+---------------------------------

FYL2X Instruction
----------------------------------------------------------------------------

  Title:    Y log(sub2)(X)

  Syntax:   FYL2X

  See also: FYL2XP1, F2XM1

  Description:

     Calculates Z = Y log(sub2)(X) where X is taken from ST and Y from
     ST(1). The stack is popped and the result, Z, replaces Y in ST. X
     must be in the range 0 < X < infinity and Y in the range
     minus infinity < Y < infinity.

----------------+-------------------------+---------------------------------
 FYL2X          | fyl2x                   |  87 900-1100
                |                         | 287 900-1100
                |                         | 387 120-538
                |                         | 486 196-329
----------------+-------------------------+---------------------------------

FYL2XP1 Instruction
----------------------------------------------------------------------------

  Title:    Y log(sub2)(X+1)

  Syntax:   FYL2XP1

  See also: FYL2X, F2XM1

  Description:

     Calculates Z = Y log(sub2)(X + 1) where X is taken from ST and Y
     from ST(1). The stack is popped once and the result, Z, replaces Y
     in ST. X must be in the range 0 <= |X| < (1 - (SQRT2 / 2)) and Y in
     the range minus infinity < Y < infinity.

----------------+-------------------------+---------------------------------
 FYL2XP1        | fyl2xp                  |  87 700-1000
                |                         | 287 700-1000
                |                         | 387 257-547
                |                         | 486 171-326
----------------+-------------------------+---------------------------------


C:\Jmm DOWNLOADS\LOAD Programmation\ASM\ZIP\asmhelp\ASMHELP.RTF

+$#Intel Pentium Instruction Set Reference
Produced by mindweaver@technologist.com

This is a complete reference of all Intel Pentium instructions, with the exception of MMX and FPU instructions.

This document has been painstakingly rendered into a nice searchable Windows help file for you to enjoy. Various source documents have been used to produce this. The official Intel Pentium Instruction Set Reference Manual for the mnenonics, opcodes, descriptions and flags; and Quantasm's instruction set reference for the opcode timing, size, and pairing data.

You can also check out the document conventionsJEUQFG and instruction page descriptionJEUQFD.

Not part of the instruction set information, but useful nonetheless is the basic architecture overviewJEUQFC.

Enjoy

Version History
1.0 15-04-99 First Version.+$#Basic Architecture Overview

The following diagram shows the general purpose registers:

{bmc bm0.BMP}

EAX Accumulator for operands and results data.
EBX Pointer to data in the DS segment.
ECX Counter for string and loop operations.
EDX I/O pointer.
EBP Pointer to data on the stack (in the SS segment).
ESI Pointer to data in the segment pointed to by the DS register; source pointer
for string operations.
EDI Pointer to data (or destination) in the segment pointed to by the ES register;
destination pointer for string operations.
ESP Stack pointer (in the SS segment).

The 16-Bit Segment Registers are: -

CS Code Segment
DS Data Segment
SS Stack Segment
ES Data Segment
FS Data Segment
GS Data Segment

The format of the EFLAGS register: -

{bmc bm1.BMP}
+$#Mnemonic - Description
Opcodes Official Operands Description

Description
Long description.

Operands Bytes Clocks
Generalised operands Size Clock cycles Pairing info

Flags
Affected Flags

___________________________________________________
Opcodes are in Hex.+$#Conventions

The following conventions are used throughout this document.

Offical Operands

rel8 A relative address in the range from 128 bytes
before the end of the instruction to 127 bytes after
the end of the instruction.
rel16 and rel32 A relative address within the same code segment
as the instruction assembled. The rel16 symbol
applies to instructions with an operand-size attribute
of 16 bits; the rel32 symbol applies to instructions
with an operand-size attribute of 32 bits.
ptr16:16 and ptr16:32 A far pointer, typically in a code segment different
from that of the instruction. The notation 16:16
indicates that the value of the pointer has two parts.
The value to the left of the colon is a 16-bit selector
or value destined for the code segment register. The
value to the right corresponds to the offset within the
destination segment. The ptr16:16 symbol is used
when the instruction's operand-size attribute is 16
bits; the ptr16:32 symbol is used when the
operand-size attribute is 32 bits.
r8 One of the byte general-purpose registers
AL, CL, DL, BL, AH, CH, DH, or BH.
r16 One of the word general-purpose registers
AX, CX, DX, BX, SP, BP, SI, or DI.
r32 One of the doubleword general-purpose registers
EAX, ECX, EDX, EBX, ESP, EBP, ESI, or EDI.
imm8 An immediate byte value. The imm8 symbol is a
signed number between -128 and +127 inclusive.
For instructions in which imm8 is combined with
a word or doubleword operand, the immediate value
is sign-extended to form a word or doubleword.
The upper byte of the word is filled with the topmost
bit of the immediate value.
imm16 An immediate word value used for instructions whose
operand-size attribute is 16 bits. This is a number
between -32,768 and +32,767 inclusive.
imm32 An immediate doubleword value used for instructions
whose operand-size attribute is 32 bits. It allows the
use of a number between +2,147,483,647 and
-2,147,483,648 inclusive.
r/m8 A byte operand that is either the contents of a byte
general-purpose register (AL, BL, CL, DL, AH, BH, CH,
and DH), or a byte from memory.
r/m16 A word general-purpose register or memory operand
used for instructions whose operand-size attribute is
16 bits. The word general-purpose registers are:
AX, BX, CX, DX, SP, BP, SI, and DI. The contents
of memory are found at the address provided by the
effective address computation.
r/m32 A doubleword general-purpose register or memory
operand used for instructions whose operand-size
attribute is 32 bits. The doubleword general-purpose
registers are: EAX, EBX, ECX, EDX, ESP, EBP,
ESI, and EDI. The contents of memory are found
at the address provided by the effective address
computation.
m A 16- or 32-bit operand in memory.
m8 A byte operand in memory, usually expressed as a
variable or array name, but pointed to by the DS:(E)SI
or ES:(E)DI registers. This nomenclature is used only
with the string instructions and the XLAT instruction.
m16 A word operand in memory, usually expressed as a
variable or array name, but pointed to by the DS:(E)SI
or ES:(E)DI registers. This nomenclature is used only
with the string instructions.
m32 A doubleword operand in memory, usually expressed
as a variable or array name, but pointed to by the
DS:(E)SI or ES:(E)DI registers. This nomenclature is
used only with the string instructions.
m64 A memory quadword operand in memory. This
nomenclature is used only with the CMPXCHG8B
instruction.
m16:16, m16:32 A memory operand containing a far pointer composed
of two numbers. The number to the left of the colon
corresponds to the pointer's segment selector. The
number to the right corresponds to its offset.
m16&32, m16&16, m32&32 A memory operand consisting of data item
pairs whose sizes are indicated on the left and the right
side of the ampersand. All memory addressing modes are
allowed. The m16&16 and m32&32 operands are used by the
BOUND instruction to provide an operand containing
an upper and lower bounds for array indices. The m16&32
operand is used by LIDT and LGDT to provide a word with
which to load the limit field, and a doubleword with which
to load the base field of the corresponding GDTR and
IDTR registers.
moffs8, moffs16, moffs32 A simple memory variable (memory offset)
of type byte, word, or doubleword used by some variants
of the MOV instruction. The actual address is given by
a simple offset relative to the segment base. No
ModR/M byte is used in the instruction. The number
shown with moffs indicates its size, which is determined
by the address-size attribute of the instruction.
Sreg A segment register. The segment register bit assignments
are ES=0, CS=1, SS=2, DS=3, FS=4, and GS=5.
m32real, m64real, m80real A single-, double-, and extended-real
(respectively) floating-point operand in memory.
m16int, m32int, m64int A word-, short-, and long-integer (respectively) floating-point
operand in memory.
ST or ST(0) The top element of the FPU register stack.
ST(i) The i th element from the top of the FPU register
stack. (i = 0 through 7)
mm An MMX™ register. The 64-bit MMX registers are: MM0
through MM7.
mm/m32 The low order 32 bits of an MMX register or a 32-bit
memory operand. The 64-bit MMX registers are: MM0
through MM7. The contents of memory are found at
the address provided by the effective address computation.
mm/m64 An MMX register or a 64-bit memory operand. The 64-bit
MMX registers are: MM0 through MM7. The contents of
memory are found at the address provided by the effective
address computation.

Generalised Operands
acc AL, AX or EAX unless specified otherwise
reg any general register
r8 any 8-bit register
r16 any general purpose 16-bit register
r32 any general purpose 32-bit register
imm immediate data
imm8 8-bit immediate data
imm16 16-bit immediate data
mem memory address
mem8 address of 8-bit data item
mem16 address of 16-bit data item
mem32 address of 32-bit data item
mem48 address of 48-bit data item
dest 16/32-bit destination
short 8-bit destination

Instruction Size
The byte count includes the opcode length and length of any required displacement or immediate data. If the displacement is optional, it is shown as d() with the possible lengths in parentheses. If the immediate data is optional, it is shown as i() with the possible lengths in parentheses.

Pairing Categories
 NP = not pairable
UV = pairable in the U pipe or V pipe
PU = pairable in the U pipe only
PV = pairable in the V pipe only

+$#Pentium Optimisations
By mindweaver@technologist.com

Instruction Timing
To time the number of clock cycles that a block of code takes you can use the rdtscMM84RZ instruction. See it's entry for full information.

The following code ultimately sets eax to the number of clock cycles taken by the usercode: -

rdtsc // get CPU clocks
mov clocks,eax // save clock counter

 [usercode]

rdtsc // get CPU clocks
mov ecx, clocks // get the old clock counter
sub eax, ecx // calc clock cycles taken
sub eax, $0E // subtract clocks wasted on rdtsc's

Where clocks is a 32-Bit variable.

If you are using assembly embedded in a high level language your assembler might not support the rdtsc mnemonic, as Borland Delphi 3 doesn't. In this case you can use the following construct in place of the rdtsc instruction: -

dw $310F // two bytes in hex

Note that if the code being timed is quite long, the time value might not be acurate due to interupts occuring during your code execution.
+$#KAAA - Ascii Adjust for Addition
37 AAA ASCII adjust AL after addition

Description
Adjusts the sum of two unpacked BCD values to create an unpacked BCD result. The AL register is the implied source and destination operand for this instruction. The AAA instruction is only useful when it follows an ADD instruction that adds (binary addition) two unpacked BCD values and stores a byte result in the AL register. The AAA instruction then adjusts the contents of the AL register to contain the correct 1-digit unpacked BCD result.

If the addition produces a decimal carry, the AH register is incremented by 1, and the CF and AF flags are set. If there was no decimal carry, the CF and AF flags are cleared and the AH register is unchanged. In either case, bits 4 through 7 of the AL register are cleared to 0.

Operands Bytes Clocks
 1 3 NP

Flags
The AF and CF flags are set to 1 if the adjustment results in a decimal carry; otherwise they are cleared to 0. The OF, SF, ZF, and PF flags are undefined.
+$#KAAD - Ascii Adjust AX Before Division
D5 0A AAD ASCII adjust AX before division
D5 ib (No mnemonic) Adjust AX before division to number base imm8

Description
Adjusts two unpacked BCD digits (the least-significant digit in the AL register and the most-significant digit in the AH register) so that a division operation performed on the result will yield a correct unpacked BCD value. The AAD instruction is only useful when it precedes a DIV instruction that divides (binary division) the adjusted value in the AX register by an unpacked BCD value.

The AAD instruction sets the value in the AL register to (AL + (10 * AH)), and then clears the AH register to 00H. The value in the AX register is then equal to the binary equivalent of the original unpacked two-digit (base 10) number in registers AH and AL.

The generalized version of this instruction allows adjustment of two unpacked digits of any number base (see the "Operation" section below), by setting the imm8 byte to the selected number base (for example, 08H for octal, 0AH for decimal, or 0CH for base 12 numbers). The AAD mnemonic is interpreted by all assemblers to mean adjust ASCII (base 10) values. To adjust values in another number base, the instruction must be hand coded in machine code (D5 imm8).

Operands Bytes Clocks
 2 10 NP

Flags
The SF, ZF, and PF flags are set according to the result; the OF, AF, and CF flags are undefined.

+$#KAAM - Ascii Adjust AX After Multiply
D4 0A AAM ASCII adjust AX after multiply
D4 ib (No mnemonic) Adjust AX after multiply to number base imm8

Description
Adjusts the result of the multiplication of two unpacked BCD values to create a pair of unpacked (base 10) BCD values. The AX register is the implied source and destination operand for this instruction. The AAM instruction is only useful when it follows an MUL instruction that multi-plies (binary multiplication) two unpacked BCD values and stores a word result in the AX register. The AAM instruction then adjusts the contents of the AX register to contain the correct 2-digit unpacked (base 10) BCD result.

The generalized version of this instruction allows adjustment of the contents of the AX to create two unpacked digits of any number base (see the "Operation" section below). Here, the imm8 byte is set to the selected number base (for example, 08H for octal, 0AH for decimal, or 0CH for base 12 numbers). The AAM mnemonic is interpreted by all assemblers to mean adjust to ASCII (base 10) values. To adjust to values in another number base, the instruction must be hand coded in machine code (D4 imm8).

Operands Bytes Clocks
2 18 NP

Flags
The SF, ZF, and PF flags are set according to the result. The OF, AF, and CF flags are undefined.

+$#KAAS - ASCII Adjust AL After Subtraction
3F AAS ASCII adjust AL after subtraction

Description
Adjusts the result of the subtraction of two unpacked BCD values to create a unpacked BCD result. The AL register is the implied source and destination operand for this instruction. The AAS instruction is only useful when it follows a SUB instruction that subtracts (binary subtraction) one unpacked BCD value from another and stores a byte result in the AL register. The AAA instruction then adjusts the contents of the AL register to contain the correct 1-digit unpacked BCD result.

If the subtraction produced a decimal carry, the AH register is decremented by 1, and the CF and AF flags are set. If no decimal carry occurred, the CF and AF flags are cleared, and the AH register is unchanged. In either case, the AL register is left with its top nibble set to 0.

Operands Bytes Clocks
 1 3 NP

Flags
The AF and CF flags are set to 1 if there is a decimal borrow; otherwise, they are cleared to 0.
The OF, SF, ZF, and PF flags are undefined.

+$#KADC - Add with Carry
14 ib ADC AL, imm8 Add with carry imm8 to AL
15 iw ADC AX, imm16 Add with carry imm16 to AX
15 id ADC EAX, imm32 Add with carry imm32 to EAX
80 /2 ib ADC r/m8, imm8 Add with carry imm8 to r/m8
81 /2 iw ADC r/m16,imm16 Add with carry imm16 to r/m16
81 /2 id ADC r/m32,imm32 Add with CF imm32 to r/m32
83 /2 ib ADC r/m16,imm8 Add with CF sign-extended imm8 to r/m16
83 /2 ib ADC r/m32,imm8 Add with CF sign-extended imm8 into r/m32
10 / r ADC r/m8,r8 Add with carry byte register to r/m8
11 / r ADC r/m16,r16 Add with carry r16 to r/m16
11 / r ADC r/m32,r32 Add with CF r32 to r/m32
12 / r ADC r8,r/m8 Add with carry r/m8 to byte register
13 / r ADC r16,r/m16 Add with carry r/m16 to r16
13 / r ADC r32,r/m32 Add with CF r/m32 to r32

Description
Adds the destination operand (first operand), the source operand (second operand), and the carry (CF) flag and stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) The state of the CF flag represents a carry from a previous addition. When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.

The ADC instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates the result for both data types and sets the OF and CF flags to indicate a carry in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result.

The ADC instruction is usually executed as part of a multibyte or multiword addition in which an ADD instruction is followed by an ADC instruction.

Operands Bytes Clocks
reg, reg 2 1 PU
mem, reg 2+d(0,2) 3 PU
reg, mem 2+d(0,2) 2 PU
reg, imm 2+i(1,2) 1 PU
mem, imm 2+d(0,2)+i(1,2) 3 PU*
acc, imm 1+i(1,2) 1 PU

* = not pairable if there is a displacement and immediate

Flags
The OF, SF, ZF, AF, CF, and PF flags are set according to the result.+$#KADD - Add
04 ib ADD AL, imm8 Add imm8 to AL
05 iw ADD AX, imm16 Add imm16 to AX
05 id ADD EAX, imm32 Add imm32 to EAX
80 /0 ib ADD r/m8,imm8 Add imm8 to r/m8
81 /0 iw ADD r/m16,imm16 Add imm16 to r/m16
81 /0 id ADD r/m32,imm32 Add imm32 to r/m32
83 /0 ib ADD r/m16,imm8 Add sign-extended imm8 to r/m16
83 /0 ib ADD r/m32,imm8 Add sign-extended imm8 to r/m32
00 / r ADD r/m8,r8 Add r8 to r/m8
01 / r ADD r/m16,r16 Add r16 to r/m16
01 / r ADD r/m32,r32 Add r32 to r/m32
02 / r ADD r8,r/m8 Add r/m8 to r8
03 / r ADD r16,r/m16 Add r/m16 to r16
03 / r ADD r32,r/m32 Add r/m32 to r32

Description
Adds the first operand (destination operand) and the second operand (source operand) and stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.

The ADD instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates the result for both data types and sets the OF and CF flags to indicate a carry in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result.

Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2+d(0,2) 3 UV
reg, mem 2+d(0,2) 2 UV
reg, imm 2+i(1,2) 1 UV
mem, imm 2+d(0,2)+i(1,2) 3 UV*
acc, imm 1+i(1,2) 1 UV

* = not pairable if there is a displacement and immediate

Flags
The OF, SF, ZF, AF, CF, and PF flags are set according to the result.
+$#KAND - Logical AND
24 ib AND AL, imm8 AL AND imm8
25 iw AND AX, imm16 AX AND i mm16
25 id AND EAX, imm32 EAX AND imm32
80 /4 ib AND r/m8,imm8 r/m8 AND imm8
81 /4 iw AND r/m16,imm16 r/m16 AND imm16
81 /4 id AND r/m32,imm32 r/m32 AND imm32
83 /4 ib AND r/m16,imm8 r/m16 AND imm8 (sign-extended)
83 /4 ib AND r/m32,imm8 r/m32 AND imm8 (sign-extended)
20 /r AND r/m8,r8 r/m8 AND r8
21 / r AND r/m16,r16 r/m16 AND r16
21 / r AND r/m32,r32 r/m32 AND r32
22 / r AND r8,r/m8 r8 AND r/m8
23 / r AND r16,r/m16 r16 AND r/m16
23 / r AND r32,r/m32 r32 AND r/m32

Description
Performs a bitwise AND operation on the destination (first) and source (second) operands and stores the result in the destination operand location. The source operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location. (However, two memory operands cannot be used in one instruction.) Each bit of the result of the AND instruction is a 1 if both corresponding bits of the operands are 1; otherwise, it becomes a 0.

Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2+d(0,2) 3 UV
reg, mem 2+d(0,2) 2 UV
reg, imm 2+i(1,2) 1 UV
mem, imm 2+d(0,2)+i(1,2) 3 UV*
acc, imm 1+i(1,2) 1 UV

* = not pairable if there is a displacement and immediate

Flags
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is undefined.
+$#KARPL - Adjust RPL Field of Segment Selector
63 / r ARPL r/m16,r16 Adjust RPL of r/m16 to not less than RPL of r16

Description
Compares the RPL fields of two segment selectors. The first operand (the destination operand) contains one segment selector and the second operand (source operand) contains the other. (The RPL field is located in bits 0 and 1 of each operand.) If the RPL field of the destination operand is less than the RPL field of the source operand, the ZF flag is set and the RPL field of the desti-nation operand is increased to match that of the source operand. Otherwise, the ZF flag is cleared and no change is made to the destination operand. (The destination operand can be a word register or a memory location; the source operand must be a word register.)

The ARPL instruction is provided for use by operating-system procedures (however, it can also be used by applications). It is generally used to adjust the RPL of a segment selector that has been passed to the operating system by an application program to match the privilege level of the application program. Here the segment selector passed to the operating system is placed in the destination operand and segment selector for the application program's code segment is placed in the source operand. (The RPL field in the source operand represents the privilege level of the application program.) Execution of the ARPL instruction then insures that the RPL of the segment selector received by the operating system is no lower (does not have a higher privilege) than the privilege level of the application program. (The segment selector for the application program's code segment can be read from the stack following a procedure call.)

Operands Bytes Clocks
reg, reg 2 7 NP
mem, reg 2+d(0-2) 7 NP

Flags
The ZF flag is set to 1 if the RPL field of the destination operand is less than that of the source operand; otherwise, is cleared to 0.+$#KBOUND - Check Array Index Against Bounds
62 / r BOUND r16,m16&16 Check if r16 (array index) is within bounds specified by m16&16
62 / r BOUND r32,m32&32 Check if r32 (array index) is within bounds specified by m16&16

Description
Determines if the first operand (array index) is within the bounds of an array specified the second operand (bounds operand). The array index is a signed integer located in a register. The bounds operand is a memory location that contains a pair of signed doubleword-integers (when the operand-size attribute is 32) or a pair of signed word-integers (when the operand-size attribute is 16). The first doubleword (or word) is the lower bound of the array and the second doubleword (or word) is the upper bound of the array. The array index must be greater than or equal to the lower bound and less than or equal to the upper bound plus the operand size in bytes. If the index is not within bounds, a BOUND range exceeded exception (#BR) is signaled. (When a this exception is generated, the saved return instruction pointer points to the BOUND instruction.)

The bounds limit data structure (two words or doublewords containing the lower and upper limits of the array) is usually placed just before the array itself, making the limits addressable via a constant offset from the beginning of the array. Because the address of the array already will be present in a register, this practice avoids extra bus cycles to obtain the effective address of the array bounds.

Operands Bytes Clocks
reg, mem 4 8 NP

Flags
None.+$#KBSF - Bit Scan Forward
0F BC BSF r16,r/m16 Bit scan forward on r/m16
0F BC BSF r32,r/m32 Bit scan forward on r/m32

Description
Searches the source operand (second operand) for the least significant set bit (1 bit). If a least significant 1 bit is found, its bit index is stored in the destination operand (first operand). The source operand can be a register or a memory location; the destination operand is a register. The bit index is an unsigned offset from bit 0 of the source operand. If the contents source operand are 0, the contents of the destination operand is undefined.

Operands Bytes Clocks
r16, r16 3 6-34 NP
r32, r32 3 6-42 NP
r16, m16 3+d(0,1,2) 6-35 NP
r32, m32 3+d(0,1,2,4) 6-43 NP

Flags
The ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag is cleared. The CF, OF, SF, AF, and PF, flags are undefined.+$#KBSR - Bit Scan Reverse
0F BD BSR r16,r/m16 Bit scan reverse on r/m16
0F BD BSR r32,r/m32 Bit scan reverse on r/m32

Description
Searches the source operand (second operand) for the most significant set bit (1 bit). If a most significant 1 bit is found, its bit index is stored in the destination operand (first operand). The source operand can be a register or a memory location; the destination operand is a register. The bit index is an unsigned offset from bit 0 of the source operand. If the contents source operand are 0, the contents of the destination operand is undefined.

Operands Bytes Clocks
r16, r16 3 7-39 NP
r32, r32 3 7-71 NP
r16, m16 3+d(0,1,2) 7-40 NP
r32, m32 3+d(0,1,2,4) 7-72 NP

Flags
The ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag is cleared. The CF, OF, SF, AF, and PF, flags are undefined.+$#KBSWAP - Byte Swap
0F C8+ rd BSWAP r32 Reverses the byte order of a 32-bit register.

Description
Reverses the byte order of a 32-bit (destination) register: bits 0 through 7 are swapped with bits 24 through 31, and bits 8 through 15 are swapped with bits 16 through 23. This instruction is provided for converting little-endian values to big-endian format and vice versa.

To swap bytes in a word value (16-bit register), use the XCHG instruction. When the BSWAP instruction references a 16-bit register, the result is undefined.

Operands Bytes Clocks
r32 2 1 NP

Flags
None.+$#KBT - Bit Test
0F A3 BT r/m16,r16 Store selected bit in CF flag
0F A3 BT r/m32,r32 Store selected bit in CF flag
0F BA /4 ib BT r/m16,imm8 Store selected bit in CF flag
0F BA /4 ib BT r/m32,imm8 Store selected bit in CF flag

Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by the bit offset operand (second operand) and stores the value of the bit in the CF flag. The bit base operand can be a register or a memory location; the bit offset operand can be a register or an immediate value. If the bit base operand specifies a register, the instruction takes the modulo 16 or 32 (depending on the register size) of the bit offset operand, allowing any bit position to be selected in a 16- or 32-bit register, respectively (see Figure 3-1). If the bit base operand specifies a memory location, it represents the address of the byte in memory that contains the bit base (bit 0 of the specified byte) of the bit string (see Figure 3-2). The offset operand then selects a bit position within the range -2^31 to 2^31 - 1 for a register offset and 0 to 31 for an immediate offset.

Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand. In this case, the low-order 3 or 5 bits (3 for 16-bit operands, 5 for 32-bit operands) of the immediate bit offset are stored in the immediate bit offset field, and the high-order bits are shifted and combined with the byte displacement in the addressing mode by the assembler. The processor will ignore the high order bits if they are not zero.

When accessing a bit in memory, the processor may access 4 bytes starting from the memory address for a 32-bit operand size, using by the following relationship:

Effective Address + (4 * (BitOffset DIV 32))

Or, it may access 2 bytes starting from the memory address for a 16-bit operand, using this relationship:

Effective Address + (2 * (BitOffset DIV 16))

It may do so even when only a single byte needs to be accessed to reach the given bit. When using this bit addressing mechanism, software should avoid referencing areas of memory close to address space holes. In particular, it should avoid references to memory-mapped I/O registers. Instead, software should use the MOV instructions to load from or store to these addresses, and use the register form of these instructions to manipulate the data.

Operands Bytes Clocks
reg, reg 3 4 NP
mem, reg 3+d(0,1,2,4) 9 NP
reg, imm8 3+i(1) 4 NP
mem, imm8 3+d(0,1,2,4)+i(1) 4 NP

Flags
The CF flag contains the value of the selected bit. The OF, SF, ZF, AF, and PF flags are undefined.+$#KBTC - Bit Test and Compliment
0F BB BTC r/m16,r16 Store selected bit in CF flag and complement
0F BB BTC r/m32,r32 Store selected bit in CF flag and complement
0F BA /7 ib BTC r/m16,imm8 Store selected bit in CF flag and complement
0F BA /7 ib BTC r/m32,imm8 Store selected bit in CF flag and complement

Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by the bit offset operand (second operand), stores the value of the bit in the CF flag, and complements the selected bit in the bit string. The bit base operand can be a register or a memory location; the bit offset operand can be a register or an immediate value. If the bit base operand specifies a register, the instruction takes the modulo 16 or 32 (depending on the register size) of the bit offset operand, allowing any bit position to be selected in a 16- or 32-bit register, respectively (see Figure 3-1). If the bit base operand specifies a memory location, it represents the address of the byte in memory that contains the bit base (bit 0 of the specified byte) of the bit string (see Figure 3-2). The offset operand then selects a bit position within the range -2^31 to 2^31 - 1 for a register offset and 0 to 31 for an immediate offset.

Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand. See "BT-Bit TestCVX_O" for more information on this addressing mechanism.

Operands Bytes Clocks
reg, reg 3 7 NP
mem, reg 3+d(0,1,2,4) 13 NP
reg, imm8 3+i(1) 7 NP
mem, imm8 3+d(0,1,2,4)+i(1) 8 NP

Flags
The CF flag contains the value of the selected bit before it is complemented. The OF, SF, ZF, AF, and PF flags are undefined.
+$#KBTR - Bit Test and Reset
0F B3 BTR r/m16,r16 Store selected bit in CF flag and clear
0F B3 BTR r/m32,r32 Store selected bit in CF flag and clear
0F BA /6 ib BTR r/m16,imm8 Store selected bit in CF flag and clear
0F BA /6 ib BTR r/m32,imm8 Store selected bit in CF flag and clear

Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by the bit offset operand (second operand), stores the value of the bit in the CF flag, and clears the selected bit in the bit string to 0. The bit base operand can be a register or a memory location; the bit offset operand can be a register or an immediate value. If the bit base operand specifies a register, the instruction takes the modulo 16 or 32 (depending on the register size) of the bit offset operand, allowing any bit position to be selected in a 16- or 32-bit register, respectively (see Figure 3-1). If the bit base operand specifies a memory location, it represents the address of the byte in memory that contains the bit base (bit 0 of the specified byte) of the bit string (see Figure 3-2). The offset operand then selects a bit position within the range -2^31 to 2^31 - 1 for a register offset and 0 to 31 for an immediate offset.

Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand. See "BT-Bit TestCVX_O" in this chapter for more information on this addressing mechanism.

Operands Bytes Clocks
reg, reg 3 7 NP
mem, reg 3+d(0,1,2,4) 13 NP
reg, imm8 3+i(1) 7 NP
mem, imm8 3+d(0,1,2,4)+i(1) 8 NP

Flags
The CF flag contains the value of the selected bit before it is cleared. The OF, SF, ZF, AF, and PF flags are undefined.+$#KBTS - Bit Test and Set
0F AB BTS r/m16,r16 Store selected bit in CF flag and set
0F AB BTS r/m32,r32 Store selected bit in CF flag and set
0F BA /5 ib BTS r/m16,imm8 Store selected bit in CF flag and set
0F BA /5 ib BTS r/m32,imm8 Store selected bit in CF flag and set

Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by the bit offset operand (second operand), stores the value of the bit in theCF flag, and sets the selected bit in the bit string to 1. The bit base operand can be a register or a memory location; the bit offset operand can be a register or an immediate value. If the bit base operand specifies a register, the instruction takes the modulo 16 or 32 (depending on the register size) of the bit offset operand, allowing any bit position to be selected in a 16- or 32-bit register, respectively (see Figure 3-1). If the bit base operand specifies a memory location, it represents the address of the byte in memory that contains the bit base (bit 0 of the specified byte) of the bit string (see Figure 3-2). The offset operand then selects a bit position within the range -2^31 to 2^31 - 1 for a register offset and 0 to 31 for an immediate offset.

Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand. See "BT-Bit TestCVX_O" for more information on this addressing mechanism.

Operands Bytes Clocks
reg, reg 3 7 NP
mem, reg 3+d(0,1,2,4) 13 NP
reg, imm8 3+i(1) 7 NP
mem, imm8 3+d(0,1,2,4)+i(1) 8 NP

Flags
The CF flag contains the value of the selected bit before it is set. The OF, SF, ZF, AF, and PF flags are undefined.+$#KCALL - Call Procedure
E8 cw CALL rel16 Call near, relative, displacement relative to next instruction
E8 cd CALL rel32 Call near, relative, displacement relative to next instruction
FF /2 CALL r/m16 Call near, absolute indirect, address given in r/m16
FF /2 CALL r/m32 Call near, absolute indirect, address given in r/m32
9A cd CALL ptr16:16 Call far, absolute, address given in operand
9A cp CALL ptr16:32 Call far, absolute, address given in operand
FF /3 CALL m16:16 Call far, absolute indirect, address given in m16:16
FF /3 CALL m16:32 Call far, absolute indirect, address given in m16:32

Description
Saves procedure linking information on the stack and branches to the procedure (called proce-dure) specified with the destination (target) operand. The target operand specifies the address of the first instruction in the called procedure. This operand can be an immediate value, a general-purpose register, or a memory location.

This instruction can be used to execute four different types of calls:

· Near call-A call to a procedure within the current code segment (the segment currently pointed to by the CS register), sometimes referred to as an intrasegment call.
· Far call-A call to a procedure located in a different segment than the current code segment, sometimes referred to as an intersegment call.
· Inter-privilege-level far call-A far call to a procedure in a segment at a different privilege level than that of the currently executing program or procedure.
· Task switch-A call to a procedure located in a different task.

The latter two call types (inter-privilege-level call and task switch) can only be executed in protected mode. See the section titled "Calling Procedures Using Call and RET" in Chapter 4 of the Intel Architecture Software Developer's Manual, Volume 1, for additional information on near, far, and inter-privilege-level calls. See Chapter 6, Task Management, in the Intel Architecture Software Developer's Manual, Volume 3, for information on performing task switches with the CALL instruction.

Near Call. When executing a near call, the processor pushes the value of the EIP register (which contains the offset of the instruction following the CALL instruction) onto the stack (for use later as a return-instruction pointer). The processor then branches to the address in the current code segment specified with the target operand. The target operand specifies either an absolute offset in the code segment (that is an offset from the base of the code segment) or a relative offset (a signed displacement relative to the current value of the instruction pointer in the EIP register, which points to the instruction following the CALL instruction). The CS register is not changed on near calls.

For a near call, an absolute offset is specified indirectly in a general-purpose register or a memory location (r/m16 or r/m32). The operand-size attribute determines the size of the target operand (16 or 32 bits). Absolute offsets are loaded directly into the EIP register. If the operand-size attribute is 16, the upper two bytes of the EIP register are cleared to 0s, resulting in a maximum instruction pointer size of 16 bits. (When accessing an absolute offset indirectly using the stack pointer [ESP] as a base register, the base value used is the value of the ESP before the instruction executes.)

A relative offset (rel16 or rel32) is generally specified as a label in assembly code, but at the machine code level, it is encoded as a signed, 16- or 32-bit immediate value. This value is added to the value in the EIP register. As with absolute offsets, the operand-size attribute determines the size of the target operand (16 or 32 bits).

Far Calls in Real-Address or Virtual-8086 Mode. When executing a far call in real-address or virtual-8086 mode, the processor pushes the current value of both the CS and EIP registers onto the stack for use as a return-instruction pointer. The processor then performs a "far branch" to the code segment and offset specified with the target operand for the called procedure. Here the target operand specifies an absolute far address either directly with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). With the pointer method, the segment and offset of the called procedure is encoded in the instruction, using a 4-byte (16-bit operand size) or 6-byte (32-bit operand size) far address immediate. With the indirect method, the target operand specifies a memory location that contains a 4-byte (16-bit operand size) or 6-byte (32-bit operand size) far address. The operand-size attribute determines the size of the offset (16 or 32 bits) in the far address. The far address is loaded directly into the CS and EIP registers. If the operand-size attribute is 16, the upper two bytes of the EIP register
are cleared to 0s.

Far Calls in Protected Mode. When the processor is operating in protected mode, the CALL instruction can be used to perform the following three types of far calls:

· Far call to the same privilege level.
· Far call to a different privilege level (inter-privilege level call).
· Task switch (far call to another task).

In protected mode, the processor always uses the segment selector part of the far address to access the corresponding descriptor in the GDT or LDT. The descriptor type (code segment, call gate, task gate, or TSS) and access rights determine the type of call operation to be performed.

If the selected descriptor is for a code segment, a far call to a code segment at the same privilege level is performed. (If the selected code segment is at a different privilege level and the code segment is non-conforming, a general-protection exception is generated.) A far call to the same privilege level in protected mode is very similar to one carried out in real-address or virtual-8086 mode. The target operand specifies an absolute far address either directly with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). The operand-size attribute determines the size of the offset (16 or 32 bits) in the far address. The new code segment selector and its descriptor are loaded into CS register, and the offset from the instruction is loaded into the EIP register.

Note that a call gate (described in the next paragraph) can also be used to perform far call to a code segment at the same privilege level. Using this mechanism provides an extra level of indi-rection and is the preferred method of making calls between 16-bit and 32-bit code segments.

When executing an inter-privilege-level far call, the code segment for the procedure being called must be accessed through a call gate. The segment selector specified by the target operand identifies the call gate. Here again, the target operand can specify the call gate segment selector either directly with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). The processor obtains the segment selector for the new code segment and the new instruction pointer (offset) from the call gate descriptor. (The offset from the target operand is ignored when a call gate is used.) On inter-privilege-level calls, the processor switches to the stack for the privilege level of the called procedure. The segment selector for the new stack segment is specified in the TSS for the currently running task. The branch to the new code segment occurs after the stack switch. (Note that when using a call gate to perform a far call to a segment at the same privilege level, no stack switch occurs.) On the new stack, the processor pushes the segment selector and stack pointer for the calling procedure's stack, an (optional) set of parameters from the calling procedures stack, and the segment selector and instruction pointer for the calling procedure's code segment. (A value in the call gate descriptor determines how many parameters to copy to the new stack.) Finally, the processor branches to the address of the procedure being called within the new code segment.

Executing a task switch with the CALL instruction, is somewhat similar to executing a call through a call gate. Here the target operand specifies the segment selector of the task gate for the task being switched to (and the offset in the target operand is ignored.) The task gate in turn points to the TSS for the task, which contains the segment selectors for the task's code and stack segments. The TSS also contains the EIP value for the next instruction that was to be executed before the task was suspended. This instruction pointer value is loaded into EIP register so that the task begins executing again at this next instruction.

The CALL instruction can also specify the segment selector of the TSS directly, which elimi-nates the indirection of the task gate. See Chapter 6, Task Management, in the Intel Architecture Software Developer's Manual, Volume 3, for detailed information on the mechanics of a task switch.

Note that when you execute at task switch with a CALL instruction, the nested task flag (NT) is set in the EFLAGS register and the new TSS's previous task link field is loaded with the old tasks TSS selector. Code is expected to suspend this nested task by executing an IRET instruction, which, because the NT flag is set, will automatically use the previous task link to return to the calling task. (See "Task Linking" in Chapter 6 of the Intel Architecture Software Developer's Manual, Volume 3, for more information on nested tasks.) Switching tasks with the CALL instruction differs in this regard from the JMP instruction which does not set the NT flag and therefore does not expect an IRET instruction to suspend the task.

Mixing 16-Bit and 32-Bit Calls. When making far calls between 16-bit and 32-bit code segments, the calls should be made through a call gate. If the far call is from a 32-bit code segment to a 16-bit code segment, the call should be made from the first 64 KBytes of the 32-bit code segment. This is because the operand-size attribute of the instruction is set to 16, so only a 16-bit return address offset is saved. Also, the call should be made using a 16-bit call gate so that 16-bit values will be pushed on the stack. See Chapter 16, Mixing 16-Bit and 32-Bit Code, in the Intel Architecture Software Developer's Manual, Volume 3, for more information on making calls between 16-bit and 32-bit code segments.

Operands Bytes Clocks
near 3 1 PV
reg 2 2 NP
mem16 2+d(0-2) 2 NP
far 5 4 NP
mem32 2+d(0-2) 4 NP

Protected Mode
far 5 4-13 NP
mem32 2+d(0-2) 5-14 NP

Cycles not shown for calls through call and task gates

Flags
All flags are affected if a task switch occurs; no flags are affected if a task switch does not occur.+$#KCBW - Convert Byte to Word
98 CBW AX ¬ sign-extend of AL
98 CWDE EAX ¬ sign-extend of AX

Description
Double the size of the source operand by means of sign extension (see Figure 6-5 in the Intel Architecture Software Developer's Manual, Volume 1). The CBW (convert byte to word) instruction copies the sign (bit 7) in the source operand into every bit in the AH register. The CWDE (convert word to doubleword) instruction copies the sign (bit 15) of the word in the AX register into the higher 16 bits of the EAX register.

The CBW and CWDE mnemonics reference the same opcode. The CBW instruction is intended for use when the operand-size attribute is 16 and the CWDE instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when CBW is used and to 32 when CWDE is used. Others may treat these mnemonics as synonyms (CBW/CWDE) and use the current setting of the operand-size attribute to determine the size of values to be converted, regardless of the mnemonic used.

The CWDE instruction is different from the CWD (convert word to double) instruction. The CWD instruction uses the DX:AX register pair as a destination operand; whereas, the CWDE instruction uses the EAX register as a destination.

Operands Bytes Clocks
 1 3 NP

Flags
None.+$#KCWDE - Convert Word to Doubleword
98 CBW AX ¬ sign-extend of AL
98 CWDE EAX ¬ sign-extend of AX

Description
Double the size of the source operand by means of sign extension (see Figure 6-5 in the Intel Architecture Software Developer's Manual, Volume 1). The CBW (convert byte to word) instruction copies the sign (bit 7) in the source operand into every bit in the AH register. The CWDE (convert word to doubleword) instruction copies the sign (bit 15) of the word in the AX register into the higher 16 bits of the EAX register.

The CBW and CWDE mnemonics reference the same opcode. The CBW instruction is intended for use when the operand-size attribute is 16 and the CWDE instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when CBW is used and to 32 when CWDE is used. Others may treat these mnemonics as synonyms (CBW/CWDE) and use the current setting of the operand-size attribute to determine the size of values to be converted, regardless of the mnemonic used.

The CWDE instruction is different from the CWD (convert word to double) instruction. The CWD instruction uses the DX:AX register pair as a destination operand; whereas, the CWDE instruction uses the EAX register as a destination.

Operands Bytes Clocks
 1 3 NP

Flags
None.
+$#KCDQ - Convert Double to Quad
99 CWD DX:AX ¬ sign-extend of AX
99 CDQ EDX:EAX ¬ sign-extend of EAX

Description
Doubles the size of the operand in register AX or EAX (depending on the operand size) by means of sign extension and stores the result in registers DX:AX or EDX:EAX, respectively. The CWD instruction copies the sign (bit 15) of the value in the AX register into every bit position in the DX register (see Figure 6-5 in the Intel Architecture Software Developer's Manual, Vo l u me 1 ). The CDQ instruction copies the sign (bit 31) of the value in the EAX register into every bit position in the EDX register.

The CWD instruction can be used to produce a doubleword dividend from a word before a word division, and the CDQ instruction can be used to produce a quadword dividend from a double-word before doubleword division.

The CWD and CDQ mnemonics reference the same opcode. The CWD instruction is intended for use when the operand-size attribute is 16 and the CDQ instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when CWD is used and to 32 when CDQ is used. Others may treat these mnemonics as synonyms (CWD/CDQ) and use the current setting of the operand-size attribute to determine the size of values to be converted, regardless of the mnemonic used.

Operands Bytes Clocks
1 2 NP

Flags
None.
+$#KCWD - Convert Word to Doubleword
99 CWD DX:AX ¬ sign-extend of AX
99 CDQ EDX:EAX ¬ sign-extend of EAX

Description
Doubles the size of the operand in register AX or EAX (depending on the operand size) by means of sign extension and stores the result in registers DX:AX or EDX:EAX, respectively. The CWD instruction copies the sign (bit 15) of the value in the AX register into every bit position in the DX register (see Figure 6-5 in the Intel Architecture Software Developer's Manual, Vo l u me 1 ). The CDQ instruction copies the sign (bit 31) of the value in the EAX register into every bit position in the EDX register.

The CWD instruction can be used to produce a doubleword dividend from a word before a word division, and the CDQ instruction can be used to produce a quadword dividend from a double-word before doubleword division.

The CWD and CDQ mnemonics reference the same opcode. The CWD instruction is intended for use when the operand-size attribute is 16 and the CDQ instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when CWD is used and to 32 when CDQ is used. Others may treat these mnemonics as synonyms (CWD/CDQ) and use the current setting of the operand-size attribute to determine the size of values to be converted, regardless of the mnemonic used.

Operands Bytes Clocks
1 2 NP

Flags
None.

+$#KCLC - Clear Carry Flag
F8 CLC Clear CF flag

Description
Clears the CF flag in the EFLAGS register.

Operands Bytes Clocks
 1 2 NP

Flags
The CF flag is cleared to 0. The OF, ZF, SF, AF, and PF flags are unaffected.+$#KCLD - Clear Direction Flag
FC CLD Clear DF flag

Description
Clears the DF flag in the EFLAGS register. When the DF flag is set to 0, string operations increment the index registers (ESI and/or EDI).

Operands Bytes Clocks
 1 2 NP

Flags
The DF flag is cleared to 0. The CF, OF, ZF, SF, AF, and PF flags are unaffected.
+$#KCLI - Clear Interrupt Flag
FA CLI Clear interrupt flag; interrupts disabled when interrupt flag cleared

Description
Clears the IF flag in the EFLAGS register. No other flags are affected. Clearing the IF flag causes the processor to ignore maskable external interrupts. The IF flag and the CLI and STI instruction have no affect on the generation of exceptions and NMI interrupts.

Operands Bytes Clocks
1 7 NP

Flags
The IF is cleared to 0 if the CPL is equal to or less than the IOPL; otherwise, it is not affected. The other flags in the EFLAGS register are unaffected.+$#KCLTS - Clear Task-Switched Flag in CR0
0F 06 CLTS Clears TS flag in CR0

Description
Clears the task-switched (TS) flag in the CR0 register. This instruction is intended for use in operating-system procedures. It is a privileged instruction that can only be executed at a CPL of 0. It is allowed to be executed in real-address mode to allow initialization for protected mode.

The processor sets the TS flag every time a task switch occurs. The flag is used to synchronize the saving of FPU context in multitasking applications. See the description of the TS flag in the section titled "Control Registers" in Chapter 2 of the Intel Architecture Software Developer's Manual, Volume 3, for more information about this flag.

Operands Bytes Clocks
2 10 NP

Flags
The TS flag in CR0 register is cleared.
+$#KCMC - Complement Carry Flag
F5 CMC Complement CF flag

Description
Complements the CF flag in the EFLAGS register.

Operands Bytes Clocks
1 2 NP

Flags
The CF flag contains the complement of its original value. The OF, ZF, SF, AF, and PF flags are unaffected.
+$#KCMP - Compare Two Operands
3C ib CMP AL, imm8 Compare imm8 with AL
3D iw CMP AX, imm16 Compare imm16 with AX
3D id CMP EAX, imm32 Compare imm32 with EAX
80 /7 ib CMP r/m8, imm8 Compare imm8 with r/m8
81 /7 iw CMP r/m16, imm16 Compare imm16 with r/m16
81 /7 id CMP r/m32,imm32 Compare imm32 with r/m32
83 /7 ib CMP r/m16,imm8 Compare imm8 with r/m16
83 /7 ib CMP r/m32,imm8 Compare imm8 with r/m32
38 / r CMP r/m8,r8 Compare r8 with r/m8
39 / r CMP r/m16,r16 Compare r16 with r/m16
39 / r CMP r/m32,r32 Compare r32 with r/m32
3A / r CMP r8,r/m8 Compare r/m8 with r8
3B / r CMP r16,r/m16 Compare r/m16 with r16
3B / r CMP r32,r/m32 Compare r/m32 with r32

Description
Compares the first source operand with the second source operand and sets the status flags in the EFLAGS register according to the results. The comparison is performed by subtracting the second operand from the first operand and then setting the status flags in the same manner as the SUB instruction. When an immediate value is used as an operand, it is sign-extended to the length of the first operand.

The CMP instruction is typically used in conjunction with a conditional jump (Jcc), condition move (CMOVcc), or SETcc instruction. The condition codes used by the Jcc, CMOVcc, and SETcc instructions are based on the results of a CMP instruction. Appendix B, EFLAGS Condi-tion Codes, in the Intel Architecture Software Developer's Manual, Volume 1, shows the rela-tionship of the status flags and the condition codes.

Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2+d(0,2) 2 UV
reg, mem 2+d(0,2) 2 UV
reg, imm 2+i(1,2) 1 UV
mem, imm 2+d(0,2)+i(1,2) 2 UV*
acc, imm 1+i(1,2) 1 UV

* = not pairable if there is a displacement and immediate

Flags
The CF, OF, SF, ZF, AF, and PF flags are set according to the result.
+$#KCMPS/CMPSB/CMPSW/CMPSD - Compare String Operands
A6 CMPS m8, m8 Compares byte at address DS:(E)SI with byte at address
ES:(E)DI and sets the status flags accordingly
A7 CMPS m16, m16 Compares word at address DS:(E)SI with word at address
ES:(E)DI and sets the status flags accordingly
A7 CMPS m32, m32 Compares doubleword at address DS:(E)SI with doubleword
at address ES:(E)DI and sets the status flags accordingly
A6 CMPSB Compares byte at address DS:(E)SI with byte at address
ES:(E)DI and sets the status flags accordingly
A7 CMPSW Compares word at address DS:(E)SI with word at address
ES:(E)DI and sets the status flags accordingly
A7 CMPSD Compares doubleword at address DS:(E)SI with doubleword
at address ES:(E)DI and sets the status flags accordingly

Description
Compares the byte, word, or double word specified with the first source operand with the byte, word, or double word specified with the second source operand and sets the status flags in the EFLAGS register according to the results. Both the source operands are located in memory. The address of the first source operand is read from either the DS:ESI or the DS:SI registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). The address of the second source operand is read from either the ES:EDI or the ES:DI registers (again depending on the address-size attribute of the instruction). The DS segment may be overridden with a segment override prefix, but the ES segment cannot be overridden.

At the assembly-code level, two forms of this instruction are allowed: the "explicit-operands" form and the "no-operands" form. The explicit-operands form (specified with the CMPS mnemonic) allows the two source operands to be specified explicitly. Here, the source operands should be symbols that indicate the size and location of the source values. This explicit-operands form is provided to allow documentation; however, note that the documentation provided by this form can be misleading. That is, the source operand symbols must specify the correct type (size) of the operands (bytes, words, or doublewords), but they do not have to specify the correct location. The locations of the source operands are always specified by the DS:(E)SI and ES:(E)DI registers, which must be loaded correctly before the compare string instruction is executed.

The no-operands form provides "short forms" of the byte, word, and doubleword versions of the CMPS instructions. Here also the DS:(E)SI and ES:(E)DI registers are assumed by the processor to specify the location of the source operands. The size of the source operands is selected with the mnemonic: CMPSB (byte comparison), CMPSW (word comparison), or CMPSD (double-word comparison).

After the comparison, the (E)SI and (E)DI registers are incremented or decremented automati-cally according to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)SI and (E)DI register are incremented; if the DF flag is 1, the (E)SI and (E)DI registers are decremented.) The registers are incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword operations.

The CMPS, CMPSB, CMPSW, and CMPSD instructions can be preceded by the REP prefix for block comparisons of ECX bytes, words, or doublewords. More often, however, these instructions will be used in a LOOP construct that takes some action based on the setting of the status flags before the next comparison is made. See "REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix" in this chapter for a description of the REP prefix.

Variations Bytes Clocks
cmpsb 1 5 NP
cmpsw 1 5 NP
cmpsd 1 5 NP
repX cmpsb 2 9+4n NP
repX cmpsw 2 9+4n NP
repX cmpsd 2 9+4n NP

Flags
The CF, OF, SF, ZF, AF, and PF flags are set according to the temporary result of the comparison.
+$#KCMPXCHG - Compare and Exchange
0F B0/ r CMPXCHG r/m8,r8 Compare AL with r/m8. If equal, ZF is set and r8 is loaded
into r/m8. Else, clear ZF and load r/m8 into AL.
0F B1/ r CMPXCHG r/m16,r16 Compare AX with r/m16. If equal, ZF is set and r16 is
loaded into r/m16. Else, clear ZF and load r/m16 into AL
0F B1/ r CMPXCHG r/m32,r32 Compare EAX with r/m32. If equal, ZF is set and r32 is
loaded into r/m32. Else, clear ZF and load r/m32 into AL

Description
Compares the value in the AL, AX, or EAX register (depending on the size of the operand) with the first operand (destination operand). If the two values are equal, the second operand (source operand) is loaded into the destination operand. Otherwise, the destination operand is loaded into the AL, AX, or EAX register.

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomi-cally. To simplify the interface to the processor's bus, the destination operand receives a write cycle without regard to the result of the comparison. The destination operand is written back if the comparison fails; otherwise, the source operand is written into the destination. (The processor never produces a locked read without also producing a locked write.)

Operands Bytes Clocks
reg, reg 3 5 NP
mem, reg 3+d(0-2) 6 NP

Flags
The ZF flag is set if the values in the destination operand and register AL, AX, or EAX are equal; otherwise it is cleared. The CF, PF, AF, SF, and OF flags are set according to the results of the comparison operation.
+$#KCMPXCHG8B - Compare and Exchange 8 Bytes
0F C7 /1 m64 CMPXCHG8B m64 Compare EDX:EAX with m64. If equal, set ZF and load
ECX:EBX into m64. Else, clear ZF and load m64 into
EDX:EAX.

Description
Compares the 64-bit value in EDX:EAX with the operand (destination operand). If the values are equal, the 64-bit value in ECX:EBX is stored in the destination operand. Otherwise, the value in the destination operand is loaded into EDX:EAX. The destination operand is an 8-byte memory location. For the EDX:EAX and ECX:EBX register pairs, EDX and ECX contain the high-order 32 bits and EAX and EBX contain the low-order 32 bits of a 64-bit value.

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomi-cally. To simplify the interface to the processor's bus, the destination operand receives a write cycle without regard to the result of the comparison. The destination operand is written back if the comparison fails; otherwise, the source operand is written into the destination. (The processor never produces a locked read without also producing a locked write.)

Operands Bytes Clocks
mem, reg 3+d(0-2) 10 NP

Flags
The ZF flag is set if the destination operand and EDX:EAX are equal; otherwise it is cleared. The CF, PF, AF, SF, and OF flags are unaffected.
+$#KCPUID - CPU Identification
0F A2 CPUID EAX ¬ Processor identification information

Description
Provides processor identification information in registers EAX, EBX, ECX, and EDX. This information identifies Intel as the vendor, gives the family, model, and stepping of processor, feature information, and cache information. An input value loaded into the EAX register determines what information is returned.

Information Returned by CPUID Instruction

Initial EAX Value Information Provided about the Processor
0 EAX Maximum CPUID Input Value (2 for the Pentium ® Pro processor and 1 for
the Pentium processor and the later versions of Intel486™ processor that
support the CPUID instruction).
EBX "Genu"
ECX "ntel"
EDX "ineI"
1 EAX Version Information (Type, Family, Model, and Stepping ID)
EBX Reserved
ECX Reserved
EDX Feature Information
2 EAX Cache and TLB Information
EBX Cache and TLB Information
ECX Cache and TLB Information
EDX Cache and TLB Information

The CPUID instruction can be executed at any privilege level to serialize instruction execution. Serializing instruction execution guarantees that any modifications to flags, registers, and memory for previous instructions are completed before the next instruction is fetched and executed (see "Serializing Instructions" in Chapter 7 of the Intel Architecture Software Developer's Manual, Volume 3).

When the input value in register EAX is 0, the processor returns the highest value the CPUID instruction recognizes in the EAX register (see Table 3-4). A vendor identification string is returned in the EBX, EDX, and ECX registers. For Intel processors, the vendor identification string is "GenuineIntel" as follows:

EBX ¬ 756e6547h (* "Genu", with G in the low nibble of BL *)
EDX ¬ 49656e69h (* "ineI", with i in the low nibble of DL *)
ECX ¬ 6c65746eh (* "ntel", with n in the low nibble of CL *)

When the input value is 1, the processor returns version information in the EAX register and feature information in the EDX register (see Figure 3-3).

{bmc bm2.BMP}

The version information consists of an Intel Architecture family identifier, a model identifier, a stepping ID, and a processor type. The model, family, and processor type for the first processor in the Intel Pentium Pro family is as follows:

· Model-0001B
· Family-0110B
· Processor Type-00B

See AP-485, Intel Processor Identification and the CPUID Instruction (Order Number 241618), the Intel Pentium ® Pro Processor Specification Update (Order Number 242689), and the Intel Pe n t i u m ® Processor Specification Update (Order Number 242480) for more information on identifying earlier Intel Architecture processors.

The available processor types are given in Table 3-5. Intel releases information on stepping IDs as needed.

Type Encoding
Original OEM Processor 00B
Intel OverDrive ® Processor 01B
Dual processor *10B
Intel reserved. 11B

Table 3-6 shows the encoding of the feature flags in the EDX register. A feature flag set to 1 indicates the corresponding feature is supported. Software should identify Intel as the vendor to properly interpret the feature flags.

BiT Feature Description
0 FPU-Floating-Point Unit Processor contains an FPU and executes the Intel 387
on Chip instruction set.
1 VME-Virtual-8086 Processor supports the following virtual-8086 mode
Mode Enhancements enhancements:
• CR4.VME bit enables virtual-8086 mode extensions.
• CR4.PVI bit enables protected-mode virtual interrupts.
• Expansion of the TSS with the software indirection bitmap.
• EFLAGS.VIF bit (virtual interrupt flag).
• EFLAGS.VIP bit (virtual interrupt pending flag).
2 DE-Debugging Processor supports I/O breakpoints, including the CR4.DE bit
Extensions for enabling debug extensions and optional trapping of access
to the DR4 and DR5 registers.
3 PSE-Page Size Processor supports 4-Mbyte pages, including the CR4.PSE bit
Extensions for enabling page size extensions, the modified bit in page
directory entries (PDEs), page directory entries, and page table
entries (PTEs).
4 TSC-Time Stamp Processor supports the RDTSC (read time stamp counter)
Counter instruction, including the CR4.TSD bit that, along with the CPL,
controls whether the time stamp counter can be read.
5 MSR-Model Specific Processor supports the RDMSR (read model-specific register)
Registers and WRMSR (write model-specific register) instructions.
6 PAE-Physical Address Processor supports physical addresses greater than 32 bits, the
Extension extended page-table-entry format, an extra level in the page
translation tables, and 2-MByte pages. The CR4.PAE bit enables
this feature. The number of address bits is implementation specific.
The Pentium ® Pro processor supports 36 bits of addressing when
the PAE bit is set.
7 MCE-Machine Check Processor supports the CR4.MCE bit, enabling machine check
Exception exceptions. However, this feature does not define the model-specific
implementations of machine-check error logging, reporting,
or processor shutdowns. Machine-check exception handlers might
have to check the processor version to do model-specific
processing of the exception or check for the presence of the
standard machine-check feature.
8 CX8-CMPXCHG8B Processor supports the CMPXCHG8B (compare and exchange 8
Instruction bytes) instruction.
9 APIC Processor contains an on-chip Advanced Programmable Interrupt
Controller (APIC) and it has been enabled and is available for use.
10,11 Reserved
12 MTRR-Memory Type Processor supports machine-specific memory-type range registers
Range Registers (MTRRs). The MTRRs contains bit fields that indicate the
processor's MTRR capabilities, including which memory types the
processor supports, the number of variable MTRRs the processor
supports, and whether the processor supports fixed MTRRs.
13 PGE-PTE Global Flag Processor supports the CR4.PGE flag enabling the global bit in
both PTDEs and PTEs. These bits are used to indicate translation
lookaside buffer (TLB) entries that are common to different tasks
and need not be flushed when control register CR3 is written.
14 MCA-Machine Check Processor supports the MCG_CAP (machine check global
Architecture capability) MSR. The MCG_CAP register indicates how many
banks of error reporting MSRs the processor supports.
15 CMOV-Conditional Processor supports the CMOV cc instruction and, if the FPU feature
Move and Compare flag (bit 0) is also set, supports the FCMOV cc and FCOMI
Instructions instructions.
16-22 Reserved
23 MMX™ Technology Processor supports the MMX instruction set. These instructions
operate in parallel on multiple data elements (8 bytes, 4 words, or 2
doublewords) packed into quadword registers or memory locations.
24-31 Reserved

When the input value is 2, the processor returns information about the processor's internal caches and TLBs in the EAX, EBX, ECX, and EDX registers. The encoding of these registers is as follows:

· The least-significant byte in register EAX (register AL) indicates the number of times the CPUID instruction must be executed with an input value of 2 to get a complete description of the processor's caches and TLBs. The Pentium ® Pro family of processors will return a 1.
· The most significant bit (bit 31) of each register indicates whether the register contains valid information (cleared to 0) or is reserved (set to 1).
· If a register contains valid information, the information is contained in 1 byte descriptors. Table 3-7 shows the encoding of these descriptors.

Descriptor Value Cache or TLB Description
00H Null descriptor
01H Instruction TLB: 4K-Byte Pages, 4-way set associative, 32 entries
02H Instruction TLB: 4M-Byte Pages, 4-way set associative, 4 entries
03H Data TLB: 4K-Byte Pages, 4-way set associative, 64 entries
04H Data TLB: 4M-Byte Pages, 4-way set associative, 8 entries
06H Instruction cache: 8K Bytes, 4-way set associative, 32 byte line size
08H Instruction cache: 16K Bytes, 4-way set associative, 32 byte line size
0AH Data cache: 8K Bytes, 2-way set associative, 32 byte line size
0CH Data cache: 16K Bytes, 2-way set associative, 32 byte line size
41H Unified cache: 128K Bytes, 4-way set associative, 32 byte line size
42H Unified cache: 256K Bytes, 4-way set associative, 32 byte line size
43H Unified cache: 512K Bytes, 4-way set associative, 32 byte line size
44H Unified cache: 1M Byte, 4-way set associative, 32 byte line size

The first member of the Pentium Pro processor family will return the following information about caches and TLBs when the CPUID instruction is executed with an input value of 2:

EAX 03 02 01 01H
EBX 0H
ECX 0H
EDX 06 04 0A 42H

These values are interpreted as follows:

· The least-significant byte (byte 0) of register EAX is set to 01H, indicating that the CPUID instruction needs to be executed only once with an input value of 2 to retrieve complete information about the processor's caches and TLBs.
· The most-significant bit of all four registers (EAX, EBX, ECX, and EDX) is set to 0, indicating that each register contains valid 1-byte descriptors.
· Bytes 1, 2, and 3 of register EAX indicate that the processor contains the following:
- 01H-A 32-entry instruction TLB (4-way set associative) for mapping 4-KByte pages.
- 02H-A 4-entry instruction TLB (4-way set associative) for mapping 4-MByte pages.
- 03H-A 64-entry data TLB (4-way set associative) for mapping 4-KByte pages.
· The descriptors in registers EBX and ECX are valid, but contain null descriptors.
· Bytes 0, 1, 2, and 3 of register EDX indicate that the processor contains the following:
- 42H-A 256-KByte unified cache (the L2 cache), 4-way set associative,
with a 32-byte cache line size.
- 0AH-An 8-KByte data cache (the L1 data cache), 2-way set associative, with a
32-byte cache line size.
- 04H-An 8-entry data TLB (4-way set associative) for mapping 4M-byte pages.
- 06H-An 8-KByte instruction cache (the L1 instruction cache), 4-way set associative,
with a 32-byte cache line size.

Operands Bytes Clocks
2 14 NP

Flags
None.
+$#KDAA - Decimal Adjust AL after Addition
27 DAA Decimal adjust AL after addition

Description
Adjusts the sum of two packed BCD values to create a packed BCD result. The AL register is the implied source and destination operand. The DAA instruction is only useful when it follows an ADD instruction that adds (binary addition) two 2-digit, packed BCD values and stores a byte result in the AL register. The DAA instruction then adjusts the contents of the AL register to contain the correct 2-digit, packed BCD result. If a decimal carry is detected, the CF and AF flags are set accordingly.

Operands Bytes Clocks
 1 3 NP

Flags
The CF and AF flags are set if the adjustment of the value results in a decimal carry in either digit of the result (see the "Operation" section above). The SF, ZF, and PF flags are set according to the result. The OF flag is undefined.
+$#KDAS - Decimal Adjust AL after Subtraction
2F DAS Decimal adjust AL after subtraction

Description
Adjusts the result of the subtraction of two packed BCD values to create a packed BCD result. The AL register is the implied source and destination operand. The DAS instruction is only useful when it follows a SUB instruction that subtracts (binary subtraction) one 2-digit, packed BCD value from another and stores a byte result in the AL register. The DAS instruction then adjusts the contents of the AL register to contain the correct 2-digit, packed BCD result. If a decimal borrow is detected, the CF and AF flags are set accordingly.

Operands Bytes Clocks
1 3 NP

Flags
The CF and AF flags are set if the adjustment of the value results in a decimal borrow in either digit of the result (see the "Operation" section above). The SF, ZF, and PF flags are set according to the result. The OF flag is undefined.
+$#KDEC - Decrement by 1
FE /1 DEC r/m8 Decrement r/m8 by 1
FF /1 DEC r/m16 Decrement r/m16 by 1
FF /1 DEC r/m32 Decrement r/m32 by 1
48+rw DEC r16 Decrement r16 by 1
48+rd DEC r32 Decrement r32 by 1

Description
Subtracts 1 from the destination operand, while preserving the state of the CF flag. The destination operand can be a register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag. (To perform a decrement operation that updates the CF flag, use a SUB instruction with an immediate operand of 1.)

Operands Bytes Clocks
r8 2 1 UV
r16 1 1 UV
r32 1 1 UV
mem 2+d(0,2) 3 UV

Flags
The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.
+$#KDIV - Unsigned Divide
F6 /6 DIV r/m8 Unsigned divide AX by r/m8; AL ¬ Quotient,
AH ¬ Remainder
F7 /6 DIV r/m16 Unsigned divide DX:AX by r/m16; AX ¬ Quotient,
DX ¬ Remainder
F7 /6 DIV r/m32 Unsigned divide EDX:EAX by r/m32 doubleword;
EAX ¬ Quotient, EDX ¬ Remainder

Description
Divides (unsigned) the value in the AX register, DX:AX register pair, or EDX:EAX register pair (dividend) by the source operand (divisor) and stores the result in the AX (AH:AL), DX:AX, or EDX:EAX registers. The source operand can be a general-purpose register or a memory loca-tion. The action of this instruction depends on the operand size, as shown in the following table:

Operand Size Dividend Divisor Quotient Remainder Maximum
Quotient
Word/byte AX r/m8 AL AH 255
Doubleword/word DX:AX r/m16 AX DX 65,535
Quadword/
doubleword EDX:EAX r/m32 EAX EDX 2^32 - 1

Non-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magnitude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag.

Operands Bytes Clocks
r8 2 17 NP
r16 2 25 NP
r32 2 41 NP
mem8 2+d(0-2) 17 NP
mem16 2+d(0-2) 25 NP
mem32 2+d(0-2) 41 NP

implied operand quotient remainder
dividend
AX / byte = AL AH
DX:AX / word = AX DX
EDX:EAX / dword = EAX EDX

Flags
The CF, OF, SF, ZF, AF, and PF flags are undefined.
+$#KENTER - Make Stack Frame for Procedure Parameters
C8 iw 00 ENTER imm16,0 Create a stack frame for a procedure
C8 iw 01 ENTER imm16,1 Create a nested stack frame for a procedure
C8 iw ib ENTER imm16,imm8 Create a nested stack frame for a procedure

Description
Creates a stack frame for a procedure. The first operand (size operand) specifies the size of the stack frame (that is, the number of bytes of dynamic storage allocated on the stack for the procedure). The second operand (nesting level operand) gives the lexical nesting level (0 to 31) of the procedure. The nesting level determines the number of stack frame pointers that are copied into the "display area" of the new stack frame from the preceding frame. Both of these operands are immediate values.

The stack-size attribute determines whether the BP (16 bits) or EBP (32 bits) register specifies the current frame pointer and whether SP (16 bits) or ESP (32 bits) specifies the stack pointer.

The ENTER and companion LEAVE instructions are provided to support block structured languages. The ENTER instruction (when used) is typically the first instruction in a procedure and is used to set up a new stack frame for a procedure. The LEAVE instruction is then used at the end of the procedure (just before the RET instruction) to release the stack frame.

If the nesting level is 0, the processor pushes the frame pointer from the EBP register onto the stack, copies the current stack pointer from the ESP register into the EBP register, and loads the ESP register with the current stack-pointer value minus the value in the size operand. For nesting levels of 1 or greater, the processor pushes additional frame pointers on the stack before adjusting the stack pointer. These additional frame pointers provide the called procedure with access points to other nested frames on the stack. See "Procedure Calls for Block-Structured Languages" in Chapter 4 of the Intel Architecture Software Developer's Manual, Volume 1, for more information about the actions of the ENTER instruction.

Operands Bytes Clocks
imm16, 0 3 11 NP
imm16, 1 4 15 NP
imm16, imm8 4 15+2i NP

i = imm8

Flags
None.
+$#KHLT - Halt
F4 HLT Halt

Description
Stops instruction execution and places the processor in a HALT state. An enabled interrupt, NMI, or a reset will resume execution. If an interrupt (including NMI) is used to resume execution after a HLT instruction, the saved instruction pointer (CS:EIP) points to the instruction following the HLT instruction.

The HLT instruction is a privileged instruction. When the processor is running in protected or virtual-8086 mode, the privilege level of a program or procedure must be 0 to execute the HLT instruction.

Operands Bytes Clocks
1 4 NP

Flags
None.
+$#KIDIV - Signed Divide
F6 /7 IDIV r/m8 Signed divide AX (where AH must contain sign-extension
of AL) by r/m byte. (Results: AL=Quotient,
AH=Remainder)
F7 /7 IDIV r/m16 Signed divide DX:AX (where DX must contain sign-extension
of AX) by r/m word. (Results: AX=Quotient,
DX=Remainder)
F7 /7 IDIV r/m32 Signed divide EDX:EAX (where EDX must contain
sign-extension of EAX) by r/m doubleword. (Results:
EAX=Quotient, EDX=Remainder)

Description
Divides (signed) the value in the AL, AX, or EAX register by the source operand and stores the result in the AX, DX:AX, or EDX:EAX registers. The source operand can be a general-purpose register or a memory location. The action of this instruction depends on the operand size, as shown in the following table:

Operand Size Dividend Divisor Quotient Remainder Quotient Range
Word/byte AX r/m8 AL AH -128 to +127
Doubleword/word DX:AX r/m16 AX DX -32,768 to +32,767
Quadword/
doubleword EDX:EAX r/m32 EAX EDX -2 31 to 2 32 - 1

Non-integral results are truncated (chopped) towards 0. The sign of the remainder is always the same as the sign of the dividend. The absolute value of the remainder is always less than the absolute value of the divisor. Overflow is indicated with the #DE (divide error) exception rather than with the OF (overflow) flag.

Operands Bytes Clocks
r8 2 22 NP
r16 2 30 NP
r32 2 46 NP
mem8 2+d(0-2) 22 NP
mem16 2+d(0-2) 30 NP
mem32 2+d(0-2) 46 NP

implied operand quotient remainder
dividend
AX / byte = AL AH
DX:AX / word = AX DX
EDX:EAX / dword = EAX EDX

Flags
The CF, OF, SF, ZF, AF, and PF flags are undefined.
+$#KIMUL - Signed Multiply
F6 /5 IMUL r/m8 AX¬ AL * r/m byte
F7 /5 IMUL r/m16 DX:AX ¬ AX * r/m word
F7 /5 IMUL r/m32 EDX:EAX ¬ EAX * r/m doubleword
0F AF / r IMUL r16,r/m16 word register ¬ word register * r/m word
0F AF / r IMUL r32,r/m32 doubleword register ¬ doubleword register * r/m
doubleword
6B / r ib IMUL r16,r/m16,imm8 word register ¬ r/m16 * sign-extended immediate byte
6B / r ib IMUL r32,r/m32,imm8 doubleword register ¬ r/m32 * sign-extended immediate
byte
6B / r ib IMUL r16,imm8 word register ¬ word register * sign-extended immediate
 byte
6B / r ib IMUL r32,imm8 doubleword register ¬ doubleword register * sign-extended
immediate byte
69 / r iw IMUL r16,r/m16,imm16 word register ¬ r/m16 * immediate word
69 / r id IMUL r32,r/m32,imm32 doubleword register ¬ r/m32 * immediate doubleword
69 / r iw IMUL r16,imm16 word register ¬ r/m16 * immediate word
69 / r id IMUL r32,imm32 doubleword register ¬ r/m32 * immediate doubleword

Description
Performs a signed multiplication of two operands. This instruction has three forms, depending on the number of operands.

One-operand form. This form is identical to that used by the MUL instruction. Here, the source operand (in a general-purpose register or memory location) is multiplied by the value in the AL, AX, or EAX register (depending on the operand size) and the product is stored in the AX, DX:AX, or EDX:EAX registers, respectively.

Two-operand form. With this form the destination operand (the first operand) is multiplied by the source operand (second operand). The destination operand is a general-purpose register and the source operand is an immediate value, a general-purpose register, or a memory location. The product is then stored in the destination operand location.

Three-operand form. This form requires a destination operand (the first operand) and two source operands (the second and the third operands). Here, the first source operand (which can be a general-purpose register or a memory location) is multiplied by the second source operand (an immediate value). The product is then stored in the destination operand (a general-purpose register).

When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.

The CF and OF flags are set when significant bits are carried into the upper half of the result. The CF and OF flags are cleared when the result fits exactly in the lower half of the result.

The three forms of the IMUL instruction are similar in that the length of the product is calculated to twice the length of the operands. With the one-operand form, the product is stored exactly in the destination. With the two- and three- operand forms, however, result is truncated to the length of the destination before it is stored in the destination register. Because of this truncation, the CF or OF flag should be tested to ensure that no significant bits are lost.

The two- and three-operand forms may also be used with unsigned operands because the lower half of the product is the same regardless if the operands are signed or unsigned. The CF and OF flags, however, cannot be used to determine if the upper half of the result is non-zero.

Accumulator Multiplies
Operands Bytes Clocks
r8 2 11 NP
r16 2 11 NP
r32 2 10 NP
mem8 2+d(0-2) 11 NP
mem16 2+d(0-2) 11 NP
mem32 2+d(0-2) 10 NP

implied operand result
multiplicand (multiplier)
AL * byte = AX
AX * word = DX:AX
EAX * dword = EDX:EAX

2 and 3 operand Multiplies
Operands Bytes Clocks
r16, imm 2+i(1,2) 10 NP
r32, imm 2+i(1,2) 10 NP
r16,r16,imm 2+i(1,2) 10 NP
r32,r32,imm 2+i(1,2) 10 NP
r16,m16,imm 2+d(0-2)+i(1,2) 10 NP
r32,m32,imm 2+d(0-2)+i(1,2) 10 NP
r16, r16 2+i(1,2) 10 NP
r32, r32 2+i(1,2) 10 NP
r16, m16 2+d(0-2)+i(1,2) 10 NP
r32, m32 2+d(0-2)+i(1,2) 10 NP

Flags
For the one operand form of the instruction, the CF and OF flags are set when significant bits are carried into the upper half of the result and cleared when the result fits exactly in the lower half of the result. For the two- and three-operand forms of the instruction, the CF and OF flags are set when the result must be truncated to fit in the destination operand size and cleared when the result fits exactly in the destination operand size. The SF, ZF, AF, and PF flags are undefined.
+$#KIN - Input from Port
E4 ib IN AL, imm8 Input byte from imm8 I/O port address into AL
E5 ib IN AX, imm8 Input byte from imm8 I/O port address into AX
E5 ib IN EAX, imm8 Input byte from imm8 I/O port address into EAX
EC IN AL,DX Input byte from I/O port in DX into AL
ED IN AX,DX Input word from I/O port in DX into AX
ED IN EAX,DX Input doubleword from I/O port in DX into EAX

Description
Copies the value from the I/O port specified with the second operand (source operand) to the destination operand (first operand). The source operand can be a byte-immediate or the DX register; the destination operand can be register AL, AX, or EAX, depending on the size of the port being accessed (8, 16, or 32 bits, respectively). Using the DX register as a source operand allows I/O port addresses from 0 to 65,535 to be accessed; using a byte immediate allows I/O port addresses 0 to 255 to be accessed.

When accessing an 8-bit I/O port, the opcode determines the port size; when accessing a 16- and 32-bit I/O port, the operand-size attribute determines the port size.

At the machine code level, I/O instructions are shorter when accessing 8-bit I/O ports. Here, the upper eight bits of the port address will be 0.

This instruction is only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 9, Input/Output, in the Intel Architecture Software Developer's Manual, Vo l u me 1 , for more information on accessing I/O ports in the I/O address space.

Operands Bytes Clocks
al, imm8 2 7 NP
ax, imm8 2 7 NP
eax, imm8 2 7 NP
al, dx 1 7 NP
ax, dx 1 7 NP
eax, dx 1 7 NP

Protected mode
acc, imm 2 4/21/19 NP
acc, dx 1 4/21/19 NP

cycles for: CPL <= IOPL / CPL > IOPL / V86

Flags
None.
+$#KINC - Increment by 1
FE /0 INC r/m8 Increment r/m byte by 1
FF /0 INC r/m16 Increment r/m word by 1
FF /0 INC r/m32 Increment r/m doubleword by 1
40+ rw INC r16 Increment word register by 1
40+ rd INC r32 Increment doubleword register by 1

Description
Adds 1 to the destination operand, while preserving the state of the CF flag. The destination operand can be a register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag. (Use a ADD instruction with an immediate operand of 1 to perform an increment operation that does updates the CF flag.)

Operands Bytes Clocks
r8 2 1 UV
r16 1 1 UV
r32 1 1 UV
mem 2+d(0,2) 3 UV

Flags
The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.
+$#KINS/INSB/INSW/INSD - Input from Port to String
6C INS m8, DX Input byte from I/O port specified in DX into memory
location specified in ES:(E)DI
6D INS m16, DX Input word from I/O port specified in DX into memory
location specified in ES:(E)DI
6D INS m32, DX Input doubleword from I/O port specified in DX into
memory location specified in ES:(E)DI
6C INSB Input byte from I/O port specified in DX into memory
location specified with ES:(E)DI
6D INSW Input word from I/O port specified in DX into memory
location specified in ES:(E)DI
6D INSD Input doubleword from I/O port specified in DX into
memory location specified in ES:(E)DI

Description
Copies the data from the I/O port specified with the source operand (second operand) to the destination operand (first operand). The source operand is an I/O port address (from 0 to 65,535) that is read from the DX register. The destination operand is a memory location, the address of which is read from either the ES:EDI or the ES:DI registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). (The ES segment cannot be overridden with a segment override prefix.) The size of the I/O port being accessed (that is, the size of the source and destination operands) is determined by the opcode for an 8-bit I/O port or by the operand-size attribute of the instruction for a 16- or 32-bit I/O port.

At the assembly-code level, two forms of this instruction are allowed: the "explicit-operands" form and the "no-operands" form. The explicit-operands form (specified with the INS mnemonic) allows the source and destination operands to be specified explicitly. Here, the source operand must be "DX," and the destination operand should be a symbol that indicates the size of the I/O port and the destination address. This explicit-operands form is provided to allow documentation; however, note that the documentation provided by this form can be misleading. That is, the destination operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does not have to specify the correct location. The location is always specified by the ES:(E)DI registers, which must be loaded correctly before the INS instruction is executed.

The no-operands form provides "short forms" of the byte, word, and doubleword versions of the INS instructions. Here also DX is assumed by the processor to be the source operand and ES:(E)DI is assumed to be the destination operand. The size of the I/O port is specified with the choice of mnemonic: INSB (byte), INSW (word), or INSD (doubleword).

After the byte, word, or doubleword is transfer from the I/O port to the memory location, the (E)DI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)DI register is incremented; if the DF flag is 1, the (E)DI register is decremented.) The (E)DI register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword operations.

The INS, INSB, INSW, and INSD instructions can be preceded by the REP prefix for block input of ECX bytes, words, or doublewords. See "REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix" in this chapter for a description of the REP prefix.

These instructions are only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 9, Input/Output, in the Intel Architecture Software Developer's Manual, Vo l u me 1 , for more information on accessing I/O ports in the I/O address space.

Operands Bytes Clocks
insb 1 9 NP
insw 1 9 NP
insd 1 9 NP

Protected Mode
1 6/24/22 NP

cycles for: CPL <= IOPL / CPL > IOPL / V86

Flags
None.
+$#KINT n/INTO/INT 3 - Call to Interrupt Procedure
CC INT 3 Interrupt 3-trap to debugger
CD ib INT imm8 Interrupt vector number specified by immediate byte
CE INTO Interrupt 4-if overflow flag is 1

Description
The INT n instruction generates a call to the interrupt or exception handler specified with the destination operand (see the section titled "Interrupts and Exceptions" in Chapter 4 of the Intel Architecture Software Developer's Manual, Volume 1). The destination operand specifies an interrupt vector number from 0 to 255, encoded as an 8-bit unsigned intermediate value. Each interrupt vector number provides an index to a gate descriptor in the IDT. The first 32 interrupt vector numbers are reserved by Intel for system use. Some of these interrupts are used for inter-nally generated exceptions.

The INT n instruction is the general mnemonic for executing a software-generated call to an interrupt handler. The INTO instruction is a special mnemonic for calling overflow exception (#OF), interrupt vector number 4. The overflow interrupt checks the OF flag in the EFLAGS register and calls the overflow interrupt handler if the OF flag is set to 1.

The INT 3 instruction generates a special one byte opcode (CC) that is intended for calling the debug exception handler. (This one byte form is valuable because it can be used to replace the first byte of any instruction with a breakpoint, including other one byte instructions, without over-writing other code). To further support its function as a debug breakpoint, the interrupt generated with the CC opcode also differs from the regular software interrupts as follows:

· Interrupt redirection does not happen when in VME mode; the interrupt is handled by a protected-mode handler.
· The virtual-8086 mode IOPL checks do not occur. The interrupt is taken without faulting at any IOPL level.

Note that the "normal" 2-byte opcode for INT 3 (CD03) does not have these special features. Intel and Microsoft assemblers will not generate the CD03 opcode from any mnemonic, but this opcode can be created by direct numeric code definition or by self-modifying code.

The action of the INT n instruction (including the INTO and INT 3 instructions) is similar to that of a far call made with the CALL instruction. The primary difference is that with the INT n instruction, the EFLAGS register is pushed onto the stack before the return address. (The return address is a far address consisting of the current values of the CS and EIP registers.) Returns from interrupt procedures are handled with the IRET instruction, which pops the EFLAGS information and return address from the stack.

The interrupt vector number specifies an interrupt descriptor in the interrupt descriptor table (IDT); that is, it provides index into the IDT. The selected interrupt descriptor in turn contains a pointer to an interrupt or exception handler procedure. In protected mode, the IDT contains an array of 8-byte descriptors, each of which is an interrupt gate, trap gate, or task gate. In real-address mode, the IDT is an array of 4-byte far pointers (2-byte code segment selector and a 2-byte instruction pointer), each of which point directly to a procedure in the selected segment. (Note that in real-address mode, the IDT is called the interrupt vector table, and it's pointers are called interrupt vectors.)

When the processor is executing in virtual-8086 mode, the IOPL determines the action of the INT n instruction. If the IOPL is less than 3, the processor generates a general protection exception (#GP); if the IOPL is 3, the processor executes a protected mode interrupt to privilege level 0. The interrupt gate's DPL must be set to three and the target CPL of the interrupt handler procedure must be 0 to execute the protected mode interrupt to privilege level 0.

The interrupt descriptor table register (IDTR) specifies the base linear address and limit of the IDT. The initial base address value of the IDTR after the processor is powered up or reset is 0.

Operands Bytes Clocks
3 (const) 1 13 NP
imm8 2 16 NP

Protected mode
1 27-82 NP

Flags
The EFLAGS register is pushed onto the stack. The IF, TF, NT, AC, RF, and VM flags may be cleared, depending on the mode of operation of the processor when the INT instruction is executed (see the "Operation" section). If the interrupt uses a task gate, any flags may be set or cleared, controlled by the EFLAGS image in the new task's TSS.
+$#KINVD - Invalidate Internal Caches
0F 08 INVD Flush internal caches; initiate flushing of external caches.

Description
Invalidates (flushes) the processor's internal caches and issues a special-function bus cycle that directs external caches to also flush themselves. Data held in internal caches is not written back to main memory.

After executing this instruction, the processor does not wait for the external caches to complete their flushing operation before proceeding with instruction execution. It is the responsibility of hardware to respond to the cache flush signal.

The INVD instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a program or procedure must be 0 to execute this instruction.

Use this instruction with care. Data cached internally and not written back to main memory will be lost. Unless there is a specific requirement or benefit to flushing caches without writing back modified cache lines (for example, testing or fault recovery where cache coherency with main memory is not a concern), software should use the WBINVD instruction.

Operands Bytes Clocks
2 15 NP

Flags
None.
+$#KINVLPG - Invalidate TLB Entry
0F 01/7 INVLPG m Invalidate TLB Entry for page that contains m

Description
Invalidates (flushes) the translation lookaside buffer (TLB) entry specified with the source operand. The source operand is a memory address. The processor determines the page that contains that address and flushes the TLB entry for that page.

The INVLPG instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a program or procedure must be 0 to execute this instruction.

The INVLPG instruction normally flushes the TLB entry only for the specified page; however, in some cases, it flushes the entire TLB. See "MOV-Move to/from Control Registers" in this chapter for further information on operations that flush the TLB.

Operands Bytes Clocks
mem32 5 25 NP

Flags
None.
+$#KIRET/IRETD - Interrupt Return
CF IRET Interrupt return (16-bit operand size)
CF IRETD Interrupt return (32-bit operand size)

Description
Returns program control from an exception or interrupt handler to a program or procedure that was interrupted by an exception, an external interrupt, or a software-generated interrupt. These instructions are also used to perform a return from a nested task. (A nested task is created when a CALL instruction is used to initiate a task switch or when an interrupt or exception causes a task switch to an interrupt or exception handler.) See the section titled "Task Linking" in Chapter 6 of the Intel Architecture Software Developer's Manual, Volume 1.

IRET and IRETD are mnemonics for the same opcode. The IRETD mnemonic (interrupt return double) is intended for use when returning from an interrupt when using the 32-bit operand size; however, most assemblers use the IRET mnemonic interchangeably for both operand sizes.

In Real-Address Mode, the IRET instruction preforms a far return to the interrupted program or procedure. During this operation, the processor pops the return instruction pointer, return code segment selector, and EFLAGS image from the stack to the EIP, CS, and EFLAGS registers, respectively, and then resumes execution of the interrupted program or procedure.

In Protected Mode, the action of the IRET instruction depends on the settings of the NT (nested task) and VM flags in the EFLAGS register and the VM flag in the EFLAGS image stored on the current stack. Depending on the setting of these flags, the processor performs the following types of interrupt returns:

· Return from virtual-8086 mode.
· Return to virtual-8086 mode.
· Intra-privilege level return.
· Inter-privilege level return.
· Return from nested task (task switch).

If the NT flag (EFLAGS register) is cleared, the IRET instruction performs a far return from the interrupt procedure, without a task switch. The code segment being returned to must be equally or less privileged than the interrupt handler routine (as indicated by the RPL field of the code segment selector popped from the stack). As with a real-address mode interrupt return, the IRET instruction pops the return instruction pointer, return code segment selector, and EFLAGS image from the stack to the EIP, CS, and EFLAGS registers, respectively, and then resumes execution of the interrupted program or procedure. If the return is to another privilege level, the IRET instruction also pops the stack pointer and SS from the stack, before resuming program execution. If the return is to virtual-8086 mode, the processor also pops the data segment registers from the stack.

If the NT flag is set, the IRET instruction performs a task switch (return) from a nested task (a task called with a CALL instruction, an interrupt, or an exception) back to the calling or interrupted task. The updated state of the task executing the IRET instruction is saved in its TSS. If the task is reentered later, the code that follows the IRET instruction is executed.

Operands Bytes Clocks
IRET 1 8-27 NP
IRETD 1 10-27 NP

Flags
All the flags and fields in the EFLAGS register are potentially modified, depending on the mode of operation of the processor. If performing a return from a nested task to a previous task, the EFLAGS register will be modified according to the EFLAGS image stored in the previous task's TSS.
+$#KJcc - Jump if Condition Is Met
77 cb JA rel8 Jump short if above (CF=0 and ZF=0)
73 cb JAE rel8 Jump short if above or equal (CF=0)
72 cb JB rel8 Jump short if below (CF=1)
76 cb JBE rel8 Jump short if below or equal (CF=1 or ZF=1)
72 cb JC rel8 Jump short if carry (CF=1)
E3 cb JCXZ rel8 Jump short if CX register is 0
E3 cb JECXZ rel8 Jump short if ECX register is 0
74 cb JE rel8 Jump short if equal (ZF=1)
7F cb JG rel8 Jump short if greater (ZF=0 and SF=OF)
7D cb JGE rel8 Jump short if greater or equal (SF=OF)
7C cb JL rel8 Jump short if less (SF<>OF)
7E cb JLE rel8 Jump short if less or equal (ZF=1 or SF<>OF)
76 cb JNA rel8 Jump short if not above (CF=1 or ZF=1)
72 cb JNAE rel8 Jump short if not above or equal (CF=1)
73 cb JNB rel8 Jump short if not below (CF=0)
77 cb JNBE rel8 Jump short if not below or equal (CF=0 and ZF=0)
73 cb JNC rel8 Jump short if not carry (CF=0)
75 cb JNE rel8 Jump short if not equal (ZF=0)
7E cb JNG rel8 Jump short if not greater (ZF=1 or SF<>OF)
7C cb JNGE rel8 Jump short if not greater or equal (SF<>OF)
7D cb JNL rel8 Jump short if not less (SF=OF)
7F cb JNLE rel8 Jump short if not less or equal (ZF=0 and SF=OF)
71 cb JNO rel8 Jump short if not overflow (OF=0)
7B cb JNP rel8 Jump short if not parity (PF=0)
79 cb JNS rel8 Jump short if not sign (SF=0)
75 cb JNZ rel8 Jump short if not zero (ZF=0)
70 cb JO rel8 Jump short if overflow (OF=1)
7A cb JP rel8 Jump short if parity (PF=1)
7A cb JPE rel8 Jump short if parity even (PF=1)
7B cb JPO rel8 Jump short if parity odd (PF=0)
78 cb JS rel8 Jump short if sign (SF=1)
74 cb JZ rel8 Jump short if zero (ZF = 1)
0F 87 cw/cd JA rel16/32 Jump near if above (CF=0 and ZF=0)
0F 83 cw/cd JAE rel16/32 Jump near if above or equal (CF=0)
0F 82 cw/cd JB rel16/32 Jump near if below (CF=1)
0F 86 cw/cd JBE rel16/32 Jump near if below or equal (CF=1 or ZF=1)
0F 82 cw/cd JC rel16/32 Jump near if carry (CF=1)
0F 84 cw/cd JE rel16/32 Jump near if equal (ZF=1)
0F 84 cw/cd JZ rel16/32 Jump near if 0 (ZF=1)
0F 8F cw/cd JG rel16/32 Jump near if greater (ZF=0 and SF=OF)
0F 8D cw/cd JGE rel16/32 Jump near if greater or equal (SF=OF)
0F 8C cw/cd JL rel16/32 Jump near if less (SF<>OF)
0F 8E cw/cd JLE rel16/32 Jump near if less or equal (ZF=1 or SF<>OF)
0F 86 cw/cd JNA rel16/32 Jump near if not above (CF=1 or ZF=1)
0F 82 cw/cd JNAE rel16/32 Jump near if not above or equal (CF=1)
0F 83 cw/cd JNB rel16/32 Jump near if not below (CF=0)
0F 87 cw/cd JNBE rel16/32 Jump near if not below or equal (CF=0 and ZF=0)
0F 83 cw/cd JNC rel16/32 Jump near if not carry (CF=0)
0F 85 cw/cd JNE rel16/32 Jump near if not equal (ZF=0)
0F 8E cw/cd JNG rel16/32 Jump near if not greater (ZF=1 or SF<>OF)
0F 8C cw/cd JNGE rel16/32 Jump near if not greater or equal (SF<>OF)
0F 8D cw/cd JNL rel16/32 Jump near if not less (SF=OF)
0F 8F cw/cd JNLE rel16/32 Jump near if not less or equal (ZF=0 and SF=OF)
0F 81 cw/cd JNO rel16/32 Jump near if not overflow (OF=0)
0F 8B cw/cd JNP rel16/32 Jump near if not parity (PF=0)
0F 89 cw/cd JNS rel16/32 Jump near if not sign (SF=0)
0F 85 cw/cd JNZ rel16/32 Jump near if not zero (ZF=0)
0F 80 cw/cd JO rel16/32 Jump near if overflow (OF=1)
0F 8A cw/cd JP rel16/32 Jump near if parity (PF=1)
0F 8A cw/cd JPE rel16/32 Jump near if parity even (PF=1)
0F 8B cw/cd JPO rel16/32 Jump near if parity odd (PF=0)
0F 88 cw/cd JS rel16/32 Jump near if sign (SF=1)
0F 84 cw/cd JZ rel16/32 Jump near if 0 (ZF=1)

Description
Checks the state of one or more of the status flags in the EFLAGS register (CF, OF, PF, SF, and ZF) and, if the flags are in the specified state (condition), performs a jump to the target instruction specified by the destination operand. A condition code (cc) is associated with each instruction to indicate the condition being tested for. If the condition is not satisfied, the jump is not performed and execution continues with the instruction following the Jcc instruction.

The target instruction is specified with a relative offset (a signed offset relative to the current value of the instruction pointer in the EIP register). A relative offset (rel8, rel16, or rel32) is generally specified as a label in assembly code, but at the machine code level, it is encoded as a signed, 8-bit or 32-bit immediate value, which is added to the instruction pointer. Instruction coding is most efficient for offsets of -128 to +127. If the operand-size attribute is 16, the upper two bytes of the EIP register are cleared to 0s, resulting in a maximum instruction pointer size of 16 bits.

The conditions for each Jcc mnemonic are given in the "Description" column of the table on the preceding page. The terms "less" and "greater" are used for comparisons of signed integers and the terms "above" and "below" are used for unsigned integers.

Because a particular state of the status flags can sometimes be interpreted in two ways, two mnemonics are defined for some opcodes. For example, the JA (jump if above) instruction and the JNBE (jump if not below or equal) instruction are alternate mnemonics for the opcode 77H.

The Jcc instruction does not support far jumps (jumps to other code segments). When the target for the conditional jump is in a different segment, use the opposite condition from the condition being tested for the Jcc instruction, and then access the target with an unconditional far jump (JMP instruction) to the other segment. For example, the following conditional far jump is illegal:

JZ FARLABEL;

To accomplish this far jump, use the following two instructions:

JNZ BEYOND;
JMP FARLABEL;
BEYOND:

The JECXZ and JCXZ instructions differs from the other Jcc instructions because they do not check the status flags. Instead they check the contents of the ECX and CX registers, respectively, for 0. Either the CX or ECX register is chosen according to the address-size attribute. These instructions are useful at the beginning of a conditional loop that terminates with a conditional loop instruction (such as LOOPNE). They prevent entering the loop when the ECX or CX register is equal to 0, which would cause the loop to execute 2 32 or 64K times, respectively, instead of zero times.

All conditional jumps are converted to code fetches of one or two cache lines, regardless of jump address or cacheability.

Operands Bytes Clocks
near8 2 1 PV
near16 3 1 PV
cycles apply to jump and no jump

Flags
None.
+$#KJMP - Jump
EB cb JMP rel8 Jump short, relative, displacement relative to next instruction
E9 cw JMP rel16 Jump near, relative, displacement relative to next instruction
E9 cd JMP rel32 Jump near, relative, displacement relative to next instruction
FF /4 JMP r/m16 Jump near, absolute indirect, address given in r/m16
FF /4 JMP r/m32 Jump near, absolute indirect, address given in r/m32
EA cd JMP ptr16:16 Jump far, absolute, address given in operand
EA cp JMP ptr16:32 Jump far, absolute, address given in operand
FF /5 JMP m16:16 Jump far, absolute indirect, address given in m16:16
FF /5 J MP m16:32 Jump far, absolute indirect, address given in m16:32

Description
Transfers program control to a different point in the instruction stream without recording return information. The destination (target) operand specifies the address of the instruction being jumped to. This operand can be an immediate value, a general-purpose register, or a memory location.

This instruction can be used to execute four different types of jumps:

· Near jump-A jump to an instruction within the current code segment (the segment currently pointed to by the CS register), sometimes referred to as an intrasegment jump.
· Short jump-A near jump where the jump range is limited to -128 to +127 from the current EIP value.
· Far jump-A jump to an instruction located in a different segment than the current code segment but at the same privilege level, sometimes referred to as an intersegment jump.
· Task switch-A jump to an instruction located in a different task.

A task switch can only be executed in protected mode (see Chapter 6, Task Management, in the Intel Architecture Software Developer's Manual, Volume 3, for information on performing task switches with the JMP instruction).

Near and Short Jumps. When executing a near jump, the processor jumps to the address (within the current code segment) that is specified with the target operand. The target operand specifies either an absolute offset (that is an offset from the base of the code segment) or a relative offset (a signed displacement relative to the current value of the instruction pointer in the EIP register). A near jump to a relative offset of 8-bits (rel8) is referred to as a short jump. The CS register is not changed on near and short jumps.

An absolute offset is specified indirectly in a general-purpose register or a memory location (r/m16 or r/m32). The operand-size attribute determines the size of the target operand (16 or 32 bits). Absolute offsets are loaded directly into the EIP register. If the operand-size attribute is 16, the upper two bytes of the EIP register are cleared to 0s, resulting in a maximum instruction pointer size of 16 bits.

A relative offset (rel8, rel 16, or rel32) is generally specified as a label in assembly code, but at the machine code level, it is encoded as a signed 8-, 16-, or 32-bit immediate value. This value is added to the value in the EIP register. (Here, the EIP register contains the address of the instruction following the JMP instruction). When using relative offsets, the opcode (for short vs. near jumps) and the operand-size attribute (for near relative jumps) determines the size of the target operand (8, 16, or 32 bits).

Far Jumps in Real-Address or Virtual-8086 Mode. When executing a far jump in real-address or virtual-8086 mode, the processor jumps to the code segment and offset specified with the target operand. Here the target operand specifies an absolute far address either directly with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). With the pointer method, the segment and address of the called procedure is encoded in the instruction, using a 4-byte (16-bit operand size) or 6-byte (32-bit operand size) far address immediate. With the indirect method, the target operand specifies a memory location that contains a 4-byte (16-bit operand size) or 6-byte (32-bit operand size) far address. The far address is loaded directly into the CS and EIP registers. If the operand-size attribute is 16, the upper two bytes of the EIP register are cleared to 0s.

Far Jumps in Protected Mode. When the processor is operating in protected mode, the JMP instruction can be used to perform the following three types of far jumps:

· A far jump to a conforming or non-conforming code segment.
· A far jump through a call gate.
· A task switch.
(The JMP instruction cannot be used to perform interprivilege level far jumps.)

In protected mode, the processor always uses the segment selector part of the far address to access the corresponding descriptor in the GDT or LDT. The descriptor type (code segment, call gate, task gate, or TSS) and access rights determine the type of jump to be performed.

If the selected descriptor is for a code segment, a far jump to a code segment at the same privilege level is performed. (If the selected code segment is at a different privilege level and the code segment is non-conforming, a general-protection exception is generated.) A far jump to the same privilege level in protected mode is very similar to one carried out in real-address or virtual-8086 mode. The target operand specifies an absolute far address either directly with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). The operand-size attribute determines the size of the offset (16 or 32 bits) in the far address. The new code segment selector and its descriptor are loaded into CS register, and the offset from the instruction is loaded into the EIP register. Note that a call gate (described in the next paragraph) can also be used to perform far call to a code segment at the same privilege level. Using this mechanism provides an extra level of indirection and is the preferred method of making jumps between 16-bit and 32-bit code segments.

When executing a far jump through a call gate, the segment selector specified by the target operand identifies the call gate. (The offset part of the target operand is ignored.) The processor then jumps to the code segment specified in the call gate descriptor and begins executing the instruction at the offset specified in the call gate. No stack switch occurs. Here again, the target operand can specify the far address of the call gate either directly with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32).

Executing a task switch with the JMP instruction, is somewhat similar to executing a jump through a call gate. Here the target operand specifies the segment selector of the task gate for the task being switched to (and the offset part of the target operand is ignored). The task gate in turn points to the TSS for the task, which contains the segment selectors for the task's code and stack segments. The TSS also contains the EIP value for the next instruction that was to be executed before the task was suspended. This instruction pointer value is loaded into EIP register so that the task begins executing again at this next instruction.

The JMP instruction can also specify the segment selector of the TSS directly, which eliminates the indirection of the task gate. See Chapter 6, Task Management, in Intel Architecture Software Developer's Manual, Volume 3, the for detailed information on the mechanics of a task switch.

Note that when you execute at task switch with a JMP instruction, the nested task flag (NT) is not set in the EFLAGS register and the new TSS's previous task link field is not loaded with the old task's TSS selector. A return to the previous task can thus not be carried out by executing the IRET instruction. Switching tasks with the JMP instruction differs in this regard from the CALL instruction which does set the NT flag and save the previous task link information, allowing a return to the calling task with an IRET instruction.

Operands Bytes Clocks
short 2 1 PV
near 3 1 PV
far 5 3 NP
r16 2 2 NP
mem16 2+d(0,2) 2 NP
mem32 2+d(4) 4 NP
r32 2 2 NP
mem32 2+d(0,2) 2 NP
mem48 2+d(6) 4 NP

Flags
All flags are affected if a task switch occurs; no flags are affected if a task switch does not occur.
+$#KJCXZ/JECXZ - Jump if CX/EAX = 0

Usage: JCXZ label
JECXZ

Description
See JMPCW1CO for description and flags

Operands Bytes Clocks
dest 2 5/6 NP
dest 2 5/6 NP

+$#KLAHF - Load Status Flags into AH Register
9F LAHF Load: AH = EFLAGS(SF:ZF:0:AF:0:PF:1:CF)

Description
Moves the low byte of the EFLAGS register (which includes status flags SF, ZF, AF, PF, and CF) to the AH register. Reserved bits 1, 3, and 5 of the EFLAGS register are set in the AH register as shown in the "Operation" section below.

Operands Bytes Clocks
1 2 NP

Flags
None (that is, the state of the flags in the EFLAGS register are not affected).
+$#KLAR - Load Access Rights Byte
0F 02 / r LAR r16,r/m16 r16 ¬ r/m16 masked by FF00H
0F 02 / r LAR r32,r/m32 r32 ¬ r/m32 masked by 00FxFF00H

Description
Loads the access rights from the segment descriptor specified by the second operand (source operand) into the first operand (destination operand) and sets the ZF flag in the EFLAGS register. The source operand (which can be a register or a memory location) contains the segment selector for the segment descriptor being accessed. The destination operand is a general-purpose register.

The processor performs access checks as part of the loading process. Once loaded in the desti-nation register, software can perform additional checks on the access rights information.

When the operand size is 32 bits, the access rights for a segment descriptor include the type and DPL fields and the S, P, AVL, D/B, and G flags, all of which are located in the second double-word (bytes 4 through 7) of the segment descriptor. The doubleword is masked by 00FXFF00H before it is loaded into the destination operand. When the operand size is 16 bits, the access rights include the type and DPL fields. Here, the two lower-order bytes of the doubleword are masked by FF00H before being loaded into the destination operand.

This instruction performs the following checks before it loads the access rights in the destination register:

· Checks that the segment selector is not null.
· Checks that the segment selector points to a descriptor that is within the limits of the GDT or LDT being accessed
· Checks that the descriptor type is valid for this instruction. All code and data segment descriptors are valid for (can be accessed with) the LAR instruction. The valid system segment and gate descriptor types are given in the following table.
· If the segment is not a conforming code segment, it checks that the specified segment descriptor is visible at the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to the DPL of the segment selector).

If the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no access rights are loaded in the destination operand.

The LAR instruction can only be executed in protected mode.

Operands Bytes Clocks
r16, r16 3 8 NP
r32, r32 3 8 NP
r16, m16 3 8 NP
r32, m32 3 8 NP

Flags
The ZF flag is set to 1 if the access rights are loaded successfully; otherwise, it is cleared to 0.
+$#KLDS - Load Far Pointer
C5 / r LDS r16,m16:16 Load DS: r16 with far pointer from memory
C5 / r LDS r32,m16:32 Load DS: r32 with far pointer from memory
0F B2 / r LSS r16,m16:16 Load SS: r16 with far pointer from memory
0F B2 / r LSS r32,m16:32 Load SS: r32 with far pointer from memory
C4 / r LES r16,m16:16 Load ES: r16 with far pointer from memory
C4 / r LES r32,m16:32 Load ES: r32 with far pointer from memory
0F B4 / r LFS r16,m16:16 Load FS: r16 with far pointer from memory
0F B4 / r LFS r32,m16:32 Load FS: r32 with far pointer from memory
0F B5 / r LGS r16,m16:16 Load GS: r16 with far pointer from memory
0F B5 / r LGS r32,m16:32 Load GS: r32 with far pointer from memory

Description
Loads a far pointer (segment selector and offset) from the second operand (source operand) into a segment register and the first operand (destination operand). The source operand specifies a 48-bit or a 32-bit pointer in memory depending on the current setting of the operand-size attribute (32 bits or 16 bits, respectively). The instruction opcode and the destination operand specify a segment register/general-purpose register pair. The 16-bit segment selector from the source operand is loaded into the segment register specified with the opcode (DS, SS, ES, FS, or GS). The 32-bit or 16-bit offset is loaded into the register specified with the destination operand.

If one of these instructions is executed in protected mode, additional information from the segment descriptor pointed to by the segment selector in the source operand is loaded in the hidden part of the selected segment register.

Also in protected mode, a null selector (values 0000 through 0003) can be loaded into DS, ES, FS, or GS registers without causing a protection exception. (Any subsequent reference to a segment whose corresponding segment register is loaded with a null selector, causes a general-protection exception (#GP) and no memory reference to the segment occurs.)

Operands Bytes Clocks
reg, mem 2+d(2) 4 NP

Flags
None.
+$#KLES - Load Far Pointer

Usage: LES dest,src

Description
See LDSCW1.O

Operands Bytes Clocks
reg, mem 2+d(2) 4 NP

+$#KLFS - Load Far Pointer

Usage: LFS dest,src

Description
See LDSCW1.O

Operands Bytes Clocks
reg, mem 3+d(2,4) 4 NP
+$#KLGS - Load Far Pointer

Usage: LGS dest,src

Description
See LDSCW1.O

Operands Bytes Clocks
reg, mem 3+d(2,4) 4 NP
+$#KLSS - Load Far Pointer

Usage: LSS dest,src

Description
See LDSCW1.O

Operands Bytes Clocks
reg, mem 3+d(2,4) 4 NP

+$#KLEA - Load Effective Address
8D / r LEA r16,m Store effective address for m in register r16
8D / r LEA r32,m Store effective address for m in register r32

Description
Computes the effective address of the second operand (the source operand) and stores it in the first operand (destination operand). The source operand is a memory address (offset part) specified with one of the processors addressing modes; the destination operand is a general-purpose register. The address-size and operand-size attributes affect the action performed by this instruction, as shown in the following table. The operand-size attribute of the instruction is determined by the chosen register; the address-size attribute is determined by the attribute of the codesegment.

Operand Size Address Size Action Performed
16 16 16-bit effective address is calculated and stored in requested
16-bit register destination.
16 32 32-bit effective address is calculated. The lower 16 bits of the
address are stored in the requested 16-bit register destination.
32 16 16-bit effective address is calculated. The 16-bit address is zero-extended
and stored in the requested 32-bit register destination.
32 32 32-bit effective address is calculated and stored in the requested
32-bit register destination.

Different assemblers may use different algorithms based on the size attribute and symbolic reference of the source operand.

Operands Bytes Clocks
r16, mem 2+d(2) 1 UV
r32, mem 2+d(2) 1 UV

Flags
None.
+$#KLEAVE - High Level Procedure Exit
C9 LEAVE Set SP to BP, then pop BP
C9 LEAVE Set ESP to EBP, then pop EBP

Description
Releases the stack frame set up by an earlier ENTER instruction. The LEAVE instruction copies the frame pointer (in the EBP register) into the stack pointer register (ESP), which releases the stack space allocated to the stack frame. The old frame pointer (the frame pointer for the calling procedure that was saved by the ENTER instruction) is then popped from the stack into the EBP register, restoring the calling procedure's stack frame.

A RET instruction is commonly executed following a LEAVE instruction to return program control to the calling procedure.

See "Procedure Calls for Block-Structured Languages" in Chapter 6 of the Intel Architecture Software Developer's Manual, Volume 1, for detailed information on the use of the ENTER and LEAVE instructions.

Operands Bytes Clocks
1 3 NP

Flags
None.
+$#KLGDT/LIDT - Load Global/Interrupt Descriptor Table Register
0F 01 /2 LGDT m16&32 Load m into GDTR
0F 01 /3 LIDT m16&32 Load m into IDTR

Description
Loads the values in the source operand into the global descriptor table register (GDTR) or the interrupt descriptor table register (IDTR). The source operand specifies a 6-byte memory location that contains the base address (a linear address) and the limit (size of table in bytes) of the global descriptor table (GDT) or the interrupt descriptor table (IDT). If operand-size attribute is 32 bits, a 16-bit limit (lower 2 bytes of the 6-byte data operand) and a 32-bit base address (upper 4 bytes of the data operand) are loaded into the register. If the operand-size attribute is 16 bits, a 16-bit limit (lower 2 bytes) and a 24-bit base address (third, fourth, and fifth byte) are loaded. Here, the high-order byte of the operand is not used and the high-order byte of the base address in the GDTR or IDTR is filled with zeros.

The LGDT and LIDT instructions are used only in operating-system software; they are not used in application programs. They are the only instructions that directly load a linear address (that is, not a segment-relative address) and a limit in protected mode. They are commonly executed in real-address mode to allow processor initialization prior to switching to protected mode.

See "SGDT/SIDT-Store Global/Interrupt Descriptor Table Register" in this chapter for information on storing the contents of the GDTR and IDTR.

Operands Bytes Clocks
mem48 5 6 NP

Flags
None.
+$#KLLDT - Load Local Descriptor Table Register
0F 00 /2 LLDT r/m16 Load segment selector r/m16 into LDTR

Description
Loads the source operand into the segment selector field of the local descriptor table register (LDTR). The source operand (a general-purpose register or a memory location) contains a segment selector that points to a local descriptor table (LDT). After the segment selector is loaded in the LDTR, the processor uses to segment selector to locate the segment descriptor for the LDT in the global descriptor table (GDT). It then loads the segment limit and base address for the LDT from the segment descriptor into the LDTR. The segment registers DS, ES, SS, FS, GS, and CS are not affected by this instruction, nor is the LDTR field in the task state segment (TSS) for the current task.

If the source operand is 0, the LDTR is marked invalid and all references to descriptors in the LDT (except by the LAR, VERR, VERW or LSL instructions) cause a general protection excep-tion (#GP).

The operand-size attribute has no effect on this instruction.

The LLDT instruction is provided for use in operating-system software; it should not be used in application programs. Also, this instruction can only be executed in protected mode.

Operands Bytes Clocks
r16 3 9 NP
mem16 3+d(0-2) 9 NP

Flags
None.
+$#KLIDT - Load Interrupt Descriptor Table Register

See LGDT/LIDTCW2CO+$#KLMSW - Load Machine Status Word
0F 01 /6 LMSW r/m16 Loads r/m16 in machine status word of CR0

Description
Loads the source operand into the machine status word, bits 0 through 15 of register CR0. The source operand can be a 16-bit general-purpose register or a memory location. Only the low-order 4 bits of the source operand (which contains the PE, MP, EM, and TS flags) are loaded into CR0. The PG, CD, NW, AM, WP, NE, and ET flags of CR0 are not affected. The operand-size attribute has no effect on this instruction.

If the PE flag of the source operand (bit 0) is set to 1, the instruction causes the processor to switch to protected mode. While in protected mode, the LMSW instruction cannot be used clear the PE flag and force a switch back to real-address mode.

The LMSW instruction is provided for use in operating-system software; it should not be used in application programs. In protected or virtual-8086 mode, it can only be executed at CPL 0.

This instruction is provided for compatibility with the Intel 286 processor; programs and procedures intended to run on the Pentium Pro, Pentium, Intel486, and Intel386 processors should use the MOV (control registers) instruction to load the whole CR0 register. The MOV CR0 instruction can be used to set and clear the PE flag in CR0, allowing a procedure or program to switch between protected and real-address modes.

This instruction is a serializing instruction.

Operands Bytes Clocks
r16 3 8 NP
mem16 3+d(0-2) 8 NP

Flags
None.
+$#KLOCK - Assert LOCK# Signal Prefix
F0 LOCK Asserts LOCK# signal for duration of the accompanying
instruction

Description
Causes the processor's LOCK# signal to be asserted during execution of the accompanying instruction (turns the instruction into an atomic instruction). In a multiprocessor environment, the LOCK# signal insures that the processor has exclusive use of any shared memory while the signal is asserted.

Note that in later Intel Architecture processors (such as the Pentium Pro processor), locking may occur without the LOCK# signal being asserted. See Intel Architecture Compatibility below.

The LOCK prefix can be prepended only to the following instructions and to those forms of the instructions that use a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. An undefined opcode exception will be generated if the LOCK prefix is used with any other instruction. The XCHG instruction always asserts the LOCK# signal regardless of the presence or absence of the LOCK prefix.

The LOCK prefix is typically used with the BTS instruction to perform a read-modify-write operation on a memory location in shared memory environment.

The integrity of the LOCK prefix is not affected by the alignment of the memory field. Memory locking is observed for arbitrarily misaligned fields.

Operands Bytes Clocks
1 1 NP

Flags
None.
+$#KLODS/LODSB/LODSW/LODSD - Load String
AC LODS m8 Load byte at address DS:(E)SI into AL
AD LODS m16 Load word at address DS:(E)SI into AX
AD LODS m32 Load doubleword at address DS:(E)SI into EAX
AC LODSB Load byte at address DS:(E)SI into AL
AD LODSW Load word at address DS:(E)SI into AX
AD LODSD Load doubleword at address DS:(E)SI into EAX

Description
Loads a byte, word, or doubleword from the source operand into the AL, AX, or EAX register, respectively. The source operand is a memory location, the address of which is read from the DS:EDI or the DS:SI registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). The DS segment may be overridden with a segment override prefix.

At the assembly-code level, two forms of this instruction are allowed: the "explicit-operands" form and the "no-operands" form. The explicit-operands form (specified with the LODS mnemonic) allows the source operand to be specified explicitly. Here, the source operand should be a symbol that indicates the size and location of the source value. The destination operand is then automatically selected to match the size of the source operand (the AL register for byte operands, AX for word operands, and EAX for doubleword operands). This explicit-operands form is provided to allow documentation; however, note that the documentation provided by this form can be misleading. That is, the source operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does not have to specify the correct location. The location is always specified by the DS:(E)SI registers, which must be loaded correctly before the load string instruction is executed.

The no-operands form provides "short forms" of the byte, word, and doubleword versions of the LODS instructions. Here also DS:(E)SI is assumed to be the source operand and the AL, AX, or EAX register is assumed to be the destination operand. The size of the source and destination operands is selected with the mnemonic: LODSB (byte loaded into register AL), LODSW (word loaded into AX), or LODSD (doubleword loaded into EAX).

After the byte, word, or doubleword is transferred from the memory location into the AL, AX, or EAX register, the (E)SI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)SI register is incremented; if the DF flag is 1, the ESI register is decremented.) The (E)SI register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword operations.

The LODS, LODSB, LODSW, and LODSD instructions can be preceded by the REP prefix for block loads of ECX bytes, words, or doublewords. More often, however, these instructions are used within a LOOP construct because further processing of the data moved into the register is usually necessary before the next transfer can be made. See "REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix" in this chapter for a description of the REP prefix.

Operands Bytes Clocks
all variants 1 2 NP

Flags
None.
+$#KLOOP - Loop According to ECX Counter
E2 cb LOOP rel8 Decrement count; jump short if count ¹ 0
E1 cb LOOPE rel8 Decrement count; jump short if count ¹ 0 and ZF=1
E1 cb LOOPZ rel8 Decrement count; jump short if count ¹ 0 and ZF=1
E0 cb LOOPNE rel8 Decrement count; jump short if count ¹ 0 and ZF=0
E0 cb LOOPNZ rel8 Decrement count; jump short if count ¹ 0 and ZF=0

Description
Performs a loop operation using the ECX or CX register as a counter. Each time the LOOP instruction is executed, the count register is decremented, then checked for 0. If the count is 0, the loop is terminated and program execution continues with the instruction following the LOOP instruction. If the count is not zero, a near jump is performed to the destination (target) operand, which is presumably the instruction at the beginning of the loop. If the address-size attribute is 32 bits, the ECX register is used as the count register; otherwise the CX register is used.

The target instruction is specified with a relative offset (a signed offset relative to the current value of the instruction pointer in the EIP register). This offset is generally specified as a label in assembly code, but at the machine code level, it is encoded as a signed, 8-bit immediate value, which is added to the instruction pointer. Offsets of -128 to +127 are allowed with this instruction.

Some forms of the loop instruction (LOOPcc) also accept the ZF flag as a condition for terminating the loop before the count reaches zero. With these forms of the instruction, a condition code (cc) is associated with each instruction to indicate the condition being tested for. Here, the LOOPcc instruction itself does not affect the state of the ZF flag; the ZF flag is changed by other instructions in the loop.

Operands Bytes Clocks
short 2 5/6 NP

Flags
None.
+$#KLOOPcc - Loop According to ECX Counter

Usage: LOOPcc label

Description
See LOOPMM81W4

Operands Bytes Clocks
2 7/8 NP
+$#KLSL - Load Segment Limit
0F 03 / r LSL r16,r/m16 Load: r16 ¬ segment limit, selector r/m16
0F 03 / r LSL r32,r/m32 Load: r32 ¬ segment limit, selector r/m32)

Description
Loads the unscrambled segment limit from the segment descriptor specified with the second operand (source operand) into the first operand (destination operand) and sets the ZF flag in the EFLAGS register. The source operand (which can be a register or a memory location) contains the segment selector for the segment descriptor being accessed. The destination operand is a general-purpose register.

The processor performs access checks as part of the loading process. Once loaded in the destination register, software can compare the segment limit with the offset of a pointer.

The segment limit is a 20-bit value contained in bytes 0 and 1 and in the first 4 bits of byte 6 of the segment descriptor. If the descriptor has a byte granular segment limit (the granularity flag is set to 0), the destination operand is loaded with a byte granular value (byte limit). If the descriptor has a page granular segment limit (the granularity flag is set to 1), the LSL instruction will translate the page granular limit (page limit) into a byte limit before loading it into the desti-nation operand. The translation is performed by shifting the 20-bit "raw" limit left 12 bits and filling the low-order 12 bits with 1s.

When the operand size is 32 bits, the 32-bit byte limit is stored in the destination operand. When the operand size is 16 bits, a valid 32-bit limit is computed; however, the upper 16 bits are trun-cated and only the low-order 16 bits are loaded into the destination operand.

This instruction performs the following checks before it loads the segment limit into the desti-nation register:

· Checks that the segment selector is not null.
· Checks that the segment selector points to a descriptor that is within the limits of the GDT or LDT being accessed
· Checks that the descriptor type is valid for this instruction. All code and data segment descriptors are valid for (can be accessed with) the LSL instruction. The valid special segment and gate descriptor types are given in the following table.
· If the segment is not a conforming code segment, the instruction checks that the specified segment descriptor is visible at the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to the DPL of the segment selector).

If the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no value is loaded in the destination operand.

Type Name Valid
0 Reserved No
1 Available 16-bit TSS Yes
2 LDT Yes
3 Busy 16-bit TSS Yes
4 16-bit call gate No
5 16-bit/32-bit task gate No
6 16-bit interrupt gate No
7 16-bit trap gate No
8 Reserved No
9 Available 32-bit TSS Yes
A Reserved No
B Busy 32-bit TSS Yes
C 32-bit call gate No
D Reserved No
E 32-bit interrupt gate No
F 32-bit trap gate No

Operands Bytes Clocks
r16, r16 3 8 NP
r32, r32 3 8 NP
r16, m16 3+d(0,2) 8 NP
r32, m32 3+d(0,2) 8 NP

Flags
The ZF flag is set to 1 if the segment limit is loaded successfully; otherwise, it is cleared to 0.
+$#KLTR - Load Task Register
0F 00 /3 LTR r/m16 Load r/m16 into task register

Description
Loads the source operand into the segment selector field of the task register. The source operand (a general-purpose register or a memory location) contains a segment selector that points to a task state segment (TSS). After the segment selector is loaded in the task register, the processor uses the segment selector to locate the segment descriptor for the TSS in the global descriptor table (GDT). It then loads the segment limit and base address for the TSS from the segment descriptor into the task register. The task pointed to by the task register is marked busy, but a switch to the task does not occur.

The LTR instruction is provided for use in operating-system software; it should not be used in application programs. It can only be executed in protected mode when the CPL is 0. It is commonly used in initialization code to establish the first task to be executed.

The operand-size attribute has no effect on this instruction.

Operands Bytes Clocks
r16 3 10 NP
mem16 3+d(0,2) 10 NP

Flags
None.
+$#KMOV - Move
88 / r MOV r/m8,r8 Move r8 to r/m8
89 / r MOV r/m16,r16 Move r16 to r/m16
89 / r MOV r/m32,r32 Move r32 to r/m32
8A / r MOV r8,r/m8 Move r/m8 to r8
8B / r MOV r16,r/m16 Move r/m16 to r16
8B / r MOV r32,r/m32 Move r/m32 to r32
8C / r MOV r/m16,Sreg** Move segment register to r/m16
8E / r MOV Sreg,r/m16** Move r/m16 to segment register
A0 MOV AL, moffs8* Move byte at ( seg:offset) to AL
A1 MOV AX, moffs16* Move word at ( seg:offset) to AX
A1 MOV EAX, moffs32* Move doubleword at ( seg:offset) to EAX
A2 MOV moffs8*,AL Move AL to ( seg:offset)
A3 MOV moffs16*,AX Move AX to ( seg:offset)
A3 MOV moffs32*,EAX Move EAX to ( seg:offset)
B0+ rb MOV r8,imm8 Move imm8 to r8
B8+ rw MOV r16,imm16 Move imm16 to r16
B8+ rd MOV r32,imm32 Move imm32 to r32
C6 / 0 MOV r/m8,imm8 Move imm8 to r/m8
C7 / 0 MOV r/m16,imm16 Move imm16 to r/m16
C7 / 0 MOV r/m32,imm32 Move imm32 to r/m32
NOTES:
*The moffs8, moffs16, and moffs32 operands specify a simple offset relative to the segment base, where 8, 16, and 32 refer to the size of the data. The address-size attribute of the instruction determines the size of the offset, either 16 or 32 bits.
** In 32-bit mode, the assembler may insert the 16-bit operand-size prefix with this instruction (see the following “Description” section for further information).

Description
Copies the second operand (source operand) to the first operand (destination operand). The source operand can be an immediate value, general-purpose register, segment register, or memory location; the destination register can be a general-purpose register, segment register, or memory location. Both operands must be the same size, which can be a byte, a word, or a doubleword.

The MOV instruction cannot be used to load the CS register. Attempting to do so results in an invalid opcode exception (#UD). To load the CS register, use the far JMP, CALL, or RET instruction.

If the destination operand is a segment register (DS, ES, FS, GS, or SS), the source operand must be a valid segment selector. In protected mode, moving a segment selector into a segment register automatically causes the segment descriptor information associated with that segment selector to be loaded into the hidden (shadow) part of the segment register. While loading this information, the segment selector and segment descriptor information is validated (see the "Operation" algorithm below). The segment descriptor data is obtained from the GDT or LDT entry for the specified segment selector.

A null segment selector (values 0000-0003) can be loaded into the DS, ES, FS, and GS registers without causing a protection exception. However, any subsequent attempt to reference a segment whose corresponding segment register is loaded with a null value causes a general protection exception (#GP) and no memory reference occurs.

Loading the SS register with a MOV instruction inhibits all interrupts until after the execution of the next instruction. This operation allows a stack pointer to be loaded into the ESP register with the next instruction (MOV ESP, stack-pointer value) before an interrupt occurs 1 . The LSS instruction offers a more efficient method of loading the SS and ESP registers.

When operating in 32-bit mode and moving data between a segment register and a general-purpose register, the Intel Architecture 32-bit processors do not require the use of the 16-bit operand-size prefix (a byte with the value 66H) with this instruction, but most assemblers will insert it if the standard form of the instruction is used (for example, MOV DS, AX). The processor will execute this instruction correctly, but it will usually require an extra clock. With most assemblers, using the instruction form MOV DS, EAX will avoid this unneeded 66H prefix. When the processor executes the instruction with a 32-bit general-purpose register, it assumes that the 16 least-significant bits of the general-purpose register are the destination or source operand. If the register is a destination operand, the resulting value in the two high-order bytes of the register is implementation dependent. For the Pentium Pro processor, the two high-order bytes are filled with zeros; for earlier 32-bit Intel Architecture processors, the two high order bytes are undefined.

Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2+d(0-2) 1 UV
reg, mem 2+d(0-2) 1 UV
mem, imm 2+d(0-2)+i(1,2) 1 UV*
reg, imm 2+i(1,2) 1 UV
acc, mem 3 1 UV
mem, acc 3 1 UV

* = not pairable if there is a displacement and immediate

Segment Register Moves

Real Mode
seg, r16 2 2-11 NP
seg, m16 2+d(0,2) 3-12 NP
r16, seg 2 1 NP
m16, seg 2+d(0,2) 1 NP

Protected Mode Differences
seg, r16 2 2-11* NP
seg, m16 2+d(0,2) 3-12* NP
* = add 8 if new descriptor; add 6 if SS

MOVE to/from special registers
r32, cr32 3 4 NP
cr32, r32 3 12/22* NP

r32, dr32 3 2/12* NP
dr32, r32 3 11/12* NP

r32, tr32 3 - NP
tr32, r32 3 - NP

* = cycles depend on which special register

Flags
None.
+$#KMOV - Move to/from Control Registers
0F 22 / r MOV CR0, r32 Move r32 to CR0
0F 22 / r MOV CR2, r32 Move r32 to CR2
0F 22 / r MOV CR3, r32 Move r32 to CR3
0F 22 / r MOV CR4, r32 Move r32 to CR4
0F 20 / r MOV r32,CR0 Move CR0 to r32
0F 20 / r MOV r32,CR2 Move CR2 to r32
0F 20 / r MOV r32,CR3 Move CR3 to r32
0F 20 / r MOV r32,CR4 Move CR4 to r32

Description
Moves the contents of a control register (CR0, CR2, CR3, or CR4) to a general-purpose register or vice versa. The operand size for these instructions is always 32 bits, regardless of the operand-size attribute. (See "Control Registers" in Chapter 2 of the Intel Architecture Software Devel-oper's Manual, Volume 3, for a detailed description of the flags and fields in the control regis-ters.)

When loading a control register, a program should not attempt to change any of the reserved bits; that is, always set reserved bits to the value previously read.

At the opcode level, the reg field within the ModR/M byte specifies which of the control registers is loaded or read. The 2 bits in the mod field are always 11B. The r/m field specifies the general-purpose register loaded or read.

These instructions have the following side effects:

· When writing to control register CR3, all non-global TLB entries are flushed (see "Translation Lookaside Buffers (TLBs)" in Chapter 3 of the Intel Architecture Software Developer's Manual, Volume 3).

Operands Bytes Clocks
See MOVCW30O

Flags
The OF, SF, ZF, AF, PF, and CF flags are undefined.

+$#KMOV - Move to/from Debug Registers
0F 21/ r MOV r32, DR0-DR7 Move debug register to r32
0F 23 / r MOV DR0-DR7, r32 Move r32 to debug register

Description
Moves the contents of a debug register (DR0, DR1, DR2, DR3, DR4, DR5, DR6, or DR7) to a general-purpose register or vice versa. The operand size for these instructions is always 32 bits, regardless of the operand-size attribute. (See Chapter 14, Debugging and Performance Monitoring, of the Intel Architecture Software Developer's Manual, Volume 3, for a detailed description of the flags and fields in the debug registers.)

The instructions must be executed at privilege level 0 or in real-address mode.

When the debug extension (DE) flag in register CR4 is clear, these instructions operate on debug registers in a manner that is compatible with Intel386 and Intel486 processors. In this mode, references to DR4 and DR5 refer to DR6 and DR7, respectively. When the DE set in CR4 is set, attempts to reference DR4 and DR5 result in an undefined opcode (#UD) exception. (The CR4 register was added to the Intel Architecture beginning with the Pentium processor.)

At the opcode level, the reg field within the ModR/M byte specifies which of the debug registers is loaded or read. The two bits in the mod field are always 11. The r/m field specifies the general-purpose register loaded or read.

Operands Bytes Clocks
See MOVCW3CO

Flags
The OF, SF, ZF, AF, PF, and CF flags are undefined.+$#KMOVS/MOVSB/MOVSW/MOVSD - Move Data from String to String
A4 MOVS m8, m8 Move byte at address DS:(E)SI to address ES:(E)DI
A5 MOVS m16, m16 Move word at address DS:(E)SI to address ES:(E)DI
A5 MOVS m32, m32 Move doubleword at address DS:(E)SI to address
ES:(E)DI
A4 MOVSB Move byte at address DS:(E)SI to address ES:(E)DI
A5 MOVSW Move word at address DS:(E)SI to address ES:(E)DI
A5 MOVSD Move doubleword at address DS:(E)SI to address
ES:(E)DI

Description
Moves the byte, word, or doubleword specified with the second operand (source operand) to the location specified with the first operand (destination operand). Both the source and destination operands are located in memory. The address of the source operand is read from the DS:ESI or the DS:SI registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). The address of the destination operand is read from the ES:EDI or the ES:DI registers (again depending on the address-size attribute of the instruction). The DS segment may be over-ridden with a segment override prefix, but the ES segment cannot be overridden.

At the assembly-code level, two forms of this instruction are allowed: the "explicit-operands" form and the "no-operands" form. The explicit-operands form (specified with the MOVS mnemonic) allows the source and destination operands to be specified explicitly. Here, the source and destination operands should be symbols that indicate the size and location of the source value and the destination, respectively. This explicit-operands form is provided to allow documentation; however, note that the documentation provided by this form can be misleading. That is, the source and destination operand symbols must specify the correct type (size) of the operands (bytes, words, or doublewords), but they do not have to specify the correct location. The locations of the source and destination operands are always specified by the DS:(E)SI and ES:(E)DI registers, which must be loaded correctly before the move string instruction is executed.

The no-operands form provides "short forms" of the byte, word, and doubleword versions of the MOVS instructions. Here also DS:(E)SI and ES:(E)DI are assumed to be the source and destination operands, respectively. The size of the source and destination operands is selected with the mnemonic: MOVSB (byte move), MOVSW (word move), or MOVSD (doubleword move).

After the move operation, the (E)SI and (E)DI registers are incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)SI and (E)DI register are incremented; if the DF flag is 1, the (E)SI and (E)DI registers are decremented.) The registers are incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword operations.

The MOVS, MOVSB, MOVSW, and MOVSD instructions can be preceded by the REP prefix (see "REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix" in this chapter) for block moves of ECX bytes, words, or doublewords.

Variations Bytes Clocks
movsb 1 4 NP
movsw 1 4 NP
movsd 1 4 NP
rep movsb 2 3+n NP
rep movsw 2 3+n NP
rep movsd 2 3+n NP

(n = count of bytes, words or dwords)

Flags
None.
+$#KMOVSX - Move with Sign-Extension
0F BE / r MOVSX r16,r/m8 Move byte to word with sign-extension
0F BE / r MOVSX r32,r/m8 Move byte to doubleword, sign-extension
0F BF / r MOVSX r32,r/m16 Move word to doubleword, sign-extension

Description
Copies the contents of the source operand (register or memory location) to the destination operand (register) and sign extends the value to 16 or 32 bits (see Figure 6-5 in the Intel Architecture Software Developer's Manual, Volume 1). The size of the converted value depends on the operand-size attribute.

Operands Bytes Clocks
reg, reg 3 3 NP
reg, mem 3+d(0,1,2,4) 3 NP
(Note: destination reg is 16 or 32-bits; source is 8 or 16 bits)

Flags
None.
+$#KMOVZX - Move with Zero-Extend
0F B6 / r MOVZX r16,r/m8 Move byte to word with zero-extension
0F B6 / r MOVZX r32,r/m8 Move byte to doubleword, zero-extension
0F B7 / r MOVZX r32,r/m16 Move word to doubleword, zero-extension

Description
Copies the contents of the source operand (register or memory location) to the destination operand (register) and zero extends the value to 16 or 32 bits. The size of the converted value depends on the operand-size attribute.

Operands Bytes Clocks
reg, reg 3 3 NP
reg, mem 3+d(0,1,2,4) 3 NP
(Note: destination reg is 16 or 32-bits; source is 8 or 16 bits)

Flags
None.
+$#KMUL - Unsigned Multiply
F6 /4 MUL r/m8 Unsigned multiply (AX ¬ AL * r/m8)
F7 /4 MUL r/m16 Unsigned multiply (DX:AX ¬ AX * r/m16)
F7 /4 MUL r/m32 Unsigned multiply (EDX:EAX ¬ EAX * r/m32)

Description
Performs an unsigned multiplication of the first operand (destination operand) and the second operand (source operand) and stores the result in the destination operand. The destination operand is an implied operand located in register AL, AX or EAX (depending on the size of the operand); the source operand is located in a general-purpose register or a memory location. The action of this instruction and the location of the result depends on the opcode and the operand size as shown in the following table.

Operand Size Source 1 Source 2 Destination
Byte AL r/m8 AX
Word AX r/m16 DX:AX
Doubleword EAX r/m32 EDX:EAX

The result is stored in register AX, register pair DX:AX, or register pair EDX:EAX (depending on the operand size), with the high-order bits of the product contained in register AH, DX, or EDX, respectively. If the high-order bits of the product are 0, the CF and OF flags are cleared; otherwise, the flags are set.

Operands Bytes Clocks
r8 2 11 NP
r16 2 11 NP
r32 2 10 NP
mem8 2+d(0-2) 11 NP
mem16 2+d(0-2) 11 NP
mem32 2+d(0-2) 10 NP

implied operand result
multiplicand (multiplier)
AL * byte = AX
AX * word = DX:AX
EAX * dword = EDX:EAX

Flags
The OF and CF flags are cleared to 0 if the upper half of the result is 0; otherwise, they are set to 1. The SF, ZF, AF, and PF flags are undefined.
+$#KNEG - Two's Complement Negation
F6 /3 NEG r/m8 Two's complement negate r/m8
F7 /3 NEG r/m16 Two's complement negate r/m16
F7 /3 NEG r/m32 Two's complement negate r/m32

Description
Replaces the value of operand (the destination operand) with its two's complement. (This operation is equivalent to subtracting the operand from 0.) The destination operand is located in a general-purpose register or a memory location.

Operands Bytes Clocks
reg 2 1 NP
mem 2+d(0-2) 3 NP

Flags
The CF flag cleared to 0 if the source operand is 0; otherwise it is set to 1. The OF, SF, ZF, AF, and PF flags are set according to the result.
+$#KNOP - No Operation
90 NOP No operation

Description
Performs no operation. This instruction is a one-byte instruction that takes up space in the instruction stream but does not affect the machine context, except the EIP register.

The NOP instruction is an alias mnemonic for the XCHG (E)AX, (E)AX instruction.

Operands Bytes Clocks
1 1 UV

Flags
None.
+$#KNOT - One's Complement Negation
F6 /2 NOT r/m8 Reverse each bit of r/m8
F7 /2 NOT r/m16 Reverse each bit of r/m16
F7 /2 NOT r/m32 Reverse each bit of r/m32

Description
Performs a bitwise NOT operation (each 1 is cleared to 0, and each 0 is set to 1) on the destination operand and stores the result in the destination operand location. The destination operand can be a register or a memory location.

Operands Bytes Clocks
reg 2 1 NP
mem 2+d(0-2) 3 NP

Flags
None.
+$#KOR - Logical Inclusive OR
0C ib OR AL, imm8 AL OR imm8
0D iw OR AX, imm16 AX OR imm16
0D id OR EAX, imm32 EAX OR imm32
80 /1 ib OR r/m8,imm8 r/m8 OR imm8
81 /1 iw OR r/m16,imm16 r/m16 OR imm16
81 /1 id OR r/m32,imm32 r/m32 OR imm32
83 /1 ib OR r/m16,imm8 r/m16 OR imm8 (sign-extended)
83 /1 ib OR r/m32,imm8 r/m32 OR imm8 (sign-extended)
08 / r OR r/m8,r8 r/m8 OR r8
09 / r OR r/m16,r16 r/m16 OR r16
09 / r OR r/m32,r32 r/m32 OR r32
0A / r OR r8,r/m8 r8 OR r/m8
0B / r OR r16,r/m16 r16 OR r/m16
0B / r OR r32,r/m32 r32 OR r/m32

Description
Performs a bitwise inclusive OR operation between the destination (first) and source (second) operands and stores the result in the destination operand location. The source operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location. (However, two memory operands cannot be used in one instruction.) Each bit of the result of the OR instruction is 0 if both corresponding bits of the operands are 0; otherwise, each bit is 1.

Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2+d(0,2) 3 UV
reg, mem 2+d(0,2) 2 UV
reg, imm 2+i(1,2) 1 UV
mem, imm 2+d(0,2)+i(1,2) 3 UV*
acc, imm 1+i(1,2) 1 UV

* = not pairable if there is a displacement and immediate

Flags
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is undefined.
+$#KOUT - Output to Port
E6 ib OUT imm8, AL Output byte in AL to I/O port address imm8
E7 ib OUT imm8, AX Output word in AX to I/O port address imm8
E7 ib OUT imm8, EAX Output doubleword in EAX to I/O port address imm8
EE OUT DX, AL Output byte in AL to I/O port address in DX
EF OUT DX, AX Output word in AX to I/O port address in DX
EF OUT DX, EAX Output doubleword in EAX to I/O port address in DX

Description
Copies the value from the second operand (source operand) to the I/O port specified with the destination operand (first operand). The source operand can be register AL, AX, or EAX, depending on the size of the port being accessed (8, 16, or 32 bits, respectively); the destination operand can be a byte-immediate or the DX register. Using a byte immediate allows I/O port addresses 0 to 255 to be accessed; using the DX register as a source operand allows I/O ports from 0 to 65,535 to be accessed.

The size of the I/O port being accessed is determined by the opcode for an 8-bit I/O port or by the operand-size attribute of the instruction for a 16- or 32-bit I/O port.

At the machine code level, I/O instructions are shorter when accessing 8-bit I/O ports. Here, the upper eight bits of the port address will be 0.

This instruction is only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 9, Input/Output, in the Intel Architecture Software Developer's Manual, Vo l u me 1 , for more information on accessing I/O ports in the I/O address space.

Operands Bytes Clocks
imm8, al 2 12 NP
imm8, ax 2 12 NP
imm8, eax 2 12 NP
dx, al 1 12 NP
dx, ax 1 12 NP
dx, eax 1 12 NP

Protected Mode
imm8, acc 2 9/26/24 NP
dx, acc 1 9/26/24 NP

cycles for: CPL <= IOPL / CPL > IOPL / V86

Flags
None.
+$#KOUTS/OUTSB/OUTSW/OUTSD - Output String to Port
6E OUTS DX, m8 Output byte from memory location specified in DS:(E)SI to
I/O port specified in DX
6F OUTS DX, m16 Output word from memory location specified in DS:(E)SI
to I/O port specified in DX
6F OUTS DX, m32 Output doubleword from memory location specified in
DS:(E)SI to I/O port specified in DX
6E OUTSB Output byte from memory location specified in DS:(E)SI to
I/O port specified in DX
6F OUTSW Output word from memory location specified in DS:(E)SI
to I/O port specified in DX
6F OUTSD Output doubleword from memory location specified in
DS:(E)SI to I/O port specified in DX

Description
Copies data from the source operand (second operand) to the I/O port specified with the destination operand (first operand). The source operand is a memory location, the address of which is read from either the DS:EDI or the DS:DI registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). (The DS segment may be overridden with a segment override prefix.) The destination operand is an I/O port address (from 0 to 65,535) that is read from the DX register. The size of the I/O port being accessed (that is, the size of the source and destination operands) is determined by the opcode for an 8-bit I/O port or by the operand-size attribute of the instruction for a 16- or 32-bit I/O port.

At the assembly-code level, two forms of this instruction are allowed: the "explicit-operands" form and the "no-operands" form. The explicit-operands form (specified with the OUTS mnemonic) allows the source and destination operands to be specified explicitly. Here, the source operand should be a symbol that indicates the size of the I/O port and the source address, and the destination operand must be DX. This explicit-operands form is provided to allow docu-mentation; however, note that the documentation provided by this form can be misleading. That is, the source operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does not have to specify the correct location. The location is always spec-ified by the DS:(E)SI registers, which must be loaded correctly before the OUTS instruction is executed.

The no-operands form provides "short forms" of the byte, word, and doubleword versions of the OUTS instructions. Here also DS:(E)SI is assumed to be the source operand and DX is assumed to be the destination operand. The size of the I/O port is specified with the choice of mnemonic: OUTSB (byte), OUTSW (word), or OUTSD (doubleword).

After the byte, word, or doubleword is transferred from the memory location to the I/O port, the (E)SI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)SI register is incremented; if the DF flag is 1, the (E)SI register is decremented.) The (E)SI register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword operations.

The OUTS, OUTSB, OUTSW, and OUTSD instructions can be preceded by the REP prefix for block input of ECX bytes, words, or doublewords. See "REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix" in this chapter for a description of the REP prefix.

This instruction is only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 9, Input/Output, in the Intel Architecture Software Developer's Manual, Vo l u me 1 , for more information on accessing I/O ports in the I/O address space.

Variations Bytes Clocks
outsb 1 13 NP
outsw 1 13 NP
outsd 1 13 NP

Protected Mode
1 10/27/25 NP

cycles for: CPL <= IOPL / CPL > IOPL / V86

Flags
None.
+$#KPOP - Pop a Value from the Stack
8F /0 POP m16 Pop top of stack into m16; increment stack pointer
8F /0 POP m32 Pop top of stack into m32; increment stack pointer
58+ rw POP r16 Pop top of stack into r16; increment stack pointer
58+ rd POP r32 Pop top of stack into r32; increment stack pointer
1F POP DS Pop top of stack into DS; increment stack pointer
07 POP ES Pop top of stack into ES; increment stack pointer
17 POP SS Pop top of stack into SS; increment stack pointer
0F A1 POP FS Pop top of stack into FS; increment stack pointer
0F A9 POP GS Pop top of stack into GS; increment stack pointer

Description
Loads the value from the top of the stack to the location specified with the destination operand and then increments the stack pointer. The destination operand can be a general-purpose register, memory location, or segment register.

The address-size attribute of the stack segment determines the stack pointer size (16 bits or 32 bits-the source address size), and the operand-size attribute of the current code segment deter-mines the amount the stack pointer is incremented (2 bytes or 4 bytes). For example, if these address- and operand-size attributes are 32, the 32-bit ESP register (stack pointer) is incre-mented by 4 and, if they are 16, the 16-bit SP register is incremented by 2. (The B flag in the stack segment's segment descriptor determines the stack's address-size attribute, and the D flag in the current code segment's segment descriptor, along with prefixes, determines the operand-size attribute and also the address-size attribute of the destination operand.)

If the destination operand is one of the segment registers DS, ES, FS, GS, or SS, the value loaded into the register must be a valid segment selector. In protected mode, popping a segment selector into a segment register automatically causes the descriptor information associated with that segment selector to be loaded into the hidden (shadow) part of the segment register and causes the selector and the descriptor information to be validated (see the "Operation" section below).

A null value (0000-0003) may be popped into the DS, ES, FS, or GS register without causing a general protection fault. However, any subsequent attempt to reference a segment whose corre-sponding segment register is loaded with a null value causes a general protection exception (#GP). In this situation, no memory reference occurs and the saved value of the segment register is null.

The POP instruction cannot pop a value into the CS register. To load the CS register from the stack, use the RET instruction.

If the ESP register is used as a base register for addressing a destination operand in memory, the POP instruction computes the effective address of the operand after it increments the ESP register.

The POP ESP instruction increments the stack pointer (ESP) before data at the old top of stack is written into the destination.

A POP SS instruction inhibits all interrupts, including the NMI interrupt, until after execution of the next instruction. This action allows sequential execution of POP SS and MOV ESP, EBP instructions without the danger of having an invalid stack during an interrupt 1 . However, use of the LSS instruction is the preferred method of loading the SS and ESP registers.

Operands Bytes Clocks
reg 1 1 UV
mem 2+d(0-2) 3 NP
seg 1 3 NP
FS/GS 2 3 NP

Protected Mode
CS/DS/ES 1 3-12 NP
SS 1 8-17 NP
FS/GS 2 3-12 NP

Flags
None.
+$#KPOPA/POPAD - Pop All General-Purpose Registers
61 POPA Pop DI, SI, BP, BX, DX, CX, and AX
61 POPAD Pop EDI, ESI, EBP, EBX, EDX, ECX, and EAX

Description
Pops doublewords (POPAD) or words (POPA) from the stack into the general-purpose registers. The registers are loaded in the following order: EDI, ESI, EBP, EBX, EDX, ECX, and EAX (if the operand-size attribute is 32) and DI, SI, BP, BX, DX, CX, and AX (if the operand-size attribute is 16). (These instructions reverse the operation of the PUSHA/PUSHAD instructions.) The value on the stack for the ESP or SP register is ignored. Instead, the ESP or SP register is incremented after each register is loaded.

The POPA (pop all) and POPAD (pop all double) mnemonics reference the same opcode. The POPA instruction is intended for use when the operand-size attribute is 16 and the POPAD instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when POPA is used and to 32 when POPAD is used (using the operand-size override prefix [66H] if necessary). Others may treat these mnemonics as synonyms (POPA/POPAD) and use the current setting of the operand-size attribute to determine the size of values to be popped from the stack, regardless of the mnemonic used. (The D flag in the current code segment's segment descriptor determines the operand-size attribute.)

Variations Bytes Clocks
popa 1 5 NP
popad 1 5 NP

popa = pop di, si, bp, sp, bx, dx, cx, ax
popad = pop edi, esi, ebp, esp, ebx, edx, ecx, eax
(sp and esp are discarded)

Flags
None.
+$#KPOPF/POPFD - Pop Stack into EFLAGS Register
9D POPF Pop top of stack into lower 16 bits of EFLAGS
9D POPFD Pop top of stack into EFLAGS

Description
Pops a doubleword (POPFD) from the top of the stack (if the current operand-size attribute is 32) and stores the value in the EFLAGS register or pops a word from the top of the stack (if the operand-size attribute is 16) and stores it in the lower 16 bits of the EFLAGS register (that is, the FLAGS register). (These instructions reverse the operation of the PUSHF/PUSHFD instructions.)

The POPF (pop flags) and POPFD (pop flags double) mnemonics reference the same opcode. The POPF instruction is intended for use when the operand-size attribute is 16 and the POPFD instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when POPF is used and to 32 when POPFD is used. Others may treat these mnemonics as synonyms (POPF/POPFD) and use the current setting of the operand-size attribute to determine the size of values to be popped from the stack, regardless of the mnemonic used.

The effect of the POPF/POPFD instructions on the EFLAGS register changes slightly, depending on the mode of operation of the processor. When the processor is operating in protected mode at privilege level 0 (or in real-address mode, which is equivalent to privilege level 0), all the non-reserved flags in the EFLAGS register except the VIP, VIF, and VM flags can be modified. The VIP and VIF flags are cleared, and the VM flag is unaffected.

When operating in protected mode, with a privilege level greater than 0, but less than or equal to IOPL, all the flags can be modified except the IOPL field and the VIP, VIF, and VM flags. Here, the IOPL flags are unaffected, the VIP and VIF flags are cleared, and the VM flag is unaffected. The interrupt flag (IF) is altered only when executing at a level at least as privileged as the IOPL. If a POPF/POPFD instruction is executed with insufficient privilege, an exception does not occur, but the privileged bits do not change.

When operating in virtual-8086 mode, the I/O privilege level (IOPL) must be equal to 3 to use POPF/POPFD instructions and the VM, RF, IOPL, VIP, and VIF flags are unaffected. If the IOPL is less than 3, the POPF/POPFD instructions cause a general-protection exception (#GP).

See the section titled "EFLAGS Register" in Chapter 3 of the Intel Architecture Software Developer's Manual, Volume 1, for information about the EFLAGS registers.

Variations Bytes Clocks
popf 1 6 NP
popfd 1 6 NP

Protected Mode
popf 1 4 NP
popfd 1 4 NP

Flags
All flags except the reserved bits and the VM bit.
+$#KPUSH - Push Word or Doubleword Onto the Stack
FF /6 PUSH r/m16 Push r/m16
FF /6 PUSH r/m32 Push r/m32
50+ rw PUSH r16 Push r16
50+ rd PUSH r32 Push r32
6A PUSH imm8 Push imm8
68 PUSH imm16 Push imm16
68 PUSH imm32 Push imm32
0E PUSH CS Push CS
16 PUSH SS Push SS
1E PUSH DS Push DS
06 PUSH ES Push ES
0F A0 PUSH FS Push FS
0F A8 PUSH GS Push GS

Description
Decrements the stack pointer and then stores the source operand on the top of the stack. The address-size attribute of the stack segment determines the stack pointer size (16 bits or 32 bits), and the operand-size attribute of the current code segment determines the amount the stack pointer is decremented (2 bytes or 4 bytes). For example, if these address- and operand-size attributes are 32, the 32-bit ESP register (stack pointer) is decremented by 4 and, if they are 16, the 16-bit SP register is decremented by 2.(The B flag in the stack segment's segment descriptor determines the stack's address-size attribute, and the D flag in the current code segment's segment descriptor, along with prefixes, determines the operand-size attribute and also the address-size attribute of the source operand.) Pushing a 16-bit operand when the stack address-size attribute is 32 can result in a misaligned the stack pointer (that is, the stack pointer is not aligned on a doubleword boundary).

The PUSH ESP instruction pushes the value of the ESP register as it existed before the instruction was executed. Thus, if a PUSH instruction uses a memory operand in which the ESP register is used as a base register for computing the operand address, the effective address of the operand is computed before the ESP register is decremented.

In the real-address mode, if the ESP or SP register is 1 when the PUSH instruction is executed, the processor shuts down due to a lack of stack space. No exception is generated to indicate this condition.

Operands Bytes Clocks
reg 1 1 UV
mem 2+d(0-2) 2 NP
seg 1 1 NP
imm 1+i(1,2) 1 NP
FS/GS 2 1 NP

Flags
None.
+$#KPUSHA/PUSHAD - Push All General-Purpose Registers
60 PUSHA Push AX, CX, DX, BX, original SP, BP, SI, and DI
60 PUSHAD Push EAX, ECX, EDX, EBX, original ESP, EBP, ESI, and EDI

Description
Pushes the contents of the general-purpose registers onto the stack. The registers are stored on the stack in the following order: EAX, ECX, EDX, EBX, EBP, ESP (original value), EBP, ESI, and EDI (if the current operand-size attribute is 32) and AX, CX, DX, BX, SP (original value), BP, SI, and DI (if the operand-size attribute is 16). (These instructions perform the reverse operation of the POPA/POPAD instructions.) The value pushed for the ESP or SP register is its value before prior to pushing the first register (see the "Operation" section below).

The PUSHA (push all) and PUSHAD (push all double) mnemonics reference the same opcode. The PUSHA instruction is intended for use when the operand-size attribute is 16 and the PUSHAD instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when PUSHA is used and to 32 when PUSHAD is used. Others may treat these mnemonics as synonyms (PUSHA/PUSHAD) and use the current setting of the operand-size attribute to determine the size of values to be pushed from the stack, regardless of the mnemonic used.

In the real-address mode, if the ESP or SP register is 1, 3, or 5 when the PUSHA/PUSHAD instruction is executed, the processor shuts down due to a lack of stack space. No exception is generated to indicate this condition.

Variations Bytes Clocks
pusha 1 5 NP
pushad 1 5 NP

pusha = push ax, cx, dx, bx, sp, bp, si, di,
pushad = push eax, ecx, edx, ebx, esp, ebp, esi, edi

Flags
None.
+$#KPUSHF/PUSHFD - Push EFLAGS Register onto the Stack
9C PUSHF Push lower 16 bits of EFLAGS
9C PUSHFD Push EFLAGS

Description
Decrements the stack pointer by 4 (if the current operand-size attribute is 32) and pushes the entire contents of the EFLAGS register onto the stack, or decrements the stack pointer by 2 (if the operand-size attribute is 16) and pushes the lower 16 bits of the EFLAGS register (that is, the FLAGS register) onto the stack. (These instructions reverse the operation of the POPF/POPFD instructions.) When copying the entire EFLAGS register to the stack, the VM and RF flags (bits 16 and 17) are not copied; instead, the values for these flags are cleared in the EFLAGS image stored on the stack. See the section titled "EFLAGS Register" in Chapter 3 of the Intel Architecture Software Developer's Manual, Volume 1, for information about the EFLAGS registers.

The PUSHF (push flags) and PUSHFD (push flags double) mnemonics reference the same opcode. The PUSHF instruction is intended for use when the operand-size attribute is 16 and the PUSHFD instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when PUSHF is used and to 32 when PUSHFD is used. Others may treat these mnemonics as synonyms (PUSHF/PUSHFD) and use the current setting of the operand-size attribute to determine the size of values to be pushed from the stack, regardless of the mnemonic used.

When in virtual-8086 mode and the I/O privilege level (IOPL) is less than 3, the PUSHF/PUSHFD instruction causes a general protection exception (#GP).

In the real-address mode, if the ESP or SP register is 1, 3, or 5 when the PUSHA/PUSHAD instruction is executed, the processor shuts down due to a lack of stack space. No exception is generated to indicate this condition.

Variations Bytes Clocks
pushf 1 9 NP
pushfd 1 9 NP

Protected Mode
pushf 1 3 NP
pushfd 1 3 NP

Flags
None.
+$#KRCL - Rotate Bits Left with CF
D0 /2 RCL r/m8,1 Rotate 9 bits (CF, r/m8) left once
D2 /2 RCL r/m8,CL Rotate 9 bits (CF, r/m8) left CL times
C0 /2 ib RCL r/m8,imm8 Rotate 9 bits (CF, r/m8) left imm8 times
D1 /2 RCL r/m16,1 Rotate 17 bits (CF, r/m16) left once
D3 /2 RCL r/m16,CL Rotate 17 bits (CF, r/m16) left CL times
C1 /2 ib RCL r/m16,imm8 Rotate 17 bits (CF, r/m16) left imm8 times
D1 /2 RCL r/m32,1 Rotate 33 bits (CF, r/m32) left once
D3 /2 RCL r/m32,CL Rotate 33 bits (CF, r/m32) left CL times
C1 /2 ib RCL r/m32,imm8 Rotate 33 bits (CF, r/m32) left imm8 times
D0 /3 RCR r/m8,1 Rotate 9 bits (CF, r/m8) right once
D2 /3 RCR r/m8,CL Rotate 9 bits (CF, r/m8) right CL times
C0 /3 ib RCR r/m8,imm8 Rotate 9 bits (CF, r/m8) right imm8 times
D1 /3 RCR r/m16,1 Rotate 17 bits (CF, r/m16) right once
D3 /3 RCR r/m16,CL Rotate 17 bits (CF, r/m16) right CL times
C1 /3 ib RCR r/m16,imm8 Rotate 17 bits (CF, r/m16) right imm8 times
D1 /3 RCR r/m32,1 Rotate 33 bits (CF, r/m32) right once
D3 /3 RCR r/m32,CL Rotate 33 bits (CF, r/m32) right CL times
C1 /3 ib RCR r/m32,imm8 Rotate 33 bits (CF, r/m32) right imm8 times
D0 /0 ROL r/m8,1 Rotate 8 bits r/m8 left once
D2 /0 ROL r/m8,CL Rotate 8 bits r/m8 left CL times
C0 /0 ib ROL r/m8,imm8 Rotate 8 bits r/m8 left imm8 times
D1 /0 ROL r/m16,1 Rotate 16 bits r/m16 left once
D3 /0 ROL r/m16,CL Rotate 16 bits r/m16 left CL times
C1 /0 ib ROL r/m16,imm8 Rotate 16 bits r/m16 left imm8 times
D1 /0 ROL r/m32,1 Rotate 32 bits r/m32 left once
D3 /0 ROL r/m32,CL Rotate 32 bits r/m32 left CL times
C1 /0 ib ROL r/m32,imm8 Rotate 32 bits r/m32 left imm8 times
D0 /1 ROR r/m8,1 Rotate 8 bits r/m8 right once
D2 /1 ROR r/m8,CL Rotate 8 bits r/m8 right CL times
C0 /1 ib ROR r/m8,imm8 Rotate 8 bits r/m16 right imm8 times
D1 /1 ROR r/m16,1 Rotate 16 bits r/m16 right once
D3 /1 ROR r/m16,CL Rotate 16 bits r/m16 right CL times
C1 /1 ib ROR r/m16,imm8 Rotate 16 bits r/m16 right imm8 times
D1 /1 ROR r/m32,1 Rotate 32 bits r/m32 right once
D3 /1 ROR r/m32,CL Rotate 32 bits r/m32 right CL times
C1 /1 ib ROR r/m32,imm8 Rotate 32 bits r/m32 right imm8 times

Description
Shifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the second operand (count operand) and stores the result in the destination operand. The destination operand can be a register or a memory location; the count operand is an unsigned integer that can be an immediate or a value in the CL register. The processor restricts the count to a number between 0 and 31 by masking all the bits in the count operand except the 5 least-significant bits.

The rotate left (ROL) and rotate through carry left (RCL) instructions shift all the bits toward more-significant bit positions, except for the most-significant bit, which is rotated to the least-significant bit location (see Figure 6-10 in the Intel Architecture Software Developer's Manual, Vo l u me 1 ). The rotate right (ROR) and rotate through carry right (RCR) instructions shift all the bits toward less significant bit positions, except for the least-significant bit, which is rotated to the most-significant bit location (see Figure 6-10 in the Intel Architecture Software Developer's Manual, Volume 1).

The RCL and RCR instructions include the CF flag in the rotation. The RCL instruction shifts the CF flag into the least-significant bit and shifts the most-significant bit into the CF flag (see Figure 6-10 in the Intel Architecture Software Developer's Manual, Volume 1). The RCR instruction shifts the CF flag into the most-significant bit and shifts the least-significant bit into the CF flag (see Figure 6-10 in the Intel Architecture Software Developer's Manual, Volume 1). For the ROL and ROR instructions, the original value of the CF flag is not a part of the result, but the CF flag receives a copy of the bit that was shifted from one end to the other.

The OF flag is defined only for the 1-bit rotates; it is undefined in all other cases (except that a zero-bit rotate does nothing, that is affects no flags). For left rotates, the OF flag is set to the exclusive OR of the CF bit (after the rotate) and the most-significant bit of the result. For right rotates, the OF flag is set to the exclusive OR of the two most-significant bits of the result.

Operands Bytes Clocks
reg, 1 2 1 PU
mem, 1 2+d(0,2) 3 PU
reg, cl 2 7-24 NP
mem, cl 2+d(0,2) 9-26 NP
reg, imm 3 8-25 NP
mem, imm 3+d(0,2) 10-27 NP

Flags
The CF flag contains the value of the bit shifted into it. The OF flag is affected only for single-bit rotates (see "Description" above); it is undefined for multi-bit rotates. The SF, ZF, AF, and PF flags are not affected.
+$#KRCR - Rotate Bits Right with CF

Usage: RCR dest, count

Description
See RCLCW50O

Operands Bytes Clocks
reg, 1 2 1 PU
mem, 1 2+d(0,2) 3 PU
reg, cl 2 7-24 NP
mem, cl 2+d(0,2) 9-26 NP
reg, imm 3 8-25 NP
mem, imm 3+d(0,2) 10-27 NP
+$#KROL - Rotate Bits Left

Usage: ROL dest, count

Description
See RCLCW50O

Operands Bytes Clocks
reg, 1 2 1 PU
mem, 1 2+d(0,2) 3 PU
reg, cl 2 4 NP
mem, cl 2+d(0,2) 4 NP
reg, imm 3 1 PU
mem, imm 3+d(0,2) 3 PU*

* = not pairable if there is a displacement and immediate
+$#KROR - Rotate Bits Right

Usage: ROR dest, count

Description
See RCLCW50O

Operands Bytes Clocks
reg, 1 2 1 PU
mem, 1 2+d(0,2) 3 PU
reg, cl 2 4 NP
mem, cl 2+d(0,2) 4 NP
reg, imm 3 1 PU
mem, imm 3+d(0,2) 3 PU*

* = not pairable if there is a displacement and immediate

+$#KRDMSR - Read from Model Specific Register
0F 32 RDMSR Load MSR specified by ECX into EDX:EAX

Description
Loads the contents of a 64-bit model specific register (MSR) specified in the ECX register into registers EDX:EAX. The EDX register is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. If less than 64 bits are implemented in the MSR being read, the values returned to EDX:EAX in unimplemented bit locations are undefined.

This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) will be generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a general protection exception.

The MSRs control functions for testability, execution tracing, performance-monitoring and machine check errors. Appendix B, Model-Specific Registers (MSRs), in the Intel Architecture Software Developer's Manual, Volume 3, lists all the MSRs that can be read with this instruction and their addresses.

The CPUID instruction should be used to determine whether MSRs are supported (EDX[5]=1) before using this instruction.

Operands Bytes Clocks
2 20-24 NP

Flags
None.
+$#KRDTSC - Read Time-Stamp Counter
0F 31 RDTSC Read time-stamp counter into EDX:EAX

Description
Loads the current value of the processor's time-stamp counter into the EDX:EAX registers. The time-stamp counter is contained in a 64-bit MSR. The high-order 32 bits of the MSR are loaded into the EDX register, and the low-order 32 bits are loaded into the EAX register. The processor increments the time-stamp counter MSR every clock cycle and resets it to 0 whenever the processor is reset.

The time stamp disable (TSD) flag in register CR4 restricts the use of the RDTSC instruction. When the TSD flag is clear, the RDTSC instruction can be executed at any privilege level; when the flag is set, the instruction can only be executed at privilege level 0. The time-stamp counter can also be read with the RDMSR instruction, when executing at privilege level 0.

The RDTSC instruction is not a serializing instruction. Thus, it does not necessarily wait until all previous instructions have been executed before reading the counter. Similarly, subsequent instructions may begin execution before the read operation is performed.

This instruction was introduced into the Intel Architecture in the Pentium processor.

Operands Bytes Clocks
2 6-7 NP

Flags
None.+$#KREP/REPE/REPZ/REPNE/REPNZ - Repeat String Operation Prefix
F3 6C REP INS r/m8, DX Input (E)CX bytes from port DX into ES:[(E)DI]
F3 6D REP INS r/m16,DX Input (E)CX words from port DX into ES:[(E)DI]
F3 6D REP INS r/m32,DX Input (E)CX doublewords from port DX into ES:[(E)DI]
F3 A4 REP MOVS m8,m8 Move (E)CX bytes from DS:[(E)SI] to ES:[(E)DI]
F3 A5 REP MOVS m16,m16 Move (E)CX words from DS:[(E)SI] to ES:[(E)DI]
F3 A5 REP MOVS m32,m32 Move (E)CX doublewords from DS:[(E)SI] to ES:[(E)DI]
F3 6E REP OUTS DX, r/m8 Output (E)CX bytes from DS:[(E)SI] to port DX
F3 6F REP OUTS DX, r/m16 Output (E)CX words from DS:[(E)SI] to port DX
F3 6F REP OUTS DX, r/m32 Output (E)CX doublewords from DS:[(E)SI] to port DX
F3 AC REP LODS AL Load (E)CX bytes from DS:[(E)SI] to AL
F3 AD REP LODS AX Load (E)CX words from DS:[(E)SI] to AX
F3 AD REP LODS EAX Load (E)CX doublewords from DS:[(E)SI] to EAX
F3 AA REP STOS m8 Fill (E)CX bytes at ES:[(E)DI] with AL
F3 AB REP STOS m16 Fill (E)CX words at ES:[(E)DI] with AX
F3 AB REP STOS m32 Fill (E)CX doublewords at ES:[(E)DI] with EAX
F3 A6 REPE CMPS m8,m8 Find nonmatching bytes in ES:[(E)DI] and DS:[(E)SI]
F3 A7 REPE CMPS m16,m16 Find nonmatching words in ES:[(E)DI] and DS:[(E)SI]
F3 A7 REPE CMPS m32,m32 Find nonmatching doublewords in ES:[(E)DI] and DS:[(E)SI]
F3 AE REPE SCAS m8 Find non-AL byte starting at ES:[(E)DI]
F3 AF REPE SCAS m16 Find non-AX word starting at ES:[(E)DI]
F3 AF REPE SCAS m32 Find non-EAX doubleword starting at ES:[(E)DI]
F2 A6 REPNE CMPS m8,m8 Find matching bytes in ES:[(E)DI] and DS:[(E)SI]
F2 A7 REPNE CMPS m16,m16 Find matching words in ES:[(E)DI] and DS:[(E)SI]
F2 A7 REPNE CMPS m32,m32 Find matching doublewords in ES:[(E)DI] and DS:[(E)SI]
F2 AE REPNE SCAS m8 Find AL, starting at ES:[(E)DI]
F2 AF REPNE SCAS m16 Find AX, starting at ES:[(E)DI]
F2 AF REPNE SCAS m32 Find EAX, starting at ES:[(E)DI]

Description
Repeats a string instruction the number of times specified in the count register ((E)CX) or until the indicated condition of the ZF flag is no longer met. The REP (repeat), REPE (repeat while equal), REPNE (repeat while not equal), REPZ (repeat while zero), and REPNZ (repeat while not zero) mnemonics are prefixes that can be added to one of the string instructions. The REP prefix can be added to the INS, OUTS, MOVS, LODS, and STOS instructions, and the REPE, REPNE, REPZ, and REPNZ prefixes can be added to the CMPS and SCAS instructions. (The REPZ and REPNZ prefixes are synonymous forms of the REPE and REPNE prefixes, respectively.) The behavior of the REP prefix is undefined when used with non-string instructions.

The REP prefixes apply only to one string instruction at a time. To repeat a block of instructions, use the LOOP instruction or another looping construct.

All of these repeat prefixes cause the associated instruction to be repeated until the count in register (E)CX is decremented to 0 (see the following table). (If the current address-size attribute is 32, register ECX is used as a counter, and if the address-size attribute is 16, the CX register is used.) The REPE, REPNE, REPZ, and REPNZ prefixes also check the state of the ZF flag after each iteration and terminate the repeat loop if the ZF flag is not in the specified state. When both termination conditions are tested, the cause of a repeat termination can be determined either by testing the (E)CX register with a JECXZ instruction or by testing the ZF flag with a JZ, JNZ, and JNE instruction.

Repeat Prefix Termination Condition 1 Termination Condition 2
REP ECX=0 None
REPE/REPZ ECX=0 ZF=0
REPNE/REPNZ ECX=0 ZF=1

When the REPE/REPZ and REPNE/REPNZ prefixes are used, the ZF flag does not require initialization because both the CMPS and SCAS instructions affect the ZF flag according to the results of the comparisons they make.

A repeating string operation can be suspended by an exception or interrupt. When this happens, the state of the registers is preserved to allow the string operation to be resumed upon a return from the exception or interrupt handler. The source and destination registers point to the next string elements to be operated on, the EIP register points to the string instruction, and the ECX register has the value it held following the last successful iteration of the instruction. This mechanism allows long string operations to proceed without affecting the interrupt response time of the system.

When a fault occurs during the execution of a CMPS or SCAS instruction that is prefixed with REPE or REPNE, the EFLAGS value is restored to the state prior to the execution of the instruction. Since the SCAS and CMPS instructions do not use EFLAGS as an input, the processor can resume the instruction after the page fault handler.

Use the REP INS and REP OUTS instructions with caution. Not all I/O ports can handle the rate at which these instructions execute.

A REP STOS instruction is the fastest way to initialize a large block of memory.

Operands Bytes Clocks
See MOVSMM82V4 (rep movs) move block
See STOSCVX0O0 (rep stos) fill block
See CMPSCVYBO (repe cmps) find non-matching memory items
See CMPSCVYBO (repe scas) find non-acc matching byte in memory

Flags
None; however, the CMPS and SCAS instructions do set the status flags in the EFLAGS register.
+$#KRET - Return from Procedure
C3 RET Near return to calling procedure
CB RET Far return to calling procedure
C2 iw RET imm16 Near return to calling procedure and pop imm16 bytes
from stack
CA iw RET imm16 Far return to calling procedure and pop imm16 bytes from
stack

Description
Transfers program control to a return address located on the top of the stack. The address is usually placed on the stack by a CALL instruction, and the return is made to the instruction that follows the CALL instruction.

The optional source operand specifies the number of stack bytes to be released after the return address is popped; the default is none. This operand can be used to release parameters from the stack that were passed to the called procedure and are no longer needed. It must be used when the CALL instruction used to switch to a new procedure uses a call gate with a non-zero word count to access the new procedure. Here, the source operand for the RET instruction must specify the same number of bytes as is specified in the word count field of the call gate.

The RET instruction can be used to execute three different types of returns:

· Near return-A return to a calling procedure within the current code segment (the segment currently pointed to by the CS register), sometimes referred to as an intrasegment return.
· Far return-A return to a calling procedure located in a different segment than the current code segment, sometimes referred to as an intersegment return.
· Inter-privilege-level far return-A far return to a different privilege level than that of the currently executing program or procedure.

The inter-privilege-level return type can only be executed in protected mode. See the section titled "Calling Procedures Using Call and RET" in Chapter 4 of the Intel Architecture Software Developer's Manual, Volume 1, for detailed information on near, far, and inter-privilege-level returns.

When executing a near return, the processor pops the return instruction pointer (offset) from the top of the stack into the EIP register and begins program execution at the new instruction pointer. The CS register is unchanged.

When executing a far return, the processor pops the return instruction pointer from the top of the stack into the EIP register, then pops the segment selector from the top of the stack into the CS register. The processor then begins program execution in the new code segment at the new instruction pointer.

The mechanics of an inter-privilege-level far return are similar to an intersegment return, except that the processor examines the privilege levels and access rights of the code and stack segments being returned to determine if the control transfer is allowed to be made. The DS, ES, FS, and GS segment registers are cleared by the RET instruction during an inter-privilege-level return if they refer to segments that are not allowed to be accessed at the new privilege level. Since a stack switch also occurs on an inter-privilege level return, the ESP and SS registers are loaded from the stack.

If parameters are passed to the called procedure during an inter-privilege level call, the optional source operand must be used with the RET instruction to release the parameters on the return. Here, the parameters are released both from the called procedure's stack and the calling procedure's stack (that is, the stack being returned to).

Varations Bytes Clocks
retn 1 2 NP
retn imm16 1+d(2) 3 NP
retf 1 4 NP
retf imm16 1+d(2) 4 NP

Flags
None.
+$#KRSM - Resume from System Management Mode
0F AA RSM Resume operation of interrupted program

Description
Returns program control from system management mode (SMM) to the application program or operating-system procedure that was interrupted when the processor received an SSM interrupt. The processor's state is restored from the dump created upon entering SMM. If the processor detects invalid state information during state restoration, it enters the shutdown state. The following invalid information can cause a shutdown:

· Any reserved bit of CR4 is set to 1.
· Any illegal combination of bits in CR0, such as (PG=1 and PE=0) or (NW=1 and CD=0).
· (Intel Pentium ® and Intel486™ processors only.) The value stored in the state dump base field is not a 32-KByte aligned address.

The contents of the model-specific registers are not affected by a return from SMM.

See Chapter 11, System Management Mode (SMM), in the Intel Architecture Software Developer's Manual, Volume 3, for more information about SMM and the behavior of the RSM instruction.

Operands Bytes Clocks
2 83 NP

Flags
All.
+$#KSAHF - Store AH into Flags
9E SAHF Loads SF, ZF, AF, PF, and CF from AH into
EFLAGS register

Description
Loads the SF, ZF, AF, PF, and CF flags of the EFLAGS register with values from the corresponding bits in the AH register (bits 7, 6, 4, 2, and 0, respectively). Bits 1, 3, and 5 of register AH are ignored; the corresponding reserved bits (1, 3, and 5) in the EFLAGS register remain as shown in the "Operation" section below.

Operands Bytes Clocks
1 2 NP

Flags
The SF, ZF, AF, PF, and CF flags are loaded with values from the AH register. Bits 1, 3, and 5 of the EFLAGS register are unaffected, with the values remaining 1, 0, and 0, respectively.
+$#KSAL - Shift Arithmetic Left
D0 /4 SAL r/m8,1 Multiply r/m8 by 2, once
D2 /4 SAL r/m8,CL Multiply r/m8 by 2, CL times
C0 /4 ib SAL r/m8,imm8 Multiply r/m8 by 2, imm8 times
D1 /4 SAL r/m16,1 Multiply r/m16 by 2, once
D3 /4 SAL r/m16,CL Multiply r/m16 by 2, CL times
C1 /4 ib SAL r/m16,imm8 Multiply r/m16 by 2, imm8 times
D1 /4 SAL r/m32,1 Multiply r/m32 by 2, once
D3 /4 SAL r/m32,CL Multiply r/m32 by 2, CL times
C1 /4 ib SAL r/m32,imm8 Multiply r/m32 by 2, imm8 times
D0 /7 SAR r/m8,1 Signed divide* r/m8 by 2, once
D2 /7 SAR r/m8,CL Signed divide* r/m8 by 2, CL times
C0 /7 ib SAR r/m8,imm8 Signed divide* r/m8 by 2, imm8 times
D1 /7 SAR r/m16,1 Signed divide* r/m16 by 2, once
D3 /7 SAR r/m16,CL Signed divide* r/m16 by 2, CL times
C1 /7 ib SAR r/m16,imm8 Signed divide* r/m16 by 2, imm8 times
D1 /7 SAR r/m32,1 Signed divide* r/m32 by 2, once
D3 /7 SAR r/m32,CL Signed divide* r/m32 by 2, CL times
C1 /7 ib SAR r/m32,imm8 Signed divide* r/m32 by 2, imm8 times
D0 /4 SHL r/m8,1 Multiply r/m8 by 2, once
D2 /4 SHL r/m8,CL Multiply r/m8 by 2, CL times
C0 /4 ib SHL r/m8,imm8 Multiply r/m8 by 2, imm8 times
D1 /4 SHL r/m16,1 Multiply r/m16 by 2, once
D3 /4 SHL r/m16,CL Multiply r/m16 by 2, CL times
C1 /4 ib SHL r/m16,imm8 Multiply r/m16 by 2, imm8 times
D1 /4 SHL r/m32,1 Multiply r/m32 by 2, once
D3 /4 SHL r/m32,CL Multiply r/m32 by 2, CL times
C1 /4 ib SHL r/m32,imm8 Multiply r/m32 by 2, imm8 times
D0 /5 SHR r/m8,1 Unsigned divide r/m8 by 2, once
D2 /5 SHR r/m8,CL Unsigned divide r/m8 by 2, CL times
C0 /5 ib SHR r/m8,imm8 Unsigned divide r/m8 by 2, imm8 times
D1 /5 SHR r/m16,1 Unsigned divide r/m16 by 2, once
D3 /5 SHR r/m16,CL Unsigned divide r/m16 by 2, CL times
C1 /5 ib SHR r/m16,imm8 Unsigned divide r/m16 by 2, imm8 times
D1 /5 SHR r/m32,1 Unsigned divide r/m32 by 2, once
D3 /5 SHR r/m32,CL Unsigned divide r/m32 by 2, CL times
C1 /5 ib SHR r/m32,imm8 Unsigned divide r/m32 by 2, imm8 times

Description
Shifts the bits in the first operand (destination operand) to the left or right by the number of bits specified in the second operand (count operand). Bits shifted beyond the destination operand boundary are first shifted into the CF flag, then discarded. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.

The destination operand can be a register or a memory location. The count operand can be an immediate value or register CL. The count is masked to 5 bits, which limits the count range to 0 to 31. A special opcode encoding is provided for a count of 1.

The shift arithmetic left (SAL) and shift logical left (SHL) instructions perform the same operation; they shift the bits in the destination operand to the left (toward more significant bit loca-tions). For each shift count, the most significant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared (see Figure 6-6 in the Intel Architecture Software Developer's Manual, Volume 1).

The shift arithmetic right (SAR) and shift logical right (SHR) instructions shift the bits of the destination operand to the right (toward less significant bit locations). For each shift count, the least significant bit of the destination operand is shifted into the CF flag, and the most significant bit is either set or cleared depending on the instruction type. The SHR instruction clears the most significant bit (see Figure 6-7 in the Intel Architecture Software Developer's Manual, Volume 1); the SAR instruction sets or clears the most significant bit to correspond to the sign (most signif-icant bit) of the original value in the destination operand. In effect, the SAR instruction fills the empty bit position's shifted value with the sign of the unshifted value (see Figure 6-8 in the Intel Architecture Software Developer's Manual, Volume 1).

The SAR and SHR instructions can be used to perform signed or unsigned division, respectively, of the destination operand by powers of 2. For example, using the SAR instruction to shift a signed integer 1 bit to the right divides the value by 2.

Using the SAR instruction to perform a division operation does not produce the same result as the IDIV instruction. The quotient from the IDIV instruction is rounded toward zero, whereas the "quotient" of the SAR instruction is rounded toward negative infinity. This difference is apparent only for negative numbers. For example, when the IDIV instruction is used to divide -9 by 4, the result is -2 with a remainder of -1. If the SAR instruction is used to shift -9 right by two bits, the result is -3 and the "remainder" is +3; however, the SAR instruction stores only the most significant bit of the remainder (in the CF flag).

The OF flag is affected only on 1-bit shifts. For left shifts, the OF flag is cleared to 0 if the most-significant bit of the result is the same as the CF flag (that is, the top two bits of the original operand were the same); otherwise, it is set to 1. For the SAR instruction, the OF flag is cleared for all 1-bit shifts. For the SHR instruction, the OF flag is set to the most-significant bit of the original operand.

Operands Bytes Clocks
reg, 1 2 1 PU
mem, 1 2+d(0,2) 3 PU
reg, cl 2 4 NP
mem, cl 2+d(0,2) 4 NP
reg, imm 3 1 PU
mem, imm 3+d(0,2) 3 PU*

* = not pairable if there is a displacement and immediate

sal = shift arithmetic left sar = shift arithmetic right
shl = shift left (same as sal) shr = shift right

Flags
The CF flag contains the value of the last bit shifted out of the destination operand; it is undefined for SHL and SHR instructions where the count is greater than or equal to the size (in bits) of the destination operand. The OF flag is affected only for 1-bit shifts (see "Description" above); otherwise, it is undefined. The SF, ZF, and PF flags are set according to the result. If the count is 0, the flags are not affected. For a non-zero count, the AF flag is undefined.
+$#KSAR - Shift Arithmetic Right

See SALMM84X4
+$#KSHL - Shift Left

See SALMM84X4+$#KSHR - Shift Right

See SALMM84X4+$#KSBB - Integer Subtraction with Borrow
1C ib SBB AL, imm8 Subtract with borrow imm8 from AL
1D iw SBB AX, imm16 Subtract with borrow imm16 from AX
1D id SBB EAX, imm32 Subtract with borrow imm32 from EAX
80 /3 ib SBB r/m8,imm8 Subtract with borrow imm8 from r/m8
81 /3 iw SBB r/m16,imm16 Subtract with borrow imm16 from r/m16
81 /3 id SBB r/m32,imm32 Subtract with borrow imm32 from r/m32
83 /3 ib SBB r/m16,imm8 Subtract with borrow sign-extended imm8 from r/m16
83 /3 ib SBB r/m32,imm8 Subtract with borrow sign-extended imm8 from r/m32
18 / r SBB r/m8,r8 Subtract with borrow r8 from r/m8
19 / r SBB r/m16,r16 Subtract with borrow r16 from r/m16
19 / r SBB r/m32,r32 Subtract with borrow r32 from r/m32
1A / r SBB r8,r/m8 Subtract with borrow r/m8 from r8
1B / r SBB r16,r/m16 Subtract with borrow r/m16 from r16
1B / r SBB r32,r/m32 Subtract with borrow r/m32 from r32

Description
Adds the source operand (second operand) and the carry (CF) flag, and subtracts the result from the destination operand (first operand). The result of the subtraction is stored in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) The state of the CF flag represents a borrow from a previous subtraction.

When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.

The SBB instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates the result for both data types and sets the OF and CF flags to indicate a borrow in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result.

The SBB instruction is usually executed as part of a multibyte or multiword subtraction in which a SUB instruction is followed by a SBB instruction.

Operands Bytes Clocks
reg, reg 2 1 PU
mem, reg 2+d(0,2) 3 PU
reg, mem 2+d(0,2) 2 PU
reg, imm 2+i(1,2) 1 PU
mem, imm 2+d(0,2)+i(1,2) 3 PU*
acc, imm 1+i(1,2) 1 PU

* = not pairable if there is a displacement and immediate

Flags
The OF, SF, ZF, AF, PF, and CF flags are set according to the result.
+$#KSCAS/SCASB/SCASW/SCASD - Scan String
AE SCAS m8 Compare AL with byte at ES:(E)DI and set status flags
AF SCAS m16 Compare AX with word at ES:(E)DI and set status flags
AF SCAS m32 Compare EAX with doubleword at ES(E)DI and set status flags
AE SCASB Compare AL with byte at ES:(E)DI and set status flags
AF SCASW Compare AX with word at ES:(E)DI and set status flags
AF SCASD Compare EAX with doubleword at ES:(E)DI and set status flags

Description
Compares the byte, word, or double word specified with the memory operand with the value in the AL, AX, or EAX register, and sets the status flags in the EFLAGS register according to the results. The memory operand address is read from either the ES:EDI or the ES:DI registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). The ES segment cannot be overridden with a segment override prefix.

At the assembly-code level, two forms of this instruction are allowed: the "explicit-operands" form and the "no-operands" form. The explicit-operand form (specified with the SCAS mnemonic) allows the memory operand to be specified explicitly. Here, the memory operand should be a symbol that indicates the size and location of the operand value. The register operand is then automatically selected to match the size of the memory operand (the AL register for byte comparisons, AX for word comparisons, and EAX for doubleword comparisons). This explicit-operand form is provided to allow documentation; however, note that the documentation provided by this form can be misleading. That is, the memory operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does not have to specify the correct location. The location is always specified by the ES:(E)DI registers, which must be loaded correctly before the compare string instruction is executed.

The no-operands form provides "short forms" of the byte, word, and doubleword versions of the SCAS instructions. Here also ES:(E)DI is assumed to be the memory operand and the AL, AX, or EAX register is assumed to be the register operand. The size of the two operands is selected with the mnemonic: SCASB (byte comparison), SCASW (word comparison), or SCASD (doubleword comparison).

After the comparison, the (E)DI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)DI register is incremented; if the DF flag is 1, the (E)DI register is decremented.) The (E)DI register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for double-word operations.

The SCAS, SCASB, SCASW, and SCASD instructions can be preceded by the REP prefix for block comparisons of ECX bytes, words, or doublewords. More often, however, these instructions will be used in a LOOP construct that takes some action based on the setting of the status flags before the next comparison is made. See "REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix" in this chapter for a description of the REP prefix.

Variations Bytes Clocks
scasb 1 4 NP
scasw 1 4 NP
scasd 1 4 NP
repX scasb 2 8+4n NP
repX scasw 2 8+4n NP
repX scasd 2 8+4n NP

repX = repe or repz or repne or repnz
(n = count of bytes, words or dwords)

Flags
The OF, SF, ZF, AF, PF, and CF flags are set according to the temporary result of the comparison.
+$#KSETcc - Set Byte on Condition
0F 97 SETA r/m8 Set byte if above (CF=0 and ZF=0)
0F 93 SETAE r/m8 Set byte if above or equal (CF=0)
0F 92 SETB r/m8 Set byte if below (CF=1)
0F 96 SETBE r/m8 Set byte if below or equal (CF=1 or ZF=1)
0F 92 SETC r/m8 Set if carry (CF=1)
0F 94 SETE r/m8 Set byte if equal (ZF=1)
0F 9F SETG r/m8 Set byte if greater (ZF=0 and SF=OF)
0F 9D SETGE r/m8 Set byte if greater or equal (SF=OF)
0F 9C SETL r/m8 Set byte if less (SF<>OF)
0F 9E SETLE r/m8 Set byte if less or equal (ZF=1 or SF<>OF)
0F 96 SETNA r/m8 Set byte if not above (CF=1 or ZF=1)
0F 92 SETNAE r/m8 Set byte if not above or equal (CF=1)
0F 93 SETNB r/m8 Set byte if not below (CF=0)
0F 97 SETNBE r/m8 Set byte if not below or equal (CF=0 and ZF=0)
0F 93 SETNC r/m8 Set byte if not carry (CF=0)
0F 95 SETNE r/m8 Set byte if not equal (ZF=0)
0F 9E SETNG r/m8 Set byte if not greater (ZF=1 or SF<>OF)
0F 9C SETNGE r/m8 Set if not greater or equal (SF<>OF)
0F 9D SETNL r/m8 Set byte if not less (SF=OF)
0F 9F SETNLE r/m8 Set byte if not less or equal (ZF=0 and SF=OF)
0F 91 SETNO r/m8 Set byte if not overflow (OF=0)
0F 9B SETNP r/m8 Set byte if not parity (PF=0)
0F 99 SETNS r/m8 Set byte if not sign (SF=0)
0F 95 SETNZ r/m8 Set byte if not zero (ZF=0)
0F 90 SETO r/m8 Set byte if overflow (OF=1)
0F 9A SETP r/m8 Set byte if parity (PF=1)
0F 9A SETPE r/m8 Set byte if parity even (PF=1)
0F 9B SETPO r/m8 Set byte if parity odd (PF=0)
0F 98 SETS r/m8 Set byte if sign (SF=1)
0F 94 SETZ r/m8 Set byte if zero (ZF=1)

Description
Set the destination operand to 0 or 1 depending on the settings of the status flags (CF, SF, OF, ZF, and PF) in the EFLAGS register. The destination operand points to a byte register or a byte in memory. The condition code suffix (cc) indicates the condition being tested for.

The terms "above" and "below" are associated with the CF flag and refer to the relationship between two unsigned integer values. The terms "greater" and "less" are associated with the SF and OF flags and refer to the relationship between two signed integer values.

Many of the SETcc instruction opcodes have alternate mnemonics. For example, the SETG (set byte if greater) and SETNLE (set if not less or equal) both have the same opcode and test for the same condition: ZF equals 0 and SF equals OF. These alternate mnemonics are provided to make code more intelligible. Appendix B, EFLAGS Condition Codes, in the Intel Architecture Software Developer's Manual, Volume 1, shows the alternate mnemonics for various test conditions.

Some languages represent a logical one as an integer with all bits set. This representation can be obtained by choosing the logically opposite condition for the SETcc instruction, then decrementing the result. For example, to test for overflow, use the SETNO instruction, then decrement the result.

Operands Bytes Clocks
r8 3 1/2 NP
mem8 3+d(0-2) 1/2 NP

Cycles are for: true/false

setCC = one of:
seta setae setb setbe setc sete
setg setge setl setle setna setnae
setnb setnbe setnc setne setng setnge
setnl setnle setno setnp setns setnz
seto setp setpe setpo sets setz

Flags
None.
+$#KSGDT/SIDT - Store Global/Interrupt Descriptor Table Register
0F 01 /0 SGDT m Store GDTR to m
0F 01 /1 SIDT m Store IDTR to m

Description
Stores the contents of the global descriptor table register (GDTR) or the interrupt descriptor table register (IDTR) in the destination operand. The destination operand specifies a 6-byte memory location. If the operand-size attribute is 32 bits, the 16-bit limit field of the register is stored in the lower 2 bytes of the memory location and the 32-bit base address is stored in the upper 4 bytes. If the operand-size attribute is 16 bits, the limit is stored in the lower 2 bytes and the 24-bit base address is stored in the third, fourth, and fifth byte, with the sixth byte filled with 0s.

The SGDT and SIDT instructions are only useful in operating-system software; however, they can be used in application programs without causing an exception to be generated.

See "LGDT/LIDT-Load Global/Interrupt Descriptor Table Register" in this chapter for information on loading the GDTR and IDTR.

Operands Bytes Clocks
mem48 5 4 NP

Flags
None.
+$#KSHLD - Double Precision Shift Left
0F A4 SHLD r/m16,r16,imm8 Shift r/m16 to left imm8 places while shifting bits from r16
in from the right
0F A5 SHLD r/m16,r16,CL Shift r/m16 to left CL places while shifting bits from r16 in
from the right
0F A4 SHLD r/m32,r32,imm8 Shift r/m32 to left imm8 places while shifting bits from r32
in from the right
0F A5 SHLD r/m32,r32,CL Shift r/m32 to left CL places while shifting bits from r32 in
from the right

Description
Shifts the first operand (destination operand) to the left the number of bits specified by the third operand (count operand). The second operand (source operand) provides bits to shift in from the right (starting with bit 0 of the destination operand). The destination operand can be a register or a memory location; the source operand is a register. The count operand is an unsigned integer that can be an immediate byte or the contents of the CL register. Only bits 0 through 4 of the count are used, which masks the count to a value between 0 and 31. If the count is greater than the operand size, the result in the destination operand is undefined.

If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. If the count operand is 0, the flags are not affected.

The SHLD instruction is useful for multiprecision shifts of 64 bits or more.

Operands Bytes Clocks
reg, reg, imm 4 4 NP
mem, reg, imm 4+d(0-2) 4 NP
reg, reg, cl 4 4 NP
mem, reg, cl 4+d(0-2) 5 NP

Flags
If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand and the SF, ZF, and PF flags are set according to the value of the result. For a 1-bit shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. For shifts greater than 1 bit, the OF flag is undefined. If a shift occurs, the AF flag is undefined. If the count operand is 0, the flags are not affected. If the count is greater than the operand size, the flags are undefined.
+$#KSHRD - Double Precision Shift Right
0F AC SHRD r/m16,r16,imm8 Shift r/m16 to right imm8 places while shifting bits from
r16 in from the left
0F AD SHRD r/m16,r16,CL Shift r/m16 to right CL places while shifting bits from r16
in from the left
0F AC SHRD r/m32,r32,imm8 Shift r/m32 to right imm8 places while shifting bits from
r32 in from the left
0F AD SHRD r/m32,r32,CL Shift r/m32 to right CL places while shifting bits from r32
in from the left

Description
Shifts the first operand (destination operand) to the right the number of bits specified by the third operand (count operand). The second operand (source operand) provides bits to shift in from the left (starting with the most significant bit of the destination operand). The destination operand can be a register or a memory location; the source operand is a register. The count operand is an unsigned integer that can be an immediate byte or the contents of the CL register. Only bits 0 through 4 of the count are used, which masks the count to a value between 0 and 31. If the count is greater than the operand size, the result in the destination operand is undefined.

If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. If the count operand is 0, the flags are not affected.

The SHRD instruction is useful for multiprecision shifts of 64 bits or more.

Operands Bytes Clocks
reg, reg, imm 4 4 NP
mem, reg, imm 4+d(0-2) 4 NP
reg, reg, cl 4 4 NP
mem, reg, cl 4+d(0-2) 5 NP

Flags
If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand and the SF, ZF, and PF flags are set according to the value of the result. For a 1-bit shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. For shifts greater than 1 bit, the OF flag is undefined. If a shift occurs, the AF flag is undefined. If the count operand is 0, the flags are not affected. If the count is greater than the operand size, the flags are undefined.
+$#KSIDT - Store Interrupt Descriptor Table Register

See SGDT/SIDTCVXCF0
+$#KSLDT - Store Local Descriptor Table Register
0F 00 /0 SLDT r/m16 Stores segment selector from LDTR in r/m16
0F 00 /0 SLDT r/m32 Store segment selector from LDTR in low-order 16 bits of
r/m32

Description
Stores the segment selector from the local descriptor table register (LDTR) in the destination operand. The destination operand can be a general-purpose register or a memory location. The segment selector stored with this instruction points to the segment descriptor (located in the GDT) for the current LDT. This instruction can only be executed in protected mode.

When the destination operand is a 32-bit register, the 16-bit segment selector is copied into the lower-order 16 bits of the register. The high-order 16 bits of the register are cleared to 0s for the Pentium Pro processor and are undefined for Pentium, Intel486, and Intel386 processors. When the destination operand is a memory location, the segment selector is written to memory as a 16-bit quantity, regardless of the operand size.

The SLDT instruction is only useful in operating-system software; however, it can be used in application programs.

Operands Bytes Clocks
r16 3 2 NP
mem16 3+d(0-2) 2 NP

Flags
None.
+$#KSMSW - Store Machine Status Word
0F 01 /4 SMSW r/m16 Store machine status word to r/m16
0F 01 /4 SMSW r32/m16 Store machine status word in low-order 16 bits of r32/m16;
high-order 16 bits of r32 are undefined

Description
Stores the machine status word (bits 0 through 15 of control register CR0) into the destination operand. The destination operand can be a 16-bit general-purpose register or a memory location.

When the destination operand is a 32-bit register, the low-order 16 bits of register CR0 are copied into the low-order 16 bits of the register and the upper 16 bits of the register are undefined. When the destination operand is a memory location, the low-order 16 bits of register CR0 are written to memory as a 16-bit quantity, regardless of the operand size.

The SMSW instruction is only useful in operating-system software; however, it is not a privileged instruction and can be used in application programs.

This instruction is provided for compatibility with the Intel 286 processor. Programs and procedures intended to run on the Pentium Pro, Pentium, Intel486, and Intel386 processors should use the MOV (control registers) instruction to load the machine status word.

Operands Bytes Clocks
r16 3 4 NP
mem16 3+d(0-2) 4 NP

Flags
None.
+$#KSTC - Set Carry Flag
F9 STC Set CF flag

Description
Sets the CF flag in the EFLAGS register.

Operands Bytes Clocks
 1 2 NP

Flags
The CF flag is set. The OF, ZF, SF, AF, and PF flags are unaffected.
+$#KSTD - Set Direction Flag
FD STD Set DF flag

Description
Sets the DF flag in the EFLAGS register. When the DF flag is set to 1, string operations decrement the index registers (ESI and/or EDI).

Operands Bytes Clocks
1 2 NP

Flags
The DF flag is set. The CF, OF, ZF, SF, AF, and PF flags are unaffected.
+$#KSTI - Set Interrupt Flag
FB STI Set interrupt flag; external, maskable interrupts enabled
at the end of the next instruction

Description
Sets the interrupt flag (IF) in the EFLAGS register. After the IF flag is set, the processor begins responding to external, maskable interrupts after the next instruction is executed. The delayed effect of this instruction is provided to allow interrupts to be enabled just before returning from a procedure (or subroutine). For instance, if an STI instruction is followed by an RET instruction, the RET instruction is allowed to execute before external interrupts are recognized 1 . This behavior allows external interrupts to be disabled at the beginning of a procedure and enabled again at the end of the procedure. If the STI instruction is followed by a CLI instruction (which clears the IF flag), the effect of the STI instruction is negated.

The IF flag and the STI and CLI instructions have no affect on the generation of exceptions and NMI interrupts.

The following decision table indicates the action of the STI instruction (bottom of the table) depending on the processor's mode of operation and the CPL and IOPL of the currently running program or procedure (top of the table).

PE = 0 1 1 1
VM = X 0 0 1
CPL X £ IOPL > IOPL =3
IOPL X X X =3
IF ¬ 1 Y Y N Y
#GP(0) N N Y N
NOTES:
X Don't care.
N Action in Column 1 not taken.
Y Action in Column 1 taken.

Operands Bytes Clocks
1 7 NP

Flags
The IF flag is set to 1.
+$#KSTOS/STOSB/STOSW/STOSD - Store String
AA STOS m8 Store AL at address ES:(E)DI
AB STOS m16 Store AX at address ES:(E)DI
AB STOS m32 Store EAX at address ES:(E)DI
AA STOSB Store AL at address ES:(E)DI
AB STOSW Store AX at address ES:(E)DI
AB STOSD Store EAX at address ES:(E)DI

Description
Stores a byte, word, or doubleword from the AL, AX, or EAX register, respectively, into the destination operand. The destination operand is a memory location, the address of which is read from either the ES:EDI or the ES:DI registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). The ES segment cannot be overridden with a segment override prefix.

At the assembly-code level, two forms of this instruction are allowed: the "explicit-operands" form and the "no-operands" form. The explicit-operands form (specified with the STOS mnemonic) allows the destination operand to be specified explicitly. Here, the destination operand should be a symbol that indicates the size and location of the destination value. The source operand is then automatically selected to match the size of the destination operand (the AL register for byte operands, AX for word operands, and EAX for doubleword operands). This explicit-operands form is provided to allow documentation; however, note that the documentation provided by this form can be misleading. That is, the destination operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does not have to specify the correct location. The location is always specified by the ES:(E)DI registers, which must be loaded correctly before the store string instruction is executed.

The no-operands form provides "short forms" of the byte, word, and doubleword versions of the STOS instructions. Here also ES:(E)DI is assumed to be the destination operand and the AL, AX, or EAX register is assumed to be the source operand. The size of the destination and source operands is selected with the mnemonic: STOSB (byte read from register AL), STOSW (word from AX), or STOSD (doubleword from EAX).

After the byte, word, or doubleword is transferred from the AL, AX, or EAX register to the memory location, the (E)DI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)DI register is incremented; if the DF flag is 1, the (E)DI register is decremented.) The (E)DI register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword operations.

The STOS, STOSB, STOSW, and STOSD instructions can be preceded by the REP prefix for block loads of ECX bytes, words, or doublewords. More often, however, these instructions are used within a LOOP construct because data needs to be moved into the AL, AX, or EAX register before it can be stored. See "REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix" in this chapter for a description of the REP prefix.

Variations Bytes Clocks
stosb 1 3 NP
stosw 1 3 NP
stosd 1 3 NP
rep stosb 2 3+n NP
rep stosw 2 3+n NP
rep stosd 2 3+n NP
(n = count of bytes, words or dwords)

Flags
None.
+$#KSTR - Store Task Register
0F 00 /1 STR r/m16 Stores segment selector from TR in r/m16

Description
Stores the segment selector from the task register (TR) in the destination operand. The destination operand can be a general-purpose register or a memory location. The segment selector stored with this instruction points to the task state segment (TSS) for the currently running task.

When the destination operand is a 32-bit register, the 16-bit segment selector is copied into the lower 16 bits of the register and the upper 16 bits of the register are cleared to 0s. When the destination operand is a memory location, the segment selector is written to memory as a 16-bit quantity, regardless of operand size.

The STR instruction is useful only in operating-system software. It can only be executed in protected mode.

Operands Bytes Clocks
r16 3 2 NP
mem16 3+d(0-2) 2 NP

Flags
None.
+$#KSUB - Subtract
2C ib SUB AL, imm8 Subtract imm8 from AL
2D iw SUB AX, imm16 Subtract imm16 from AX
2D id SUB EAX, imm32 Subtract imm32 from EAX
80 /5 ib SUB r/m8,imm8 Subtract imm8 from r/m8
81 /5 iw SUB r/m16,imm16 Subtract imm16 from r/m16
81 /5 id SUB r/m32,imm32 Subtract imm32 from r/m32
83 /5 ib SUB r/m16,imm8 Subtract sign-extended imm8 from r/m16
83 /5 ib SUB r/m32,imm8 Subtract sign-extended imm8 from r/m32
28 / r SUB r/m8,r8 Subtract r8 from r/m8
29 / r SUB r/m16,r16 Subtract r16 from r/m16
29 / r SUB r/m32,r32 Subtract r32 from r/m32
2A / r SUB r8,r/m8 Subtract r/m8 from r8
2B / r SUB r16,r/m16 Subtract r/m16 from r16
2B / r SUB r32,r/m32 Subtract r/m32 from r32

Description
Subtracts the second operand (source operand) from the first operand (destination operand) and stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, register, or memory location. (However, two memory operands cannot be used in one instruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.

The SUB instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates the result for both data types and sets the OF and CF flags to indicate a borrow in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result.

Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2+d(0,2) 3 UV
reg, mem 2+d(0,2) 2 UV
reg, imm 2+i(1,2) 1 UV
mem, imm 2+d(0,2)+i(1,2) 3 UV*
acc, imm 1+i(1,2) 1 UV

* = not pairable if there is a displacement and immediate

Flags
The OF, SF, ZF, AF, PF, and CF flags are set according to the result.
+$#KTEST - Logical Compare
A8 ib TEST AL, imm8 AND imm8 with AL; set SF, ZF, PF according to result
A9 iw TEST AX, imm16 AND imm16 with AX; set SF, ZF, PF according to result
A9 id TEST EAX, imm32 AND imm32 with EAX; set SF, ZF, PF according to result
F6 /0 ib TEST r/m8,imm8 AND imm8 with r/m8; set SF, ZF, PF according to result
F7 /0 iw TEST r/m16,imm16 AND imm16 with r/m16; set SF, ZF, PF according to result
F7 /0 id TEST r/m32,imm32 AND imm32 with r/m32; set SF, ZF, PF according to result
84 / r TEST r/m8,r8 AND r8 with r/m8; set SF, ZF, PF according to result
85 / r TEST r/m16,r16 AND r16 with r/m16; set SF, ZF, PF according to result
85 / r TEST r/m32,r32 AND r32 with r/m32; set SF, ZF, PF according to result

Description
Computes the bit-wise logical AND of first operand (source 1 operand) and the second operand (source 2 operand) and sets the SF, ZF, and PF status flags according to the result. The result is then discarded.

Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2+d(0,2) 2 UV
reg, mem 2+d(0,2) 2 UV
reg, imm 2+i(1,2) 1 UV
mem, imm 2+d(0,2)+i(1,2) 2 UV*
acc, imm 1+i(1,2) 1 UV

* = not pairable if there is a displacement and immediate

Flags
The OF and CF flags are cleared to 0. The SF, ZF, and PF flags are set according to the result (see the "Operation" section above). The state of the AF flag is undefined.+$#KVERR/VERW - Verify a Segment for Reading or Writing
0F 00 /4 VERR r/m16 Set ZF=1 if segment specified with r/m16 can be read
0F 00 /5 VERW r/m16 Set ZF=1 if segment specified with r/m16 can be written

Description
Verifies whether the code or data segment specified with the source operand is readable (VERR) or writable (VERW) from the current privilege level (CPL). The source operand is a 16-bit register or a memory location that contains the segment selector for the segment to be verified. If the segment is accessible and readable (VERR) or writable (VERW), the ZF flag is set; otherwise, the ZF flag is cleared. Code segments are never verified as writable. This check cannot be performed on system segments.

To set the ZF flag, the following conditions must be met:

· The segment selector is not null.
· The selector must denote a descriptor within the bounds of the descriptor table (GDT or LDT).
· The selector must denote the descriptor of a code or data segment (not that of a system segment or gate).
· For the VERR instruction, the segment must be readable.
· For the VERW instruction, the segment must be a writable data segment.
· If the segment is not a conforming code segment, the segment's DPL must be greater than or equal to (have less or the same privilege as) both the CPL and the segment selector's RPL.

The validation performed is the same as is performed when a segment selector is loaded into the DS, ES, FS, or GS register, and the indicated access (read or write) is performed. The segment selector's value cannot result in a protection exception, enabling the software to anticipate possible segment access problems.

Operands Bytes Clocks
r16 3 7 NP
mem16 3+d(0,2) 7 NP

Flags
The ZF flag is set to 1 if the segment is accessible and readable (VERR) or writable (VERW); otherwise, it is cleared to 0.
+$#KWAIT - Wait
9B WAIT Check pending unmasked floating-point exceptions.
9B FWAIT Check pending unmasked floating-point exceptions.

Description
Causes the processor to check for and handle pending, unmasked, floating-point exceptions before proceeding. (FWAIT is an alternate mnemonic for the WAIT).

This instruction is useful for synchronizing exceptions in critical sections of code. Coding a WAIT instruction after a floating-point instruction insures that any unmasked floating-point exceptions the instruction may raise are handled before the processor can modify the instruction's results. See the section titled "Floating-Point Exception Synchronization" in Chapter 7 of the Intel Architecture Software Developer's Manual, Volume 1, for more information on using the WAIT/FWAIT instruction.

Operands Bytes Clocks
1 1 NP

FPU Flags
The C0, C1, C2, and C3 flags are undefined.
+$#KWBINVD - Write Back and Invalidate Cache
0F 09 WBINVD Write back and flush Internal caches; initiate writing-back
and flushing of external caches.

Description
Writes back all modified cache lines in the processor's internal cache to main memory and invalidates (flushes) the internal caches. The instruction then issues a special-function bus cycle that directs external caches to also write back modified data and another bus cycle to indicate that the external caches should be invalidated.

After executing this instruction, the processor does not wait for the external caches to complete their write-back and flushing operations before proceeding with instruction execution. It is the responsibility of hardware to respond to the cache write-back and flush signals.

The WDINVD instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a program or procedure must be 0 to execute this instruction. This instruction is also a serializing instruction (see "Serializing Instructions" in Chapter 7 of the Intel Architecture Software Developer's Manual, Volume 3).

In situations where cache coherency with main memory is not a concern, software can use the INVD instruction.

Operands Bytes Clocks
2 2000+ NP

Flags
None.
+$#KWRMSR - Write to Model Specific Register
0F 30 WRMSR Write the value in EDX:EAX to MSR specified by ECX

Description
Writes the contents of registers EDX:EAX into the 64-bit model specific register (MSR) specified in the ECX register. The high-order 32 bits are copied from EDX and the low-order 32 bits are copied from EAX. Always set the undefined or reserved bits in an MSR to the values previously read.

This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) will be generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a general protection exception.

When the WRMSR instruction is used to write to an MTRR, the TLBs are invalidated, including the global entries (see "Translation Lookaside Buffers (TLBs)" in Chapter 3 of the Intel Architecture Software Developer's Manual, Volume 3). (MTRRs are an implementation-specific feature of the Pentium Pro processor.)

The MSRs control functions for testability, execution tracing, performance monitoring and machine check errors. Appendix B, Model-Specific Registers (MSRs), in the Intel Architecture Software Developer's Manual, Volume 3, lists all the MSRs that can be written to with this instruction and their addresses.

The WRMSR instruction is a serializing instruction (see "Serializing Instructions" in Chapter 7 of the Intel Architecture Software Developer's Manual, Volume 3).

The CPUID instruction should be used to determine whether MSRs are supported (EDX[5]=1) before using this instruction.

Operands Bytes Clocks
2 30-45 NP

Flags
None.
+$#KXADD - Exchange and Add
0F C0/r XADD r/m8,r8 Exchange r8 and r/m8; load sum into r/m8.
0F C1/r XADD r/m16,r16 Exchange r16 and r/m16; load sum into r/m16.
0F C1/r XADD r/m32,r32 Exchange r32 and r/m32; load sum into r/m32.

Description
Exchanges the first operand (destination operand) with the second operand (source operand), then loads the sum of the two values into the destination operand. The destination operand can be a register or a memory location; the source operand is a register.

This instruction can be used with a LOCK prefix.

Operands Bytes Clocks
reg, reg 3 3 NP
mem, reg 3+d(0-2) 4 NP

Flags
The CF, PF, AF, SF, ZF, and OF flags are set according to the result of the addition, which is stored in the destination operand.
+$#KXCHG - Exchange Register/Memory with Register
90+ rw XCHG AX, r16 Exchange r16 with AX
90+ rw XCHG r16,AX Exchange AX with r16
90+ rd XCHG EAX, r32 Exchange r32 with EAX
90+ rd XCHG r32,EAX Exchange EAX with r32
86 / r XCHG r/m8,r8 Exchange r8 (byte register) with byte from r/m8
86 / r XCHG r8,r/m8 Exchange byte from r/m8 with r8 (byte register)
87 / r XCHG r/m16,r16 Exchange r16 with word from r/m16
87 / r XCHG r16,r/m16 Exchange word from r/m16 with r16
87 / r XCHG r/m32,r32 Exchange r32 with doubleword from r/m32
87 / r XCHG r32,r/m32 Exchange doubleword from r/m32 with r32

Description
Exchanges the contents of the destination (first) and source (second) operands. The operands can be two general-purpose registers or a register and a memory location. If a memory operand is referenced, the processor's locking protocol is automatically implemented for the duration of the exchange operation, regardless of the presence or absence of the LOCK prefix or of the value of the IOPL. (See the LOCK prefix description in this chapter for more information on the locking protocol.)

This instruction is useful for implementing semaphores or similar data structures for process synchronization. (See "Bus Locking" in Chapter 7 of the Intel Architecture Software Developer's Manual, Volume 3, for more information on bus locking.)

The XCHG instruction can also be used instead of the BSWAP instruction for 16-bit operands.

Operands Bytes Clocks
reg, reg 2 3 NP
reg, mem 2+d(0-2) 3 NP
mem, reg 2+d(0-2) 3 NP

acc, reg 1 2 NP
reg, acc 1 2 NP
in above: acc = AX or EAX only

Flags
None.
+$#KXLAT/XLATB - Table Look-up Translation
D7 XLAT m8 Set AL to memory byte DS:[(E)BX + unsigned AL]
D7 XLATB Set AL to memory byte DS:[(E)BX + unsigned AL]

Description
Locates a byte entry in a table in memory, using the contents of the AL register as a table index, then copies the contents of the table entry back into the AL register. The index in the AL register is treated as an unsigned integer. The XLAT and XLATB instructions get the base address of the table in memory from either the DS:EBX or the DS:BX registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). (The DS segment may be overridden with a segment override prefix.)

At the assembly-code level, two forms of this instruction are allowed: the "explicit-operand" form and the "no-operand" form. The explicit-operand form (specified with the XLAT mnemonic) allows the base address of the table to be specified explicitly with a symbol. This explicit-operands form is provided to allow documentation; however, note that the documentation provided by this form can be misleading. That is, the symbol does not have to specify the correct base address. The base address is always specified by the DS:(E)BX registers, which must be loaded correctly before the XLAT instruction is executed.

The no-operands form (XLATB) provides a "short form" of the XLAT instructions. Here also the processor assumes that the DS:(E)BX registers contain the base address of the table.

Operands Bytes Clocks
1 4 NP

Flags
None.
+$#KXOR - Logical Exclusive OR
34 ib XOR AL, imm8 AL XOR imm8
35 iw XOR AX, imm16 AX XOR imm16
35 id XOR EAX, imm32 EAX XOR imm32
80 /6 ib XOR r/m8,imm8 r/m8 XOR imm8
81 /6 iw XOR r/m16,imm16 r/m16 XOR imm16
81 /6 id XOR r/m32,imm32 r/m32 XOR imm32
83 /6 ib XOR r/m16,imm8 r/m16 XOR imm8 (sign-extended)
83 /6 ib XOR r/m32,imm8 r/m32 XOR imm8 (sign-extended)
30 / r XOR r/m8,r8 r/m8 XOR r8
31 / r XOR r/m16,r16 r/m16 XOR r16
31 / r XOR r/m32,r32 r/m32 XOR r32
32 / r XOR r8,r/m8 r8 XOR r/m8
33 / r XOR r16,r/m16 r8 XOR r/m8
33 / r XOR r32,r/m32 r8 XOR r/m8

Description
Performs a bitwise exclusive OR (XOR) operation on the destination (first) and source (second) operands and stores the result in the destination operand location. The source operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location. (However, two memory operands cannot be used in one instruction.) Each bit of the result is 1 if the corresponding bits of the operands are different; each bit is 0 if the corresponding bits are the same.

Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2+d(0,2) 3 UV
reg, mem 2+d(0,2) 2 UV
reg, imm 2+i(1,2) 1 UV
mem, imm 2+d(0,2)+i(1,2) 3 UV*
acc, imm 1+i(1,2) 1 UV

* = not pairable if there is a displacement and immediate

Flags
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is undefined.


Assembly Optimization Tips

by

Mark Larson
The most important thing to remember is to TIME your code. Trying different tricks might or might not speed up your code. So it is very important to time your code to see if you do get a speedup as you try each trick.

Beginner

  1. Freeing up all 8 CPU registers for use in your code.

        push ebx
    push esi
    push edi
    push ebp                    ; has to be done before changing ESP

    ;load up ESI and EDI and your other registers with the vales passed
    ;in on the stack. This has to be done before freeing up ESP.

    movd mm0,esp                ; no pushing/popping past this point.
    xor  ebx,ebx                ; So how do you save?  A variable.
    mov  esp,5

inner_loop:
    mov   [eax_save],eax        ; eax_save is a global variable. Can't be
    movzx eax,word ptr [fred_2] ; local because that requires EBP to point to it.
    add   ebx,eax
    mov   eax,[eax_save]        ; restore eax

    movd  esp,mm0               ; has to be done before you do the POPs

    pop   ebp
    pop   edi
    pop   esi
    pop   ebx
    ret

  2. Maximize register usage.

    Most high level compilers generate a lot of memory accesses to variables. I usually get around that by trying to keep most of them in registers. Having all 8 cpu registers free can really come in handy.

  3. Complex instructions

    Avoid complex instructions ( lods, stos, movs, cmps, scas, loop, xadd, enter, leave). Complex instructions are instructions that do multiple things. For instance stosb writes a byte to memory and also increments EDI. They stopped making these fast with the original Pentium because they were trying to make it more RISC like. Using REP and the string instructions is still fast. That is the only exception to the case.

  4. Don't use INC/DEC on P4

    On the P4 use ADD/SUB in place of INC/DEC. Generally it is faster. ADD/SUB runs in 0.5 cycles. INC/DEC takes 1 cycle.

  5. Rotating

    Avoid rotate by a register or rotate by an immediate value of anything but a 1.

  6. Eliminate unnecessary compare instructions

    Eliminate unnecessary compare instructions by doing the appropriate conditional jump instruction based on the flags that are already set from a previous arithmetic instruction.

            dec     ecx
        cmp     ecx,0
        jnz     loop_again

;gets changed to
        dec     ecx
        jnz     loop_again

  7. LEA is still really cool, except for on the P4 it tends to be slow.

    You can perform multiple math operations all in one instruction and it does not affect the flags register so you can put in in between one register being modified and a flags comparison jump on the next line.

    top_of_loop:

    dec   eax
    lea   edx,[edx*4+3]     ; multiply by 4 and add 3. Does not affect flags
    jnz   top_of_loop       ; so the next instruction doesn't get hosed.

  8. ADC and SBB.

    Most compilers don't really make good use of ADC and SBB. You can get good speeds ups with that. Adding 2 64-bit numbers together, or adding big numbers together. Keep in mind that on the P4 ADC and SBB are slow. As a work around you can use "addq", and use MMX to do this. So the second optimization suggestion for this is to use MMX to do the adding or subtracting. You just have to have a processor that supports MMX.

        add    eax,[fred]
    adc    edx,[fred+4]

    ; the above 2 statements are the same as the below 3 statements

    movd   mm0,[fred]       ; Get 32-bit value in MM0
    movd   mm1,[fred+4]     ; Get 32-bit value in MM1
    paddq  mm0,mm1          ; This is an unoptimized way to do it. You would
                            ; really pre-read MM0 and MM1 a loop in advance.
                            ; I did it this way for ease of understanding.

  9. ROL, ROR, RCL, and RCR and BSWAP.

    It is a cool trick to switch from Big Endian to Little Endian using BSWAP. Also you can use it for temporary storage of a 16-bit or 8-bit value in the upper half of the register. Likewise you can use ROL and ROR for storing 8-bit and 16-bit values. It's a way to get more "registers". If all you are dealing with are 16-bit values, you can turn your 8 32-bit registers into 16 16-bit registers. Which gives you a lot more registers to use. RCL and RCR can also easily be used for counting the number of bits that are set in a register. Keep in mind that ROL, ROR, RCL, RCR and BSWAP are all slow on the P4. The rotate instructions are about twice as fast as BSWAP. So if you have to use one or the other on the P4 use the rotate ones.

        xor   edx,edx           ; set both 16-bit registers to 0
    mov   dx,234            ; set the first 16-bit register to 234
    bswap edx               ; swap it so the second one is ready
    mov   dx,345            ; set the second 16-bit register to 345
    bswap edx               ; swap to the first one
    add   dx,5              ; add 5 to the first one
    bswap edx               ; swap to the second one
    add   dx,7              ; add 7 to it

  10. String instructions.

    Most compilers don't make good use of the string instructions ( scas, cmps, stos, movs, and lods). So checking to see if that is faster than some library routine can be a win. For instance I was really surprised when I looked at strlen() in VC++. In the radix40 code it ran in 416 cycles for a 100 byte string!!! I thought that was absurdly slow.

  11. Multiply to divide.

    If you have a full 32-bit number and you need to divide, you can simply do a multiply and take the top 32-bit half as the result. This is faster because multiplication is faster than division. ( thanks to pdixon for the tip).

  12. Dividing by a constant.

    There's some nice information now how to divide by a constant in Agner Fog's pentopt.pdf document. I wrote a program that you pass in the number you want to divide by, and it will print out the assembler code sequence. I will dig it up later and post it. Here is a link to Agner's document. Agner's Pentopt PDF (http://www.agner.org/assem/)

  13. Unrolling.

    This is a guideline. Unrolling falls in the General Optimiation category but I wanted to add a footnote. I always set up my Unrolling with a macro that unrolls an EQUATE value amount. That way you can try different values and see which is best easily. You want the unrolling to fit in the L1 code cache ( or trace cache). Using an equate makes it easy to try different unroll amounts to find the fastest one.

    UNROLL_AMT       equ   16   ; # of times to unroll the loop
UNROLL_NUM_BYTES equ    4   ; # of bytes handled in 1 loop iteration

        mov     ecx,1024
looper:
offset2 = 0
REPEAT UNROLL_AMT
        add     eax,[edi+offset2]
offset2 = offset2 + UNROLL_NUM_BYTES
        add     edi,UNROLL_AMT * UNROLL_NUM_BYTES   ; we dealt with 16*4 bytes.
        sub     ecx,UNROLL_AMT  ; subtract from loop counter the # of loops we unrolled.
        jnz     looper

  14. MOVZX.

    Use MOVZX to avoid partial register stalls. I use MOVZX a lot. A lot of people XOR the full 32-bit register first. But MOVZX does the equivalent thing without having to have an extra XOR instruction. Also you had to do the XOR enough in advance to give it time to complete. With MOVZX you don't have to worry about that.

  15. Using MOVZX to avoid a SHIFT and AND instruction

    I ran across this bit of C code I was trying to speed up using assembler. The_array is a dword array. The code is trying to get a different byte from a dword in the array passed upon which pass this is over the data. "Pass" is a variable that goes from 0 to 3 for each byte in a particular dword.

            unsigned char c = ((the_array[i])>>(Pass<<3)) & 0xFF;

; I got rid of the "pass" variable by unrolling the loop 4 times.
; So I had 4 of these each one seperated by lots of C code.
        unsigned char c = (the_array[i])>>0) & 0xFF;
        unsigned char c = (the_array[i])>>8) & 0xFF;
        unsigned char c = (the_array[i])>>16) & 0xFF;
        unsigned char c = (the_array[i])>>24) & 0xFF;
    What if I can get rid of the SHIFT and the AND using assembler? That would save me 2 instructions. Not to mention the fact that the P4 is very slow when doing SHIFT instructions ( 4 cycles!!!). So try to avoid shifts where possible. SO taking just the second to last line that shifts right 16 as our example
    ; esi points to the_array

        mov     eax,[esi]
        shr     eax,16
        and     eax,0FFh

; So how do we change that to get rid of the AND and SHR?
; We do a MOVZx with the 3rd byte in the dword.

        movzx   eax,byte ptr [esi+2]            ;unsigned char c = (the_array[i])>>16) & 0xFF;

  16. Align, align, align.

    It is really important to align both your code and data to get a good speed up. I generally align code on 4 byte boundaries. For data I align 2 byte data on 2 byte boundaries, 4 byte data on 4 byte boundaries, 8 byte data on 8 byte boundaries, 16 byte data on 16 byte boundaries. In general if you don't align your SSE or SSE2 data on a 16-byte boundary you will get an exception. You can align your data in VC++ if you have the processor pack. They added support for both static data and dynamic memory. For static data you use __declspec(align(4)) - alignes on a 4 byte boundary.

  17. BSR for powers of 2.

    You can use BSR to count the highest power of 2 that goes into a variable.

  18. XORing a register with itself to zero it.

    This is an oldie, but I am including it anyway. It also has a side benefit of clearing dependencies on the register. That is why sometimes you will see people use XOR in that fashion, before doing a partial register access. I prefer using MOVZX to doing it that way because it is trickier to do using a XOR ( read my above comments about in #12 above talking about MOVZX) . On the P4 they also added support for PXOR to break dependencies in that fashion. I think the P3 does the same thing.

  19. Use XOR and DIV.

    If you know your data can be unsigned for a DIVISION, use XOR EDX, EDX, then DIV. It's faster than CDQ and IDIV.

  20. Try to avoid obvious dependencies.

    If you modify a register and then compare it to some value on the very next line, instead try and put some other register modification in between. Dependencies are any time you modify a register and then read it or write it shortly afterwards.

       inc edi
   inc eax
   cmp eax,1    ; this line has a dependency with the previous line, so it will stall.
   jz  fred

;shuffling the instructions around we can help break up dependencies.
   inc eax
   inc edi
   cmp eax,1
   jz  fred

  21. Instructions to avoid on P4.

    On P4's try to avoid the following instructions, adc, sbb, rotate instructions, shift instructions, inc, dec, lea, and any instruction taking more than 4 uops. How do you know the processor running the code is a P4? CPUID.

  22. Using lookup tables.

    On the P4 sometimes you can get around the long latency instructions that I listed previously by doing lookup tables. Thankfully on P4's they come with really fast memory. So having to do a lookup table doesn't hurt performance as much if it isn't in the cache.

  23. Use pointers instead of calculating indexes.

    A lot of times in loops in C there will be multiplications by non-powers of 2 numbers. You can easily get around this by adding instead. Here is an example that uses a structure.

    typedef struct fred
{
   int fred;
   char bif;
} freddy_type;

freddy_type charmin[80];

    The size of freddy_type is 5 bytes. If you try and access them in a loop the compiler will generate code for multipling by 5 for each array access!!!! (Ewwwwwwwwwwwww). So how do we do it properly?

    for ( int t = 0; t < 80; t++)
{
   charmin[t].fred = rand(); // the compiler multiplies by 5 to get the offset, EWWWWWWWW!
   charmin[t].bif = (char)(rand() % 256);
}

; in assembler we start with an offset of 0, that points to the first data item.
; And then we add 5 to it each loop iteration to avoid the MUL.

   mov   esi,offset charmin
   mov   ecx,80
fred_loop:
   ;... perform operations on the FRED and BIF elements in freddy_type
   add   esi,5                     ;make it point to the next structure entry.
   dec   ecx
   jnz   fred_loop

    The MUL removal applies to loops as well. I have seen people do multiplies in loops as part of incrementing the variable or for terminating condition. So try doing addition instead.

  24. Conform to default branch predictions.

    Try to set up your code such that backward conditional jumps are usually taken, and forward conditional loops are almost never taken. That has to do with branch prediction. The static branch predictor uses that simple rule to guess if a conditional jump is taken or not. So have a loop that has a backwards conditional jump at the end. And then have special exit conditions from that same loop that executes a forward jump that only exits on a certain condition that doesn't often occur.

  25. Eliminate branches

    Eliminate branch where possible. This might seem obvious, but I have seen some people use too many branches in their assembler code. Keep it simple. Use as few branches as possible.

  26. Using CMOVcc to remove branches

    I have yet to see the CMOVcc instructions actually be faster than a conditional jump. So I recommend using conditional jumps over CMOVcc. It might be faster in the case where your jumps aren't easily guessable by the branch prediction logic. So if that is the case with you, benchmark it and see.

  27. Local vs. Global variables

    Use local variables for a procedure over using a global variable. If you use local variables you'll get less cache misses.

  28. Address Calculation

    Compute address calculations before you need them. Let's say you have to do some funky stuff to get to a particular address. Such as multiplying by 20. You can pre-compute that before you get to the point in the code where you need it.

  29. Smaller registers

    Sometimes using smaller registers will give you a speed up. I did this on the radix40 code. If you change the below code to use EDX it runs slightly slower.

            movzx           edx,byte ptr [esi]              ;get the data from the ascii array
        test            dl,ILLEGAL                      ;bit 7 set?  if so do ILLEGAL handling
        jnz             skip_illegal

  30. Instruction Length

    Try and keep your instructions to 8 bytes or less.

  31. Use registers to pass parameters

    Try passing parameters in registers instead of on the stack where possible. If you have 3 variables that you have to push onto the stack as paramaters, that is at least 6 memory reads and 3 memory writes. You have to read each variable from memory into a CPU register and then push it on the stack. That is 3 memory reads right there. Then the 3 pushes onto the stack make 3 writes. Then why would you push parameters you'd never use? So figure at least 3 ( maybe more) reads from the stack of the pushed data.

  32. Don't pass big data on the stack

    Don't pass 64-bit data or 128-bit data ( or bigger) on the stack. Instead pass a pointer to the data.

Intermediate

  1. Adding to memory faster than adding memory to a register

    This has to do with the number of micro-ops the instruction takes. Give preference to doing an add with memory over adding memory to a register.

            add     eax,[edi]       ;don't do this if possible
        add     [edi],eax       ;This is preferred

  2. Instruction selection

    Try and pick instructions with the fewest micro-ops and shortest latencies.

  3. Handling an unaligned byte data stream that needs to be dword aligned

    Parsing a byte array a dword at a time will get you performance hits due to the buffer not being aligned to a 4 byte boundary. You can get around this by dealing with the first X bytes ( 0 to 3), until you come to an aligned to a 4 byte boundary.

  4. Using CMOVcc to reset an infinite loop pointer

    If you are making multiple passes through an array, and want to reset it to the beginning when you have reached the end of the array, you can use CMOVcc.

            dec ecx             ; decrement index into array
        cmovz ecx,MAX_COUNT ; if we are at the beginning, then reset the index
                            ; to MAX_COUNT (the end).

  5. Multiplying by 0.5 by doing a subtraction

    This probably won't work for everything, but multiplying by 0.5, or dividing by 2.0 in real4 ( in floating point), you can just subtract 1 from the exponent. Won't work with 0.0. For real8, the subtract value is 00100000h ( donkey posted this)

    .data
        somefp real4    2.5
.code
        sub dword ptr [somefp],00800000h        ;divide real4 by 2.

  6. Self Modifying Code

    The P4 optimization manual recommends avoiding self-modifying code. I have seen cases where it can run faster. But as always you need to time it to verify in your case that it is faster.

  7. MMX, SSE, SSE2

    Most compilers don't generate good code for MMX, SSE and SSE2. GCC and the Intel compiler have gotten a lot better at it. But hand tooled assembler is still a big win in this area.

  8. Using EMMS.

    EMMS tends to be a really slow instruction on Intel processors. On AMD it is faster. Generally I don't do it on a per routine basis, because it is so slow. I very rarely use a lot of floating point in a program that I already have a lot of MMX in (and vice versa). So I usually wait to do the EMMS before doing any floating point. If you have a lot of floating point and very little MMX, then do the EMMS at the end of all the MMX routines you call (if you call any). But adding it in every routine that does MMX just makes the code run slow.

  9. Converting to MMX,SSE, or SSE2

    Can your code be convert to MMX, SSE, or SSE2? If so you can get a big speed up by doing stuff in parallel.

  10. Prefetching data.

    This is underutilized a lot. If you are processing a huge array ( 256KB and up), using the "prefetch" instruction on P3 and up processors can speed up your code anywhere from 10-30%. You can actually get a degradation in performance if you don't use it right. Unrolling works well with this, because I unroll to the number of bytes fetched with this instruction. On a P3 it is 32, but on a P4 it is 128. That means you can easily unroll your loops to handle 128 bytes at a time on a P4 and get the benfit from unrolling and prefetching. It is not always the case that if you unroll it for 128 bytes that you will get the best speed up. So try different variations.

    UNROLL_NUM_BYTES equ    4                       ; # of bytes handled in one
                                                ; iteration of the loop.
UNROLL_AMT       equ    128/UNROLL_NUM_BYTES    ; We want to unroll the loop such
                                                ; that we handle 128 bytes per loop.

        mov     ecx,1024
looper:
offset2 = 0
REPEAT UNROLL_AMT
        prefetchnta [edi+offset2+128] ; prefetch 128 bytes into the L1 cache before we need it.
        add     eax,[edi+offset2]
offset2 = offset2 + UNROLL_NUM_BYTES
        add     edi,UNROLL_AMT * UNROLL_NUM_BYTES ;we dealt with 16*4 bytes.
        sub     ecx,UNROLL_AMT        ; subtract from loop counter the # of loops we unrolled.
        jnz     looper

  11. Cache Blocking

    Let's say you have to call multiple procedures on this big array in memory. It is better to break it up into blocks that fit into the cache to reduce cache misses. For example if you were doing 3D code, the first procedure might translate your coordinates, the second might scale and the third might rotate. So instead of going through the whole huge array in one fell swoop. You break off a "chunk" of the data that fits into the cache, and then call all 3 procedures, and then go to the next chunk and repeat.

  12. TLB Priming

    The TLB is the Translation Lookaside Buffer. The TLB is cache that is used to improve performance of the translation of a virtual memory address to a physical memory address by providing fast access to page table entries. Having it not in the TLB cache forces a cache misse which slows the code down. The trick is to pre-read a data byte from the next page before you have to read it. I will show an example later on in another one of the tips.

  13. Intermix your code to break dependencies.

    In C code the C compiler treats different chunks of code as seperate. To break dependencies, when you get to the assembler level you can intermix them

  14. Parallelization.

    Most Compilers don't take advantage of the fact you have 2 pipelines for ALU stuff, which is the majority of what people use. On the P4 you have it even sweeter. You can execute 4 ALU instructions in 1 cycle if you do it right. If you break things up into doing stuff in parallel it also helps break up dependencies. So you kill two birds with one stone. Assume this piece is in a loop.

    looper:
        mov     eax,[esi]
        xor     eax,0E5h        ;dependency with the line above it.
        add     [edi],eax       ;dependency with the line above it.
        add     esi,4
        add     edi,4
        dec     ecx
        jnz     looper

;So how do we 'parallelize' it and reduce dependencies?
looper:
        mov     eax,[esi]
        mov     ebx,[esi+4]
        xor     eax,0E5
        xor     ebx,0E5
        add     [edi],eax
        add     [edi+4],ebx
        add     esi,8
        add     edi,8
        sub     ecx,2
        jnz     looper

  15. Avoiding memory accesses

    Re-structing the code to avoid memory accesses ( or other I/O). One method is to accumulate a value in a register before writing it to memory. Here is an example of that below. In this example assuming we are adding 3 bytes from the source array to the destination array which is an array of dwords. The destination array is zeroed.

            mov     ecx,AMT_TO_LOOP
looper:
        movzx byte ptr eax,[esi]
        add     [edi],eax
        movzx byte ptr eax,[esi+1]
        add     [edi],eax
        movzx byte ptr eax,[esi+3]
        add     [edi],eax
        add     edi,4
        add     esi,3
        dec     ecx
        jnz     looper
    We can accumulate the result in a register, and then only do one write to memory.
            mov     ecx,AMT_TO_LOOP
looper:
        xor     edx,edx                 ;zero out register to accumulate the result in.
        movzx byte ptr eax,[esi]
        add     edx,eax
        movzx byte ptr eax,[esi+1]
        add     edx,eax
        movzx byte ptr eax,[esi+3]
        add     edx,eax
        add     esi,3
        mov     [edi],edx
        add     edi,4
        dec     ecx
        jnz     looper

  16. When to convert a call to a jump

    if the last statement in a routine is a call consider converting it to a jump to get rid of one call/ret.

  17. Using arrays for data structures

    (This is non-assembler related, but it's a great one). You can use an array for data structures such as trees and linked lists. By using an array the memory ends up being contiguous and you get a speed up due to less cache misses.

Advanced

  1. Avoid prefixes

    Try to avoid prefixes ( prefixes get generated for a number of things including segment overrides, branch hints, operand-size override, address-size override, LOCKs, and REPs). Prefixes make your instructions longer.

  2. Grouping reads/writes in code

    If there is a bunch of alternating between read and write transactions on the bus, look at grouping and doing more reads at a time and more writes at a time. Here is what we are trying to avoid:

            mov eax,[esi]
        mov [edi],eax
        mov eax,[esi+4]
        mov [edi+4],eax
        mov eax,[esi+8]
        mov [edi+8],eax
        mov eax,[esi+12]
        mov [edi+12],eax

;Grouping the reads and writes together this gets converted to
        mov eax,[esi]
        mov ebx,[esi+4]
        mov ecx,[esi+8]
        mov edx,[esi+12]
        mov [edi],eax
        mov [edi+4],ebx
        mov [edi+8],ecx
        mov [edi+12],edx

  3. Making use of execution units to make your code run faster

    Choose instructions that execute on different execution units. If you do this properly the time to execute the code will be the throughput time and not the latency time. For most instructions the throughput time is less.

  4. Interleaving 2 loops out of sync

    You can unroll a loop twice, and instead of running each instruction after each other, you can run them out of sync. Why is this useful? 2 reasons. First, sometimes you have instructions that have to use a certain register and have a long latency such as MUL or DIV. That creates a dependency on EDX:EAX for the two MUL instructions in a row. Second, sometimes some instructions just have really long latencies. So you want to try and place a number of instructions after it from the other loop to help delay until it returns the result. A lot of MMX, SSE, and SSE2 instructions on the P4 fall into that category. Here is an example loop: A1 ; instruction 1 loop 1 D2 ; instruction 4 loop 2 B1 ; instruction 2 loop 1 A2 ; instruction 1 loop 2 C1 ; instruction 3 loop 1 B2 ; instruction 2 loop 2 D1 ; instruction 4 loop 1 C2 ; instruction 3 loop 2

  5. Different tricks you can do with masks created by comparison instructions using MMX/SSE/SSE2.

    With MMX and SSE and SSE2 you can generate masks when doing comparisons. This can be helpful in some cases when looking for a pattern in a file, such as a line feed. So you can use it to search for patterns, not just math operations.

    You can use MMX, SSE, and SSE2 masks that get generated by a compare instruction to control doing math on only part of a MMX or SSE register. The following piece of code only adds a 9 to the dword parts of an MMX register if it has a 5 in it.

    ; if (fredvariable == 5)
;       fredvariable += 9;
    movq     mm5,[two_fives]        ;mm5 has 2 DWORD 5's in it.
    movq     mm6,[two_nines]        ;mm6 has 2 DWORD 9's in it.
    movq     mm0,[array_in_memory]  ;get value
    movq     mm1,mm0                ;get backup copy
    pcmpeqd  mm1,mm5                ;mm1 now has an FFFFFFFF in each dword location
                                    ; in MM1 with a 5 all other locations have 0.
    pand     mm1,mm6                ;zero out the locations in MM6 that don't
                                    ; have 5's in them for MM0.
    paddd    mm0,mm1                ;add 9 ONLY to the locations in MM0 that
                                    ; have a 5 in them.

  6. PSHUFD and PSHUFW.

    On the P4 MMX, SSE and SSE2 move instructionns are slow. You can get around this by doind "pshufd" for the SSE and SSE2 and "pshufw" for MMX. It is 2 cycles faster. There is one caveat. It has to do with what pipeline the opcode goes down. So without getting too technical, sometimes it is faster to use the slower "MOVDQA" than to replace it with a "PSHUFD". So time your code.

            pshufd  xmm0,[edi],0E4h     ;copy 16 bytes at location EDI into XMM0.
                                    ; The 0E4h makes it a straight copy.
        pshufw  mm0,[edi],0E4h      ;copy 8 bytes at location EDI into MM0.
                                    ; The 0E4h makes it a straight copy.

  7. Write directly to memory - bypass the cache.

    Another optimization dealing with memory. If you have to write to a lot of memory (256KB and up) it is faster to write directly to memory bypassing the cache. If you have a P3 you can use "movntq" or "movntps". The first does an 8 byte write, the second a 16-byte. The 16-byte write needs to be 16-byte aligned. On the P4 you also get "movntdq", which does 16-bytes also, but needs to be 16-byte aligned. This trick applies to both memory fills and memory copies. Both do a write operation. Here is some sample code. I personally would do 8 XMM registers in parallel to help break up some of the latencies for the P4 MOVDQA instruction. However to help understanding, I did not do that.

            mov     ecx,16384           ;write 16384 16-byte values, 16384*16 = 256KB.
                                    ; So we are copying a 256KB array
        mov     esi,offset src_arr  ;pointer to the source array which has to be
                                    ; 16-byte aligned or you will get an exception.
        mov     edi,offset dst_arr  ;pointer to the destination array which has to be
                                    ; 16-byte aligned or you will get an exception.
looper:
        movdqa  xmm0,[esi]          ;works on P3 and up
        movntps [edi],xmm0          ;Works on P3 and up
        add     esi,16
        add     edi,16
        dec     ecx
        jnz     looper

  8. Handle 2 cases per loop for MMX/SSE/SSE2.

    On the P4 the latencies are usually so long on the MMX, SSE and SSE2 instructions that I always handle 2 cases per loop, or read a loop in advance. Or more than 2 cases if I have enough registers. All the various MOVE ( including MOVD) instructions on P4 are slow. So adding 2 32-bit arrays of numbers together is going to be slower on the P4 than the P3. A faster way would be to do two per loop, where you pre-read the loops initial values MM0 and MM1 before the FRED label. You just have to have special handling if you have an odd number of array elements. Just check that at the end, and if so add code for that one extra dword. Here is the code that does not read a value in advance. I think converting this to read a value in advance is easy. So that is why I am not posting both. This is how you would avoid ADC on a P4, which is a slow instruction, to add two arrays together.

        pxor    mm7,mm7     ; the previous loops carry stays in here.
fred:
    movd    mm0,[esi]   ; esi points to src1
    movd    mm1,[edi]   ; edi points to src2, also to be used as the destination.
    paddq   mm0,mm1     ; add both values together
    paddq   mm0,mm7     ; add in remainder from last add.
    movd    [edi],mm0   ; save value to memory
    movq    mm7,mm0
    psrlq   mm7,32      ; shift the carry over to bit 0.
    add     esi,8
    add     edi,8
    sub     ecx,1
    jnz     fred
    movd    [edi],mm7   ; save carry

  9. Pre-reading MMX or XMM register to get around long latency

    Pre-reading an SSE2 register before you need it will give a speed up. That is because MOVDQA takes 6 cycles on a P4. That is really slow. So because it has such a long latency, I want to read it in advance of where I use it to make sure it doens't stall. Here is an example. movdqa xmm1,[edi+16] ;read in XMM1 before we use it, takes 6 cycles on P4, not including the time to get it from cache. por xmm5,xmm0 ;do an OR with XMM0 which was previously read. Takes 2 cycles on the P4. pand xmm6,xmm0 ;do an AND with XMM0 which was previously read. Takes 2 cycles on the P4. movdqa xmm2,[edi+32] ;read in XMM2 before we use it, takes 6 cycles on P4, not including the time to get it from cache. por xmm5,xmm1 ;do an OR with XMM1 which was previously read. Takes 2 cycles on the P4. pand xmm6,xmm1 ;do an AND with XMM1 which was previously read. Takes 2 cycles on the P4.

  10. Accumulating a result in a register or registers to avoid doing a slow instruction

    Accumulating a result in a register or registers to avoid doing a slow instruction. I did this to speed up a compare/read loop written in SSE2. The slow instruction was PMOVMSKB. So instead of executing it every loop, I accumulated a result in a register. And then every 4KB of memory read, I would do a PMOVMSKB. This gave a good speed up. The example below will also demonstrate using PREFETCH and TLB Priming. Their are 2 loops in the below code. The inner loop is unrolled to 128 bytes( the number of bytes fetched by PREFETCH on a P4). The outer loop is unrolled to 4KB, so that it can do TLB Priming. If you are using a system that doesn't use a 4KB page size, you'd have to do modify the code appropriately. On the system I tested this on ( a Dell Server) with 6.4 GB/s of max memory bandwidth, I was able to do a read and a compare at 5.55 GB/s ( in a non-Windows environment. Under windows it will run slower). I left out the code that at label "compare_failed", for 2 reasons. 1) The cut/paste of code is already big. 2) It doesn't demosntrate any techniques I want to show. The code at "compare_failed" simply does a REP SCASD to find the failing address after PCMPEQD finds it to the nearest 4KB block. This one has a HUGE code example, so I put it last in case you fall asleep reading it ;)

    read_compare_pattern_sse2 proc near

                mov         edi,[start_addr]        ;Starting Address
                mov         ecx,[stop_addr]         ;Last addr to NOT test.
                mov         ebx,0FFFFFFFFh          ;AND mask
                movd        xmm6,ebx                ;AND mask
                pshufd      xmm6,xmm6,00000000b     ;AND mask
                movdqa      xmm0,[edi]              ;Get first 16 bytes
                mov         eax,[pattern]           ;EAX holds pattern
                pxor        xmm5,xmm5               ;OR mask
                movd        xmm7,eax                ;Copy EAX to XMM7
                pshufd      xmm7,xmm7,00000000b     ;Blast to all DWORDS
outer_loop:
                mov         ebx,32                  ;128 32 byte blocks
                mov         esi,edi                 ;save start of block

if DO_TLB_PRIMING
                mov         eax,[edi+4096]          ;TLB priming
endif ; if DO_TLB_PRIMING

fred_loop:
                movdqa      xmm1,[edi+16]           ;read 16 bytes
                por         xmm5,xmm0               ;OR into mask
                pand        xmm6,xmm0               ;AND into mask

                movdqa      xmm2,[edi+32]           ;read 16 bytes
                por         xmm5,xmm1               ;OR into mask
                pand        xmm6,xmm1               ;AND into mask

                movdqa      xmm3,[edi+48]           ;read 16 bytes
                por         xmm5,xmm2               ;OR into mask
                pand        xmm6,xmm2               ;AND into mask

                movdqa      xmm0,[edi+64]           ;read 16 bytes
                por         xmm5,xmm3               ;OR into mask
                pand        xmm6,xmm3               ;AND into mask

                movdqa      xmm1,[edi+80]           ;read 16 bytes
                por         xmm5,xmm0               ;OR into mask
                pand        xmm6,xmm0               ;AND into mask

                movdqa      xmm2,[edi+96]           ;read 16 bytes
                por         xmm5,xmm1               ;OR into mask
                pand        xmm6,xmm1               ;AND into mask

                movdqa      xmm3,[edi+112]          ;read 16 bytes
                por         xmm5,xmm2               ;OR into mask
                pand        xmm6,xmm2               ;AND into mask

                por         xmm5,xmm3               ;OR into mask
                prefetchnta [edi+928]               ;Prefetch 928 ahead
                pand        xmm6,xmm3               ;AND into mask

                add         edi,128                 ;Go next 128byteblock
                cmp         edi,ecx                 ;At end?
                jae         do_compare              ;No, jump

                movdqa      xmm0,[edi]              ;read 16 bytes

                sub         ebx,1                   ;Incr for inner loop
                jnz         fred_loop

do_compare:
                pcmpeqd     xmm5,xmm7               ;Equal?
                pmovmskb    eax,xmm5                ;Grab high bits in EAX
                cmp         eax,0FFFFh              ;all set?
                jne         compare_failed          ;No, exit failure

                mov         edx,0FFFFFFFFh          ;AND mask
                pxor        xmm5,xmm5
                pcmpeqd     xmm6,xmm7               ;Equal?

                pmovmskb    eax,xmm6                ;Grab high bits in EAX
                cmp         eax,0FFFFh              ;All Set?
                jne         compare_failed          ;No, exit failure

                movd        xmm6,edx                ;AND mask
                pshufd      xmm6,xmm6,00000000b     ;AND mask

                cmp         edi,ecx                 ;We at end of range
                jb          outer_loop              ;No, loop back up

                jmp         compare_passed          ;Done!!! Success!!!

  11. Prefetch distance and location within the loop

    You will notice in the previous example that I prefetch 928 bytes ahead instead of 128, when 128 is the number of bytes fetched on a P4. Why is that? Well Intel recmomends prefetching 128 bytes ( 2 cache lines) ahead at the start of your loop. I found both statements ( doing at the beginning of the loop and prefetching 128 bytes ahead) to be wrong. I don't prefetch at the beginning of the loop nor do I prefetch 128 bytes ahead. Why? Well when I was playing with the code I found that I could make it run faster by moving the PREFETCH instruction around in the loop and changing the offest for how far ahead it prefetches. So being the geek I am I wrote code to try all combinations of the location of the prefetch instruction in the loop and offsets to begin prefetching. The code takes an assembler file and moves the "prefetch" instruction around inside a loop, and also modifies the offset to begin prefetching. Then a batch file compiles the just modified code, and runs a benchmark. I ran the benchmark over several hours to try the different combinations ( I started at a prefetch distance of 32, and went up to 1024, in increments of 32). On the system I wrote the code on 928 ahead instead of 128 was the fastest. And prefetching almost at the end of the loop was fastest ( the prefetchnta instruction is about 8 lines above the do_compare: label)

# # #

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Intel x86 Instruction Reference

This help file provides a list of assembly instructions and a short description of the function of each one.

It is not intended to be exhaustive documentation on the fine details of the instructions function, such as which exceptions they can trigger etc. - for such documentation, you should consult Intel's manuals - Intel's Web site is here http://www.intel.com

This is intended primarily to provide documentation on the way the instructions may be used within the LCC-Win32 compiler and using AT&T's syntax.

Key to Operand Specifications
Key to Opcode Descriptions
Key to Instruction Flags

AAA, AAS, AAM, AAD: ASCII Adjustments
ADC: Add with Carry
ADD: Add Integers
AND: Bitwise AND
ARPL: Adjust RPL Field of Selector
BOUND: Check Array Index against Bounds
BSF, BSR: Bit Scan
BSWAP: Byte Swap
BT, BTC, BTR, BTS: Bit Test

CALL: Call Subroutine
CBW, CWD, CDQ, CWDE: Sign Extensions
CLC, CLD, CLI, CLTS: Clear Flags
CMC: Complement Carry Flag
CMOVcc: Conditional Move
CMP: Compare Integers
CMPSB, CMPSW, CMPSD: Compare Strings
CMPXCHG: Compare and Exchange
CMPXCHG8B: Compare and Exchange Eight Bytes
CPUID: Get CPU Identification Code
DAA, DAS: Decimal Adjustments
DEC: Decrement Integer
DIV: Unsigned Integer Divide
ENTER: Create Stack Frame
HLT: Halt Processor
IDIV: Signed Integer Divide
IMUL: Signed Integer Multiply
IN: Input from I/O Port
INC: Increment Integer
INSB, INSW, INSD: Input String from I/O Port
INT: Software Interrupt
INT3, INT1, ICEBP, INT01: Breakpoints
INTO: Interrupt if Overflow
INVD: Invalidate Internal Caches
IRET, IRETW, IRETD: Return from Interrupt
JCXZ, JECXZ: Jump if CX/ECX Zero
JMP: Jump
JCC: Conditional Branch
LAHF: Load AH from Flags
LAR: Load Access Rights
LDS, LES, LFS, LGS, LSS: Load Far Pointer
LEA: Load Effective Address
LEAVE: Destroy Stack Frame
LGDT, LIDT, LLDT: Load Descriptor Tables
LMSW: Load/Store Machine Status Word
LOCK: Lock Bus
LODSB, LODSW, LODSD: Load from String
LOOP, LOOPE, LOOPZ, LOOPNE, LOOPNZ: Loop with Counter
LSL: Load Segment Limit
LTR: Load Task Register
MOV: Move Data
MOVD: Move Doubleword to/from MMX Register
MOVQ: Move Quadword to/from MMX Register
MOVSB, MOVSW, MOVSD: Move String
MOVSX, MOVZX: Move Data with Sign or Zero Extend
MUL: Unsigned Integer Multiply
NEG, NOT: Two's and One's Complement
NOP: No Operation
OR: Bitwise OR
OUT: Output Data to I/O Port
OUTSB, OUTSW, OUTSD: Output String to I/O Port
POP: Pop Data from Stack
POPA: Pop All General-Purpose Registers
POPF: Pop Flags Register
PUSH: Push Data on Stack
PUSHA: Push All General-Purpose Registers
PUSHF: Push Flags Register
RCL, RCR: Bitwise Rotate through Carry Bit
RDMSR: Read Model-Specific Registers
RDPMC: Read Performance-Monitoring Counters
RDTSC: Read Time-Stamp Counter
RET, LRET: Return from Procedure Call
ROL, ROR: Bitwise Rotate
RSM: Resume from System-Management Mode
SAHF: Store AH to Flags
SAL, SAR: Bitwise Arithmetic Shifts
SBB: Subtract with Borrow
SCASB, SCASW, SCASD: Scan String
SETcc: Set Register from Condition
SGDT, SIDT, SLDT: Store Descriptor Table Pointers
SHL, SHR: Bitwise Logical Shifts
SHLD, SHRD: Bitwise Double-Precision Shifts
SMSW: Store Machine Status Word
STC, STD, STI: Set Flags
STOSB, STOSW, STOSD: Store Byte to String
STR: Store Task Register
SUB: Subtract Integers
TEST: Test Bits (notional bitwise AND)
WAIT FWAIT: Wait for Floating-Point Processor
WBINVD: Write Back and Invalidate Cache
WRMSR: Write Model-Specific Registers
XADD: Exchange and Add
XCHG: Exchange
XLAT: Translate Byte in Lookup Table

XOR: Bitwise Exclusive OR


AAA, AAS, AAM, AAD: ASCII Adjustments

aaa
aas
aad
aad imm
aam
aam imm

These instructions are used in conjunction with the add, subtract, multiply and divide instructions to perform binary-coded decimal arithmetic in unpacked (one BCD digit per byte – easy to translate to and from ASCII, hence the instruction names) form. There are also packed BCD instructions. DAA, DAS.

AAA should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the low nibble of AL and also the auxiliary carry flag AF, it determines whether the addition has overflowed, and adjusts it (and sets the carry flag) if so. You can add long BCD strings together by doing ADD/AAA on the low digits, then doing ADC/AAA on each subsequent digit.

AAS works similarly to AAA, but is for use after SUB instructions rather than ADD.

AAM is for use after you have multiplied two decimal digits together and left the result in AL: it divides AL by ten and stores the quotient in AH, leaving the remainder in AL. The divisor 10 can be changed by specifying an operand to the instruction: a particularly handy use of this is AAM 16, causing the two nibbles in AL to be separated into AH and AL.

AAD performs the inverse operation to AAM: it multiplies AH by ten, adds it to AL, and sets AH to zero. Again, the multiplier 10 can be changed.


ADC: Add with Carry

adc reg8,r/m8
adc reg16,r/m16
adc reg32,r/m32
adc r/m8,reg8
adc r/m16,reg16
adc r/m32,reg32
adc imm8,r/m8
adc imm16,r/m16
adc imm32,r/m32
adc imm8,r/m16
adc imm8,r/m32
adc imm8,al
adc imm16,ax
adc imm32,eax

ADC performs integer addition, it adds its two operands together, plus the value of the carry flag, and leaves the result in its destination (first) operand. The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction.

In the forms with an 8-bit immediate first operand and a longer second operand, the first operand is considered to be signed, and is sign-extended to the length of the second operand.

To add two numbers without also adding the contents of the carry flag, use ADD (ADD).


ADD: Add Integers

add reg8,r/m8
add reg16,r/m16
add reg32,r/m32
add r/m8,reg8
add r/m16,reg16
add r/m32,reg32
add imm8,r/m8
add imm16r/m16
add imm32,r/m32
add imm8,r/m16
add imm8,r/m32
add imm8,al
add imm16,ax
add imm32,eax

ADD performs integer addition: it adds its two operands together, and leaves the result in its destination (second) operand. The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent ADC instruction (ADC).

In the forms with an 8-bit immediate first operand and a longer second operand, the first operand is considered to be signed, and is sign-extended to the length of the second operand.


AND: Bitwise AND

and reg8,r/m8
and reg16,r/m16
and reg32,r/m32
and r/m8,reg8
and r/m16,reg16
and reg32,r/m32
and imm8,r/m8
and imm16,r/m16
and imm32,r/m32
and imm8,r/m16
and imm8,r/m32
and imm8,al
and imm16,ax
and imm32,eax

AND performs a bitwise AND operation between its two operands (i.e. each bit of the result is 1 if and only if the corresponding bits of the two inputs were both 1), and stores the result in the destination (first) operand.

In the forms with an 8-bit immediate first operand and a longer second operand, the first operand is considered to be signed, and is sign-extended to the length of the second operand.

The MMX instruction PAND (see PAND, PANDN) performs the same operation on the 64-bit MMX registers.


ARPL: Adjust RPL Field of Selector

arpl reg16,r/m16

ARPL expects its two word operands to be segment selectors. It adjusts the RPL (requested privilege level – stored in the bottom two bits of the selector) field of the destination (first) operand to ensure that it is no less (i.e. no more privileged than) the RPL field of the source operand. The zero flag is set if and only if a change had to be made.


BOUND: Check Array Index against Bounds

boundw mem,reg16
boundl mem,reg32

BOUND expects its first operand to point to an area of memory containing two signed values of the same size as its second operand (i.e. two words for the 16-bit form; two doublewords for the 32-bit form). It performs two signed comparisons: if the value in the register passed as its second operand is less than the second of the in-memory values, or is greater than or equal to the first, it throws a BR exception. Otherwise, it does nothing.


BSF, BSR: Bit Scan

bsfw r/m16,reg16
bsfl r/m32,reg32
bsrw r/m16,reg16
bsrl r/m32,reg32

BSF searches for a set bit in its source (first) operand, starting from the bottom, and if it finds one, stores the index in its destination (second) operand. If no set bit is found, the contents of the destination operand are undefined.

BSR performs the same function, but searches from the top instead, so it finds the most significant set bit.

Bit indices are from 0 (least significant) to 15 or 31 (most significant).


BSWAP: Byte Swap

bswap reg32

BSWAP swaps the order of the four bytes of a 32-bit register: bits 0-7 exchange places with bits 24-31, and bits 8-15 swap with bits 16-23. There is no explicit 16-bit equivalent: to byte-swap AX, BX, CX or DX, XCHG can be used.


BT, BTC, BTR, BTS: Bit Test

bt  reg16,r/m16
bt  reg32,r/m32
bt  imm8,r/m16
bt  imm8,r/m32
btc reg16,r/m16
btc reg32,r/m32
btc imm8,r/m16
btc imm8,r/m32
btr reg16,r/m16
btr reg32,r/m32
btr imm8,r/m16
btr imm8,r/m32
bts reg16,r/m16
bts reg32,r/m32
bts imm,r/m16
bts imm,r/m32

These instructions all test one bit of their second operand, whose index is given by the first operand, and store the value of that bit into the carry flag. Bit indices are from 0 (least significant) to 15 or 31 (most significant).

In addition to storing the original value of the bit into the carry flag, BTR also resets (clears) the bit in the operand itself. BTS sets the bit, and BTC complements the bit. BT does not modify its operands.

The bit offset should be no greater than the size of the operand.


CALL: Call Subroutine

call  imm
call  label
call  r/m32
lcall imm:imm
lcall label

CALL calls a subroutine, by means of pushing the current instruction pointer (EIP) and (CS) as well on the stack, and then jumping to a given address.


CBW, CWD, CDQ, CWDE: Sign Extensions

cbw
cwd
cdq
cwde

All these instructions sign-extend a short value into a longer one, by replicating the top bit of the original value to fill the extended one.

CBW extends AL into AX by repeating the top bit of AL in every bit of AH. CWD extends AX into DX:AX by repeating the top bit of AX throughout DX. CWDE extends AX into EAX, and CDQ extends EAX into EDX:EAX.


CLC, CLD, CLI, CLTS: Clear Flags

clc
cld
cli
clts

These instructions clear various flags. CLC clears the carry flag; CLD clears the direction flag; CLI clears the interrupt flag (thus disabling interrupts); and CLTS clears the task-switched (TS) flag in CR0.

To set the carry, direction, or interrupt flags, use the STC, STD and STI instructions (STC, STD, STI). To invert the carry flag, use CMC (CMC).


CMC: Complement Carry Flag

cmc

CMC changes the value of the carry flag: if it was 0, it sets it to 1, and vice versa.


CMOVcc: Conditional Move

cmova   r/m16,r16 Move if above (CF=0 and ZF=0)
cmova   r/m32,r32 Move if above (CF=0 and ZF=0)
cmovae  r/m16,r16 Move if above or equal (CF=0)
cmovae  r/m32,r32 Move if above or equal (CF=0)
cmovb   r/m16,r16 Move if below (CF=1)
cmovb   r/m32,r32 Move if below (CF=1)
cmovbe  r/m16,r16 Move if below or equal (CF=1 or ZF=1)
cmovbe  r/m32,r32 Move if below or equal (CF=1 or ZF=1)
cmovc   r/m16,r16 Move if carry (CF=1)
cmovc   r/m32,r32 Move if carry (CF=1)
cmove   r/m16,r16 Move if equal (ZF=1)
cmove   r/m32,r32 Move if equal (ZF=1)
cmovg   r/m16,r16 Move if greater (ZF=0 and SF=of)
cmovg   r/m32,r32 Move if greater (ZF=0 and SF=of)
cmovge  r/m16,r16 Move if greater or equal (SF=of)
cmovge  r/m32,r32 Move if greater or equal (SF=of)
cmovl   r/m16,r16 Move if less (SF<>of)
cmovl   r/m32,r32 Move if less (SF<>of)
cmovle  r/m16,r16 Move if less or equal (ZF=1 or SF<>of)
cmovle  r/m32,r32 Move if less or equal (ZF=1 or SF<>of)
cmovna  r/m16,r16 Move if not above (CF=1 or ZF=1)
cmovna  r/m32,r32 Move if not above (CF=1 or ZF=1)
cmovnae r/m16,r16 Move if not above or equal (CF=1)
cmovnae r/m32,r32 Move if not above or equal (CF=1)
cmovnb  r/m16,r16 Move if not below (CF=0)
cmovnb  r/m32,r32 Move if not below (CF=0)
cmovnbe r/m16,r16 Move if not below or equal (CF=0 and ZF=0)
cmovnbe r/m32,r32 Move if not below or equal (CF=0 and ZF=0)
cmovnc  r/m16,r16 Move if not carry (CF=0)
cmovnc  r/m32,r32 Move if not carry (CF=0)
cmovne  r/m16,r16 Move if not equal (ZF=0)
cmovne  r/m32,r32 Move if not equal (ZF=0)
cmovng  r/m16,r16 Move if not greater (ZF=1 or SF<>of)
cmovng  r/m32,r32 Move if not greater (ZF=1 or SF<>of)
cmovnge r/m16,r16 Move if not greater or equal (SF<>of)
cmovnge r/m32,r32 Move if not greater or equal (SF<>of)
cmovnl  r/m16,r16 Move if not less (SF=of)
cmovnl  r/m32,r32 Move if not less (SF=of)
cmovnle r/m16,r16 Move if not less or equal (ZF=0 and SF=OF)
cmovnle r/m32,r32 Move if not less or equal (ZF=0 and SF=OF)
cmovno  r/m16,r16 move if not overflow (OF=0)
cmovno  r/m32,r32 move if not overflow (OF=0)
cmovnp  r/m16,r16 move if not parity (PF=0)
cmovnp  r/m32,r32 move if not parity (PF=0)
cmovns  r/m16,r16 move if not sign (SF=0)
cmovns  r/m32,r32 move if not sign (SF=0)
cmovnz  r/m16,r16 move if not zero (ZF=0)
cmovnz  r/m32,r32 move if not zero (ZF=0)
cmovo   r/m16,r16 move if overflow (OF=0)
cmovo   r/m32,r32 move if overflow (OF=0)
cmovp   r/m16,r16 move if parity (PF=1)
cmovp   r/m32,r32 move if parity (PF=1)
cmovpe  r/m16,r16 move if parity even (PF=1)
cmovpe  r/m32,r32 move if parity even (PF=1)
cmovpo  r/m16,r16 move if parity odd (PF=0)
cmovpo  r/m32,r32 move if parity odd (PF=0)
cmovs   r/m16,r16 move if sign (SF=1)
cmovs   r/m32,r32 move if sign (SF=1)
cmovz   r/m16,r16 move if zero (ZF=1)
cmovz   r/m32,r32 move if zero (ZF=1)

CMOV moves its source (first) operand into its destination (second) operand if the given condition code is satisfied; otherwise it does nothing.

Although the CMOV instructions are flagged P6 above, they may not be supported by all Pentium Pro processors; the CPUID instruction (CPUID) will return a bit which indicates whether conditional moves are supported.


CMP: Compare Integers

cmpb reg8,r/m8
cmpl reg32,r/m32
cmpb r/m8,reg8
cmpw r/m16,reg16
cmpl r/m32,reg32
cmpb imm8,r/m8
cmpw imm16,r/m16
cmpl imm32,r/m32
cmpb imm8,r/m16
cmpb imm8,r/m32
cmpb imm8,al
cmpw imm16,ax
cmpl imm32,eax

CMP performs a 'mental' subtraction of its first operand from its second operand, and affects the flags as if the subtraction had taken place, but does not store the result of the subtraction anywhere.

In the forms with an 8-bit immediate first operand and a longer second operand, the first operand is considered to be signed, and is sign-extended to the length of the first operand.


CMPSB, CMPSW, CMPSL: Compare Strings

cmpsb
cmpsw
cmpsl

CMPSB compares the byte at [ESI] with the byte at [EDI], and sets the flags accordingly. It then increments or decrements (depending on the direction flag: increments if the flag is clear, decrements if it is set) ESI and EDI.

CMPSW and CMPSL work in the same way, but they compare a word or a doubleword instead of a byte, and increment or decrement the addressing registers by 2 or 4 instead of 1.

The REPE and REPNE prefixes (equivalently, REPZ and REPNZ) may be used to repeat the instruction up to CX or ECX times until the first unequal or equal byte is found.


CMPXCHG: Compare and Exchange

_asm("lock");
_asm("cmpxchg (%ecx),%ebx");

cmpxchg reg8,r/m8
cmpxchg reg16,r/m16
cmpxchg reg32,r/m32

CMPXCHG compares its destination (first) operand to the value in AL, AX or EAX (depending on the size of the instruction). If they are equal, it copies its source (second) operand into the destination and sets the zero flag. Otherwise, it clears the zero flag and leaves the destination alone.

CMPXCHG is intended to be used for atomic operations in multitasking or multiprocessor environments. To safely update a value in shared memory, for example, you might load the value into EAX, load the updated value into EBX, and then execute the instruction lock cmpxchg [value],ebx. If value has not changed since being loaded, it is updated with your desired new value, and the zero flag is set to let you know it has worked. (The LOCK prefix prevents another processor doing anything in the middle of this operation: it guarantees atomicity.) However, if another processor has modified the value in between your load and your attempted store, the store does not happen, and you are notified of the failure by a cleared zero flag, so you can go round and try again.


CMPXCHG8B: Compare and Exchange Eight Bytes

cmpxch8b mem

This is a larger and more unwieldy version of CMPXCHG: it compares the 64-bit (eight-byte) value stored at [mem] with the value in EDX:EAX. If they are equal, it sets the zero flag and stores ECX:EBX into the memory area. If they are unequal, it clears the zero flag and leaves the memory area untouched.


CPUID: Get CPU Identification Code

cpuid

CPUID returns various information about the processor it is being executed on. It fills the four registers EAX, EBX, ECX and EDX with information, which varies depending on the input contents of EAX.

CPUID also acts as a barrier to serialise instruction execution: executing the CPUID instruction guarantees that all the effects (memory modification, flag modification, register modification) of previous instructions have been completed before the next instruction gets fetched.

The information returned is as follows:

If EAX is zero on input, EAX on output holds the maximum acceptable input value of EAX, and EBX:EDX:ECX contain the string "GenuineIntel" (or not, if you have a clone processor). That is to say, EBX contains "Genu", EDX contains "ineI" and ECX contains "ntel".

If EAX is one on input, EAX on output contains version information about the processor, and EDX contains a set of feature flags, showing the presence and absence of various features. For example, bit 8 is set if the CMPXCHG8B instruction is supported, bit 15 is set if the conditional move instructions (CMOV and FCMOV) are supported, and bit 23 is set if MMX instructions are supported.

If EAX is two on input, EAX, EBX, ECX and EDX all contain information about caches and TLBs (Translation Lookahead Buffers).

For more information on the data returned from CPUID, see the documentation on Intel's web site.


DAA, DAS: Decimal Adjustments

daa
das

These instructions are used in conjunction with the add and subtract instructions to perform binary-coded decimal arithmetic in packed (one BCD digit per nibble) form. For the unpacked equivalents, see AAA, AAS, AAM, AAD.

DAA should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the AL and also the auxiliary carry flag AF, it determines whether either digit of the addition has overflowed, and adjusts it (and sets the carry and auxiliary-carry flags) if so. You can add long BCD strings together by doing ADD/DAA on the low two digits, then doing ADC/DAA on each subsequent pair of digits.

DAS works similarly to DAA, but is for use after SUB instructions rather than ADD.


DEC: Decrement Integer

decw reg16
decl reg32
decb r/m8
decw r/m16
decl r/m32

DEC subtracts 1 from its operand. It does not affect the carry flag: to affect the carry flag, use SUB. (see SUB and INC).


DIV: Unsigned Integer Divide

div r/m8
div r/m16
div r/m32

DIV performs unsigned integer division. The explicit operand provided is the divisor; the dividend and destination operands are implicit, in the following way:

For DIV r/m8, AX is divided by the given operand; the quotient is stored in AL and the remainder in AH.

For DIV r/m16, DX:AX is divided by the given operand; the quotient is stored in AX and the remainder in DX.

For DIV r/m32, EDX:EAX is divided by the given operand; the quotient is stored in EAX and the remainder in EDX.

Signed integer division is performed by the IDIV instruction.


ENTER: Create Stack Frame

enter imm,imm

ENTER constructs a stack frame (intended for high-level languages). The first operand (the iw in the opcode definition above refers to the first operand) gives the amount of stack space to allocate for local variables; the second (the ib above) gives the nesting level of the procedure (for languages like Pascal, with nested procedures).

The function of ENTER, with a nesting level of zero, is equivalent to

PUSHL EBP

MOVL ESP,EBP

SUBL $xx,ESP

This creates a stack frame with the procedure parameters accessible upwards from EBP, and local variables accessible downwards from EBP.

With a nesting level of one, the stack frame created is 4 (or 2) bytes bigger, and the value of the final frame pointer EBP is accessible in memory at -4(%EBP).

This allows ENTER, when called with a nesting level of two, to look at the stack frame described by the previous value of EBP, find the frame pointer at offset –4 from that, and push it along with its new frame pointer, so that when a level-two procedure is called from within a level-one procedure, -4(%EBP) holds the frame pointer of the most recent level-one procedure call and -8(%EBP) holds that of the most recent level-two call. And so on, for nesting levels up to 31.

Stack frames created by ENTER can be destroyed by the LEAVE instruction.


HLT: Halt Processor

hlt

HLT puts the processor into a halted state, where it will perform no more operations until restarted by an interrupt or a reset.


IDIV: Signed Integer Divide

idiv r/m8
idiv r/m16
idiv r/m32

IDIV performs signed integer division. The explicit operand provided is the divisor; the dividend and destination operands are implicit, in the following way:

For IDIV r/m8, AX is divided by the given operand; the quotient is stored in AL and the remainder in AH.

For IDIV r/m16, DX:AX is divided by the given operand; the quotient is stored in AX and the remainder in DX.

For IDIV r/m32, EDX:EAX is divided by the given operand; the quotient is stored in EAX and the remainder in EDX.

Unsigned integer division is performed by the DIV instruction.


IMUL: Signed Integer Multiply

imul r/m8
imul r/m16
imul r/m32
imul r/m16,reg16
imul r/m32,reg32
imul imm8,reg16
imul imm16,reg16
imul imm8,reg32,
imul imm32,reg32
imul imm8,r/m16,reg16
imul imm16,r/m16,reg16
imul imm8,r/m32,reg32
imul imm32,r/m32,reg32

IMUL performs signed integer multiplication. For the single-operand form, the other operand and destination are implicit, in the following way:

For IMUL r/m8, AL is multiplied by the given operand; the product is stored in AX.

For IMUL r/m16, AX is multiplied by the given operand; the product is stored in DX:AX.

For IMUL r/m32, EAX is multiplied by the given operand; the product is stored in EDX:EAX.

The two-operand form multiplies its two operands and stores the result in the destination (second) operand. The three-operand form multiplies its first two operands and stores the result in the last operand.

The two-operand form is in fact a shorthand for the three-operand form, as can be seen by examining the opcode descriptions.

In the forms with an 8-bit immediate operand and another longer source operand, the immediate operand is considered to be signed, and is sign-extended to the length of the other source operand.

Unsigned integer multiplication is performed by the MUL instruction.


IN: Input from I/O Port

inb imm8,al
inw imm8,ax
inl imm8,eax
inb dx,al
inw dx,ax
inl dx,eax

IN reads a byte, word or doubleword from the specified I/O port, and stores it in the given destination register. The port number may be specified as an immediate value if it is between 0 and 255, and otherwise must be stored in DX. See also OUT.


INC: Increment Integer

inc reg16
inc reg32
inc r/m8
inc r/m16
inc r/m32

INC adds 1 to its operand. It does not affect the carry flag: to affect the carry flag, use ADD.

see ADD also DEC


INSB, INSW, INSL: Input String from I/O Port

insb
insw
insl
insb dx,m8
insw dx,m16
insl dx,m32

INSB inputs a byte from the I/O port specified in DX and stores it at (%EDI). It then increments or decrements EDI depending on the direction flag.

INSW and INSL work in the same way, but they input a word or a doubleword instead of a byte, and increment or decrement the addressing register by 2 or 4 instead of 1.

The REP prefix may be used to repeat the instruction with ECX as the count register.

See also OUTSB, OUTSW and OUTSL.


INT: Software Interrupt

int imm8

INT causes a software interrupt through a specified vector number from 0 to 255.

The code generated by the INT instruction is always two bytes long: although there are short forms for some INT instructions. Generally of no use when code-ing for Windows.


INT3, INT1, ICEBP, INT01: Breakpoints

int1
icebp
int01
int3

INT1 and INT3 are short one-byte forms of the instructions INT 1 and INT 3 (see INT). They perform a similar function to their longer counterparts, but take up less code space. They are used as breakpoints by debuggers.

INT1, and its alternative synonyms INT01 and ICEBP, is an instruction used by in-circuit emulators (ICEs). It is present, though not documented, on some processors down to the 286, but is only documented for the Pentium Pro. INT3 is the instruction normally used as a breakpoint by debuggers.

INT3 is not precisely equivalent to INT 3: the short form, since it is designed to be used as a breakpoint, bypasses the normal IOPL checks in virtual-8086 mode, and also does not go through interrupt redirection.


INTO: Interrupt if Overflow

into

INTO performs an INT 4 software interrupt (see INT) if and only if the overflow flag is set.


INVD: Invalidate Internal Caches

invd

INVD invalidates and empties the processor's internal caches, and causes the processor to instruct external caches to do the same. It does not write the contents of the caches back to memory first: any modified data held in the caches will be lost. To write the data back first, use WBINVD.


INVLPG: Invalidate TLB Entry

invlpg mem

INVLPG invalidates the translation lookahead buffer (TLB) entry associated with the supplied memory address.


IRETL: Return from Interrupt

iretl

IRETL returns from an interrupt (hardware or software) by means of popping EIP and the flags off the stack and then continuing execution from the new EIP.


JCXZ, JECXZ: Jump if CX/ECX Zero

jcxz  label/imm8
jecxzZ label/imm8

JCXZ performs a short jump (with maximum range 128 bytes) if and only if the contents of the CX register is 0. JECXZ does the same thing, but with ECX.


JMP: Jump

jmp  imm
jmp  label
jmp  r/m32
ljmp imm:imm
ljmp label

JMP jumps to a given address. The address may be specified as an absolute address, or as a relative jump within the current segment. jmp -8 or jmp label

JMP imm has a maximum range of 128 bytes, since the displacement is specified as only 8 bits, but takes up less code space.

JMP r/m forms execute a jump loading the destination address out of memory or out of a register.


Jcc: Conditional Branch

jxx imm
jxx label

The conditional jump instructions execute a near (same segment) jump if and only if their conditions are satisfied. For example, JNZ jumps only if the zero flag is not set.

ja         Jump if above                 CF=0 and ZF=0
jae        Jump if above or equal        CF=0
jb         Jump if below                 CF=1
jbe        Jump if below or equal        CF=1 or ZF=1
jc         Jump if carry                 CF=1

jcxz       Jump if cx zero cx=0
je         Jump if equal ZF=1
jg         Jump if greater (signed)      ZF=0 and SF=OF
jge        Jump if greater or equal      (signed) SF=OF
jl         Jump if less (signed)         SF != OF
jle        Jump if less or equal         (signed) ZF=1 or SF != OF
jmp        unconditional                 Jump unconditional

jna        Jump if not above             CF=1 or ZF=1
jnae       Jump if not above or equal    CF=1
jnb        Jump if not below             CF=0
jnbe       Jump if not below or equal    CF=0 and ZF=0
jnc        Jump if not carry             CF=0
jne        Jump if not equal             ZF=0
jng        Jump if not greater           (signed) ZF=1 or SF != OF

jnge       Jump if not greater or equal  (signed) SF != OF
jnl        Jump if not less (signed)     SF=OF
jnle       Jump if not less or equal     (signed) ZF=0 and SF=OF
jno        Jump if not overflow (signed) OF=0
jnp        Jump if no parity             PF=0
jns        Jump if not signed (signed)   SF=0
jnz        Jump if not zero              ZF=0

jo         Jump if overflow (signed)     OF=1
jp         Jump if parity                PF=1
jpe        Jump if parity even           PF=1
jpo        Jump if parity odd            PF=0
js         Jump if signed (signed)       SF=1
jz         Jump if zero                  ZF=1


LAHF: Load AH from Flags

lahf

LAHF sets the AH register according to the contents of the low byte of the flags word. See also SAHF.


LAR: Load Access Rights

lar r/m16,reg16
lar r/m32,reg32

LAR takes the segment selector specified by its source (first) operand, finds the corresponding segment descriptor in the GDT or LDT, and loads the access-rights byte of the descriptor into its destination (second) operand.


LDS, LES, LFS, LGS, LSS: Load Far Pointer

lds mem,reg16
lds mem,reg32
les mem,reg16
les mem,reg32
lfs mem,reg16
lfs mem,reg32
lgs mem,reg16
lgs mem,reg32
lss mem,reg16
lss mem,reg32

Loads 32-bit pointer from memory source to destination register and DS. The offset is placed in the destination register and the segment is placed in DS. To use this instruction the word at the lower memory address must contain the offset and the word at the higher address must contain the segment. This simplifies the loading of far pointers from the stack and the interrupt vector table.


LEA: Load Effective Address

leaw reg16,mem
leal reg32,mem

LEA, despite its syntax, does not access memory. It calculates the effective address specified by its second operand as if it were going to load or store data from it, but instead it stores the calculated address into the register specified by its first operand. This can be used to perform quite complex calculations (e.g. LEA $100(%EBX,%ECX,4),%EAX in one instruction.

LEA, despite being a purely arithmetic instruction which accesses no memory, still requires brackets around its first operand, as if it were a memory reference.

Using LEA to Multiply

The asm instruction LEA can be used for fast additions + multiply.

    _asm("movl 4(%esp), %edx");        // base into edx
    _asm("movl 8(%esp), %ecx");        // index into ecx
    _asm("leal (%edx,%ecx,4), %eax");  // base + (index * 4) into eax

This is particularly useful when calculating offsets for arrays but can equally be used for normal calculations. LEA (load effective address) does not access memory it only calculates.

Here's some examples.

_asm("leal (%eax,%eax,2),%eax");   // 3*eax

_asm("leal (%eax,%eax,8),%eax");   // 9*eax

_asm("leal (%ecx,%eax,8),%eax");   // (8*eax) + ecx

_asm("leal (%eax,%eax,8),%eax");   // 9*eax
_asm("shll $2,%eax");              // 18*eax

Using this method to multiply numbers is much faster than using MUL.


LEAVE: Destroy Stack Frame

leave

LEAVE destroys a stack frame of the form created by the ENTER instruction. It is functionally equivalent to MOV EBP,ESP followed by POPL EBP.


LGDT, LIDT, LLDT: Load Descriptor Tables

lgdt mem
lidt mem
lldt r/m16

LGDT and LIDT both take a 6-byte memory area as an operand: they load a 32-bit linear address and a 16-bit size limit from that area (in the opposite order) into the GDTR (global descriptor table register) or IDTR (interrupt descriptor table register). These are the only instructions which directly use linear addresses, rather than segment/offset pairs.

LLDT takes a segment selector as an operand. The processor looks up that selector in the GDT and stores the limit and base address given there into the LDTR (local descriptor table register).

See also SGDT, SIDT and SLDT.


LMSW: Load/Store Machine Status Word

lmsw r/m16

LMSW loads the bottom four bits of the source operand into the bottom four bits of the CR0 control register (or the Machine Status Word, on 286 processors). See also SMSW.


LOCK: Lock Bus

lock

This instruction is a prefix that causes the CPU assert bus lock signal during the execution of the next instruction. Used to avoid two processors from updating the same data location. Asserts lock during an XCHG with memory operands. This should only be used to lock the bus prior to XCHG, MOV, IN and OUT instructions.


LODSB, LODSW, LODSL: Load from String

lodsb
lodsw
lodsl

LODSB loads a byte from [ESI] into AL. It then increments or decrements (depending on the direction flag: increments if the flag is clear, decrements if it is set) ESI.

LODSW and LODSL work in the same way, but they load a word or a doubleword instead of a byte, and increment or decrement the addressing registers by 2 or 4 instead of 1.


LOOP, LOOPE, LOOPZ, LOOPNE, LOOPNZ: Loop with Counter

loop   imm/label
loope  imm/label
loopz  imm/label
loopne imm/label
loopnz imm/label

LOOP decrements its counter register (either CX or ECX) by one, and if the counter does not become zero as a result of this operation, it jumps to the given label. The jump has a range of 128 bytes.

LOOPE (or its synonym LOOPZ) adds the additional condition that it only jumps if the counter is nonzero and the zero flag is set. Similarly, LOOPNE (and LOOPNZ) jumps only if the counter is nonzero and the zero flag is clear.


LSL: Load Segment Limit

lsl r/m16,reg16
lsl r/m32,reg32

LSL is given a segment selector in its source (first) operand; it computes the segment limit value by loading the segment limit field from the associated segment descriptor in the GDT or LDT. (This involves shifting left by 12 bits if the segment limit is page-granular, and not if it is byte-granular; so you end up with a byte limit in either case.) The segment limit obtained is then loaded into the destination (second) operand.


LTR: Load Task Register

ltr r/m16

LTR looks up the segment base and limit in the GDT or LDT descriptor specified by the segment selector given as its operand, and loads them into the Task Register.


MOV: Move Data

movb reg8,r/m8
movw reg16,r/m16
movl reg32,r/m32
movb r/m8,reg8
movw r/m16,reg16
movl r/m32,reg32
movb imm8,reg8
movw imm16,reg16
movl imm32,reg32
movb imm8,r/m8
movw imm16,r/m16
movl imm32,r/m32
movb memoffs8,al
movw memoffs16,ax
movl memoffs32,eax
movb al,memoffs8
movw ax,memoffs16
movl eax,memoffs32
movw segreg,r/m16
movl segreg,r/m32
movw r/m16,segreg
movl r/m32,segreg
movl cr0/2/3/4,reg32
movl dr0/1/2/3/6/7,reg32
movl tr3/4/5/6/7,reg32
movl reg32,cr0/2/3/4
movl reg32,dr0/1/2/3/6/7
movl reg32,tr3/4/5/6/7

MOV copies the contents of its source (first) operand into its destination (second) operand.

In all forms of the MOV instruction, the two operands are the same size, except for moving between a segment register and an r/m32 operand.

MOV may not use CS as a destination.

CR4 is only a supported register on the Pentium and above.


MOVD: Move Doubleword to/from MMX Register

movd r/m32,mmxreg [PENT,MMX]
movd mmxreg,r/m32 [PENT,MMX]

MOVD copies 32 bits from its source (first) operand into its destination (second) operand. When the destination is a 64-bit MMX register, the top 32 bits are set to zero.


MOVQ: Move Quadword to/from MMX Register

movq r/m64,mmxreg
movq mmxreg,r/m64

MOVQ copies 64 bits from its source (first) operand into its destination (second) operand.


MOVSB, MOVSW, MOVSD: Move String

MOVSB, MOVSW, MOVSL: Move String

movsb
movsw
movsl

MOVSB copies the byte at [EDI] to [ESI]. It then increments or decrements (depending on the direction flag: increments if the flag is clear, decrements if it is set) ESI and EDI.

MOVSW and MOVSL work in the same way, but they copy a word or a doubleword instead of a byte, and increment or decrement the addressing registers by 2 or 4 instead of 1.

The REP prefix may be used to repeat the instruction using CX or ECX as the count.


MOVSX, MOVZX: Move Data with Sign or Zero Extend

movsx r/m8,reg16
movsx r/m8,reg32
movsx r/m16,reg32
movzx r/m8,reg16
movzx r/m8,reg32
movzx r/m16,reg32

MOVSX sign-extends its source (first) operand to the length of its destination (second) operand, and copies the result into the destination operand. MOVZX does the same, but zero-extends rather than sign-extending.


MUL: Unsigned Integer Multiply

mul r/m8
mul r/m16
mul r/m32

MUL performs unsigned integer multiplication. The other operand to the multiplication, and the destination operand, are implicit, in the following way:

For MUL r/m8, AL is multiplied by the given operand; the product is stored in AX.

For MUL r/m16, AX is multiplied by the given operand; the product is stored in DX:AX.

For MUL r/m32, EAX is multiplied by the given operand; the product is stored in EDX:EAX.

Signed integer multiplication is performed by the IMUL instruction.


NEG, NOT: Two's and One's Complement

neg r/m8
neg r/m16
neg r/m32
not r/m8
not r/m16
not r/m32

NEG replaces the contents of its operand by the two's complement negation (invert all the bits and then add one) of the original value. NOT, similarly, performs one's complement (inverts all the bits).


NOP: No Operation

nop

NOP performs no operation. Its opcode is the same as that generated by XCHG AX,AX or XCHG EAX,EAX (depending on the processor mode; see XCHG


OR: Bitwise OR

orb reg8,r/m8
orw reg16,r/m16
orl reg32,r/m32
orb r/m8,reg8
orw r/m16,reg16
orl r/m32,reg32
orb imm8,r/m8
orw imm16,r/m16
orb imm32,r/m32
orb imm8,r/m16
orb imm8,r/m32
orb imm8,al
orw imm16,ax
orl imm32,eax

OR performs a bitwise OR operation between its two operands (i.e. each bit of the result is 1 if and only if at least one of the corresponding bits of the two inputs was 1), and stores the result in the destination (second) operand.

In the forms with an 8-bit immediate second operand and a longer first operand, the second operand is considered to be signed, and is sign-extended to the length of the first operand.

The MMX instruction POR performs the same operation on the 64-bit MMX registers.


OUT: Output Data to I/O Port

outb al,imm8
outw ax,imm8
outl eax,imm8
outb al,dx
outw ax,dx
outl eax,dx

OUT writes the contents of the given source register to the specified I/O port. The port number may be specified as an immediate value if it is between 0 and 255, and otherwise must be stored in DX. See also IN.


OUTSB, OUTSW, OUTSL: Output String to I/O Port

outsb
outsw
outsl

OUTSB loads a byte from [ESI] and writes it to the I/O port specified in DX. It then increments or decrements (depending on the direction flag: increments if the flag is clear, decrements if it is set) SI or ESI.

The register used is ESI if it is 32 bits.

OUTSW and OUTSL work in the same way, but they output a word or a doubleword instead of a byte, and increment or decrement the addressing registers by 2 or 4 instead of 1.

The REP prefix may be used to repeat the instruction with CX or ECX as the count.


POP: Pop Data from Stack

popw reg16
popl reg32
popw r/m16
popl r/m32

POP loads a value from the stack [ESP] and then increments the stack pointer.

The operand-size attribute of the instruction determines whether the stack pointer is incremented by 2 or 4. See PUSH


POPAL: Pop All General-Purpose Registers

popal

POPAL pops doublewords from the stack into the general-purpose registers. The registers are loaded in the following order: EDI, ESI, EBP, EBX, EDX, ECX, and EAX. This instruction reverses the operation of the PUSHAL instruction. The value on the stack for the ESP is ignored. Instead, ESP is incremented after each register is loaded.


POPF: Pop Flags Register

popf

POPF pops a word from the stack and stores it in the bottom 16 bits of the flags register.

See also PUSHF


PUSH: Push Data on Stack

pushw r/m16
pushl r/m32
pushw imm16
pushl imm32

PUSH decrements the stack pointer ESP by 2 or 4, and then stores the given value at [ESP].

The operand-size attribute of the instruction determines whether the stack pointer is decremented by 2 or 4.


PUSHAL: Push All General-Purpose Registers

pushal

PUSHAL pushes, in succession, EAX, ECX, EDX, EBX, ESP, EBP, ESI and EDI on the stack, decrementing the stack pointer by a total of 32.

The value of ESP pushed is its original value, as it had before the instruction was executed.

See also POPAL


PUSHF: Push Flags Register

pushf

PUSHF pushes the flags word onto the stack.

See also POPF


RCL, RCR: Bitwise Rotate through Carry Bit

rcl 1,r/m8
rcl cl,r/m8
rcl imm8,r/m8
rcl 1,r/m16
rcl cl,r/m16
rcl imm8,r/m16
rcl 1,r/m32
rcl cl,r/m32
rcl imm8,r/m32
rcr 1,r/m8
rcr cl,r/m8
rcr imm8,r/m8
rcr 1,r/m16
rcr cl,r/m16
rcr imm8,r/m16
rcr 1,r/m32
rcr cl,r/m32
rcr imm8,r/m32

RCL and RCR perform a 9-bit, 17-bit or 33-bit bitwise rotation operation, involving the given source/destination (second) operand and the carry bit. Thus, for example, in the operation RCR AL,1, a 9-bit rotation is performed in which AL is shifted left by 1, the top bit of AL moves into the carry flag, and the original value of the carry flag is placed in the low bit of AL.

The number of bits to rotate by is given by the first operand. Only the bottom five bits of the rotation count are considered by processor.


RDMSR: Read Model-Specific Registers

rdmsr

RDMSR reads the processor Model-Specific Register (MSR) whose index is stored in ECX, and stores the result in EDX:EAX. See also WRMSR


RDPMC: Read Performance-Monitoring Counters

rdpmc

RDPMC reads the processor performance-monitoring counter whose index is stored in ECX, and stores the result in EDX:EAX.


RDTSC: Read Time-Stamp Counter

rdtsc

RDTSC reads the processor's time-stamp counter into EDX:EAX.


RET, LRET: Return from Procedure Call

ret           Near ret to calling procedure
lret          Far ret to calling procedure
ret imm16     Near ret to calling procedure, pop imm16 bytes from stack
lret imm16    Far ret to calling procedure, pop imm16 bytes from stack

This instruction transfers program control to a return address located on the top of the stack. The address is usually placed on the stack by a CALL instruction, and the return is made to the instruction that follows the CALL instruction.

The optional source operand specifies the number of stack bytes to be released after the return address is popped; the default is none. This operand can be used to release parameters from the stack that were passed to the called procedure and are no longer needed. It must be used when the CALL instruction used to switch to a new procedure uses a call gate with a non-zero word count to access the new procedure. Here, the source operand for the RET instruction must specify the same number of bytes as is specified in the word count field of the call gate. The RET instruction can be used to execute three different types of returns:

Near return—A return to a calling procedure within the current code segment (the segment currently pointed to by the CS register), sometimes referred to as an intrasegment return.

Far return—A return to a calling procedure located in a different segment than the current code segment, sometimes referred to as an intersegment return.

Inter-privilege-level far return—A far return to a different privilege level than that of the currently executing program or procedure.

The inter-privilege-level return type can only be executed in protected mode. Refer to Section
4.3., Calling Procedures Using CALL and RET in Chapter 4, Procedure Calls, Interrupts, and
Exceptions of the Intel Architecture Software Developer’s Manual, Volume 1, for detailed infor-mation
on near, far, and inter-privilege-level returns.

When executing a near return, the processor pops the return instruction pointer (offset) from the top of the stack into the EIP register and begins program execution at the new instruction pointer. The CS register is unchanged.

When executing a far return, the processor pops the return instruction pointer from the top of the
stack into the EIP register, then pops the segment selector from the top of the stack into the CS
register. The processor then begins program execution in the new code segment at the new
instruction pointer.


ROL, ROR: Bitwise Rotate

rol  1,r/m8
rol  cl,r/m8
rol  imm8,r/m8
rolw 1,r/m16
rolw cl,r/m16
rolw imm8,r/m16
roll 1,r/m32
roll cl,r/m32
roll imm8,r/m32

ror  1,r/m8
ror  cl,r/m8
ror  imm8,r/m8
rorw 1,r/m16
rorw cl,r/m16
rorw imm8,r/m16
rorl 1,r/m32
rorl cl,r/m32
rorl imm8,r/m32

ROL and ROR perform a bitwise rotation operation on the given source/destination (first) operand. Thus, for example, in the operation ROR AL,1, an 8-bit rotation is performed in which AL is shifted left by 1 and the original top bit of AL moves round into the low bit.

The number of bits to rotate by is given by the first operand. Only the bottom 3, 4 or 5 bits (depending on the source operand size) of the rotation count are considered by processors above the 8086.


RSM: Resume from System-Management Mode

rsm

RSM returns the processor to its normal operating mode when it was in System-Management Mode.


SAHF: Store AH to Flags

sahf

SAHF sets the low byte of the flags word according to the contents of the AH register. See also LAHF.


SAL, SAR: Bitwise Arithmetic Shifts

salb 1,r/m8
salb cl,r/m8
salb imm8,r/m8
salw 1,r/m16
salw cl,r/m16
salw imm8,r/m16
sall 1,r/m32
sall cl,r/m32
sall imm8,r/m32
sarb 1,r/m8
sarb cl,r/m8
sarb imm8,r/m8
sarw 1,r/m16
sarw cl,r/m16
sarw imm8,r/m16
sarl 1,r/m32
sarl cl,r/m32
sarl imm8,r/m32

SAL and SAR perform an arithmetic shift operation on the given source/destination (second) operand. The vacated bits are filled with zero for SAL, and with copies of the original high bit of the source operand for SAR.

SAL is a synonym for SHL.

The number of bits to shift by is given by the first operand. Only the bottom 3, 4 or 5 bits (depending on the source operand size) of the shift count are considered by processors above the 8086.


SBB: Subtract with Borrow

sbbb reg8,r/m8
sbbw reg16,r/m16
sbbl reg32,r/m32
sbbb r/m8,reg8
sbbw r/m16,reg16
sbbl r/m32,reg32
sbbb imm8,r/m8
sbbw imm16,r/m16
sbbl imm32,r/m32
sbbb imm8,r/m16
sbbl imm8,r/m32
sbbb al,imm8
sbbw ax,imm16
sbbl eax,imm32

SBB performs integer subtraction: it subtracts its first operand, plus the value of the carry flag, from its second, and leaves the result in its destination (second) operand. The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent SBB instruction.

In the forms with an 8-bit immediate second operand and a longer first operand, the second operand is considered to be signed, and is sign-extended to the length of the first operand.

To subtract one number from another without also subtracting the contents of the carry flag, use SUB.


SCASB, SCASW, SCASD: Scan String

SCASB, SCASW, SCASL: Scan String

scasb
scasw
scasl

SCASB compares the byte in AL with the byte at [EDI], and sets the flags accordingly. It then increments or decrements (depending on the direction flag: increments if the flag is clear, decrements if it is set) EDI.

SCASW and SCASL work in the same way, but they compare a word to AX or a doubleword to EAX instead of a byte to AL, and increment or decrement the addressing registers by 2 or 4 instead of 1.

The REPE and REPNE prefixes (equivalently, REPZ and REPNZ) may be used to repeat the instruction with CX or ECX as the count.


SETcc: Set Register from Condition

seta   r/m8     Set byte if above (CF=0 and ZF=0)
setae  r/m8     Set byte if above or equal (CF=0)
setb   r/m8     Set byte if below (CF=1)
setbe  r/m8     Set byte if below or equal (CF=1 or ZF=1)
setc   r/m8     Set if carry (CF=1)
sete   r/m8     Set byte if equal (ZF=1)
setg   r/m8     Set byte if greater (ZF=0 and SF=OF)
setge  r/m8     Set byte if greater or equal (SF=OF)
setl   r/m8     Set byte if less (SF<>OF)
setle  r/m8     Set byte if less or equal (ZF=1 or SF<>OF)
setna  r/m8     Set byte if not above (CF=1 or ZF=1)
setnae r/m8     Set byte if not above or equal (CF=1)
setnb  r/m8     Set byte if not below (CF=0)
setnbe r/m8     Set byte if not below or equal (CF=0 and ZF=0)
setnc  r/m8     Set byte if not carry (CF=0)
setne  r/m8     Set byte if not equal (ZF=0)
setng  r/m8     Set byte if not greater (ZF=1 or SF<>OF)
setnge r/m8     Set if not greater or equal (SF<>OF)
setnl  r/m8     Set byte if not less (SF=OF)
setnle r/m8     Set byte if not less or equal (ZF=0 and SF=OF)
setno  r/m8     Set byte if not overflow (OF=0)
setnp  r/m8     Set byte if not parity (PF=0)
setns  r/m8     Set byte if not sign (SF=0)
setnz  r/m8     Set byte if not zero (ZF=0)
seto   r/m8     Set byte if overflow (OF=1)
setp   r/m8     Set byte if parity (PF=1)
setpe  r/m8     Set byte if parity even (PF=1)
setpo  r/m8     Set byte if parity odd (PF=0)
sets   r/m8     Set byte if sign (SF=1)
setz   r/m8     Set byte if zero (ZF=1)

SETcc sets the given 8-bit operand to zero if its condition is not satisfied, and to 1 if it is.


SGDT, SIDT, SLDT: Store Descriptor Table Pointers

sgdt mem
sidt mem
sldt r/m16

SGDT and SIDT both take a 6-byte memory area as an operand: they store the contents of the GDTR (global descriptor table register) or IDTR (interrupt descriptor table register) into that area as a 32-bit linear address and a 16-bit size limit from that area (in that order). These are the only instructions which directly use linear addresses, rather than segment/offset pairs.

SLDT stores the segment selector corresponding to the LDT (local descriptor table) into the given operand.

See also LGDT, LIDT, LLDT


SHL, SHR: Bitwise Logical Shifts

shlb 1,r/m8
shlb cl,r/m8
shlb imm8,r/m8
shlw 1,r/m16
shlw cl,r/m16
shlw imm8,r/m16
shll 1,r/m32
shll cl,r/m32
shll imm8,r/m32
shrb 1,r/m8
shrb cl,r/m8
shrb imm8,r/m8
shrw 1,r/m16
shrw cl,r/m16
shrw imm8,r/m16
shrl 1,r/m32
shrl cl,r/m32
shrl imm8,r/m32

SHL and SHR perform a logical shift operation on the given source/destination (first) operand. The vacated bits are filled with zero.

A synonym for SHL is SAL

The number of bits to shift by is given by the second operand. Only the bottom 3, 4 or 5 bits (depending on the source operand size) of the shift count are considered by processors above the 8086.


SHLD, SHRD: Bitwise Double-Precision Shifts

shld imm8,reg16,r/m16
shld imm8,reg32,r/m16
shld cl,reg16,r/m16 ;
shld cl,reg32,r/m16 ;
shrd imm8,reg16,r/m16
shrd imm8,reg32,r/m32
shrd cl,reg16,r/m16
shrd cl,reg32,r/m32

SHLD performs a double-precision left shift. It notionally places its second operand to the right of its third, then shifts the entire bit string thus generated to the left by a number of bits specified in the first operand. It then updates only the third operand according to the result of this. The second operand is not modified.

SHRD performs the corresponding right shift: it notionally places the second operand to the left of the third, shifts the whole bit string right, and updates only the third operand.

The number of bits to shift by is given by the third operand. Only the bottom 5 bits of the shift count are considered.


SMSW: Store Machine Status Word

smsw

SMSW stores the bottom half of the CR0 control register (or the Machine Status Word, on 286 processors) into the destination operand. See also LMSW


STC, STD, STI: Set Flags

stc
std
sti

These instructions set various flags. STC sets the carry flag; STD sets the direction flag; and STI sets the interrupt flag (thus enabling interrupts).

To clear the carry, direction, or interrupt flags, use the CLC, CLD and CLI. To invert the carry flag, use CMC


STOSB, STOSW, STOSD: Store Byte to String

STOSB, STOSW, STOSL: Store Byte to String

stosb
stosw
stosl

STOSB stores the byte in AL at [EDI], and sets the flags accordingly. It then increments or decrements (depending on the direction flag: increments if the flag is clear, decrements if it is set) EDI.

STOSW and STOSL work in the same way, but they store the word in AX or the doubleword in EAX instead of the byte in AL, and increment or decrement the addressing registers by 2 or 4 instead of 1.

The REP prefix may be used to repeat the instruction, count isd in CX or ECX.


STR: Store Task Register

str (privileged)

STR stores the segment selector corresponding to the contents of the Task Register into its operand.


SUB: Subtract Integers

sub reg8,r/m8
sub reg16,r/m16
sub reg32,r/m32
sub r/m8,reg8
sub r/m16,reg16
sub r/m32,reg32
sub imm8,r/m8
sub imm16,r/m16
sub imm32,r/m32
sub imm8,r/m16
sub imm8,r/m32
sub imm8,al
sub imm16,ax
sub imm32,eax

SUB performs integer subtraction: it subtracts its second operand from its first, and leaves the result in its destination (second) operand. The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a subsequent SBB instruction.

In the forms with an 8-bit immediate second operand and a longer first operand, the second operand is considered to be signed, and is sign-extended to the length of the first operand.


TEST: Test Bits (notional bitwise AND)

testb reg8,r/m8
testw reg16,r/m16
testl reg32,r/m32
testb imm8,r/m8
testw imm16,r/m16
testl imm32,r/m32
testb imm8,al
testw imm16,ax
testl imm32,eax

TEST performs a 'mental' bitwise AND of its two operands, and affects the flags as if the operation had taken place, but does not store the result of the operation anywhere.


WAIT FWAIT: Wait for Floating-Point Processor

wait
fwait

WAIT or FWAIT on 8086 systems with a separate 8087 FPU, waits for the FPU to have finished any operation it is engaged in before continuing main processor operations, so that (for example) an FPU store to main memory can be guaranteed to have completed before the CPU tries to read the result back out.

On higher processors, WAIT is unnecessary for this purpose, and it has the alternative purpose of ensuring that any pending unmasked FPU exceptions have happened before execution continues.


WBINVD: Write Back and Invalidate Cache

wbinvd

WBINVD invalidates and empties the processor's internal caches, and causes the processor to instruct external caches to do the same. It writes the contents of the caches back to memory first, so no data is lost. To flush the caches quickly without bothering to write the data back first, use INVD.


WRMSR: Write Model-Specific Registers

wrmsr

WRMSR writes the value in EDX:EAX to the processor Model-Specific Register (MSR) whose index is stored in ECX. See also RDMSR


XADD: Exchange and Add

xadd reg8,r/m8
xadd reg16,r/m16
xadd reg32,r/m32

XADD exchanges the values in its two operands, and then adds them together and writes the result into the destination (second) operand. This instruction can be used with a LOCK prefix for multi-processor synchronisation purposes.


XCHG: Exchange

xchg r/m8,reg8
xchg r/m8,reg16
xchg r/m32,reg32
xchg reg8,r/m8
xchg reg16,r/m16
xchg reg32,r/m32
xchg reg16,ax
xchg reg32,eax
xchg ax,reg16
xchg eax,reg32

XCHG exchanges the values in its two operands. It can be used with a LOCK prefix for purposes of multi-processor synchronisation.

XCHG AX,AX or XCHG EAX,EAX is a synonym for NOP


XLAT: Translate Byte in Lookup Table

xlat

XLAT adds the value in AL treated as an unsigned byte from the address pointed to by [EBX] and loads the byte from the resulting address back into AL.


XOR: Bitwise Exclusive OR

xorb reg8,r/m8
xorw reg16,r/m16
xorl reg32,r/m32
xorb imm8,reg8
xorw r/m16,reg16
xorl r/m32,reg32
xorb imm8,r/m8
xorw imm16,r/m16
xorl imm32,r/m32
xorb imm8,r/m16
xorw imm8,r/m32
xorb imm8,al
xorw imm16,ax
xorl imm32,eax

XOR performs a bitwise XOR operation between its two operands (i.e. each bit of the result is 1 if and only if exactly one of the corresponding bits of the two inputs was 1), and stores the result in the destination (second) operand.

In the forms with an 8-bit immediate second operand and a longer first operand, the second operand is considered to be signed, and is sign-extended to the length of the first operand.

The MMX instruction PXOR performs the same operation on the 64-bit MMX registers.


Intel x86 FPU Instruction Reference

Intel x86 FPU Instruction Reference

This help file provides a list of FPU assembly instructions and a short description of the function of each one.

It is not intended to be exhaustive documentation on the fine details of the instructions' function, such as which exceptions they can trigger etc. - for such documentation, you should consult Intel's documentation Intel's Web site is here http://www.intel.com

This is intended primarily to provide documentation on the way the instructions may be used within the LCC-Win32 compiler and using AT&T's syntax.

F2XM1: Calculate 2^X-1

FABS: Floating-Point Absolute Value
FADD, FADDP: Floating-Point Addition
FBLD, FBSTP: BCD Floating-Point Load and Store
FCHS: Floating-Point Change Sign
FCLEX, FNCLEX: Clear Floating-Point Exceptions
FCMOVcc: Floating-Point Conditional Move
FCOM, FCOMP, FCOMPP, FCOMI, FCOMIP: Floating-Point Compare
FCOS: Cosine
FDECSTP: Decrement Floating-Point Stack Pointer
FDIV, FDIVP, FDIVR, FDIVRP: Floating-Point Division
FFREE: Flag Floating-Point Register as Unused
FICOM, FICOMP: Floating-Point/Integer Compare
FILD, FIST, FISTP: Floating-Point/Integer Conversion
FIMUL: Floating-Point/Integer Multiplication
FINCSTP: Increment Floating-Point Stack Pointer
FINIT, FNINIT: Initialise Floating-Point Unit
FISUB: Floating-Point/Integer Subtraction
FLD: Floating-Point Load
FLDxx: Floating-Point Load Constants
FLDCW: Load Floating-Point Control Word
FLDENV: Load Floating-Point Environment
FMUL, FMULP: Floating-Point Multiply
FNOP: Floating-Point No Operation
FPATAN, FPTAN: Arctangent and Tangent
FPREM, FPREM1: Floating-Point Partial Remainder
FRNDINT: Floating-Point Round to Integer
FSAVE, FRSTOR: Save/Restore Floating-Point State
FSCALE: Scale Floating-Point Value by Power of Two
FSIN, FSINCOS: Sine and Cosine
FSQRT: Floating-Point Square Root
FST, FSTP: Floating-Point Store
FSTCW: Store Floating-Point Control Word
FSTENV: Store Floating-Point Environment
FSTSW: Store Floating-Point Status Word
FSUB, FSUBP, FSUBR, FSUBRP: Floating-Point Subtract
FTST: Test ST0 Against Zero
FUCOMxx: Floating-Point Unordered Compare
FXAM: Examine Class of Value in ST0
FXCH: Floating-Point Exchange
FXTRACT: Extract Exponent and Significand
FYL2X, FYL2XP1: Compute Y times Log2(X) or Log2(X+1)


F2XM1: Calculate 2^X-1

f2xm1

F2XM1 raises 2 to the power of st(0), subtracts one, and stores the result back into st(0). The initial contents of st(0) must be a number in the range –1 to +1.


FABS: Floating-Point Absolute Value

fabs

FABS computes the absolute value of st(0), storing the result back in st(0).


FADD, FADDP, FIADD: Floating-Point Addition

fadd m32real      m32real + st(0) and store result in st(0)
fadd m64real      m64real + st(0) and store result in st(0)
fadd st(i),st(0)  st(0) + st(i) and store result in st(0)
fadd st(0),st(i)  st(i) + st(0) and store result in st(i)
faddp st(0),st(i) st(0) + st(i), store result in st(i), and pop stack
faddp             st(0) + st(1), store result in st(1), and pop stack
fiadd m32int      m32int + st(0) and store result in st(0)
fiadd m16int      m16int + st(0) and store result in st(0)

This instruction adds the destination and source operands and stores the sum in the destination location. The destination operand is always an FPU register; the source operand can be a register or a memory location. Source operands in memory can be in single-real, double-real, word-integer, or short-integer formats.

The no-operand version of the instruction adds the contents of the st(0) register to the st(1) register. The one-operand version adds the contents of a memory location (either a real or an integer value) to the contents of the st(0) register. The two-operand version, adds the contents of the st(0) register to the stST(i) register or vice versa. The value in st(0) can be doubled by coding:

fadd st(0), st(0);

The FADDP instructions perform the additional operation of popping the FPU register stack after storing the result. To pop the register stack, the processor marks the st(0) register as empty and increments the stack pointer (TOP) by 1. (The no-operand version of the floating-point add instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FADD rather than FADDP.)

The FIADD instructions convert an integer source operand to extended-real format before performing the addition.

When the sum of two operands with opposite signs is 0, the result is +0, except for the round toward (-INF) mode, in which case the result is -0. When the source operand is an integer 0, it is treated as a +0.

When both operand are infinities of the same sign, the result is (INF) of the expected sign. If both operands are infinities of opposite signs, an invalid operation exception is generated.


FBLD, FBSTP: BCD Floating-Point Load and Store

fbld  mem80
fbstp mem80

FBLD loads an 80-bit (ten-byte) packed binary-coded decimal number from the given memory address, converts it to a real, and pushes it on the register stack. FBSTP stores the value of st(0), in packed BCD, at the given address and then pops the register stack.


FCHS: Floating-Point Change Sign

fchs

FCHS negates the number in st(0): negative numbers become positive, and vice versa.


FCLEX, FNCLEX: Clear Floating-Point Exceptions

fclex
fnclex

FCLEX clears any floating-point exceptions which may be pending. FNCLEX does the same thing but doesn't wait for previous floating-point operations (including the handling of pending exceptions) to finish first.


FCMOVcc: Floating-Point Conditional Move

fcmovb   st(0),st(i)   Move if below (CF=1)
fcmovb   st(i)         Move if below (CF=1)
fcmovbe  st(0),st(i)   Move if below or equal (CF=1 or ZF=1)
fcmovbe  st(i)         Move if below or equal (CF=1 or ZF=1)
fcmove   st(0),st(i)   Move if equal (ZF=1)
fcmove   st(i)         Move if equal (ZF=1)
fcmovnb  st(0),st(i)   Move if not below (CF=0)
fcmovnb  st(i)         Move if not below (CF=0)
fcmovne  st(0),st(i)   Move if not equal (ZF=0)
fcmovne  st(i)         Move if not equal (ZF=0)
fcmovnu  st(0),st(i)   Move if unordered (PF=0)
fcmovnu  st(i)         Move if unordered (PF=0)
fcmovu   st(0),st(i)   Move if unordered (PF=1)
fcmovu   st(i)         Move if unordered (PF=1)
fcmovnbe st(0),st(i)   Move if not below or equal (CF=0 and ZF=0)
fcmovnbe st(i)         Move if not below or equal (CF=0 and ZF=0)

The FCMOV instructions perform conditional move operations: each of them moves the contents of the given register into st(0) if its condition is satisfied, and does nothing if not.

The conditions are not the same as the standard condition codes used with conditional jump instructions. The conditions B, BE, NB, NBE, E and NE are exactly as normal, but none of the other standard ones are supported. Instead, the condition U and its counterpart NU are provided; the U condition is satisfied if the last two floating-point numbers compared were unordered, i.e. they were not equal but neither one could be said to be greater than the other, for example if they were NaNs. (The flag state which signals this is the setting of the parity flag: so the U condition is notionally equivalent to PE, and NU is equivalent to PO.)

The FCMOV conditions test the main processor's status flags, not the FPU status flags, so using FCMOV directly after FCOM will not work. Instead, you should either use FCOMI which writes directly to the main CPU flags word, or use FSTSW to extract the FPU flags.

Although the FCMOV instructions are flagged P6 above, they may not be supported by all Pentium Pro processors; the CPUID instruction will return a bit which indicates whether conditional moves are supported.


FCOM, FCOMP, FCOMPP, FCOMI, FCOMIP: Floating-Point Compare

fcom   mem32
fcom   mem64
fcom   st(i)
fcom   st(i),st(0)
fcomp  mem32
fcomp  mem64
fcomp  st(i)
fcomp  st(i),st(0)
fcompp
fcomi  st(i)
fcomi  st(i),st(0)
fcomip st(i)
fcomip st(i),st(0)

FCOM compares st(0) with the given operand, and sets the FPU flags accordingly. st(0) is treated as the right-hand side of the comparison, so that the carry flag is set (for a 'less-than' result) if st(0) is less than the given operand.

FCOMP does the same as FCOM, but pops the register stack afterwards. FCOMPP compares st(0) with ST1 and then pops the register stack twice.

FCOMI and FCOMIP work like the corresponding forms of FCOM and FCOMP, but write their results directly to the CPU flags register rather than the FPU status word, so they can be immediately followed by conditional jump or conditional move instructions.

The FCOM instructions differ from the FUCOM instructions only in the way they handle quiet NaNs: FUCOM will handle them silently and set the condition code flags to an 'unordered' result, whereas FCOM will generate an exception.


FCOS: Cosine

fcos

FCOS computes the cosine of st(0) (in radians), and stores the result in st(0). See also FSINCOS


FDECSTP: Decrement Floating-Point Stack Pointer

fdecstp

FDECSTP decrements the 'top' field in the floating-point status word. This has the effect of rotating the FPU register stack by one, as if the contents of st(7) had been pushed on the stack. See also FINCSTP


FDIV, FDIVP, FDIVR, FDIVRP: Floating-Point Division

fdiv m32real;       st(0)/m32real and store result in st(0)
fdiv m64real;       st(0)/m64real and store result in st(0)
fdiv st(i),st(0);  st(0)/st(i) and store result in st(0)
fdiv st(0),st(i);  st(i)/st(0) and store result in st(i)
fdivp st(0),st(i); st(i)/st(0), store result in st(i), and pop
fdivp               st(1)/by st(0), store result in st(1), and pop
fidiv m32int;       st(0)/m32int and store result in st(0)
fidiv m16int;       st(0)/m16int and store result in st(0)

These instructions divide the destination operand by the source operand and stores the result in the destination location. The destination operand (dividend) is always in an FPU register; the source operand (divisor) can be a register or a memory location. Source operands in memory can be in single-real, double-real, word-integer, or short-integer formats.

The no-operand version of the instruction divides the contents of the st(1) register by the contents of the st(0) register. The one-operand version divides the contents of the st(0) register by the contents of a memory location (either a real or an integer value). The two-operand version, divides the contents of the st(0) register by the contents of the st(i) register or vice versa.

The FDIVP instructions perform the additional operation of popping the FPU register stack after storing the result. To pop the register stack, the processor marks the st(0) register as empty and increments the stack pointer (TOP) by 1. The no-operand version of the floating-point divide instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FDIV rather than FDIVP.

The FIDIV instructions convert an integer source operand to extended-real format before performing the division. When the source operand is an integer 0, it is treated as a +0. If an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an (Inf) of the appropriate sign is stored in the destination operand.


FFREE: Flag Floating-Point Register as Unused

ffree st(i)

This instruction sets the tag in the FPU tag register associated with register st(i) to empty. The contents of st(i) and the FPU stack-top pointer (TOP) are not affected.


FICOM, FICOMP: Floating-Point/Integer Compare

ficom  mem16
ficom  mem32
ficomp mem16
ficomp mem32

FICOM compares st(0) with the 16-bit or 32-bit integer stored in the given memory location, and sets the FPU flags accordingly. FICOMP does the same, but pops the register stack afterwards.

These instruction compare the value in st(0) with an integer source operand and sets the condition code flags C0, C2, and C3 in the FPU status word according to the results (refer to table below). The integer value is converted to extended-real format before the comparison is made.

These instructions perform an “unordered comparison.” An unordered comparison also checks the class of the numbers being compared (refer to “FXAM—Examine” in this chapter). If either operand is a NaN or is in an undefined format, the condition flags are set to “unordered.”

The sign of zero is ignored, so that –0.0 = +0.0.

The FICOMP instructions pop the register stack following the comparison. To pop the register stack, the processor marks the st(0) register empty and increments the stack pointer (TOP) by 1.

Condition | C3 | C2 | C0
st(0) > SRC | 0 | 0 | 0
st(0) < SRC | 0 | 0 | 1
st(0) = SRC | 1 | 0 | 0
Unordered | 1 | 1 | 1


FILD, FIST, FISTP: Floating-Point/Integer Conversion

filds  m16int  Push m16int onto the FPU register stack
fildl  m32int  Push m32int onto the FPU register stack
fildq  m64int  Push m64int onto the FPU register stack
fists  m16int  Store st(0) in m16int
fistl  m32int  Store st(0) in m32int

fistps m16int  Store st(0) in m16int and pop register stack
fistpl m32int  Store st(0) in m32int and pop register stack
fistpq m64int  Store st(0) in m64int and pop register stack

The FILD instruction converts the signed-integer source operand into extended-real format and pushes the value onto the FPU register stack. The source operand can be a word, short, or long integer value. It is loaded without rounding errors. The sign of the source operand is preserved.

The FIST instruction converts the value in the st(0) register to a signed integer and stores the result in the destination operand. Values can be stored in word- or short-integer format. The destination operand specifies the address where the first byte of the destination value is to be stored.

The FISTP instruction performs the same operation as the fist instruction and then pops the register stack. To pop the register stack, the processor marks the st(0) register as empty and increments the stack pointer (TOP) by 1. The FISTP instruction can also stores values in long-integer format.


FIMUL: Floating-Point/Integer Multiplication

fimuls m16int
fimull m32int

FIMUL multiplies st(0) by the 16-bit or 32-bit integer stored in the given memory location, and stores the result in st(0).


FINCSTP: Increment Floating-Point Stack Pointer

fincstp

FINCSTP increments the 'top' field in the floating-point status word. This has the effect of rotating the FPU register stack by one, as if the register stack had been popped; however, unlike the popping of the stack performed by many FPU instructions, it does not flag the new st(7) (previously st(0)) as empty. See also FDECSTP


FINIT, FNINIT: Initialise Floating-Point Unit

finit
fninit

These instructions set the FPU control, status, tag, instruction pointer, and data pointer registers to their default states. The FPU control word is set to 037FH (round to nearest, all exceptions masked, 64-bit precision). The status word is cleared (no exception flags set, TOP is set to 0).

The data registers in the register stack are left unchanged, but they are all tagged as empty.

Both the instruction and data pointers are cleared.

The FINIT instruction checks for and handles any pending unmasked floating-point exceptions before performing the initialization; the FNINIT instruction does not.


FISUB: Floating-Point/Integer Subtraction

fisubs  mem16
fisubl  mem32
fisubrs mem16
fisubrl mem32

FISUB subtracts the 16-bit or 32-bit integer stored in the given memory location from st(0), and stores the result in st(0). FISUBR does the subtraction the other way round, i.e. it subtracts st(0) from the given integer, but still stores the result in st(0).


FLD: Floating-Point Load

flds mem32
fldl mem64
fldt mem80
fld  st(i)

FLD loads a floating-point value out of the given register or memory location, and pushes it on the FPU register stack.

FLDS loads a float

FLDL loads a double

FLDT loads a long double


FLDxx: Floating-Point Load Constants

fld1
fldl2e
fldl2t
fldlg2
fldln2
fldpi
fldz

These instructions push specific standard constants on the FPU register stack.

FLD1 pushes the value 1

FLDL2E pushes the base-2 logarithm of e

FLDL2T pushes the base-2 log of 10

FLDLG2 pushes the base-10 log of 2

FLDLN2 pushes the base-e log of 2

FLDPI pushes PI

FLDZ pushes zero.


FLDCW: Load Floating-Point Control Word

fldcw mem16

FLDCW loads a 16-bit value out of memory and stores it into the FPU control word (governing things like the rounding mode, the precision, and the exception masks). See also FSTCW


FLDENV: Load Floating-Point Environment

fldenv mem

FLDENV loads the FPU operating environment (control word, status word, tag word, instruction pointer, data pointer and last opcode) from memory. The memory area is 14 or 28 bytes long, depending on the CPU mode at the time. See also FSTENV


FMUL, FMULP: Floating-Point Multiply

fmuls m32real         st(0) * m32real and store result in st(0)
fmull m64real         st(0) * m64real and store result in st(0)
fmul  st(0), st(i)    st(0) * st(i) and store result in st(0)
fmul  st(i), st(0)    st(i) * st(0) and store result in st(i)
fmulp st(i), st(0)    st(i) * st(0), store result in st(i), and pop
fmulp                 st(1) * st(0), store result in st(1), and pop
fmul                  st(1) * st(0), store result in st(1)

These instructions multiply the destination and source operands and stores the product in the destination location. The destination operand is always an FPU data register; the source operand can be an FPU data register or a memory location. Source operands in memory can be in single-real or double-real formats.

The no-operand version of the instruction multiplies the contents of the st(1) register by the contents of the st(0) register and stores the product in the st(1) register. The one-operand version multiplies the contents of the st(0) register by the contents of a memory location (either a real or an integer value) and stores the product in the st(0) register. The two-operand version, multiplies the contents of the st(0) register by the contents of the st(i) register, or vice versa, with the result being stored in the register specified with the second operand (the destination operand).

The FMULP instructions perform the additional operation of popping the FPU register stack after storing the product. To pop the register stack, the processor marks the st(0) register as empty and increments the stack pointer (TOP) by 1. The no-operand version of the floating-point multiply instructions always results in the register stack being popped. In some assem-blers, the mnemonic for this instruction is FMUL rather than FMULP.


FNOP: Floating-Point No Operation

fnop

This instruction performs no FPU operation. This instruction takes up space in the instruction stream but does not affect the FPU or machine context, except the EIP register.


FPATAN, FPTAN: Arctangent and Tangent

fpatan
fptan

The FPATAN instruction computes the arctangent of the source operand in register st(1) divided by the source operand in register st(0), stores the result in st(1), and pops the FPU register stack. The result in register st(0) has the same sign as the source operand st(1) and a magnitude less than +PI.

The FPATAN instruction returns the angle between the X axis and the line from the origin to the point (X,Y), where Y (the ordinate) is st(1) and X (the abscissa) is st(0). The angle depends on the sign of X and Y independently, not just on the sign of the ratio Y/X. This is because a point (-X,Y) is in the second quadrant, resulting in an angle between PI/2 and PI, while a point (X,-Y) is in the fourth quadrant, resulting in an angle between 0 and -PI/2. A point (-X,-Y) is in the third quadrant, giving an angle between -PI/2 and -PI.

The FPTAN instruction This instruction computes the tangent of the source operand in register st(0), stores the result in st(0), and pushes a 1.0 onto the FPU register stack. The source operand must be given in radians and must be less than ±2^63 .


FPREM, FPREM1: Floating-Point Partial Remainder

fprem
fprem1

These instructions both produce the remainder obtained by dividing st(0) by st(1). This is calculated, notionally, by dividing st(0) by st(1), rounding the result to an integer, multiplying by st(1) again, and computing the value which would need to be added back on to the result to get back to the original value in st(0).

The two instructions differ in the way the notional round-to-integer operation is performed. FPREM does it by rounding towards zero, so that the remainder it returns always has the same sign as the original value in st(0); FPREM1 does it by rounding to the nearest integer, so that the remainder always has at most half the magnitude of st(1).

Both instructions calculate partial remainders, meaning that they may not manage to provide the final result, but might leave intermediate results in st(0) instead. If this happens, they will set the C2 flag in the FPU status word; therefore, to calculate a remainder, you should repeatedly execute FPREM or FPREM1 until C2 becomes clear.


FRNDINT: Floating-Point Round to Integer

frndint

FRNDINT rounds the contents of st(0) to an integer, according to the current rounding mode set in the FPU control word, and stores the result back in st(0).


FSAVE, FRSTOR: Save/Restore Floating-Point State

fsave  mem
fnsave mem
frstor mem

FSAVE saves the entire floating-point unit state, including all the information saved by FSTENV plus the contents of all the registers, to a 94 or 108 byte area of memory (depending on the CPU mode). FRSTOR restores the floating-point state from the same area of memory.

FNSAVE does the same as FSAVE, without first waiting for pending floating-point exceptions to clear.


FSCALE: Scale Floating-Point Value by Power of Two

fscale

FSCALE scales a number by a power of two, it rounds st(1) towards zero to obtain an integer, then multiplies st(0) by two to the power of that integer, and stores the result in st(0).


FSIN, FSINCOS: Sine and Cosine

fsin
fsincos

FSIN calculates the sine of st(0) (in radians) and stores the result in st(0). FSINCOS does the same, but then pushes the cosine of the same value on the register stack, so that the sine ends up in st(1) and the cosine in st(0). FSINCOS is faster than executing FSIN and FCOS in succession.


FSQRT: Floating-Point Square Root

fsqrt

FSQRT calculates the square root of st(0) and stores the result in st(0).


FST, FSTP: Floating-Point Store

fsts   mem32
fstps  mem32
fstl   mem64
fstpl  mem64
fstpt  mem80
fst    st(i)
fstp   st(i)

The FST instruction copies the value in the st(0) register to the destination operand, which can be a memory location or another register in the FPU register stack. When storing the value in memory, the value is converted to single (float) or double format.

The FSTP instruction performs the same operation as the FST instruction and then pops the register stack. To pop the register stack, the processor marks the st(0) register as empty and increments the stack pointer (TOP) by 1. The FSTP instruction can also store values in memory in extended-real format.

If the destination operand is a memory location, the operand specifies the address where the first byte of the destination value is to be stored. If the destination operand is a register, the operand specifies a register in the register stack relative to the top of the stack.

If the destination size is single or double, the significand of the value being stored is rounded to the width of the destination (according to rounding mode specified by the RC field of the FPU control word), and the exponent is converted to the width and bias of the destination format. If the value being stored is too large for the destination format, a numeric overflow exception (#O) is generated and, if the exception is unmasked, no value is stored in the destination operand. If the value being stored is a denormal value, the denormal exception (#D) is not generated. This condition is simply signaled as a numeric underflow exception (#U) condition.

If the value being stored is ±0, ±INF, or a NaN, the least-significant bits of the significand and the exponent are truncated to fit the destination format. This operation preserves the value’s identity as a 0, INF, or NaN.


FSTCW: Store Floating-Point Control Word

fstcw  mem16
fnstcw mem16

FSTCW stores the FPU control word (governing things like the rounding mode, the precision, and the exception masks) into a 2-byte memory area. See also FLDCW

FNSTCW does the same thing as FSTCW, without first waiting for pending floating-point exceptions to clear.


FSTENV: Store Floating-Point Environment

fstenv  mem
fnstenv mem

FSTENV stores the FPU operating environment (control word, status word, tag word, instruction pointer, data pointer and last opcode) into memory. The memory area is 14 or 28 bytes long, depending on the CPU mode at the time. See also FLDENV.

FNSTENV does the same thing as FSTENV, without first waiting for pending floating-point exceptions to clear.


FSTSW: Store Floating-Point Status Word

fstsw  mem16
fstsw  ax
fnstsw mem16
fnstsw ax

FSTSW stores the FPU status word into AX or into a 2-byte memory area.

FNSTSW does the same thing as FSTSW, without first waiting for pending floating-point exceptions to clear.


FSUB, FSUBP, FSUBR, FSUBRP: Floating-Point Subtract

fsubs  mem32
fsubl  mem64
fsub   st(i)
fsub   st(i),st(0)
fsub
fsub   st(0),st(i)
fsubp  st(0),st(i)
fsubp  st(i)
fsubrs mem32
fsubrl mem64
fsubr  st(i)
fsubr  st(i),st(0)
fsubr
fsubr  st(0),st(i)
fsubrp st(i)
fsubrp st(0),st(i)

FSUB: These instructions subtract the source operand from the destination operand and stores the difference in the destination location. The destination operand is always an FPU data register; the source operand can be a register or a memory location. Source operands in memory can be in single, double format.

The no-operand version of the instruction subtracts the contents of the st(0) register from the st(1) register and stores the result in st(1). The one-operand version subtracts the contents of a memory location from the contents of the st(0) register and stores the result in st(0). The two-operand version, subtracts the contents of the st(0) register from the st(i) register or vice versa.

The FSUBP instructions perform the additional operation of popping the FPU register stack following the subtraction. To pop the register stack, the processor marks the st(0) register as empty and increments the stack pointer (TOP) by 1. The no-operand version of the floating-point subtract instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FSUB rather than FSUBP.

When the difference between two operands of like sign is 0, the result is +0, except for the round toward -INF mode, in which case the result is -0. This instruction also guarantees that +0 - (-0) = +0, and that -0 - (+0) = -0. When the source operand is an integer 0, it is treated as a +0.

When one operand is INF, the result is INF of the expected sign. If both operands are INF of the same sign, an invalid operation exception is generated.

FSUBR: These instructions subtract the destination operand from the source operand and stores the difference in the destination location. The destination operand is always an FPU register; the source operand can be a register or a memory location. Source operands in memory can be in single and double formats.

These instructions perform the reverse operations of the FSUB, FSUBP, and FISUB instructions.

They are provided to support more efficient coding.

The no-operand version of the instruction subtracts the contents of the st(1) register from the st(0) register and stores the result in st(1). The one-operand version subtracts the contents of the st(0) register from the contents of a memory location and stores the result in st(0). The two-operand version, subtracts the contents of the st(i) register from the st(0) register or vice versa.

The FSUBRP instructions perform the additional operation of popping the FPU register stack following the subtraction. To pop the register stack, the processor marks the st(0) register as empty and increments the stack pointer (TOP) by 1. The no-operand version of the floating-point reverse subtract instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FSUBR rather than FSUBRP.

When the difference between two operands of like sign is 0, the result is +0, except for the round toward -INF mode, in which case the result is -0. This instruction also guarantees that +0 - (-0) = +0, and that -0 - (+0) = -0. When the source operand is an integer 0, it is treated as a +0.


FTST: Test ST0 Against Zero

ftst

FTST compares st(0) with zero and sets the FPU flags accordingly. st(0) is treated as the left-hand side of the comparison, so that a 'less-than' result is generated if st(0) is negative.


FUCOMxx: Floating-Point Unordered Compare

fucom st(i)        Compare st(0) with st(i)
fucom              Compare st(0) with st(1)
fucomp st(i)       Compare st(0) with st(i) and pop register stack
fucomp             Compare st(0) with st(1) and pop register stack
fucompp            Compare st(0) with st(1) and pop register stack twice
fucomi st(i),st(0) Compare and check for ordered values, and set status flags
fucomip st(i),st(0) and pop register stack

FUCOM compares st(0) with the given operand, and sets the FPU flags accordingly. st(0) is treated as the left-hand side of the comparison, so that the carry flag is set (for a 'less-than' result) if st(0) is less than the given operand.

FUCOMP does the same as FUCOM, but pops the register stack afterwards. FUCOMPP compares st(0) with st(1) and then pops the register stack twice.

FUCOMI and FUCOMIP work like the corresponding forms of FUCOM and FUCOMP, but write their results directly to the CPU flags register rather than the FPU status word, so they can be immediately followed by conditional jump or conditional move instructions.

The FUCOM instructions differ from the FCOM instructions only in the way they handle quiet NaNs: FUCOM will handle them silently and set the condition code flags to an 'unordered' result, whereas FCOM will generate an exception.


FXAM: Examine Class of Value in ST0

fxam

FXAM sets the FPU flags C3, C2 and C0 depending on the type of value stored in st(0):

000 (respectively) for an unsupported format

001 for a NaN

010 for a normal finite number

011 for an infinity

100 for a zero

101 for an empty register

110 for a denormal.

It also sets the C1 flag to the sign of the number.

Class | C3 | C2 | C0
Unsupported | 0 | 0 | 0
Nan | 0 | 1 | 0
Normal Finite Number | 0 | 1 | 0
Infinity | 0 | 1 | 1
Zer | 1 | 0 | 0
Empty | 1 | 0 | 1
Denormal Number | 1 | 1 | 0


FXCH: Floating-Point Exchange

fxch st(i)

FXCH exchanges st(0) with a given FPU register.


FXTRACT: Extract Exponent and Significand

fxtract

FXTRACT separates the number in st(0) into its exponent and significand (mantissa), stores the exponent back into st(0), and then pushes the significand on the register stack so that the significand ends up in st(0), and the exponent in st(1).


FYL2X, FYL2XP1: Compute Y times Log2(X) or Log2(X+1)

fyl2x
fyl2xp1

FYL2X multiplies st(1) by the base-2 logarithm of st(0), stores the result in st(1), and pops the register stack (so that the result ends up in st(0)). st(0) must be non-zero and positive.

FYL2XP1 works the same way, but replacing the base-2 log of st(0) with that of st(0) plus one. This time, st(0) must have magnitude no greater than 1 minus half the square root of two.


Intel x86 MMX Instruction Reference

This help file provides a list of assembly instructions and a short description of the function of each one.

It is not intended to be exhaustive documentation on the fine details of the instructions' function, such as which exceptions they can trigger etc. - for such documentation, you should go to Intel's Web site, http://www.intel.com

This is intended primarily to provide documentation on the way the instructions may be used within the LCC-Win32 compiler and using AT&T's syntax.

EMMS: Empty MMX State
MASKMOVQ: Byte Mask Write
MOVNTQ: Move 64 Bits Non Tempora
MOVD: Move 32 Bits
MOVQ: Move 64 Bits
PACKSSDW, PACKSSWB, PACKUSWB: Pack Data
PADDSIW: MMX Packed Addition to Implicit Destination
PADDxx: MMX Packed Addition
PAND, PANDN: MMX Bitwise AND and AND-NOT
PCMPxx: MMX Packed Comparison
PMADDWD: MMX Packed Multiply and Add
PMULHW, PMULLW: MMX Packed Multiply
POR: MMX Bitwise OR
PSLLx, PSRLx, PSRAx: MMX Bit Shifts
PSUBxx: MMX Packed Subtraction
PUNPCKxxx: Unpack Data
PXOR: MMX Bitwise XOR


EMMS: Empty MMX State

emms

EMMS sets the FPU tag word (marking which floating-point registers are available) to all ones, meaning all registers are available for the FPU to use. It should be used after executing MMX instructions and before executing any subsequent floating-point operations.


MASKMOVQ: Byte Mask Write

maskmovq mm2,mm1

Move 64-bits representing integer data from MM1 register to memory location specified by the edi register, using the byte mask in MM2 register.

Data is stored from the mm1 register to the location specified by the edi register. The size of the store depends on the address-size attribute. The most significant bit in each byte of the mask register mm2 is used to selectively write the data (0 = no write, 1 = write) on a per-byte basis. Behavior with a mask of all zeroes is as follows:

No data will be written to memory. However, transition from FP to MMX™ technology state (if necessary) will occur, irrespective of the value of the mask.

For memory references, a zero byte mask does not prevent addressing faults (i.e., #GP, SS) from being signaled.

Signaling of page faults (#PG) is implementation-specific.

#UD, #NM, #MF, and #AC faults are signaled irrespective of the value of the mask.

Signaling of breakpoints (code or data) is not guaranteed; different processor implementations may signal or not signal these breakpoints.

If the destination memory region is mapped as UC or WP, enforcement of associated semantics for these memory types is not guaranteed (i.e., is reserved) and is implementation specific. Dependence on the behavior of a specific implementation in this case is not recommended, and may lead to future incompatibility.


MOVNTQ: Move 64 Bits Non Temporal

movntq mmx,mm64

MOVNTQ Moves 64 bits representing integer operands (8b, 16b, 32b) from MM register to memory, minimizing pollution within cache hierarchy.

The linear address corresponds to the address of the least-significant byte of the referenced memory data. This store instruction minimizes cache pollution.


MOVD: Move 32 Bits

MOVQ: Move 64 Bits

movq r/mm64,mmxreg
movq mmxreg,r/mm64

The MOVQ instruction moves 64 bits from memory or another MMX register into an MMX register or moves from an MMX register to a 64 bits memory. Data cannot be transferred from one memory location to another.


PACKSSDW, PACKSSWB, PACKUSWB: Pack Data

packssdw r/m64,mmxreg ; 0F 6B /r [PENT,MMX]
packsswb r/m64,mmxreg ; 0F 63 /r [PENT,MMX]
packuswb r/m64,mmxreg ; 0F 67 /r [PENT,MMX]

All these instructions start by forming a notional 128-bit word by placing the source (second) operand on the left of the destination (first) operand. PACKSSDW then splits this 128-bit word into four doublewords, converts each to a word, and loads them side by side into the destination register; PACKSSWB and PACKUSWB both split the 128-bit word into eight words, converts each to a byte, and loads those side by side into the destination register.

PACKSSDW and PACKSSWB perform signed saturation when reducing the length of numbers: if the number is too large to fit into the reduced space, they replace it by the largest signed number (7FFFh or 7Fh) that will fit, and if it is too small then they replace it by the smallest signed number (8000h or 80h) that will fit. PACKUSWB performs unsigned saturation: it treats its input as unsigned, and replaces it by the largest unsigned number that will fit.


PADDxx: MMX Packed Addition

paddb   r/m64,mmxreg
paddw   r/m64,mmxreg
paddd   r/m64,mmxreg
paddsb  r/m64,mmxreg
paddsw  r/m64,mmxreg
paddusb r/m64,mmxreg
paddusw r/m64,mmxreg

PADDxx all perform packed addition between their two 64-bit operands, storing the result in the destination (second) operand. The PADDxB forms treat the 64-bit operands as vectors of eight bytes, and add each byte individually; PADDxW treat the operands as vectors of four words; and PADDD treats its operands as vectors of two doublewords.

PADDSB and PADDSW perform signed saturation on the sum of each pair of bytes or words: if the result of an addition is too large or too small to fit into a signed byte or word result, it is clipped (saturated) to the largest or smallest value which will fit. PADDUSB and PADDUSW similarly perform unsigned saturation, clipping to 0FFh or 0FFFFh if the result is larger than that.


PAND, PANDN: MMX Bitwise AND and AND-NOT

pand  r/m64,mmxreg
pandn r/m64,mmxreg

PAND performs a bitwise AND operation between its two operands (i.e. each bit of the result is 1 if and only if the corresponding bits of the two inputs were both 1), and stores the result in the destination (second) operand.

PANDN performs the same operation, but performs a one's complement operation on the destination (second) operand first.


PCMPxx: MMX Packed Comparison

pcmpeqb r/m64,mmxreg
pcmpeqw r/m64,mmxreg
pcmpeqd r/m64,mmxreg
pcmpgtb r/m64,mmxreg
pcmpgtw r/m64,mmxreg
pcmpgtd r/m64,mmxreg

The PCMPxx instructions all treat their operands as vectors of bytes, words, or doublewords; corresponding elements of the source and destination are compared, and the corresponding element of the destination (second) operand is set to all zeros or all ones depending on the result of the comparison.

PCMPxxB treats the operands as vectors of eight bytes, PCMPxxW treats them as vectors of four words, and PCMPxxD as two doublewords.

PCMPEQx sets the corresponding element of the destination operand to all ones if the two elements compared are equal; PCMPGTx sets the destination element to all ones if the element of the second (destination) operand is greater (treated as a signed integer) than that of the first (source) operand.


PMADDWD: MMX Packed Multiply and Add

pmaddwd r/m64,mmxreg

PMADDWD treats its two inputs as vectors of four signed words. It multiplies corresponding elements of the two operands, giving four signed doubleword results. The top two of these are added and placed in the top 32 bits of the destination (second) operand; the bottom two are added and placed in the bottom 32 bits.


PMULHW, PMULLW: MMX Packed Multiply

pmulhw r/m64,mmxreg
pmullw r/m64,mmxreg

PMULxW treats its two inputs as vectors of four signed words. It multiplies corresponding elements of the two operands, giving four signed doubleword results.

PMULHW then stores the top 16 bits of each doubleword in the destination (second) operand; PMULLW stores the bottom 16 bits of each doubleword in the destination operand.


POR: MMX Bitwise OR

por r/m64,mmxreg

POR performs a bitwise OR operation between its two operands (i.e. each bit of the result is 1 if and only if at least one of the corresponding bits of the two inputs was 1), and stores the result in the destination (second) operand.


PSLLx, PSRLx, PSRAx: MMX Bit Shifts

psllw r/m64,mmxreg
psllw imm8,mmxreg
pslld r/m64,mmxreg
pslld imm8,mmxreg
psllq r/m64,mmxreg
psllq imm8,mmxreg
psraw r/m64,mmxreg
psraw imm8,mmxreg
psrad r/m64,mmxreg
psrad imm8,mmxreg
psrlw r/m64,mmxreg
psrlw imm8,mmxreg
psrld r/m64,mmxreg
psrld imm8,mmxreg
psrlq r/m64,mmxreg
psrlq imm8,mmxreg

PSxxQ perform simple bit shifts on the 64-bit MMX registers: the destination (second) operand is shifted left or right by the number of bits given in the source (first) operand, and the vacated bits are filled in with zeros (for a logical shift) or copies of the original sign bit (for an arithmetic right shift).

PSxxW and PSxxD perform packed bit shifts: the destination operand is treated as a vector of four words or two doublewords, and each element is shifted individually, so bits shifted out of one element do not interfere with empty bits coming into the next.

PSLLx and PSRLx perform logical shifts: the vacated bits at one end of the shifted number are filled with zeros. PSRAx performs an arithmetic right shift: the vacated bits at the top of the shifted number are filled with copies of the original top (sign) bit.


PSUBxx: MMX Packed Subtraction

psubb   r/m64,mmxreg
psubw   r/m64,mmxreg
psubd   r/m64,mmxreg
psubsb  r/m64,mmxreg
psubsw  r/m64,mmxreg
psubusb r/m64,mmxreg
psubusw r/m64,mmxreg

PSUBxx all perform packed subtraction between their two 64-bit operands, storing the result in the destination (second) operand. The PSUBxB forms treat the 64-bit operands as vectors of eight bytes, and subtract each byte individually; PSUBxW treat the operands as vectors of four words; and PSUBD treats its operands as vectors of two doublewords.

In all cases, the elements of the operand on the right are subtracted from the corresponding elements of the operand on the left, not the other way round.

PSUBSB and PSUBSW perform signed saturation on the sum of each pair of bytes or words: if the result of a subtraction is too large or too small to fit into a signed byte or word result, it is clipped (saturated) to the largest or smallest value which will fit. PSUBUSB and PSUBUSW similarly perform unsigned saturation, clipping to 0x0FF or 0x0FFFF if the result is larger than that.


PUNPCKxxx: Unpack Data

punpckhbw r/m64,mmxreg
punpckhwd r/m64,mmxreg
punpckhdq r/m64,mmxreg
punpcklbw r/m64,mmxreg
punpcklwd r/m64,mmxreg
punpckldq r/m64,mmxreg

PUNPCKxx all treat their operands as vectors, and produce a new vector generated by interleaving elements from the two inputs. The PUNPCKHxx instructions start by throwing away the bottom half of each input operand, and the PUNPCKLxx instructions throw away the top half.

The total remaining elements of 64 bits are then interleaved into the destination, alternating elements from the first (source) operand and the second (destination) operand: so the leftmost element in the result always comes from the second operand, and the rightmost from the destination.

PUNPCKxBW works a byte at a time, PUNPCKxWD a word at a time, and PUNPCKxDQ a doubleword at a time.

So, for example, if the first operand held 0x7A6A5A4A3A2A1A0A and the second held 0x7B6B5B4B3B2B1B0B, then:

PUNPCKHBW would return 0x7B7A6B6A5B5A4B4A.

PUNPCKHWD would return 0x7B6B7A6A5B4B5A4A.

PUNPCKHDQ would return 0x7B6B5B4B7A6A5A4A.

PUNPCKLBW would return 0x3B3A2B2A1B1A0B0A.

PUNPCKLWD would return 0x3B2B3A2A1B0B1A0A.

PUNPCKLDQ would return 0x3B2B1B0B3A2A1A0A.


PXOR: MMX Bitwise XOR

pxor r/m64,mmxreg

PXOR performs a bitwise XOR operation between its two operands (i.e. each bit of the result is 1 if and only if exactly one of the corresponding bits of the two inputs was 1), and stores the result in the destination (first) operand.


AMD 3DNOW Instruction Reference

AMD 3DNOW Instruction Reference

This help file provides a list of AMD 3DNOW assembly instructions and a short description of the function of each one.

It is not intended to be exhaustive documentation on the fine details of the instructions' function, such as which exceptions they can trigger etc. - for such documentation, you should consult other documentation from AMD's Web site http://www.amd.com

This is intended primarily to provide documentation on the way the instructions may be used within the LCC-Win32 compiler and using AT&T's syntax.

FEMMS: Empty MMX State

PAVGUSB: Average of unsigned packed 8-bit values
PF2ID: Converts packed floating-point operand to packed 32 bit integers
PFACC: Floating-point accumulate
PFADD: Packed floating-point addition
PFCMPEQ: Packed floating-point comparison, equal to
PFCMPGE: Packed floating-point comparison, greater than or equal to
PFCMPGT: Packed floating-point comparison, greater than
PFMAX: Packed floating-point maximum
PFMIN: Packed floating-point minimum
PFMUL: Packed floating-point multiplication
PFRCP: Floating-point reciprocal approximation
PFRCPIT1: Packed floating-point reciprocal, first iteration step
PFRCPIT2: Packed floating-point reciprocal/reciprocal square root, second iteration step
PFRSQIT1: Packed floating-point reciprocal square root, first iteration step
PFRSQRT: Floating-point reciprocal square root approximation
PFSUB: Packed floating-point subtraction
PFSUBR: Packed floating-point reverse subtraction
PI2FD: Packed 32-bit integer to floating-point conversion
PMULHRW: Multiply signed packed 16-bit values with rounding and store the high 16 bits
PREFETCH(W): Prefetch processor cache line into L1 data cache (Dcache)
Division and Square Root


FEMMS: Empty MMX State

femms

Like the MMX EMMS instruction, the FEMMS instruction can be used to clear the MMX state following the execution of a block of MMX instructions. Because the MMX registers and tag words are shared with the floating-point unit, it is necessary to clear the state before executing floating-point instructions. Unlike the EMMS instruction, the contents of the MMX/floating-point registers are undefined after a FEMMS instruction is executed. Therefore, the FEMMS instruction offers a faster context switch at the end of an MMX routine where the values in the MMX registers are no longer required. FEMMS can also be used prior to executing MMX instructions where the preceding floating-point register values are no longer required, which facilitates faster context switching.


PAVGUSB: Average of unsigned packed 8-bit values

pavgusb m64/mmxreg,mmxreg

The PAVGUSB instruction produces the rounded averages of the eight unsigned 8-bit integer values in the source operand (an MMX register or a 64-bit memory location) and the eight corresponding unsigned 8-bit integer values in the destination operand (an MMX register). It does so by adding the source and destination byte values and then adding a 001h to the 9-bit intermediate value. The intermediate value is then divided by 2 (shifted right one place) and the eight unsigned 8-bit results are stored in the MMX register specified as the destination operand.


PF2ID: Converts packed floating-point operand to packed 32 bit integers

pf2id m64/mmxreg2,mmxreg1

PF2ID is a vector instruction that converts a vector register containing single-precision, floating-point operands rto 32-bit signed integers using truncation.

if (mmxreg2/mem64 [31:0 ] >> = 2^31 )
    mmxreg1 [31:0 ] == 0x7FFFFFFF
else if (mmxreg2/mem64 [31:0 ] << = –2^31 )
    mmxreg1 [31:0 ] == 0x80000000
else mmxreg1 [31:0 ] == int(mmxreg2/mem64 [31:0 ])
if (mmxreg2/mem64 [63:32 ] >>= 2^31 )
    mmxreg1 [63:32 ] == 0x7FFFFFFF
else if (mmxreg2/mem64 [63:32 ] << = –2^31 )
    mmxreg1 [63:32 ] == 0x80000000
else mmxreg1 [63:32 ] == int(mmxreg2/mem64 [63:32 ])


PFACC: Floating-point accumulate

pfacc m64/mmxreg2,mmxreg1

PFACC is a vector instruction that accumulates the two words of the destination operand and the source operand and stores the results in the low and high words of destination operand respectively. Both operands are single-precision, floating-point operands with 24-bit significands.

temp =mmxreg2/mem64
mmxreg1 [31:0 ] == mmxreg1 [31:0 ] + mmxreg1 [63:32 ]
mmxreg1 [63:32 ] == temp [31:0 ] + temp [63:32 ]


PFADD: Packed floating-point addition

pfadd m64/mmxreg2,mmxreg1

PFADD is a vector instruction that performs addition of the destination operand and the source operand. Both operands are single-precision, floating-point operands with 24-bit significands.

mmxreg1 [31:0 ] == mmxreg1 [31:0 ] + mmxreg2/mem64 [31:0 ]
mmxreg1 [63:32 ] == mmxreg1 [63:32 ] + mmxreg2/mem64 [63:32 ]


PFCMPEQ: Packed floating-point comparison, equal to

pfcmpeq m64/mmxreg2,mmxreg1

PFCMPEQ is a vector instruction that performs a comparison of the destination operand and the source operand and generates all one bits or all zero bits based on the result of the corresponding comparison. Table 8 on page 28 shows the numerical range of the PFCMPEQ instruction.

The PFCMPEQ instruction performs the following operations:

if (mmxreg1 [31:0 ] == mmxreg2/mem64 [31:0 ])
    mmxreg1 [31:0 ] == 0xFFFFFFFF
else (mmxreg1 [31:0 ] == 0x00000000)
if (mmxreg1 [63:32 ] == mmxreg2/mem64 [63:32 ]
    mmxreg1 [63:32 ] == 0xFFFFFFFF
else
    mmxreg1 [63:32 ] == 0x00000000


PFCMPGE: Packed floating-point comparison, greater than or equal to

pfcmpge m64/mmxreg2,mmxreg1

PFCMPGE is a vector instruction that performs a comparison of the destination operand and the source operand and generates all one bits or all zero bits based on the result of the corresponding comparison. Table 9 on page 30 shows the numerical range of the PFCMPGE instruction.

The PFCMPGE instruction performs the following operations:

if (mmxreg1 [31:0 ] >>=mmxreg2/mem64 [31:0 ])
then mmxreg1 [31:0 ] == 0xFFFFFFFF
else mmxreg1 [31:0 ] == 0x00000000
if (mmxreg1 [63:32 ] >>= mmxreg2/mem64 [63:32 ]
then mmxreg1 [63:32 ] == 0xFFFFFFFF
else mmxreg1 [63:32 ] == 0x00000000


PFCMPGT: Packed floating-point comparison, greater than

pfcmpgt m64/mmxreg2,mmxreg1

PFCMPGT is a vector instruction that performs a comparison of the destination operand and the source operand and generates all one bits or all zero bits based on the result of the corresponding comparison. Table 10 on page 32 shows the numerical range of the PFCMPGT instruction.

The PFCMPGT instruction performs the following operations:

if (mmxreg1 [31:0 ] >> mmxreg2/mem64 [31:0 ])
then mmxreg1 [31:0 ] == 0xFFFFFFFF
else mmxreg1 [31:0 ] == 0x00000000
if (mmxreg1 [63:32 ] >> mmxreg2/mem64 [63:32 ]
then mmxreg1 [63:32 ] == 0xFFFFFFFF
else mmxreg1 [63:32 ] == 0x00000000


PFMAX: Packed floating-point maximum

pfmax m64/mmxreg2,mmxreg1

PFMAX is a vector instruction that returns the larger of the two single-precision, floating-point operands. Any operation with a zero and a negative number returns positive zero. An operation consisting of two zeros returns positive zero. Table 11 on page 34 shows the numerical range of the PFMAX instruction.

The PFMAX instruction performs the following operations:

if (mmxreg1 [31:0 ] >> mmxreg2/mem64 [31:0 ])
then mmxreg1 [31:0 ] == mmxreg1 [31:0 ]
else mmxreg1 [31:0 ] == mmxreg2/mem64 [31:0 ]
if (mmxreg1 [63:32 ] >> mmxreg2/mem64 [63:32 ])
then mmxreg1 [63:32 ] == mmxreg1 [63:32 ]
else mmxreg1 [63:32 ] == mmxreg2/mem64 [63:32 ]


PFMIN: Packed floating-point minimum

pfmin mmxreg2/mem64,mmxreg1

PFMIN is a vector instruction that returns the smaller of the two single-precision, floating-point operands. Any operation with a zero and a positive number returns positive zero. An operation consisting of two zeros returns positive zero.

The PFMIN instruction performs the following operations:

if (mmxreg1 [31:0 ] << mmxreg2/mem64 [31:0 ])
then mmxreg1 [31:0 ] == mmxreg1 [31:0 ]
else mmxreg1 [31:0 ] == mmxreg2/mem64 [31:0 ]
if (mmxreg1 [63:32 ] << mmxreg2/mem64 [63:32 ])
then mmxreg1 [63:32 ] == mmxreg1 [63:32 ]
else mmxreg1 [63:32 ] == mmxreg2/mem64 [63:32 ]


PFMUL: Packed floating-point multiplication

pfmul mmxreg2/mem64,mmxreg1

PFMUL is a vector instruction that performs multiplication of the destination operand and the source operand. Both operands are single-precision, floating-point operands with 24-bit significands.

The PFMUL instruction performs the following operations:

mmxreg1 [31:0 ]  == mmxreg1 [31:0 ]  * mmxreg2/mem64 [31:0 ]
mmxreg1 [63:32 ] == mmxreg1 [63:32 ] * mmxreg2/mem64 [63:32 ]


PFRCP: Floating-point reciprocal approximation

pfrcp mmxreg2/mem64,mmxreg1

PFRCP is a scalar instruction that returns a low-precision estimate of the reciprocal of the source operand. The single result value is duplicated in both high and low halves of this instruction’s 64-bit result. The source operand is single-precision with a 24-bit significand, and the result is accurate to 14 bits.

Increased accuracy (the full 24 bits of a single-precision significand) requires the use of two additional instructions (PFRCPIT1 and PFRCPIT2). The first stage of this increase or refinement in accuracy (PFRCPIT1) requires that the input and output of the already executed PFRCP instruction be used as input to the PFRCPIT1 instruction.

The PFRCP instruction performs the following operations:

mmxreg1 [31:0 ]  == reciprocal(mmxreg2/mem64 [31:0 ])
mmxreg1 [63:32 ] == reciprocal(mmxreg2/mem64 [31:0 ])


PFRCPIT1: Packed floating-point reciprocal, first iteration step

pfrcpit1 mmxreg2/mem64,mmxreg1

PFRCPIT1 is a vector instruction that performs the first intermediate step in the Newton-Raphson iteration to refine the reciprocal approximation produced by the PFRCP instruction (the second and final step completes the iteration and is accurate to 24 bits).

The behavior of this instruction is only defined for those combinations of operands such that one source operand was the input to the PFRCP instruction and the other source operand was the output of the same PFRCP instruction. Refer to Division and Square Root for an application-specific example of how to use this instruction and related instructions.


PFRCPIT2: Packed floating-point reciprocal/reciprocal square root, second iteration step

pfrcpit2 mmxreg2/mem64,mmxreg1

PFRCPIT2 is a vector instruction that performs the second and final intermediate step in the Newton-Raphson iteration to refine the reciprocal or reciprocal square root approximation produced by the PFRCP and PFSQRT instructions, respectively.

The behavior of this instruction is only defined for those combinations of operands such that the first source operand (mmreg1) was the output of either the PFRCPIT1 or PFRSQIT1 instructions and the second source operand (mmreg2/mem64) was the output of either the PFRCP or PFRSQRT instructions. Refer to Division and Square Root example of how to use this instruction and related instructions.


PFRSQIT1: Packed floating-point reciprocal square root, first iteration step

pfrsqit1 mmxreg2/mem64,mmxreg1

PFRSQIT1 is a vector instruction that performs the first intermediate step in the Newton-Raphson iteration to refine the reciprocal square root approximation produced by the PFSQRT instruction (the second and final step completes the iteration and is accurate to 24 bits).

The behavior of this instruction is only defined for those combinations of operands such that one source operand was the input to the PFRSQRT instruction and the other source operand is the square of the output of the same PFRSQRT instruction. Refer to Division and Square Root for an application-specific example of how to use this instruction and related instructions.


PFRSQRT: Floating-point reciprocal square root approximation

pfrsqrt mmxreg2/mem64,mmxreg1

PFRSQRT is a scalar instruction that returns a low-precision estimate of the reciprocal square root of the source operand. The single result value is duplicated in both high and low halves of this instruction’s 64-bit result. The source operand is single-precision with a 24-bit significand, and the result is accurate to 15 bits.

Negative operands are treated as positive operands for purposes of reciprocal square root computation, with the sign of the result the same as the sign of the source operand.

Increased accuracy (the full 24 bits of a single-precision significand) requires the use of two additional instructions (PFRSQIT1 and PFRCPIT2). The first stage of this increase or refinement in accuracy (PFRSQIT1) requires that the input and squared output of the already executed PFRSQRT instruction be used as input to the PFRSQIT1 instruction. Refer to Division and Square Root for an application-specific example of how to use this instruction and related instructions.


PFSUB: Packed floating-point subtraction

pfsub mmxreg2/mem64,mmxreg1

PFSUB is a vector instruction that performs subtraction of the source operand from
the destination operand. Both operands are single-precision, floating-point operands
with 24-bit significands.

The PFSUB instruction performs the following operations:

mmxreg1 [31:0 ]  == mmxreg1 [31:0 ]  – mmxreg2/mem64 [31:0 ]
mmxreg1 [63:32 ] == mmxreg1 [63:32 ] – mmxreg2/mem64 [63:32 ]


PFSUBR: Packed floating-point reverse subtraction

pfsubr mmxreg2/mem64,mmxreg1

PFSUBR is a vector instruction that performs subtraction of the destination operand from the source operand. Both operands are single-precision, floating-point operands with 24-bit significands. Table 20 on page 52 shows the numerical range of the PFSUBR instruction.

The PFSUBR instruction performs the following operations:

mmreg1[31:0]  = mmreg2/mem64[31:0]  – mmreg1[31:0]
mmreg1[63:32] = mmreg2/mem64[63:32] – mmreg1[63:32]


PI2FD: Packed 32-bit integer to floating-point conversion

pi2fd mmxreg2/mem64,mmxreg1

PI2FD is a vector instruction that converts a vector register containing signed, 32-bit integers to single-precision, floating-point operands. When PI2FD converts an input operand with more significant digits than are available in the output, the output is truncated.

The PI2FD instruction performs the following operations:

mmreg1 [31:0 ]  == float(mmreg2/mem64 [31:0 ])
mmreg1 [63:32 ] == float(mmreg2/mem64 [63:32 ])


PMULHRW: Multiply signed packed 16-bit values with rounding and store the high 16 bits

pmulhrw mmxreg2/mem64,mmxreg1

The PMULHRW instruction multiplies the four signed 16-bit integer values in the source operand (an MMX register or a 64-bit memory location) by the four corresponding signed 16-bit integer values in the destination operand (an MMX register). The PMULHRW instruction then adds 8000h to the lower 16 bits of the 32-bit result, which results in the rounding of the high-order, 16-bit result. The high-order 16 bits of the result (including the sign bit) are stored in the destination operand.

The PMULHRW instruction provides a numerically more accurate result than the PMULMH instruction, which truncates the result instead of rounding.


PREFETCH(W): Prefetch processor cache line into L1 data cache (Dcache)

prefetch mem8

The PREFETCH instruction loads a processor cache line into the data cache. The address of this line is specified by the mem8 value. For the AMD processor, the line size is 32 bytes. In all future processors, the size of the line that is loaded by the PREFETCH instruction will be at least 32-bytes. The PREFETCH instruction loads a cache line even if the mem8 address is not aligned with the start of the line (although some implementations, including the AMD-K6 family of processors, may perform the cache fill starting from the cache miss or mem8 address). If a cache hit occurs (the line is already in the Dcache) or a memory fault is detected, no bus cycle is initiated and the instruction is treated as a NOP.

In applications where a large number of data sets must be processed, the PREFETCH instruction can pre-load the next data set into the Dcache while, simultaneously, the processor is operating on the present set of data. This instruction allows the programmer to explicitly code operation concurrency. When the present set of data values is completed, the next set is already available in the Dcache. An example of a concurrent operation is vertices processing in 3D transformations, where the next set of vertices can be prefetched into the data cache while the present set is being transformed.

The PREFETCH instruction format in the processor is defined to allow extensions in future AMD K86™ processors. The instruction mnemonic for the PREFETCH instruction includes the modR/M byte. Only the memory form of modR/M is valid (use of the register form results in an invalid opcode exception). Because there is no destination register, the three destination register field bits of the modR/M byte are used to define the type of prefetch to be performed. The PREFETCH and PREFETCHW instructions are defined by the bit pattern 000b and 001b, respectively. All other bit patterns are reserved for future use.

The PREFETCHW instruction loads the prefetched line and sets the cache line MESI state to modified (in anticipation of subsequent data writes to the line), unlike the PREFETCH instruction, which typically sets the state to exclusive. If the data that is prefetched into the Dcache is to be modified, use of the PREFETCHW instruction.


Division and Square Root

Division

The 3DNow! instructions can be used to compute a very fast, highly accurate reciprocal or quotient. Consider the quotient q = a/b. An on-chip, ROM-based table lookup can be used to quickly produce a 14– 15 bit precision approximation of 1/b (using just one two-cycle latency instruction PFRCP). A full-precision reciprocal can then quickly be computed from this approximation using a Newton-Raphson algorithm.

The general Newton-Raphson recurrence for the reciprocal is as follows:

Zi + 1 <- Zi * (2 – b * Zi)

Given that the initial approximation is accurate to at least 14 bits, and that full IEEE single precision contains 24 bits of mantissa, just one Newton-Raphson iteration is required. The following shows the 3DNow! instruction sequence to produce the initial reciprocal approximation, to compute the full-precision reciprocal from this, and lastly, to complete the required division of a/b.

    x 0 = pfrcp(b)
    x 1 = pfrcpit1(b, x 0 )
    x 2 = pfrcpit2(x 1 , x 0 )
    q   = pfmul(a, x 2 )

The 24-bit final reciprocal value is X 2 . In the AMD processor implementation, the estimate contains the correct round-to-nearest value for approximately 99% of all arguments. The remaining arguments differ from the correct round-to-nearest value for the reciprocal by 1 unit-in-the-last-place (ulp). The quotient is formed in the last step by multiplying the reciprocal by the dividend a.

Divide Examples

These examples illustrate the use of 3DNow! instructions to perform divides.

(14-Bit Precision)

    movd [mem],mm0 ; 0   | w
    pfrcp mm0,mm0  ; 1/w | 1/w (approx.)
    movq [mem],mm2 ; y   | x
    pfmul mm0,mm2  ; y/w | x/w

(24-Bit Precision)

    movd [mem],mm0    ; 0   | w
    pfrcp mm0,mm1     ; 1/w | 1/w (approx.)
    punpckldq mm0,mm0 ; w   | w (mmx instruction)
    pfrcpit1 mm1,mm0  ; 1/w | 1/w (intermed.)
    movq [mem],mm2    ; y   | x
    pfrcpit2mm0,mm1   ; 1/w | 1/w (full prec.)
    pfmul mm2,mm0     ; y/w | x/w

Square Root

The 3DNow! instructions can also be used to compute a reciprocal square root or square root with high performance. The general Newton-Raphson reciprocal square root recurrence is as follows:

Zi + 1 <- 1/2 * Zi * (3 – b * Zi^2)

To reduce the number of iterations, the initial approximation is read from a table. The 3DNow! reciprocal square root approximation is accurate to at least 15 bits. Accordingly, to obtain a single-precision 24-bit reciprocal square root of an input operand b, one Newton-Raphson iteration is required using the following 3DNow! instructions:

1. X 0 = PFRSQRT(b)
2. X 1 = PFMUL(X 0 , X 0 )
3. X 2 = PFRSQIT1(b, X 1 )
4. X 3 = PFRCPIT2(X 2 , X 0 )
5. X 4 = PFMUL(b, X 3 )

The 24-bit final reciprocal square root value is X 3 . In the AMD implementation, the estimate contains the correct round-to-nearest value for approximately 87% of all arguments. The remaining arguments differ from the correct round-to-nearest value by 1 ulp. The square root (X 4 ) is formed in the last step by multiplying by the input operand b.

Square Root Examples

These examples illustrate the use of 3DNow! technology to perform square roots.

(15-Bit Precision)

    movd [mem],mm0    ; 0         | a
    pfrsqrt mm0,mm1   ; 1/(sqrt a)| 1/(sqrt a)(approx.)
    punpckldq mm0,mm0 ; a         | a (mmx instr.)
    pfmul mm1,mm0     ;(sqrt a)   | (sqrt a)

(24-Bit Precision)

    movd [mem],mm0    ; 0         | a
    pfrsqrt mm0,mm1   ; 1/(sqrt a)| 1/(sqrt a)(approx.)
    movq mm1,mm2      ; x_0 = 1/(sqrt a)(approx.)
    pfmul mm1,mm1     ; x_0 *x_0  | x_0 *x_0 step 1
    punpckldq mm0,mm0 ; a         | a (mmx instr.)
    pfrsqit1 mm0,mm1  ; (intermediate)step 2
    pfrcpit2 mm2,mm1  ; 1/(sqrt a)(full prec.)step 3
    pfmul mm1,mm0     ; (sqrt a)  | (sqrt a)


Appendix

Flags Register

FPU Control Register

FPU Status Register


Flags Register

The flags register, also known as the condition codes register is comprised of 16 bits shown below. Actually for the 16 bits shown below it's called FLAGS when 32 bits it's called EFLAGS!

The carry, parity, zero, sign, and overflow flags are used primarily with conditional jump instructions but you can also use the SETcc instructions and pushf/popf instructions to manage these flags.

Flag Register Instructions

clc | Clears the Carry Flag
cld | Clears the Direction Flag causing string instructions to increment the ESI and EDI index registers.
std | Sets the Direction Flag to 1 causing string instructions to decrement ESI and EDI instead of increment.
clts | Clears the Task Switched Flag in the Machine Status Register. This is a privileged operation and is generally used only by operating system code.
cmc | Toggles (inverts) the Carry Flag
lahf | Copies bits 0-7 of the flags register into AH. This includes flags AF, CF, PF, SF and ZF other bits are undefined.
sahf | Transfers bits 0-7 of AH into the Flags Register. This includes AF, CF, PF, SF and ZF.
pushf | Transfers the Flags Register onto the stack.
popf | Pops word from stack into the Flags Register and then increments ESP by 2
stc | Sets the Carry Flag to 1.
cli | Disables the mask-able hardware interrupts by clearing the Interrupt flag. NMI's and software interrupts are not inhibited.
sti | Sets the Interrupt Flag to 1, which enables recognition of all hardware interrupts.


FPU Control Register

The FPU Control Register

Bits 0-5 are the exception masks. If any of these bits are set, the corresponding condition is ignored by the FPU. If any bit is zero, and the corresponding condition occurs, then the FPU immediately generates an interrupt so the program can handle the exception condition.

Bit 0 is the invalid operation mask. Problems which arise generating an invalid exception include pushing more than eight values onto the stack or attempting to pop an item off an empty stack, trying to take the square root of a negative number, or loading a non-empty register.

Bit 1 masks the denormalised interrupt which occurs if an attemp is made to use a denormalised value. A denormalised value is generally a very small number just beyond the range of the FPU's precision capabilities.

Bit 2 masks the zero divide exception. The FPU will generate an interrupt for a divide by zero or will produce a NaN (Not A Number) depending on this mask.

Bit 3 three masks the overflow exception. This can occur for example if one tries to store a long double in a float variable that is too large for the float.

Bit 4 masks the underflow exception. This can occur for example if one tries to store a long double in a float variable that is too small for the float.

Bit 5 controls whether the precision exception can occur. Floating point values are often an approximation and not an exact representation of the precise figure. This precision exception occurs if the FPU produces an imprecise result, generally the result of an internal rounding operation. Dividing one by ten (1/10) will produce an imprecise result, therefore this exception often occurs since imprecise results are very common.

Bits 6-7, 12-15 are reserved.


FPU Status Register

The FPU Status Register

Bits 0-5 the exception flags. These bits are in the same order as the exception masks in the control register. If the corresponding condition exists, then the bit is set. These bits are independent of the exception masks in the control register. The FPU sets or clears these bits regardless of the corresponding mask setting in the control register.

Bit 6 indicates a stack fault. A stack fault occurs whenever there is a stack overflow or underflow. When this bit is set, the C1 condition code bit determines whether there was a stack overflow (C1=1) or stack underflow (C1=0) condition.

Bit 7 is set if any error condition bit is set. It is the logical OR of bits zero through five. A program can test this bit to quickly determine if an error condition exists.

Bits eight, nine, ten, and fourteen are the coprocessor condition code bits.

Status Register Condition Codes
Class | C3 | C2 | C0
Unsupported | 0 | 0 | 0
NaN | 0 | 0 | 1
Normal Finite Number | 0 | 1 | 0
Infinity | 0 | 1 | 1
Zero | 1 | 0 | 0
Empty | 1 | 0 | 1
Denormal Number | 1 | 1 | 0

The condition code C1 (bit 9) is the sign bit and can be tested using BT (bit test) instruction.

The FPU instruction FXAM tests the value in st(0) and sets these condition codes accordingly. Here is a routine to test if the value in st(0) is a normal finite number.

int is_normal(double a)
{
_asm("fldl 8(%ebp)");
_asm("fxam");
_asm("fstsw %ax");
_asm("andw $0x4500, %ax"); // mask out all but
relevant bits
_asm("cmpw $0x400, %ax");  // check for bit 10
only
_asm("jnz notnorm4");
// not normal
_asm("movl $1, %eax");     //
yes normal
_asm("jmp exit5");
_asm("notnorm5:");
_asm("xorl %eax, %eax");   // clear eax
_asm("exit5:");
_asm("fstp %st(0)");
}


Introduction

Le langage Assembleur de la famille des 80x86 est de loin le plus populaire des langages assembleurs à avoir été développé. De plus, ses différents modes de fonctionnement (Mode réel, Mode protégé, Mode virtuel) sont le résultat d'un manque de vision d'extension vers le futur. Hélas, on ne peut pas tout prévoir, mais le prix a payer fut des programmes a réécrire, un microprocesseur de plus en plus complexe de style CISC. En faite, tout le contraire des microprocesseurs RISC.

Le bon côté de la complexité de son fonctionnement, tiens du fait qu'il est possible d'écrire des programmes en langages machines avec très peu de code si on est habile pour utiliser spécifiquement ce qu'on a vraiment besoin. Ainsi, si on veut effectué des calculs ne nécessitant que 8 bits et non 16 bits, cette opération est toujours possible. De plus, les experts de ce langage assembleur arrive a effectuer deux opérations 8 bits avec une seule instruction, a mettre la valeur d'un registre avec un opérateur de «ou exclusif binaire» (exemple: XOR AX,AX ou XOR EAX,EAX), lequel est beaucoup compacte en terme de code. Et bien que la folie des grandeurs poussent les programmeurs a consommer toujours le maximum d'un registre, il est souvent préférable d'écrire un code très petit, qu'avec des instructions plus rapide, car, bien que ses processeurs soit très rapide, les programmes, eux sont toujours aussi lent a charger en mémoire!

Avantages

p align="justify"> Bien que très peu utilisé, quels sont les avantages d'utiliser le langage de programmation Assembleur ?

  • Les langages assembleurs sont beaucoup plus rapide d'exécution que les langages évolué.
  • Les langages assembleurs sont beaucoup plus petit en terme de taille total d'un programme. Généralement, ils sont 10 fois plus petits qu'une application écrit en langage évolue (3GL ou 4GL).
  • Il est possible d'avoir un contrôle total sur le contexte d'utilisation de la mémoire.
  • Il est possible de tout faire en assembleur, ainsi, si on souhaite écrire un secteur de démarrage entrant spécifiquement dans un espace réduit, c'est possible! Dans un langage évolué, comme le langage C ou Pascal, cette idée peut paraitre à la fois farfelue et dangereuse, car totalement imprévisible en fonction des versions et du fabricant du compilateur.

Inconvénient

Qu'est-ce qu'y bloc l'utilisation du langage de programmation Assembleur ?

  • Les programmes écrits en assembleurs sont destinés au microprocesseur et le matériel pour lequel ils ont étés écrits. Ils ne sont pas portable.
  • Le temps de développements est souvent beaucoup plus long qu'un autre langage, car des erreurs souvent banales, peuvent faire planter le système.
  • Le temps de formation d'un professionnel est beaucoup plus long.

Microprocesseur | Fabricant | Génération | Mode de fonctionnement | Registre | Coprocesseur | Coeur
8088 | Intel | 1re | Mode réel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, ES, IP, SI, SP, SS | 8087 | 1
V20 | NEC | 1re | Mode réel, mode émulation 8080 | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, ES, IP, SI, SP, SS |  | 1
8086 | Intel | 1re | Mode réel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, ES, IP, SI, SP, SS | 8087 | 1
V30 | NEC | 1re | Mode réel, mode émulation 8080 | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, ES, IP, SI, SP, SS |  | 1
80188 | Intel | 1re | Mode réel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, ES, IP, SI, SP, SS | 8087 | 1
80186 | Intel | 1re | Mode réel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, ES, IP, SI, SP, SS | 8087 | 1
80286 | Intel | 2e | Mode réel, mode protégé | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, ES, IP, SI, SP, SS | 80287 | 1
80386DX | Intel | 3e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS | 80387DX | 1
80386DXL | AMD | 3e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS |  | 1
80386DXLV | AMD | 3e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS |  | 1
80386SX | Intel | 3e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS | 80387SX | 1
80386SXL | AMD | 3e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS |  | 1
80386SXLV | AMD | 3e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS |  | 1
80386SL | Intel | 3e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS | 80387SL | 1
80386SLC | IBM | 3e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS |  | 1
80486 | Intel | 4e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
80486DX | Intel | 4e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
80486SL | Intel | 4e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
80486SLC2 | IBM | 4e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS |  | 1
80486SX | Intel | 4e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS | 80487SX | 1
Pentium | Intel | 5e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
Pentium MMX | Intel | 5e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
Pentium Pro | Intel | 6e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
Pentium II | Intel | 6e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
Pentium III | Intel | 6e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
Pentium M | Intel | 6e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
Pentium 4 | Intel | 7e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
Pentium D | Intel | 7e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 2
Core 2 | Intel | 7e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 2
... | ... | ... | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | ...

Voir également

Articles - Les géants de l'informatique - Intel

Références

Assembleur - Référence, Edition Micro Application, Pierre Maurette, 2003, ISBN: 2-7429-3061-2, page 84 à 100.
The Undocumented PC: A programmer's Guide to I/O, CPUs, and Fixed Memory Areas - Second Edition, Edition Addison-Wesley, Frank van Gilluwe, 1997, ISBN: 0-201-47950-8, page 51 à 62.

Dernière mise à jour : Samedi, le 2 août 2014


Langage de programmation - Assembleur 80x86 - Lexique et dictionnaire d'instruction assembleur 80x86

Vu dans ... Gladir.com Cliquez sur l'instruction recherchée pour atteindre plus rapidement votre commande du langage de programmation assembleur de la famille 80x86 recherché.

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Instruction | Description | CPU/MPU
AAA | Cette instruction permet d'adapter le résultat obtenu par l'addition de 2 valeurs en format DCB. | INTEL 8088+
AAD | Cette instruction permet de convertir une valeur de format DCB non compactée. | INTEL 8088+
AAM | Cette instruction offre la possibilité de convertir le produit de la multiplication de 2 valeurs de format DCB en un format DCB. | INTEL 8088+
AAS | Cette instruction permet d'adapter le résultat de la soustraction de nombre de format DCB. | INTEL 8088+
ADC | Cette instruction additionne 2 quantités numériques sur 8, 16, 32 ou 64 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu. | INTEL 8088+
ADD | Cette instruction additionne 2 quantités numériques sur 8, 16, 32 ou 64 bits. | INTEL 8088+
ADDPD | Cette instruction permet d'effectuer une addition de 2 paquets de valeurs réels de double précision d'un opérande source et d'un opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de double précision. | INTEL Pentium 4+
ADDPS | Cette instruction permet d'effectuer une addition SIMD de 4 paquets de valeurs réels de simple précision d'un opérande source et d'un opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de simple précision. | INTEL Pentium III (SSE)+
ADDSD | Cette instruction permet d'effectuer une addition de la partie basse d'une valeur réel de double précision d'un opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de double précision. | INTEL Pentium 4+
ADDSS | Cette instruction permet d'effectuer une addition de la partie basse d'une valeur réel de simple précision d'un opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de simple précision. | INTEL Pentium III (SSE)+
ADDSUBPD | Cette instruction permet d'effectuer une soustraction de la partie basse d'une valeur réel de double précision d'un opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de double précision et d'effectuer une addition de la partie haute d'une valeur réel de double précision d'un opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de double précision. | INTEL Pentium 4 (SSE3)+
ADDSUBPS | Cette instruction permet d'effectuer une soustraction de la partie basse d'un paquet de valeur réel de simple précision d'un opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de simple précision et d'effectuer une addition de la partie haute d'un paquet de valeur réel de simple précision d'une opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de simple précision. | INTEL Pentium 4 (SSE3)+
AESDEC | Cette instruction permet d'effectuer un arrondissement du décryptage AES en utilisant l'équivalence de Cipher inversé, avec un clef arrondie pour le deuxième opérande source, opération dans une données de 128 bits du premier opérande source, et enregistre le résultat dans l'opérande de destination. | Intel AES
AESDECLAST | Cette instruction permet d'effectuer le dernier arrondissement du décryptage AES en utilisant l'équivalence de Cipher inversé, avec un clef arrondie pour le deuxième opérande source, opération dans une données de 128 bits du premier opérande source, et enregistre le résultat dans l'opérande de destination. | Intel AES
AESENC | Cette instruction permet d'effectuer un arrondissement d'encryptage AES en utilisant la clef arrondie pour le deuxième opérande source, opération dans une données de 128 bits du premier opérande source, et enregistre le résultat dans l'opérande de destination. | Intel AES
AESENCLAST | Cette instruction permet d'effectuer le dernier arrondissement d'encryptage AES en utilisant la clef arrondie pour le deuxième opérande source, opération dans une données de 128 bits du premier opérande source, et enregistre le résultat dans l'opérande de destination. | Intel AES
AESIMC | Cette instruction permet d'effectuer une transformation InvMixColumns de l'opérande source et enregistre le résultat dans l'opérande de destination. | Intel AES
AESKEYGENASSIST | Cette instruction permet d'effectuer l'expansion de clef AES Cipher, en calculant la génération des clefs arrondies pour l'encryption, en utilisant les données 128 bits spécifiés de l'opérande source et de la constante arrondie arrondie 8 bits spécifié immédiate et enregistre le résultat dans l'opérande de destination. | Intel AES
AND | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés. | INTEL 8088+
ANDNPD | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 paquets d'opérandes de valeur de format réel de double précision et inverse chacun des bits du résultat. | INTEL Pentium 4+
ANDNPS | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes 128 bits spécifiés et inverse chacun des bits du résultat. | INTEL Pentium III (SSE)+
ANDPD | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 paquets d'opérandes de valeur de format réel de double précision. | INTEL Pentium 4+
ANDPS | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes 128 bits spécifiés. | INTEL Pentium III (SSE)+
ARPL | Cette instruction permet de contrôler et corriger le niveau de privilège du segment de code en mode protégée. | INTEL 80286+
BLENDPD | Cette instruction permet de copier le paquet de valeurs réel de double précisions de l'opérande source dans l'opérande de destination si la condition de masque de l'opérande immédiate est rempli. | SSE4.1
BLENDPS | Cette instruction permet de copier le paquet de valeurs réel de simple précisions de l'opérande source dans l'opérande de destination si la condition de masque de l'opérande immédiate est rempli. | SSE4.1
BLENDVPD | Cette instruction permet de copier le paquet de valeurs réel de double précisions de l'opérande source dans l'opérande de destination si la condition de masque de l'opérande du troisième opérande en registre est rempli. | SSE4.1
BLENDVPS | Cette instruction permet de copier le paquet de valeurs réel de simple précisions de l'opérande source dans l'opérande de destination si la condition de masque de l'opérande du troisième opérande en registre est rempli. | SSE4.1
BOUND | Cette instruction permet de vérifier la validité pouvant exister entre avec un tableau et son indexation. | INTEL 80186+
BSF | Cette instruction permet d'effectuer une comparaison binaire de la droite vers la gauche. | INTEL 80386+
BSR | Cette instruction permet d'effectuer une comparaison binaire de la gauche vers la droite. | INTEL 80386+
BSWAP | Cette instruction permet d'inverse l'ordre des 4 octets d'un registre de taille de 32 bits. | INTEL 80486+
BT | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue. | INTEL 80386+
BTC | Cette instruction transfère une Opérande vers l'indicateur de retenue le bit spécifié et inverser la valeur du bit correspondant. | INTEL 80386+
BTR | Cette instruction permet de transférer l'Opérande vers l'indicateur de retenue le bit spécifié puis met le bit correspondant de l'Opérande à 0. | INTEL 80386+
BTS | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue le bit spécifié puis ensuite met le bit correspondant dans Opérande à 1. | INTEL 80386+
CALL | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse d'appel avant de continuer. | INTEL 8088+
CBW | Cette instruction permet de convertir un nombre contenu dans le registre AL en un format sur 16 bits pour se retrouver dans le registre AX en appliquant une extension du signe. | INTEL 8088+
CDQ | Cette instruction permet de convertir le double mot en un quadruple mot, le résultat tient sur une taille de 64 bits. | INTEL 80386+
CDQE | Cette instruction permet de convertir le double mot du registre EAX en un quadruple mot RAX, le résultat tient sur une taille de 64 bits. | x86-64+
CLC | Cette instruction permet de mettre l'indicateur d'état de retenu CF à 0. | INTEL 8088+
CLD | Cette instruction met l'indicateur d'état DF à 0. | INTEL 8088+
CLFLUSH | Cette instruction permet de vider la ligne de cache d'une adresse linéaire. | INTEL Pentium 4 (SSE2)+
CLGI | Cette instruction permet d'effacer le drapeau global d'interruption (GIF). Quand le GIF est à 0, toutes les interruptions externes sont désactivées. | AMD-V
CLI | Cette instruction met l'indicateur d'état IF à 0. | INTEL 8088+
CLTS | Cette instruction permet de mettre à 0 le drapeau de l'indicateur de tâche (Task-Switch) du registre CR0. | INTEL 80286+
CMC | Cette instruction offre la possibilité d'inverser la valeur de l'indicateur de retenue. Si ce dernier vaut 1, elle le met à 0 et inversement. | INTEL 8088+
CMOV | Cette instruction copie des données d'une source (valeur) à une destination (registre) à la condition que la condition demandée soit remplie. | INTEL Pentium Pro+
CMP | Cette instruction offre la possibilité essentielle de comparer 2 registres ou emplacements de mémoire. | INTEL 8088+
CMPPD | Cette instruction permet d'effectuer une comparaison SIMD de 2 paquets de valeurs réels de double précision d'un opérande source et d'un opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination. | INTEL Pentium 4 (SSE2)+
CMPPS | Cette instruction permet d'effectuer une comparaison SIMD de 4 paquets de valeurs réels de simple précision d'un opérande source et d'un opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination. | INTEL Pentium III (SSE)+
CMPS | Cette instruction permet d'effectuer la comparaison d'un octet, d'un mot ou double mot spécifié avec l'opérande source et destination spécifié et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison. | INTEL 8088+
CMPSB | Cette instruction permet d'effectuer la comparaison d'un octet avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison. | INTEL 8086+
CMPSD | Cette instruction permet d'effectuer la comparaison d'un double mot avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison. | INTEL 80386+
CMPSD | Cette instruction permet d'effectuer une comparaison de la partie basse de valeurs réelles de double précision d'un opérande source et d'un opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination. | INTEL Pentium 4 (SSE2)+
CMPSQ | Cette instruction permet d'effectuer la comparaison d'un quadruple mot avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison. | x86-64+
CMPSS | Cette instruction permet d'effectuer une comparaison de la partie basse de valeurs réelles de simple précision d'un opérande source et d'un opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination. | INTEL Pentium III (SSE)+
CMPSW | Cette instruction permet d'effectuer la comparaison d'un mot avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison. | INTEL 8086+
CMPXCHG | Cette instruction compare la destination avec l'accumulateur (AL, AX ou EAX) et les échanges si la condition est vraie. | INTEL Pentium+
CMPXCHG8B | Cette instruction compare un nombre de 64 bits et les échanges si la condition est vraie. | INTEL Pentium+
CMPXCHG16B | Cette instruction permet de comparer un nombre de 128 bits et les échanges si la condition est vraie. | INTEL x86-64+
COMISD | Cette instruction permet de comparer deux valeurs réel de double-précision dans la partie faible du quadruple mot de deux opérande et fixe les drapeaux de ZF, PF et FC du registre EFLAGS en fonction du résultat (non-ordonnée, supérieur à, inférieur ou égal). | INTEL Pentium III+
COMISS | Cette instruction permet de comparer deux valeurs réel de simple-précision dans la partie faible du quadruple mot de deux opérande et fixe les drapeaux de ZF, PF et FC du registre EFLAGS en fonction du résultat (non-ordonnée, supérieur à, inférieur ou égal). | INTEL Pentium III+
CPUID | Cette instruction retourne le code d'identification du microprocesseur. | INTEL Pentium+
CQO | Cette instruction permet de convertir le quadruple mot du registre EAX en deux quadruples mots RDX:RAX, le résultat tient sur une taille de 128 bits. | x86-64+
CRC32 | Cette instruction débute avec une valeur initiale dans l'opérande de destination, accumule une valeur de code CRC-32 (polynomial de 11EDC6F41h) dans l'opérande source et enregistre le résultat dans l'opérande de destination. | Nehalem (SSE4.2)+
CVTDQ2PD | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de double précision. | INTEL Pentium 4+
CVTDQ2PS | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de simple précision. | INTEL Pentium 4+
CVTPD2DQ | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en double mot entier et fixe à 0 le reste du paquet. | INTEL Pentium 4+
CVTPD2PI | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en double mot entier. | INTEL Pentium 4+
CVTPD2PS | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en valeurs réel de simple précision et fixe à 0 le reste du paquet. | INTEL Pentium 4+
CVTPI2PD | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de double précision compacté. | INTEL Pentium 4+
CVTPI2PS | Cette instruction permet de convertir un entier de format double mot en une valeur réel de simple précision compacté. | Pentium III (KNI/MMX2)+
CVTPS2DQ | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de simple précision en paquet de doubles mots entiers. | INTEL Pentium 4+
CVTPS2PD | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de simple précision en paquet de valeurs réel de double précision. | INTEL Pentium 4+
CVTPS2PI | Cette instruction permet de convertir une valeur réel de simple précision compacté en un entier de format double mot. | Pentium III (KNI/MMX2)+
CVTSD2SI | Cette instruction permet d'effectuer la conversion d'une valeur réel de simple précision en valeur entier de double mots. | INTEL Pentium 4+
CVTSD2SS | Cette instruction permet d'effectuer la conversion d'une valeur réel de double précision en valeur réel de simple précision. | INTEL Pentium 4+
CVTSI2SD | Cette instruction permet de convertir un entier de format double mot en une valeur réel de double précision. | INTEL Pentium 4+
CVTSI2SS | Cette instruction permet de convertir un entier de format double mot en une valeur réel de simple précision. | Pentium III (KNI/MMX2)+
CVTSS2SD | Cette instruction permet de convertir une valeur réel de simple précision en une valeur réel de double précision. | INTEL Pentium 4+
CVTSS2SI | Cette instruction permet de convertir une valeur réel de simple précision en un entier de format double mot. | Pentium III (KNI/MMX2)+
CVTTPD2DQ | Cette instruction permet de convertir un paquet de valeur réel de double précision avec en un paquet d'entier de format double mot tronquer et fixe à 0 le reste du paquet. | INTEL Pentium 4+
CVTTPD2PI | Cette instruction permet de convertir une valeur réel de double précision compacté avec tronquage en un entier de format double mot compacté. | INTEL Pentium 4+
CVTTPS2DQ | Cette instruction permet de convertir un paquet de valeur réel de simple précision avec en un paquet d'entier de format double mot tronquer. | INTEL Pentium 4+
CVTTPS2PI | Cette instruction permet de convertir une valeur réel de simple précision compacté avec tronquage en un entier de format double mot compacté. | Pentium III (KNI/MMX2)+
CVTTSD2SI | Cette instruction permet de convertir une valeur réel de double précision avec en un entier de format double mot tronquer. | INTEL Pentium 4+
CVTTSS2SI | Cette instruction permet de convertir un entier de format double mot avec tronquage en une valeur réel de simple précision. | Pentium III (KNI/MMX2)+
CWD | Cette instruction est l'alternative pour convertir le mot du registre AX en un double mot contenu dans le couple de registre DX et AX par extension du signe. | INTEL 8088+
CWDE | Cette instruction est l'alternative pour convertir le mot du registre AX en un double mot contenu dans le registre EAX par extension du signe. | INTEL 80386+
DAA | Cette instruction corrige après coup les retenues lors de la manipulation de valeur DCB. | INTEL 8088+
DAS | Cette instruction offre l'intéressante possibilité de corrige le résultat d'une soustraction de 2 nombres de format DCB compactées. | INTEL 8088+
DEC | Cette instruction décrément de 1 le registre ou l'adresse mémoire spécifié. | INTEL 8088+
DIV | Cette instruction permet d'effectuer une division non-signée (nombre naturel). | INTEL 8088+
DIVPD | Cette instruction permet d'effectuer une division de valeur réel de double précision de registre XMM ou d'emplacement mémoire de 128 bits. | INTEL Pentium 4+
DIVPS | Cette instruction permet d'effectuer une division de valeur réel de simple précision de registre XMM ou d'emplacement mémoire de 128 bits. | INTEL Pentium III (KNI/MMX2)+
DIVSD | Cette instruction permet d'effectuer une division scalaire de valeur réel de double précision de registre XMM ou d'emplacement mémoire de 128 bits. | INTEL Pentium 4+
DIVSS | Cette instruction permet d'effectuer une division scalaire de valeur réel de simple précision de registre XMM ou d'emplacement mémoire de 128 bits. | Pentium III (KNI/MMX2)+
DPPD | Cette instruction permet d'effectuer une multiplication conditionnel d'un paquet de valeurs réel de double précision dans l'opérande de destination avec le paquet de valeurs réel de l'opérande source et effectue un masque des bits extrait d'un opérande immédiat. | SSE4.1
DPPS | Cette instruction permet d'effectuer une multiplication conditionnel d'un paquet de valeurs réel de simple précision dans l'opérande de destination avec le paquet de valeurs réel de l'opérande source et effectue un masque des bits extrait d'un opérande immédiat. | SSE4.1
EMMS | Cette instruction fixe les mots marqués du MPU de chacun un. | INTEL Pentium-MMX
ENTER | Cette instruction permet de créer les structures de paramètres nécessaires aux procédures des langages de haut niveau. | INTEL 80186+
ESC | Cette instruction active le coprocesseur, lequel se permettra d'utiliser les méthodes d'adressage du processeur principal (CPU). | INTEL 8088 au 80386
F2XM | Cette instruction s'applique à calculer 2 puissance le registre mathématique ST(0) moins 1 et enregistre son produit dans le registre mathématique ST(0). Alias de F2XM1, mais déconseillé. | INTEL MPU 8087+
F2XM1 | Cette instruction permet d'effectuer le calcul de 2 puissance le registre mathématique ST(0) moins 1 et enregistre son produit dans le registre mathématique ST(0). | INTEL MPU 8087+
FABS | Cette instruction permet de convertir le nombre réel contenu dans le registre mathématique ST(0) en sa valeur absolue. | INTEL MPU 8087+
FADD | Cette instruction offre l'essentiel possibilité d'ajouter le nombre réel de valeur positive «source» à «cible» et enregistre la somme dans «cible». | INTEL MPU 8087+
FADDP | Cette instruction complémentaire ajoute le nombre réel source au nombre réel cible et enregistrer la somme dans cible puis prendre le registre mathématique ST(0) et le dépile. | INTEL MPU 8087+
FBLD | Cette instruction charge la valeur de format DCB compactée après le registre mathématique ST(0). | INTEL MPU 8087+
FBSTP | Cette instruction extrait la valeur de format DCB compactée du registre mathématique ST(0), l'enregistrer dans cible et prendre le registre mathématique ST(0) et sort de la pile. | INTEL MPU 8087+
FCHS | Cette instruction inverse tout simplement le signe du registre mathématique ST(0). | INTEL MPU 8087+
FCLEX | Cette instruction efface toutes les exceptions contenu dans les drapeaux de registres du coprocesseur mathématique. | INTEL MPU 8087+
FCMOV | Cette instruction permet de déplacé des nombres réel (virgule flottante) si la condition en question est satisfaite. | INTEL P6+
FCOM | Cette instruction permet de comparer le nombre réel de valeur positive source avec le registre mathématique ST(0) et mettre les indicateurs d'état C0 à C3 avec la valeur 1. | INTEL MPU 8087+
FCOMI | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats. | INTEL Pentium III+
FCOMIP | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats et désempile de la pile la valeur dans le registre. | INTEL Pentium III+
FCOMP | Cette instruction compare le nombre réel de valeur positive «source» avec le registre mathématique ST(0), mettre les indicateurs d'état C0 à C3 avec la valeur 1 et dépile le registre mathématique ST(0) de la pile de registres. | INTEL MPU 8087+
FCOMPP | Cette instruction permet de comparer les nombres réels du registre mathématique ST(1) avec le registre mathématique ST(0), ensuite de mettre les indicateurs d'état C0 à C3 à la valeur 1 et prendre le couple de registre mathématique ST(1) et ST(0) dans la pile de registres (2 dépilages). | INTEL MPU 8087+
FCOS | Cette instruction calcule le cosinus du registre mathématique ST(0). | INTEL MPU 80387+
FDECSTP | Cette instruction permet de décrémenter le pointeur de pile de registres. | INTEL MPU 8087+
FDISI | Cette instruction permettait de désactiver les interruptions. | INTEL MPU 8087+
FDIV | Cette instruction offre la possibilité d'effectuer des division de nombre réel de valeur positive. | INTEL MPU 8087+
FDIVP | Cette instruction offre la possibilité d'effectuer des division de nombre réel et place ST(0) dans la pile. | INTEL MPU 8087+
FDIVR | Cette instruction offre la possibilité d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source». | INTEL MPU 8087+
FDIVRP | Cette instruction offre la possibilité d'effectuer des division de nombre réel avec les registres inversés «cible» par «source» et place ST(0) dans la pile. | INTEL MPU 8087+
FEMMS | Cette instruction permet d'effacer les états MMX après le passage d'instructions MMX. | AMD 3DNow!
FENI | Cette instruction permet d'autoriser les interruptions. | INTEL MPU 8087
FFREE | Cette instruction permet de libérer un des registres de la pile. | INTEL MPU 8087+
FFREEP | Cette instruction permet de libérer un des registres de la pile et d'ensuite de désempiler le registre de la pile. | INTEL MPU 80287+
FIADD | Cette instruction offre l'essentiel possibilité d'ajouter le nombre réel source à cible et enregistre la somme dans cible. | INTEL MPU 8087+
FICOM | Cette instruction permet de comparer le nombre réel source avec le registre mathématique ST(0) et mettre les indicateurs d'état C0 à C3 avec la valeur 1. | INTEL MPU 8087+
FICOMP | Cette instruction compare le nombre réel «source» avec le registre mathématique ST(0), mettre les indicateurs d'état C0 à C3 avec la valeur 1 et dépile le registre mathématique ST(0) de la pile de registres. | INTEL MPU 8087+
FIDIV | Cette instruction offre la possibilité d'effectuer des division de nombre réel. | INTEL MPU 8087+
FIDIVR | Cette instruction offre la possibilité d'effectuer des division de nombre réel avec les registres inversés «cible» par «source». | INTEL MPU 8087+
FILD | Cette instruction permet de charger le nombre entier auprès du registre ST(0). | INTEL MPU 8087+
FIMUL | Cette instruction permet de multiplier le nombre réel «source» par «cible» et sauvegarde le résultat dans «cible». | INTEL MPU 8087+
FINCSTP | Cette instruction permet d'incrémenter le pointeur de pile de registres. | INTEL MPU 8087+
FINIT | Cette instruction permet d'effectuer l'initialisation du coprocesseur mathématique. | INTEL MPU 8087+
FIST | Cette instruction permet de sauvegarder le nombre du registre ST(0) dans «cible». | INTEL MPU 8087+
FISTP | Cette instruction permet de sauvegarder le nombre du registre ST(0) dans «cible» et prendre le registre ST(0) de la pile du registres. | INTEL MPU 8087+
FISTTP | Cette instruction permet de convertir la valeur contenu dans le registre ST dans un entier en utilisant on tronquage, de type chop, lequel est un mode d'arrondissement, et transfert le résultat dans la destination et ensuite effectuer un désempilage de ST. | SSE3+
FISUB | Cette instruction offre l'essentielle possibilité de soustraire le nombre «source» du registre ST(0). | INTEL MPU 8087+
FISUBR | Cette instruction offre l'essentielle possibilité de soustraire le nombre du registre ST(0) de «source». | INTEL MPU 8087+
FLD | Cette instruction permet de charger le nombre réel du registre ST(0) dans la pile. | INTEL MPU 8087+
FLD1 | Cette instruction permet de charger la constante 1,0 du registre ST(0) dans la pile. | INTEL MPU 8087+
FLDCW | Cette instruction permet de charger le «mot de contrôle» avec «source». | INTEL MPU 8087+
FLDENV | Cette instruction permet de charger l'environnement à partir de «source». | INTEL MPU 8087+
FLDL2E | Cette instruction permet de mettre le résultat du logarithme de «e» de la base 2 dans ST(0). | INTEL MPU 8087+
FLDL2T | Cette instruction permet de mettre le résultat du logarithme de 10 de la base 2 dans ST(0). | INTEL MPU 8087+
FLDLG2 | Cette instruction permet de mettre le résultat du logarithme de 2 de la base 10 dans ST(0). | INTEL MPU 8087+
FLDLN2 | Cette instruction permet de mettre le résultat du logarithme de «e» de la base 10 dans ST(0). | INTEL MPU 8087+
FLDPI | Cette instruction permet de mettre le résultat de la constante PI (Π) dans le registre ST(0). | INTEL MPU 8087+
FLDZ | Cette instruction permet de mettre le résultat de la constante 0,0 dans le registre ST(0). | INTEL MPU 8087+
FMUL | Cette instruction permet de multiplier le nombre réel de valeur positive «source» par «cible» et sauvegarde le résultat dans «cible». | INTEL MPU 8087+
FMULP | Cette instruction permet de multiplier le nombre réel de valeur positive «source» par «cible» et sauvegarde le résultat dans «cible» et prend ensuite ST(0) dans la pile de registres. | INTEL MPU 8087+
FNCLEX | Cette instruction permet d'éliminer et de gérer les exceptions non masquées. | INTEL MPU 8087+
FNDISI | Cette instruction permet de désactiver les interruptions et de gérer les exceptions non masquées. | INTEL MPU 8087
FNENI | Cette instruction permet d'activer les interruptions et de gérer les exceptions non masquées. | INTEL MPU 8087
FNINIT | Cette instruction permet d'initialiser le coprocesseur mathématique et de gérer les exceptions non masquées. | INTEL MPU 8087+
FNOP | Cette instruction permet de ne rien faire et de simplement passer à l'instruction suivante. | INTEL MPU 8087+
FNSAVE | Cette instruction permet de sauvegarder l'état courant du coprocesseur mathématique dans l'emplacement mémoire à partir de «source» et gérer les exceptions numériques non masquées. | INTEL MPU 8087+
FNSTCW | Cette instruction permet de sauvegarder le «mot de contrôle» dans «cible» et gérer les exceptions numériques non masquées. | INTEL MPU 8087+
FNSTENV | Cette instruction permet de copier l'environnement du coprocesseur mathématique vers une cible mais sans toutefois attendre que l'exception de nombre réel (virgule flottante) soit effacé. | INTEL MPU 8087+
FNSTSW | Cette instruction permet de copier le mot d'état du coprocesseur mathématique vers une cible mais sans toutefois attendre que l'exception de nombre réel (virgule flottante) soit effacé. | INTEL MPU 8087+
FPATAN | Cette instruction permet de calculer le résultat de l'arc tangente de ST(1) par ST(0) et de mettre le résultat dans le registre ST(0). | INTEL MPU 8087+
FPREM | Cette instruction permet de diviser le registre ST(0) par le registre ST(1) et enregistre le reste dans registre ST(0). | INTEL MPU 8087+
FPREM1 | Cette instruction permet de diviser le registre ST(0) par le registre ST(1) et enregistre le reste IEEE dans registre ST(0). | INTEL MPU 80387+
FPTAN | Cette instruction permet d'effectuer le calcule de la fonction trigonométrique de la tangente du registre ST(0) et enregistre son résultat dans le registre ST(0). | INTEL MPU 8087+
FRICHOP | Cette instruction permet d'effectuer le calcul de l'arrondissement de ST avec 0 décimal selon la méthode CHOP. | Cyrix 486 avec FPU
FRINEAR | Cette instruction permet d'effectuer le calcul de l'arrondissement de ST avec 0 décimal selon la méthode du plus proche. | Cyrix 486 avec FPU
FRINT2 | Cette instruction permet d'effectuer le calcul de l'arrondissement de ST avec 0 décimal selon la méthode du plus proche et si le nombre est exactement la moitié, alors l'instruction arrondit au signe de l'infini. | Cyrix 486 avec FPU
FRNDINT | Cette instruction permet d'arrondir le registre ST(0) à l'entier le plus proche et enregistre son résultat dans le registre ST(0). | INTEL MPU 8087+
FRSTOR | Cette instruction permet de restituer l'état du coprocesseur précédemment sauvegardé dans l'emplacement mémoire spécifié par source. | INTEL MPU 8087+
FSAVE | Cette instruction permet de sauvegarder l'état courant du coprocesseur dans l'emplacement mémoire spécifié par source. | INTEL MPU 8087+
FSCALE | Cette instruction permet d'effectuer la multiplication du registre ST(0) par 2 puissance le registre ST(1) et sauvegarde le résultat dans le registre ST(0). | INTEL MPU 8087+
FSETPM | Cette instruction permet de faire passer le coprocesseur mathématique en mode protégé. | INTEL MPU 80287
FSIN | Cette instruction permet d'effectuer le calcule de la fonction trigonométrique du sinus du registre ST(0) et le copie dans le registre ST(1), le registre ST(0) prend la valeur 1,0. | INTEL MPU 80387+
FSINCOS | Cette instruction permet d'effectuer le calcule de la fonction trigonométrique du sinus et du cosinus du registre ST(0) puis copie le résultat du sinus dans le registre ST(0) et le cosinus dans le registre ST(1). | INTEL MPU 80387+
FSQRT | Cette instruction permet d'extraire la racine carrée du registre ST(0) et de copier son résultat dans le registre ST(0). | INTEL MPU 8087+
FST | Cette instruction permet de copier la valeur réel contenu le registre ST(0) vers une cible. | INTEL MPU 8087+
FSTCW | Cette instruction permet de copier le mot de contrôle CW vers une cible. | INTEL MPU 8087+
FSTENV | Cette instruction permet de copier l'environnement du coprocesseur mathématique vers une cible. | INTEL MPU 8087+
FSTP | Cette instruction permet de copier un nombre entier et prendre le contenu du registre ST(0) dans la pile de registres (dépilage). | INTEL MPU 8087+
FSTSW | Cette instruction permet de copier le mot d'état du coprocesseur mathématique vers une cible. | INTEL MPU 8087+
FSUB | Cette instruction permet de soustraire un nombre entier du registre ST(0). | INTEL MPU 8087+
FSUBP | Cette instruction permet de soustraire un nombre entier du registre ST(0) et copie le registre ST(0) dans la pile de registres. | INTEL MPU 8087+
FSUBPP | Cette instruction permet de soustraire un nombre entier du registre ST(0) et copie le registre ST(0) dans la pile de registres. Cette instruction est déconseillée. | INTEL MPU 8087+
FSUBR | Cette instruction permet de soustraire le registre ST(0) du nombre entier et place le résultat dans le registre ST(0). | INTEL MPU 8087+
FSUBRP | Cette instruction permet de soustraire le registre ST(0) du nombre entier et place le résultat dans le registre ST(0) et copie le registre ST(0) dans la pile de registres. | INTEL MPU 8087+
FTST | Cette instruction permet de comparer le sommet de la pile avec la valeur 0,0 et définit les indicateurs d'états C0 et C3 de façon approprié. | INTEL MPU 8087+
FUCOM | Cette instruction compare le registre ST0 avec un opérande et fixe les drapeaux de façon approprié. | INTEL MPU 80387+
FUCOMI | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et vérifie l'ordre des valeurs et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats. | INTEL Pentium III+
FUCOMIP | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et vérifie l'ordre des valeurs et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats et désempile de la pile la valeur dans le registre. | INTEL Pentium III+
FUCOMP | Cette instruction compare le registre ST0 avec un opérande et fixe les drapeaux de façon approprié et désempile la pile. | INTEL MPU 80387+
FUCOMPP | Cette instruction compare le registre ST0 avec le registre ST1 et fixe les drapeaux de façon approprié et désempile les registres ST0 et ST1 de la pile. | INTEL MPU 80387+
FWAIT | Cette instruction permet d'attendre la fin de l'exécution d'une commande avant de poursuivre. | INTEL MPU 8087+
FXAM | Cette instruction permet d'examiner le sommet de la pile et définit les indicateurs d'état C0 et C3 de façon approprié. | INTEL MPU 8087+
FXCH | Cette instruction permet d'échanger le contenu d'une expression avec celle du registre ST(0) s'il est omis. | INTEL MPU 8087+
FXRSTOR | Cette instruction permet de restituer rapidement 94 (en mode 16 bits) ou 108 (en mode 32 bits) octets d'un contexte de coprocesseur mathématique vers la mémoire. | INTEL MMX-2+
FXSAVE | Cette instruction permet de sauvegarder rapidement 94 (en mode 16 bits) ou 108 (en mode 32 bits) octets d'un contexte de coprocesseur mathématique de la mémoire. | INTEL MMX-2+
FXTRACT | Cette instruction permet de copier l'exposant du registre ST(0) dans le registre ST(1) comme nombre entier puis copie la mantisse dans la registre ST(0) comme nombre entier. | INTEL MPU 8087+
FYL2X | Cette instruction permet de calculer la multiplication du registre ST(1) par le logarithme du registre ST(0) dans la base 2 et copie le résultat dans le registre ST(0). | INTEL MPU 8087+
FYL2XP1 | Cette instruction permet de calculer la multiplication du registre ST(1) par le logarithme du registre ST(0) plus 1 dans la base 2 et copie le résultat dans le registre ST(0). | INTEL MPU 8087+
HADDPD | Cette instruction permet d'effectuer l'addition horizontal de paquet de nombre réel de double précision des deux opérandes. | INTEL Pentium 4 (SSE3)+
HADDPS | Cette instruction permet d'effectuer l'addition horizontal de paquet de nombre réel de simple précision des deux opérandes. | INTEL Pentium 4 (SSE3)+
HLT | Cette instruction permet de faire passer le microprocesseur en mode d'arrêt. Toutefois, le processeur peut quitter cet état lorsqu'une ligne matérielle RESET ou lorsqu'une interruption non-masquable (NMI) reçoit un signal. | INTEL 8088+
HSUBPD | Cette instruction permet d'effectuer la soustraction horizontal de paquet de nombre réel de double précision des deux opérandes. | INTEL Pentium 4 (SSE3)+
HSUBPS | Cette instruction permet d'effectuer la soustraction horizontal de paquet de nombre réel de simple précision des deux opérandes. | INTEL Pentium 4 (SSE3)+
IBTS | Cette instruction permet de faire un tableau de bits du deuxième opérande et le met dans le premier. | INTEL 80386+
ICEBP | Cette instruction permet de passer en mode d'instruction ICE (In-Circuit Emulator) si le bit 12 du registre DR7 vaut 1 sinon il exécute l'interruption 1. | INTEL 80386 au Pentium Pro
IDIV | Cette instruction permet d'effectuer une division signée (nombre entier). | INTEL 8086+
IMUL | Cette instruction permet d'effectuer une multiplication signée (nombre entier). | INTEL 8086+
IN | Cette instruction permet de demander un octet, un mot ou un double mot provenant du port d'entrée/sortie et le retourne dans le registre accumulateur (AL, AX, EAX). | INTEL 8086+
INC | Cette instruction permet d'incrémenter un registre ou un emplacement mémoire. | INTEL 8086+
INS | Cette instruction permet de demander un octet, un mot ou un double mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | INTEL 8086+
INSB | Cette instruction permet de demander un octet du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction. | INTEL 80286+
INSD | Cette instruction permet de demander un double mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
INSERTPS | Cette instruction permet d'insérer une valeur réel de simple précision d'un opérande source dans l'emplacement d'un registre d'opérande de destination et met des 0 dans les données en dehors du masque de destination. | SSE4.1+
INSW | Cette instruction permet de demander un mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction. | INTEL 80286+
INT | Cette instruction permet d'exécuter l'interruption avec le numéro spécifié. | INTEL 8086+
INTO | Cette instruction permet d'exécuter l'interruption numéro 4 si le drapeau de débordement (OF) est fixé sur 1 | INTEL 8086+
INVD | Cette instruction permet de désactiver et de vider le tampon interne du micro-processeur. | INTEL 80486+
INVEPT | Cette instruction permet d'invalider la cartographie dans translation des tampons (TLB) et des caches de pagination structuré dérivé des tables de pages étendue (EPT). | INTEL VMX (Virtualisation)
INVLPG | Cette instruction permet d'invalider les transferts du TLB (Translation Lookaside Buffer) du micro-processeur | INTEL 80486+
INVLPGA | Cette instruction permet d'invalider la cartographie TLB (Translation Lookaside Buffer) pour une page virtuel et un ASID spécifié. | x86-64+
INVVPID | Cette instruction permet d'invalider la cartographie dans translation des tampons (TLB) et des caches de pagination structuré basé sur l'identificateur de processeur virtuel (VPID). | INTEL VMX (Virtualisation)
IRET | Cette instruction permet d'effectuer un retour précédemment provoquer par une interruption. | INTEL 8086+
IRETD | Cette instruction permet d'effectuer un retour 32-bits précédemment provoquer par une interruption. | INTEL 80386+
IRETQ | Cette instruction permet d'effectuer un retour 64-bits précédemment provoquer par une interruption. | x86-64+
JA | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si supérieur. | INTEL 8086+
JAE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si supérieur ou égal. | INTEL 8086+
JB | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si inférieur. | INTEL 8086+
JBE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si inférieur ou égal. | INTEL 8086+
JC | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si l'indicateur de retenue est égal à 1. | INTEL 8086+
JCXZ | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si CX = 0. | INTEL 8086+
JE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si zéro (égal). | INTEL 8086+
JECXZ | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si ECX = 0. | INTEL 80386+
JG | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si supérieur. | INTEL 8086+
JGE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si supérieur ou égal. | INTEL 8086+
JL | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si inférieur. | INTEL 8086+
JLE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si inférieur ou égal. | INTEL 8086+
JMP | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | INTEL 8086+
JNA | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas supérieur. | INTEL 8086+
JNAE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si ni supérieur ni égal. | INTEL 8086+
JNB | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas inférieur. | INTEL 8086+
JNC | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si indicateur de retenue égal à 0. | INTEL 8086+
JNE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas égal (zéro). | INTEL 8086+
JNG | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas supérieur. | INTEL 8086+
JNGE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si ni supérieur ni égal. | INTEL 8086+
JNL | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas inférieur. | INTEL 8086+
JNLE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si ni inférieur ni égal. | INTEL 8086+
JNO | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas de débordement (indicateur de débordement égal à 0). | INTEL 8086+
JNP | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas de parité. | INTEL 8086+
JNS | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas de signe. | INTEL 8086+
JNZ | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas zéro. | INTEL 8086+
JO | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si débordement (indicateur de débordement égal à 1). | INTEL 8086+
JP | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si parité. | INTEL 8086+
JPE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si parité paire. | INTEL 8086+
JPO | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si parité impaire. | INTEL 8086+
JRCXZ | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si RCX = 0. | x86-64+
JS | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si signe. | INTEL 8086+
JZ | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si zéro. | INTEL 8086+
LAHF | Cette instruction permet de transférer les bits d'indicateurs du registre d'état vers le registre AH. | INTEL 8086+
LAR | Cette instruction permet de charger le registre des indicateurs d'un descripteur. | INTEL 80286+
LDDQU | Cette instruction permet de copier un quadruple mot d'une opérande source vers une opérande destination. | INTEL Pentium 4 (SSE3)+
LDMXCSR | Cette instruction permet d'effectuer le chargement du mot de contrôle et d'état du flux d'extension SIMD d'une opérande mémoire 32 bits. | INTEL Pentium III (KNI/MMX2)+
LDS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment DS et dans un registre d'offset spécifié. | INTEL 8086+
LEA | Cette instruction permet de copier l'offset d'une adresse de mémoire contenu dans un registre spécifié. | INTEL 8086+
LEAVE | Cette instruction permet de libérer une zone de mémoire attribué par l'instruction «ENTER» lorsqu'on utilise des procédures dans des langages de programmation de haut niveau. | INTEL 80286+
LES | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment ES et dans un registre d'offset spécifié. | INTEL 8086+
LFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant le LFENCE et les instructions de chargement suivant le LFENCE. | INTEL Pentium 4 (SSE2)+
LFS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment FS et dans un registre d'offset spécifié. | INTEL 80386+
LGDT | Cette instruction permet de charger un descripteur de tables globale. | INTEL 80286+
LGS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment GS et dans un registre d'offset spécifié. | INTEL 80386+
LIDT | Cette instruction permet de charger un descripteur de tables d'interruption. | INTEL 80286+
LLDT | Cette instruction permet de charger un descripteur de tables local. | INTEL 80286+
LMSW | Cette instruction permet de copier 4 des bits d'une opérande vers les 4 bits de registre de contrôle CR0. | INTEL 80286+
LOADALL | Cette instruction permet d'effectuer le chargement de tous les registres de descripteur de cache. | INTEL 80286 ou 80386
LOCK | Cette instruction est utilisé comme préfixe avec d'autres instructions pour amener le microprocesseur à émettre un signal de verrouillage (Lock) sur le bus lors du traitement de l'instruction suivante. | INTEL 8086+
LODS | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction. | INTEL 8086+
LODSB | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 1 en fonction de l'état du drapeau de direction. | INTEL 8086+
LODSD | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
LODSQ | Cette instruction permet de copier un élément de l'adresse DS:(R)SI dans le registre accumulateur et incrémente/décrémente le registre (R)SI de 8 en fonction de l'état du drapeau de direction. | x86-64+
LODSW | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 2 en fonction de l'état du drapeau de direction. | INTEL 8086+
LOOP | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0. | INTEL 8086+
LOOPD | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0. | INTEL 80386+
LOOPE | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1. | INTEL 8086+
LOOPED | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0 et si le drapeau ZF vaut 1. | INTEL 80386+
LOOPNE | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0. | INTEL 8086+
LOOPNED | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0 et si le drapeau ZF vaut 0. | INTEL 80386+
LOOPNZ | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0. | INTEL 8086+
LOOPNZD | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0 et si le drapeau ZF vaut 0. | INTEL 80386+
LOOPZ | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1. | INTEL 8086+
LOOPZD | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0 et si le drapeau ZF vaut 1. | INTEL 80386+
LSL | Cette instruction permet de charger la limite de segment d'un descripteur de segment spécifié avec l'opérande source dans l'opérande de destination et fixe le drapeau ZF du registre EFLAGS. | INTEL 80286+
LSS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment SS (Segment de pile) et dans un registre d'offset spécifié. | INTEL 80386+
LTR | Cette instruction permet de charger l'opérande source dans le champ du sélecteur de segment du registre de tâche. | INTEL 80286+
LZCNT | Cette instruction permet de compter le nombre de bits à 0 dans un registre 16, 32 ou 64 bits contenu dans l'opérande source. | AMD K10 (SSE4a)+
MASKMOVDQU | Cette instruction permet d'entreposer les octets sélectionnés par l'opérande source dans une emplacement mémoire de 128 bits. | INTEL Pentium 4 (SSE2)+
MASKMOVQ | Cette instruction permet d'entreposer les octets sélectionner de l'opérande source dans un emplacement mémoire de 64 bits. | Pentium III (KNI/MMX2)+
MAXPD | Cette instruction permet de retourner la valeur maximal de chacune des paires de valeur entre l'opérande source et l'opérande de destination de nombre réel de double précision. | INTEL Pentium 4 (SSE2)+
MAXPS | Cette instruction permet de retourner la valeur maximal de chacune des paires de valeur entre l'opérande source et l'opérande de destination. | Pentium III (KNI/MMX2)+
MAXSD | Cette instruction permet de retourner la valeur maximal entre l'opérande source et destination de nombre réel de simple précision. | INTEL Pentium 4 (SSE2)+
MAXSS | Cette instruction permet de retourner la valeur maximal entre l'opérande source et destination. | Pentium III (KNI/MMX2)+
MFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant le MFENCE et les instructions de chargement et d'entreposage précédent le MFENCE. | INTEL Pentium 4 (SSE2)+
MINPD | Cette instruction permet de retourner la valeur minimal de chacune des paires de valeur entre l'opérande source et l'opérande de destination de nombre réel de double précision. | INTEL Pentium 4 (SSE2)+
MINPS | Cette instruction permet de retourner la valeur minimal de chacune des paires de valeur entre l'opérande source et l'opérande de destination. | Pentium III (KNI/MMX2)+
MINSD | Cette instruction permet de retourner la valeur minimal entre l'opérande source et destination de nombre réel de simple précision. | INTEL Pentium 4 (SSE2)+
MINSS | Cette instruction permet de retourner la valeur minimal entre l'opérande source et destination. | Pentium III (KNI/MMX2)+
MONITOR | Cette instruction permet d'indiquer au microprocesseur quel rangé d'adresse est à surveiller par l'instruction STORE. | INTEL Pentium 4+
MOV | Cette instruction permet de copier opérande source dans une opérande destinataire. | INTEL 8086+
MOVAPD | Cette instruction permet de copier le contenu de 2 paquets alignés de valeurs réel de double précision. | INTEL Pentium 4 (SSE2)+
MOVAPS | Cette instruction permet de copier le contenu de 4 paquets alignés de valeurs réel de simple précision (4 x 32 bits). | Pentium III (KNI/MMX2)+
MOVBE | Cette instruction permet d'effectuer l'échange des octets lors de l'opération de copiage de l'opérande source dans l'opérande de destination. | SSE4.2+
MOVD | Cette instruction permet de copier l'opérande dans un registre XMM ou vice-versa. | INTEL Pentium MMX+
MOVDDUP | Cette instruction permet de copier les 64 bits d'une opérande dans la partie basse et haute d'une opérande de 128 bits. | INTEL Pentium 4 (SSE3)+
MOVDQ2Q | Cette instruction permet de copier la partie basse d'un quadruple mots d'un opérande source vers un opérande de destination. | INTEL Pentium 4 (SSE2)+
MOVDQA | Cette instruction permet de copier un double quadruple mots d'un opérande source vers un opérande de destination. | INTEL Pentium 4 (SSE2)+
MOVDQU | Cette instruction permet de copier un double quadruple mots désaligné d'un opérande source vers un opérande de destination. | INTEL Pentium 4 (SSE2)+
MOVHLPS | Cette instruction permet de copier le contenu du haut d'un paquet de valeurs réel de simple précision dans sa partie basse. | Pentium III (KNI/MMX2)+
MOVHPD | Cette instruction permet de copier le contenu du haut de deux paquets de valeurs réel de double précision dans une opérande de destination. | INTEL Pentium 4 (SSE2)+
MOVHPS | Cette instruction permet de copier le contenu du haut de deux paquets de valeurs réel de simple précision dans une opérande de destination. | Pentium III (KNI/MMX2)+
MOVLHPS | Cette instruction permet de copier le contenu du bas d'un paquet de valeurs réel de simple précision dans sa partie haute. | Pentium III (KNI/MMX2)+
MOVLPD | Cette instruction permet de copier le contenu du bas de deux paquets de valeurs réel de double précision dans un opérande de destination. | INTEL Pentium 4 (SSE2)+
MOVLPS | Cette instruction permet de copier le contenu du bas de deux paquets de valeurs réel de simple précision dans un opérande de destination. | Pentium III (KNI/MMX2)+
MOVMSKPD | Cette instruction permet de copier les bits de signes de deux paquets de valeurs réels de double précision d'un registre XMM dans les 2 bits les plus bas d'un registre 32 bits. Les autres bits du registres 32 bits sont fixés à 0. | INTEL Pentium 4 (SSE2)+
MOVMSKPS | Cette instruction permet de copier les bits de signes de quatre paquets de valeurs réels de simple précision d'un registre XMM dans les 4 bits les plus bas d'un registre 32 bits. Les autres bits du registres 32 bits sont fixés à 0. | INTEL Pentium 3 (SSE)+
MOVNTI | Cette instruction permet de copier une valeur 32 ou 64 bits dans un emplacement mémoire afin de minimiser la pollution du cache dans un processus léger. | INTEL Pentium 4 (SSE2)+
MOVNTDQ | Cette instruction permet de copier le contenu de double quadruple mots d'un opérande source vers un opérande de destination sans utiliser la méthode temporel pour minimiser la pollution du cache. | SSE4.1+
MOVNTDQA | Cette instruction permet de copier le contenu aligné de double quadruple mots d'un opérande source vers un opérande de destination sans utiliser la méthode temporel pour minimiser la pollution du cache. | SSE4.1+
MOVNTPD | Cette instruction permet de copier le contenu de valeur réel de double précision d'un opérande source vers un opérande de destination sans utiliser la méthode temporel pour minimiser la pollution du cache. | INTEL Pentium 4 (SSE2)+
MOVNTPS | Cette instruction permet de copier le contenu de 4 paquets alignés de valeurs réel de simple précision sans utiliser la méthode temporel pour minimiser la pollution du cache. | Pentium III (KNI/MMX2)+
MOVNTQ | Cette instruction permet de copier une valeur 64 bits sans utiliser la méthode temporel pour minimiser la pollution du cache. | Pentium III (KNI/MMX2)+
MOVQ | Cette instruction permet de copier un quadruple mot d'une opérande source vers une opérande destination dans le cas des registres XMM. | INTEL Pentium MMX+
MOVQ2DQ | Cette instruction permet de copier un quadruple mot d'un opérande source vers la partie basse d'un opérande destination dans le cas des registres XMM. | INTEL Pentium 4 (SSE2)+
MOVS | Cette instruction permet de copier un élément de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction. | INTEL 8086+
MOVSB | Cette instruction permet de copier un octet de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 1 en fonction de l'état du drapeau de direction. | INTEL 8086+
MOVSD | Cette instruction permet de copier un double mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
MOVSD | Cette instruction permet de copier un scalaire de valeur de double précision d'un opérande source vers un opérande destination. | INTEL Pentium 4 (SSE2)+
MOVSHDUP | Cette instruction permet de copier la partie du haut de 32 bits d'une valeur 64 bits dans sa partie basse et haute d'une valeur réel de simple précision de 64 bits contenu dans un paquet de 128 bits. | INTEL Pentium 4 (SSE3)+
MOVSLDUP | Cette instruction permet de copier la partie du basse de 32 bits d'une valeur 64 bits dans sa partie basse et haute d'une valeur réel de simple précision de 64 bits contenu dans un paquet de 128 bits. | INTEL Pentium 4 (SSE3)+
MOVSQ | Cette instruction permet de copier un quadruple mot de l'adresse DS:(R)SI dans l'adresse ES:(R)DI et incrémente/décrémente les registres (R)DI et (R)SI de 8 en fonction de l'état du drapeau de direction. | x86-64+
MOVSS | Cette instruction permet de copier une valeur réel de simple précision d'une opérande source vers une opérande de destination. | Pentium III (KNI/MMX2)+
MOVSW | Cette instruction permet de copier un mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 2 en fonction de l'état du drapeau de direction. | INTEL 8086+
MOVSX | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires avec l'extension des signes. | INTEL 80386+
MOVSXD | Cette instruction permet de copier un registre de taille inférieur dans un registre 64 bits en remplissant les bits supplémentaires avec l'extension des signes. | x86-64+
MOVUPD | Cette instruction permet de copier le contenu de 2 paquets désalignés de valeurs réel de double précision. | Intel Pentium 4 (SSE2)+
MOVUPS | Cette instruction permet de copier le contenu de 4 paquets désalignés de valeurs réel de simple précision (4 x 32 bits). | Pentium III (KNI/MMX2)+
MOVZX | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires par des 0. | INTEL 80386+
MPSADBW | Cette instruction permet d'effectuer le calcul de la somme de la différence absolue (SAD) d'une paire d'octets d'un groupe de 4 octets paires et produit 8 résultats SAD entreposé dans 8 entier contenu dans l'opérande de destination. | SSE4.1+
MUL | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). | INTEL 8086+
MULPD | Cette instruction permet d'effectuer la multiplication de chacune des paires de valeur de double précision de l'opérande source et l'opérande de destination. | Intel Pentium 4 (SSE2)+
MULPS | Cette instruction permet d'effectuer la multiplication de chacune des paires de valeur de l'opérande source et l'opérande de destination. | Pentium III (KNI/MMX2)+
MULSD | Cette instruction permet d'effectuer la multiplication scalaire de valeurs réel de double précision de l'opérande source et l'opérande de destination. | Intel Pentium 4 (SSE2)+
MULSS | Cette instruction permet d'effectuer la multiplication scalaire de l'opérande source et l'opérande de destination. | Pentium III (KNI/MMX2)+
MWAIT | Cette instruction permet d'indiquer au microprocesseur que l'état de l'alimentation de la ligne de cache est en attente d'écriture dans la plage d'adresse, mettant fin à la plupart des activités dans le noyau en le faisant. | INTEL Pentium 4+
NEG | Cette instruction permet d'effectuer le complément à 2 d'une opérande. | INTEL 8086+
NOP | Cette instruction ne fait rien. | INTEL 8086+
NOT | Cette instruction permet d'inverser la valeur de chacun des bits d'une opérande. | INTEL 8086+
OIO | Cette instruction permet de provoquer l'exécution d'un code indéfinie. | Cyrix Cx6x86/AMD Am5k86
OR | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandes spécifiés. | INTEL 8086+
ORPD | Cette instruction permet d'effectuer un OU BINAIRE de 128 bits sur les 2 opérandes réels de double précisions spécifiés. | Intel Pentium 4 (SSE2)+
ORPS | Cette instruction permet d'effectuer un OU BINAIRE de 128 bits sur les 2 opérandes spécifiés. | Pentium III (KNI/MMX2)+
OUT | Cette instruction permet d'envoyer un octet, un mot ou un double mot sur le port d'entrée/sortie. | INTEL 8086+
OUTS | Cette instruction permet d'envoyer un octet, un mot ou un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | INTEL 80286+
OUTSB | Cette instruction permet d'envoyer un octet contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 1 en fonction de l'état du drapeau de direction. | INTEL 80286+
OUTSD | Cette instruction permet d'envoyer un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
OUTSW | Cette instruction permet d'envoyer un mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 2 en fonction de l'état du drapeau de direction. | INTEL 80286+
PABSB | Cette instruction permet d'effectuer le calcul de la valeur absolue de chacun des octets d'un opérande source et entrepose le résultat dans un opérande destination. | SSSE3+
PABSD | Cette instruction permet d'effectuer le calcul de la valeur absolue de chacun des doubles mots d'un opérande source et entrepose le résultat dans un opérande destination. | SSSE3+
PABSW | Cette instruction permet d'effectuer le calcul de la valeur absolue de chacun des mots d'un opérande source et entrepose le résultat dans un opérande destination. | SSSE3+
PACKSSDW | Cette instruction permet de compacté 8 paquets de double mots en mots. | INTEL Pentium MMX+
PACKSSWB | Cette instruction permet de compacté 8 paquets d'entier en octets. | INTEL Pentium MMX+
PACKUSDW | Cette instruction permet de compacté 8 paquets de double mots naturel en mots naturel. | SSE4.1+
PACKUSWB | Cette instruction permet de compacté 8 paquets de mots en octets. | INTEL Pentium Pro+
PADDB | Cette instruction permet d'effectuer une addition scalaire sur un paquet de 8 octets. | INTEL Pentium Pro+
PADDD | Cette instruction permet d'effectuer une addition scalaire sur un paquet de 2 double mots. | INTEL Pentium Pro+
PADDQ | Cette instruction permet d'effectuer une addition scalaire sur un paquet de quadruple mots. | INTEL Pentium 4 (SSE2)+
PADDSB | Cette instruction permet d'effectuer une addition scalaire avec saturation sur un paquet de 8 octets signés. | INTEL Pentium Pro+
PADDSIW | Cette instruction permet d'effectuer l'addition du mot de format entier de l'opérande source au mot de format entier de l'opérande de destination et écrit le résultat dans le registre MMX. | Cyrix 6x86MX (EMMX)+
PADDSW | Cette instruction permet d'effectuer une addition scalaire avec saturation sur un paquet de 4 entiers. | INTEL Pentium Pro+
PADDUSB | Cette instruction permet d'effectuer une addition scalaire avec saturation sur un paquet de 8 octets. | INTEL Pentium Pro+
PADDUSW | Cette instruction permet d'effectuer une addition scalaire avec saturation sur un paquet de 4 mots. | INTEL Pentium Pro+
PADDW | Cette instruction permet d'effectuer une addition scalaire sur un paquet de 4 mots. | INTEL Pentium Pro+
PALIGNR | Cette instruction permet d'effectuer la concaténation de l'opérande de destination et de l'opérande source et effectue un décalage d'une constante immédiate de la composante de granulité d'octets, et enfin extrait le résultat aligné dans l'opérande de destination. | SSSE3+
PAND | Cette instruction permet d'effectuer un «ET BINAIRE» d'un quadruple mot d'une opérande source avec une opérande destination dans le cas des registres XMM. | INTEL Pentium MMX+
PANDN | Cette instruction permet d'effectuer un «ET BINAIRE» et une «NEGATION» de chacun des bits d'un quadruple mot d'une opérande source avec une opérande destination dans le cas des registres XMM. | INTEL Pentium Pro+
PAUSE | Cette instruction permet d'améliorer les performances des boucles de «SPIN», en fournissant une indication pour le microprocesseur que le code courant est dans une boucle en «SPIN». | INTEL Pentium 4 (SSE2)+
PAVEB | Cette instruction permet d'effectuer le calcul de la moyenne des paquets spécifiés. | Cyrix 6x86MX (EMMX)+
PAVGB | Cette instruction permet d'effectuer le calcul de la moyenne des paquets d'octets spécifiés. | Intel Pentium III (SSE)+
PAVGUSB | Cette instruction permet d'effectuer le calcul de la moyenne de paquets de 8 octets spécifiés. | AMD 3DNow!
PAVGW | Cette instruction permet d'effectuer le calcul de la moyenne des paquets des mots spécifiés. | Intel Pentium III (SSE)+
PBLENDVB | Cette instruction permet d'effectuer une copie conditionnel d'un élément d'octets d'un opérande source vers un opérande de destination en fonction des bits de masque définit dans un troisième opérande. | SSE4.1+
PBLENDW | Cette instruction permet d'effectuer une copie conditionnel d'un élément d'octets d'un opérande source vers un opérande de destination en fonction des bits de masque définit dans un troisième opérande. | SSE4.1+
PCLMULQDQ | Cette instruction permet d'effectuer une multiplication de quadruple mots avec une retenue en sélectionnant l'opérande destination et source et une valeur immédiate pour sélectionner les critères. | INTEL AES+
PCMPEQB | Cette instruction permet d'effectuer une comparaison sur un paquet d'octets et fixe la valeur de chacun d'eux à FFh s'ils sont égales sinon à 00h. | INTEL Pentium Pro+
PCMPEQD | Cette instruction permet d'effectuer une comparaison sur un paquet de double mots et fixe la valeur de chacun d'eux à FFFFFFFFh s'ils sont égales sinon à 00000000h. | INTEL Pentium Pro+
PCMPEQQ | Cette instruction permet d'effectuer une comparaison d'égalité SIMD d'un paquet de quadruple mots de l'opérande destination et de l'opérande source. | SSE4.1+
PCMPEQW | Cette instruction permet d'effectuer une comparaison sur un paquet de mots et fixe la valeur de chacun d'eux à FFFFh s'ils sont égales sinon à 0000h. | INTEL Pentium Pro+
PCMPESTRI | Cette instruction permet d'effectuer une comparaison ainsi qu'un processus de fragments de deux chaine de caractères basé sur une valeur d'encodage indiquer par un opérande immédiate et génère un index entreposé dans le registre ECX. | Nehalem (SSE4.2)+
PCMPESTRM | Cette instruction permet d'effectuer une comparaison ainsi qu'un processus de fragments de deux chaine de caractères basé sur une valeur d'encodage indiquer par un opérande immédiate et génère un masque entreposé dans le registre XMM0. | Nehalem (SSE4.2)+
PCMPGTB | Cette instruction permet d'effectuer une comparaison sur un paquet d'octets et fixe la valeur de chacun d'eux à FFh si l'opérande destinataire est supérieur à l'opérande source sinon à 00h. | INTEL Pentium Pro+
PCMPGTD | Cette instruction permet d'effectuer une comparaison sur un paquet de double mots et fixe la valeur de chacun d'eux à FFFFFFFFFh si l'opérande destinataire est supérieur à l'opérande source sinon à 00000000h. | INTEL Pentium Pro+
PCMPGTQ | Cette instruction permet d'effectuer une comparaison sur un paquet de quadruple mots et fixe la valeur de chacun d'eux à FFFFFFFFFFFFFFFFh si l'opérande destinataire est supérieur à l'opérande source sinon à 0000000000000000h. | Nehalem (SSE4.2)+
PCMPGTW | Cette instruction permet d'effectuer une comparaison sur un paquet de mots et fixe la valeur de chacun d'eux à FFFFFh si l'opérande destinataire est supérieur à l'opérande source sinon à 0000h. | INTEL Pentium Pro+
PCMPISTRI | Cette instruction permet d'effectuer une comparaison ainsi qu'un processus de fragments de deux chaines de caractères basé sur une valeur d'encodage implicite indiquer par un opérande immédiate et génère un index entreposé dans le registre ECX. | Nehalem (SSE4.2)+
PCMPISTRM | Cette instruction permet d'effectuer une comparaison ainsi qu'un processus de fragments de deux chaine de caractères basé sur une valeur d'encodage implicite indiquer par un opérande immédiate et génère un masque entreposé dans le registre XMM0. | Nehalem (SSE4.2)+
PDISTIB | Cette instruction permet d'effectuer le calcul de la distance entre des octets de deux opérandes, le résultat de l'addition d'octet de l'opérande de destination et la saturation du résultat. | Cyrix 6x86MX (EMMX)+
PEXTRB | Cette instruction permet de copier l'octet de l'opérande source spécifié par un compteur d'opérande dans l'opérande de destination. | SSE4.1+
PEXTRD | Cette instruction permet de copier le double mot de l'opérande source spécifié par un compteur d'opérande dans l'opérande de destination. | SSE4.1+
PEXTRQ | Cette instruction permet de copier le quadruple mot de l'opérande source spécifié par un compteur d'opérande dans l'opérande de destination. | SSE4.1+
PEXTRW | Cette instruction permet de copier le mot de l'opérande source spécifié par un compteur d'opérande dans l'opérande de destination. | INTEL Pentium III (KNI/MMX2)+
PF2ID | Cette instruction permet de convertir un double mots d'un format réel à un format d'entier 32 bits. | AMD 3DNow!
PF2IW | Cette instruction permet de convertir un double mots d'un format réel à un format d'entier 16 bits. | AMD 3DNow!
PFACC | Cette instruction permet d'effectuer l'accumulation de double mots. | AMD 3DNow!
PFADD | Cette instruction permet d'effectuer l'addition de double mots. | AMD 3DNow!
PFCMPEQ | Cette instruction permet d'effectuer la comparaison d'égalité d'un paquet de double mots contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFCMPGE | Cette instruction permet d'effectuer la comparaison d'égalité ou de supériorité d'un paquet de double mots contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFCMPGT | Cette instruction permet d'effectuer la comparaison de supériorité d'un paquet de double mots contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFMAX | Cette instruction permet de retourner la valeur maximal de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFMIN | Cette instruction permet de retourner la valeur minimal de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFMUL | Cette instruction permet d'effectuer la multiplication de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFNACC | Cette instruction permet d'effectuer l'accumulation négative de double mots. | AMD 3DNow!
PFPNACC | Cette instruction permet d'effectuer un mixe d'accumulation positive et négative de double mots. | AMD 3DNow!
PFRCP | Cette instruction permet d'effectuer la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFRCPIT1 | Cette instruction permet d'effectuer la première étape d'itération de la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFRCPIT2 | Cette instruction permet d'effectuer la deuxième étape d'itération de la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFRSQIT1 | Cette instruction permet d'effectuer la première étape d'itération de la racine carré de la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFRSQRT | Cette instruction permet d'effectuer la racine carré approximative de la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFSUB | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFSUBR | Cette instruction permet d'effectuer la soustraction inversé de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PHADDD | Cette instruction permet d'effectuer l'addition de double mot entier horizontalement adjacent d'un opérande source et opérande destination et met le résultat dans l'opérande destination. | SSSE3+
PHADDSW | Cette instruction permet d'effectuer l'addition de mot entier horizontalement adjacent avec saturation d'un opérande source et opérande destination et met le résultat dans l'opérande destination. | SSSE3+
PHADDW | Cette instruction permet d'effectuer l'addition de mot entier horizontalement adjacent d'un opérande source et opérande destination et met le résultat dans l'opérande destination. | SSSE3+
PHMINPOSUW | Cette instruction permet de demander le minimum des valeurs de mot de l'opérande source et place dans la partie basse de l'opérande le mot. | SSE4.1+
PHSUBD | Cette instruction permet d'effectuer la soustraction de double mot entier horizontalement adjacent d'un opérande source et opérande destination et met le résultat dans l'opérande destination. | SSSE3+
PHSUBSW | Cette instruction permet d'effectuer la soustraction de mot entier horizontalement adjacent avec saturation d'un opérande source et opérande destination et met le résultat dans l'opérande destination. | SSSE3+
PHSUBW | Cette instruction permet d'effectuer la soustraction de mot entier horizontalement adjacent d'un opérande source et opérande destination et met le résultat dans l'opérande destination. | SSSE3+
PI2FD | Cette instruction permet de convertir un paquet de format d'entier 32 bits à double mots d'un format réel. | AMD 3DNow!
PI2FW | Cette instruction permet de convertir un paquet de format d'entier 16 bits à double mots d'un format réel. | AMD 3DNow!
PINSRB | Cette instruction permet d'effectuer une copie d'un octet d'un opérande source et de l'insérer dans l'opérande de destination de l'emplacement spécifié par un compteur d'opérande. | SSE4.1+
PINSRD | Cette instruction permet d'effectuer une copie d'un double mot d'un opérande source et de l'insérer dans l'opérande de destination de l'emplacement spécifié par un compteur d'opérande. | SSE4.1+
PINSRQ | Cette instruction permet d'effectuer une copie d'un quadruple mot d'un opérande source et de l'insérer dans l'opérande de destination de l'emplacement spécifié par un compteur d'opérande. | SSE4.1+
PINSRW | Cette instruction permet d'effectuer une copie d'un mot d'un opérande source et de l'insérer dans l'opérande de destination de l'emplacement spécifié par un compteur d'opérande. | INTEL Pentium III (KNI/MMX2)+
PMACHRIW | Cette instruction permet d'effectuer une multiplication de 2 opérandes sources en utilisant la méthode décrite par PMULHRW et accumule le résultat avec la valeur dans un registre de destination en utilisant un arrondissement arithmétique. | Cyrix 6x86MX (EMMX)+
PMADDUBSW | Cette instruction permet d'effectuer une multiplication vertical de chacun des octets d'un opérande de destination avec les octets (entier) d'un opérande source et produit des entiers 16 bits intermédiaire. | SSSE3+
PMADDWD | Cette instruction permet d'effectuer une multiplication de 2 registres MMX contenant dans un paquet de mots d'un emplacement/mémoire. | INTEL Pentium Pro+
PMAGW | Cette instruction permet d'effectuer la comparaison de la valeur absolue d'un paquet de mots de l'opérande source et de l'ensemble des mots de destination et fixe l'opérande de destination avec la valeur de la plus large magnétude. | Cyrix 6x86MX (EMMX)+
PMAXSB | Cette instruction permet de retourner la valeur maximal de chacun des octets (entier) des paquets contenu dans deux opérandes. | SSE4.1+
PMAXSD | Cette instruction permet de retourner la valeur maximal de chacun des doubles mots des paquets contenu dans deux opérandes. | SSE4.1+
PMAXSW | Cette instruction permet de retourner la valeur maximal de chacun des mots (entier) des paquets contenu dans deux opérandes. | INTEL Pentium III (KNI/MMX2)+
PMAXUB | Cette instruction permet de retourner la valeur maximal de chacun des octets des paquets contenu dans deux opérandes. | INTEL Pentium III (KNI/MMX2)+
PMAXUD | Cette instruction permet de retourner la valeur maximal de chacun des doubles mots (naturel) des paquets contenu dans deux opérandes. | SSE4.1+
PMAXUW | Cette instruction permet de retourner la valeur maximal de chacun des mots (naturel) des paquets contenu dans deux opérandes. | SSE4.1+
PMINSB | Cette instruction permet de retourner la valeur minimal de chacun des octets (entier) des paquets contenu dans deux opérandes. | SSE4.1+
PMINSD | Cette instruction permet de retourner la valeur minimal de chacun des doubles mots des paquets contenu dans deux opérandes. | SSE4.1+
PMINSW | Cette instruction permet de retourner la valeur minimal de chacun des mots des paquets contenu dans deux opérandes. | INTEL Pentium III (KNI/MMX2)+
PMINUB | Cette instruction permet de retourner la valeur minimal de chacun des octets des paquets contenu dans deux opérandes. | INTEL Pentium III (KNI/MMX2)+
PMINUD | Cette instruction permet de retourner la valeur minimal de chacun des doubles mots (naturel) des paquets contenu dans deux opérandes. | SSE4.1+
PMOVMSKB | Cette instruction permet de copiés les masques de chacun des octets d'un paquet contenu dans une opérande. | INTEL Pentium III (KNI/MMX2)+
PMOVSXBD | Cette instruction permet d'étendre les signes du paquet des entiers de 8 bits de la partie basse de l'opérande source en entiers 32 bits dans l'opérande de destination. | SSE4.1+
PMOVSXBQ | Cette instruction permet d'étendre les signes du paquet des entiers de 8 bits de la partie basse de l'opérande source en entiers 64 bits dans l'opérande de destination. | SSE4.1+
PMOVSXBW | Cette instruction permet d'étendre les signes du paquet des entiers de 8 bits de la partie basse de l'opérande source en entiers 16 bits dans l'opérande de destination. | SSE4.1+
PMOVSXDQ | Cette instruction permet d'étendre les signes du paquet des entiers de 32 bits de la partie basse de l'opérande source en entiers 64 bits dans l'opérande de destination. | SSE4.1+
PMOVSXWD | Cette instruction permet d'étendre les signes du paquet des entiers de 16 bits de la partie basse de l'opérande source en entiers 32 bits dans l'opérande de destination. | SSE4.1+
PMOVSXWQ | Cette instruction permet d'étendre les signes du paquet des entiers de 16 bits de la partie basse de l'opérande source en entiers 64 bits dans l'opérande de destination. | SSE4.1+
PMOVZXBD | Cette instruction permet d'étendre les zéros du paquet des entiers de 8 bits de la partie basse de l'opérande source en entiers 32 bits dans l'opérande de destination. | SSE4.1+
PMOVZXBQ | Cette instruction permet d'étendre les zéros du paquet des entiers de 8 bits de la partie basse de l'opérande source en entiers 64 bits dans l'opérande de destination. | SSE4.1+
PMOVZXBW | Cette instruction permet d'étendre les zéros du paquet des entiers de 8 bits de la partie basse de l'opérande source en entiers 16 bits dans l'opérande de destination. | SSE4.1+
PMOVZXDQ | Cette instruction permet d'étendre les zéros du paquet des entiers de 32 bits de la partie basse de l'opérande source en entiers 64 bits dans l'opérande de destination. | SSE4.1+
PMOVZXWD | Cette instruction permet d'étendre les zéros du paquet des entiers de 16 bits de la partie basse de l'opérande source en entiers 32 bits dans l'opérande de destination. | SSE4.1+
PMOVZXWQ | Cette instruction permet d'étendre les zéros du paquet des entiers de 16 bits de la partie basse de l'opérande source en entiers 64 bits dans l'opérande de destination. | SSE4.1+
PMULDQ | Cette instruction permet d'effectuer la multiplication de deux valeurs signés de deux paires de double mots entier et entrepose les résultats dans un opérande en paquet de 64 bits. | SSE4.1+
PMULHRIW | Cette instruction permet de retourner le résultat d'une matrice de 16x16 bits avec un arrondissement LSB avant de tronquer les 16 bits et place ce résultat dans un registre MMX. | Cyrix 6x86MX (EMMX)+
PMULHRSW | Cette instruction permet d'effectuer multiplication vertical de chaque entier de 16 bits de l'opérande de destination avec l'opérande source et produit un résultat d'entiers de 32 bits dans l'opérande de destination. | SSSE3+
PMULHRW | Cette instruction permet de retourner le résultat d'une matrice de 16x16 bits avec un arrondissement LSB avant de tronquer les 16 bits. | Cyrix 6x86MX (EMMX)+
PMULHUW | Cette instruction permet d'effectuer la multiplication de la partie haute de chacun des entiers des 2 paquets d'opérandes. | INTEL Pentium III (KNI/MMX2)+
PMULHW | Cette instruction permet d'effectuer la multiplication de la partie haute de chacun des mots des 2 paquets d'opérandes. | INTEL Pentium Pro+
PMULLD | Cette instruction permet d'effectuer la multiplication de la partie basse de chacun des double mots des 2 paquets d'opérandes. | SSE4.1+
PMULLW | Cette instruction permet d'effectuer la multiplication de la partie basse de chacun des mots des 2 paquets d'opérandes. | INTEL Pentium Pro+
PMULUDQ | Cette instruction permet d'effectuer la multiplication de paquets d'opérandes de double mots. | INTEL Pentium 4 (SSE2)+
PMVGEZB | Cette instruction permet de copier l'octet de paquet correspondant de l'opérande source dans l'opérande de destination si l'octet de l'opérande destination est supérieur à 0 et effectue se traitement pour chacun des 8 octets du paquet. | Cyrix 6x86MX (EMMX)+
PMVLZB | Cette instruction permet de copier l'octet de paquet correspondant de l'opérande source dans l'opérande de destination si l'octet de l'opérande destination est inférieur à 0 et effectue se traitement pour chacun des 8 octets du paquet. | Cyrix 6x86MX (EMMX)+
PMVNZB | Cette instruction permet de copier l'octet de paquet correspondant de l'opérande source dans l'opérande de destination si l'octet de l'opérande destination ne vaut pas 0 et effectue se traitement pour chacun des 8 octets du paquet. | Cyrix 6x86MX (EMMX)+
PMVZB | Cette instruction permet de copier l'octet de paquet correspondant de l'opérande source dans l'opérande de destination si l'octet de l'opérande destination vaut 0 et effectue se traitement pour chacun des 8 octets du paquet. | Cyrix 6x86MX (EMMX)+
POP | Cette instruction permet de désempiler de la pile un mot ou un double mot et la met dans une opérande. | INTEL 8086+
POPA | Cette instruction permet de désempiler de la pile respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX. | INTEL 80286+
POPAD | Cette instruction permet de désempiler de la pile respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX. | INTEL 80386+
POPCNT | Cette instruction permet de compter le nombre de bits à 1 que possède une opérande source et place le résultat dans un registre destinataire. | AMD K10 (SSE4a)+
POPF | Cette instruction permet de désempiler de la pile le registre 16 bits de drapeau contenant les indicateurs d'état. | INTEL 8086+
POPFD | Cette instruction permet de désempiler de la pile le registre 32 bits de drapeau contenant les indicateurs d'état. | INTEL 80386+
POPFQ | Cette instruction permet de désempiler de la pile le registre 64 bits de drapeau (RFLAGS) contenant les indicateurs d'état. | x86-64+
POR | Cette instruction permet d'effectuer un «OU BINAIRE» d'un quadruple mot d'une opérande source avec une opérande destination dans le cas des registres XMM. | INTEL Pentium MMX+
PREFETCH | Cette instruction permet d'effectuer le chargement de l'entrée d'une séquence d'alignement de mémoire de 64 bits de l'adresse mémoire spécifié dans le cache de données L1 du microprocesseur. | AMD K6-2+
PREFETCH0 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T0 du microprocesseur. Alias de PREFETCHT0. | INTEL Pentium III (SSE)+
PREFETCH1 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T1 du microprocesseur. Alias de PREFETCHT1. | INTEL Pentium III (SSE)+
PREFETCH2 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T2 du microprocesseur. Alias de PREFETCHT2. | INTEL Pentium III (SSE)+
PREFETCHNTA | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données NTA du microprocesseur. | INTEL Pentium III (SSE)+
PREFETCHT0 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T0 du microprocesseur. Alias de PREFETCH0. | INTEL Pentium III (SSE)+
PREFETCHT1 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T1 du microprocesseur. Alias de PREFETCH1. | INTEL Pentium III (SSE)+
PREFETCHT2 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T2 du microprocesseur. Alias de PREFETCH2. | INTEL Pentium III (SSE)+
PREFETCHW | Cette instruction permet d'effectuer le chargement de l'entrée d'une séquence d'alignement de mémoire de 64 bits de l'adresse mémoire spécifié dans le cache de données L1 du microprocesseur dans un état de modification. | AMD K6-2+
PSADBW | Cette instruction permet d'effectuer le calcul la valeur de absolue de la différence des octets de paquet contenu dans une opérande source et destination. | INTEL Pentium III (SSE)+
PSHUFB | Cette instruction permet d'effectuer un mélange des octets en place dans l'opérande de destination avec un masque de contrôle dans l'opérande source. | SSSE3+
PSHUFD | Cette instruction permet de copier un double mots d'une opérande source avec emplacement spécifié par un opérande immédiate dans un opérande de destination. | INTEL Pentium 4 (SSE2)+
PSHUFHW | Cette instruction permet de copier un mot d'une opérande source avec emplacement spécifié par un opérande immédiate dans la partie haute d'un opérande de destination. | INTEL Pentium 4 (SSE2)+
PSHUFLW | Cette instruction permet de copier un mot d'une opérande source avec emplacement spécifié par un opérande immédiate dans la partie basse d'un opérande de destination. | INTEL Pentium 4 (SSE2)+
PSHUFW | Cette instruction permet de copier une double mots d'un opérande source avec emplacement spécifié par un opérande immédiate dans un opérande de destination. | INTEL Pentium III (SSE)+
PSIGNB | Cette instruction permet d'effectuer la négation de chaque octets de l'opérande de destination si la valeur du signe de l'entier des octets correspondant à l'opérande source est inférieur à 0. | SSSE3+
PSIGND | Cette instruction permet d'effectuer la négation de chaque double mots de l'opérande de destination si la valeur du signe de l'entier des double mots correspondant à l'opérande source est inférieur à 0. | SSSE3+
PSIGNW | Cette instruction permet d'effectuer la négation de chaque mots de l'opérande de destination si la valeur du signe de l'entier des mots correspondant à l'opérande source est inférieur à 0. | SSSE3+
PSLLD | Cette instruction permet d'effectuer le décalage de bits vers la gauche d'un paquet de double mots. | INTEL Pentium Pro+
PSLLDQ | Cette instruction permet d'effectuer le décalage de bits vers la gauche d'un paquet de double quadruple mots. | INTEL Pentium 4 (SSE2)+
PSLLQ | Cette instruction permet d'effectuer le décalage de bits vers la gauche d'un quadruple mot. | INTEL Pentium Pro+
PSLLW | Cette instruction permet d'effectuer le décalage de bits vers la gauche d'un paquet de mots. | INTEL Pentium Pro+
PSRAD | Cette instruction permet d'effectuer le décalage arithmétique de bits vers la droite d'un paquet de double mots. | INTEL Pentium Pro+
PSRAW | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un paquet de mots. | INTEL Pentium Pro+
PSRLD | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un paquet de double mots. | INTEL Pentium Pro+
PSRLDQ | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un paquet de double quadruple mots. | INTEL Pentium 4 (SSE2)+
PSRLQ | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un quadruple mot. | INTEL Pentium Pro+
PSRLW | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un paquet de mots. | INTEL Pentium Pro+
PSUBB | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des octets d'un paquet contenu dans des opérandes de 64 bits. | INTEL Pentium Pro+
PSUBD | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | INTEL Pentium Pro+
PSUBQ | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des quadruples mots d'un paquet contenu dans des opérandes. | INTEL Pentium 4 (SSE2)+
PSUBSB | Cette instruction permet d'effectuer la soustraction avec saturation de la valeur de chacun des octets signés d'un paquet contenu dans des opérandes de 64 bits. | INTEL Pentium Pro+
PSUBSIW | Cette instruction permet d'effectuer la soustraction du mot de format entier de l'opérande source au mot de format entier de l'opérande de destination et écrit le résultat dans le registre MMX. | Cyrix 6x86MX (EMMX)+
PSUBSW | Cette instruction permet d'effectuer la soustraction du mot de format entier de l'opérande source au mot de format entier de l'opérande de destination et écrit le résultat dans l'opérande destinataire. | INTEL Pentium Pro+
PSUBUSB | Cette instruction permet d'effectuer la soustraction avec saturation de la valeur de chacun des octets d'un paquet contenu dans des opérandes de 64 bits. | INTEL Pentium Pro+
PSUBUSW | Cette instruction permet d'effectuer la soustraction avec saturation de la valeur de chacun des mots d'un paquet contenu dans des opérandes de destinations. | INTEL Pentium Pro+
PSUBW | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des mots d'un paquet contenu dans des opérandes de 64 bits. | INTEL Pentium Pro+
PSWAPD | Cette instruction permet d'effectuer l'échange de la partie basse de 32 bits avec la partie haute de 32 bits dans des opérandes source de 64 bits et met le résultat dans une opérande 64 bits destinataire. | 3DNow!
PTEST | Cette instruction permet d'effectuer une comparaison de paquet avec un «Et binaire» sans modifier les opérandes. | SSE4.1+
PUNPCKHBW | Cette instruction permet de décompacter des octets en mots dans le haut d'un paquets de 64 bits. | INTEL Pentium Pro+
PUNPCKHDQ | Cette instruction permet de décompacter des doubles mots en quadruples mots dans le haut d'un paquets de 64 bits. | INTEL Pentium Pro+
PUNPCKHQDQ | Cette instruction permet de décompacter des doubles mots en quadruples mots dans le haut d'un paquets de 128 bits. | INTEL Pentium 4 (SSE2)+
PUNPCKHWD | Cette instruction permet de décompacter des mots en double mots dans le haut d'un paquets de 64 bits. | INTEL Pentium Pro+
PUNPCKLBW | Cette instruction permet de décompacter des octets en mots dans le bas d'un paquets de 64 bits. | INTEL Pentium Pro+
PUNPCKLDQ | Cette instruction permet de décompacter des doubles mots en quadruples mots dans le bas d'un paquets de 64 bits. | INTEL Pentium Pro+
PUNPCKLQDQ | Cette instruction permet de décompacter des doubles mots en quadruples mots dans le bas d'un paquets de 128 bits. | INTEL Pentium 4 (SSE2)+
PUNPCKLWD | Cette instruction permet de décompacter des mots en double mots dans le bas d'un paquets de 64 bits. | INTEL Pentium Pro+
PUSH | Cette instruction permet d'empiler un mot ou un double mot dans la pile. | INTEL 8086+
PUSHA | Cette instruction permet d'empiler respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX dans la pile. | INTEL 80286+
PUSHAD | Cette instruction permet d'empiler respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX dans la pile. | INTEL 80386+
PUSHF | Cette instruction permet d'empiler respectivement le registre 16 bits de drapeau des indicateurs d'état dans la pile. | INTEL 8086+
PUSHFD | Cette instruction permet d'empiler respectivement le registre 32 bits de drapeau des indicateurs d'état dans la pile. | INTEL 80386+
PUSHFQ | Cette instruction permet d'empiler respectivement le registre 64 bits de drapeau (RFLAGS) des indicateurs d'état dans la pile. | x86-64+
PXOR | Cette instruction permet d'effectuer un ou exclusif binaire d'un quadruple mot d'une opérande source avec une opérande destination dans le cas des registres XMM. | INTEL Pentium MMX+
RCL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | INTEL 8088+
RCPPS | Cette instruction permet d'effectuer le calcul de la réciproque d'un paquet de valeurs de réel de simple précision. | INTEL Pentium III (KNI/MMX2)+
RCPSS | Cette instruction permet d'effectuer le calcul de la réciproque d'une valeur de réel de simple précision. | INTEL Pentium III (KNI/MMX2)+
RCR | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | INTEL 8088+
RDMSR | Cette instruction permet de charger le contenu du modèle de registre 64-bits (MSR) indiquer par le registre ECX dans le couple de registre EDX:EAX. | INTEL Pentium+
RDPMC | Cette instruction permet d'effectuer la lecture du compteur du moniteur de performance. | INTEL Pentium Pro+
RDSHR | Cette instruction permet d'effectuer la lecture du registre de pointeur vers l'entête SMM. | Cyrix CX6x86MX+
RDTSC | Cette instruction permet de charger la valeur courante du compteur de temps du microprocesseur dans le couple de registres EDX:EAX. | INTEL Pentium+
RDTSCP | Cette instruction permet de charger la valeur courante du compteur de temps du microprocesseur dans le couple de registres EDX:EAX et la valeur du TSC_AUX dans le registre ECX. | x86-64+
REP | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions tant que CX ne vaut pas 0. | INTEL 8086+
REPE | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0. | INTEL 8086+
REPNE | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1. | INTEL 8086+
REPNZ | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1. | INTEL 8086+
REPZ | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0. | INTEL 8086+
RES3 | Cette instruction permet d'effectuer le chargement de tous les registres de descripteur de cache pour les 386. | AMD Am386SXLV, Am386DXLV
RES4 | Cette instruction permet d'effectuer le chargement de tous les registres de descripteur de cache pour les 486. | AMD Am486SXLV, Am486DXLV
RET | Cette instruction permet de quitter une procédure. | INTEL 8086+
RETF | Cette instruction permet de quitter une procédure ayant lieu avec un appel long (FAR CALL). | INTEL 8086+
RETN | Cette instruction permet de quitter une procédure ayant lieu avec un appel court (NEAR CALL). | INTEL 8086+
ROL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | INTEL 8088+
ROR | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | INTEL 8088+
ROUNDPD | Cette instruction permet d'effectuer l'arrondissement de 2 valeurs réel de double précision dans l'opérande source en utilisant le mode spécifié par l'opérande immédiate et place le résultat dans l'opérande de destination. | SSE4.1+
ROUNDPS | Cette instruction permet d'effectuer l'arrondissement de 4 valeurs réel de simple précision dans l'opérande source en utilisant le mode spécifié par l'opérande immédiate et place le résultat dans l'opérande de destination. | SSE4.1+
ROUNDSD | Cette instruction permet d'effectuer l'arrondissement scalaire de valeurs réel de double précision, dans sa partie basse du quadruple mot, dans l'opérande source en utilisant le mode spécifié par l'opérande immédiate et place le résultat dans l'opérande de destination. | SSE4.1+
ROUNDSS | Cette instruction permet d'effectuer l'arrondissement scalaire de valeurs réel de simple précision, dans sa partie basse du quadruple mot, dans l'opérande source en utilisant le mode spécifié par l'opérande immédiate et place le résultat dans l'opérande de destination. | SSE4.1+
RSDC | Cette instruction permet d'effectuer le restauration de la structure des registres et des descripteurs. | Quelques 486
RSLDT | Cette instruction permet d'effectuer la restauration des LDTR et des descripteurs. | Quelques 486
RSM | Cette instruction permet de retourner le contrôle du programme du mode de gestion système (SMM) pour le programme d'application ou la procédure du système d'exploitation ayant été interrompu lorsque le microprocesseur à recu un signal SSM. | INTEL 80486+
RSQRTPS | Cette instruction permet de calculer la réciproque approximative de la racine carré d'un paquet de simple précision. | INTEL Pentium III (KNI/MMX2)+
RSQRTSS | Cette instruction permet de calculer la réciproque approximative de la racine carré d'un scalaire de simple précision. | INTEL Pentium III (KNI/MMX2)+
RSTS | Cette instruction permet d'effectuer le restauration des TR et des descripteurs. | Quelques 486
SAHF | Cette instruction permet de copier les bits du registre AH dans l'octet de poids faible dans le registre des drapeaux (les indicateurs d'état). | INTEL 8088+
SAL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | INTEL 8088+
SAR | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | INTEL 8088+
SBB | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande. | INTEL 8088+
SCAS | Cette instruction permet de comparer un octet, un mot ou un double mot avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | INTEL 8086+
SCASB | Cette instruction permet de comparer le registre AL avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction. | INTEL 8086+
SCASD | Cette instruction permet de comparer le registre EAX avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
SCASW | Cette instruction permet de comparer le registre AX avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction. | INTEL 8086+
SET | Ces instructions permettent de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | INTEL 80386+
SETALC | Cette instruction permet de copier la valeur du drapeau de retenue dans le registre AL en la multipliant par 0FFh. | INTEL 8086+
SFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant emmagasiner du SFENCE et les instructions suivant le SFENCE. | Pentium III (SSE)+
SGDT | Cette instruction permet d'entreposer le sélecteur de segment dans le registre GDTR (registre de table global de descripteur) dans l'opérande de destination. | INTEL 80386+
SHL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | INTEL 8088+
SHLD | Cette instruction permet d'effectuer une rotation des bits d'un double mot vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | INTEL 80386+
SHR | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | INTEL 8088+
SHRD | Cette instruction permet d'effectuer une rotation des bits d'un double mot vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | INTEL 80386+
SHUFPD | Cette instruction permet de copier 4 paquets de valeurs de format réel de double précision dans un opérande destinataire dans la partie basse d'un quadruple mot de celle-ci et copie 2 des 4 paquets de valeurs de format réel de simple précision dans l'opérande source dans la partie haute d'un quadruple mot de l'opérande destinataire. | INTEL Pentium 4 (SSE2)+
SHUFPS | Cette instruction permet de copier 4 paquets de valeurs de format réel de simple précision dans une opérande destinataire dans la partie basse d'un quadruple mot de celle-ci et copie 2 des 4 paquets de valeurs de format réel de simple précision dans l'opérande source dans la partie haute d'un quadruple mot de l'opérande destinataire. | INTEL Pentium III (KNI/MMX2)+
SIDT | Cette instruction permet d'entreposer le registre de descripteur de table d'interruption (IDTR) dans l'opérande de destination. | INTEL 80386+
SKINIT | Cette instruction permet de réinitialiser de façon sécuritaire le microprocesseur et de démarrer un logiciel de confiance comme un VMM. | AMD-V
SLDT | Cette instruction permet d'entreposer le sélecteur de segment dans le registre LDTR (registre de table local de descripteur) dans l'opérande de destination. | INTEL 80386+
SMI | Cette instruction permet de gérer les interruptions systèmes en mode de déboguage. | AMD Am386SXLV,Am386DXLV
SMINT | Cette instruction permet de faire entrée le microprocesseur en mode SMM (System Management Mode). | P6, Cyrix
SMINTOLD | Cette instruction permet de faire entrée le microprocesseur en mode SMM (System Management Mode). | Quelques 486
SMSW | Cette instruction permet d'entreposer le mot des états (soit les bits de 0 à 15 du registre de contrôle CR0) à partir du registre de tâche (TR) dans l'opérande cible. | INTEL 80386+
SQRTPD | Cette instruction permet d'effectuer le calcul de la racine carré d'un paquet de valeur de double précision réel de l'opérande source et de mettre son résultat dans l'opérande de destination sous forme d'un réel de double précision. | INTEL Pentium 4 (SSE2)+
SQRTPS | Cette instruction permet d'effectuer le calcul de la racine carré d'un paquet de valeur de simple précision réel de l'opérande source et de mettre son résultat dans l'opérande de destination sous forme d'un réel de simple précision. | INTEL Pentium III (KNI/MMX2)+
SQRTSD | Cette instruction permet d'effectuer le calcul de la racine carré d'une valeur de double précision réel de l'opérande source et de mettre son résultat dans l'opérande de destination sous forme d'un réel de double précision. | INTEL Pentium 4 (SSE2)+
SQRTSS | Cette instruction permet d'effectuer le calcul de la racine carré d'une valeur de simple précision réel de l'opérande source et de mettre son résultat dans l'opérande de destination sous forme d'un réel de simple précision. | INTEL Pentium III (KNI/MMX2)+
SS: | Ce préfixe permet d'indiquer à une instruction d'utiliser le Segment de Pile (Stack Segment) pour adresse dans l'opérande. | INTEL 8088+
STC | Cette instruction permet de fixer l'indicateur de retenue (CF) à la valeur 1. | INTEL 8088+
STD | Cette instruction permet de fixer l'indicateur de direction (DF) à la valeur 1. | INTEL 8088+
STGI | Cette instruction permet de fixer les drapeaux global d'interruption (GIF). Quand le GIF est à 1, les interruptions externes sont réactivés. | AMD-V
STI | Cette instruction permet de fixer l'indicateur d'interruption (IF) à la valeur 1. | INTEL 8088+
STMXCSR | Cette instruction permet de copier le MXCSR dans un emplacement mémoire de 32 bits. | INTEL Pentium III (KNI/MMX2)+
STOS | Cette instruction permet de copier un octet, un mot ou un double mot dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | INTEL 8086+
STOSB | Cette instruction permet de copier le registre AL dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction. | INTEL 8086+
STOSD | Cette instruction permet de copier le registre EAX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
STOSQ | Cette instruction permet de copier le registre RAX dans la cellule mémoire à l'adresse ES:[(R)DI] et incrémente/décrémente le registre (R)DI de 8 en fonction de l'état du drapeau de direction. | x86-64+
STOSW | Cette instruction permet de copier le registre AX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction. | INTEL 8086+
STR | Cette instruction permet d'entreposer le sélecteur de segment à partir du registre de tâche (TR) à l'opérande cible | INTEL 80286+
SUB | Cette instruction permet de soustraire une valeur à une opérande. | INTEL 8088+
SUBPD | Cette instruction permet d'effectuer une soustraction de 2 paquets de valeurs réels de double précision d'un opérande source et d'un opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de double précision. | INTEL Pentium 4 (SSE2)+
SUBPS | Cette instruction permet d'effectuer une soustraction de 4 paquets de valeurs réels de simple précision d'une opérande source et d'une opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de simple précision. | INTEL Pentium III (KNI/MMX2)+
SUBSD | Cette instruction permet d'effectuer une soustraction de la partie basse d'une valeur réel de double précision d'un opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de double précision. | INTEL Pentium 4 (SSE2)+
SUBSS | Cette instruction permet d'effectuer une soustraction de la partie basse d'une valeur réel de simple précision d'une opérande source et destination et entrepose le résultat dans une opérande de destination de valeur réel de simple précision. | INTEL Pentium III (KNI/MMX2)+
SVDC | Cette instruction permet de sauvegarder le registre et le descripteur. | Quelques 486
SVLDT | Cette instruction permet de sauvegarder le LDTR et le descripteur. | Quelques 486
SVTS | Cette instruction permet de sauvegarder le TR et le descripteur. | Quelques 486
SWAPGS | Cette instruction permet de fournir une méthode à un logiciel système pour charger un pointeur sur une structure de données système. | x86-64+
SYSCALL | Cette instruction permet d'effectuer le transfert du contrôle d'un point d'entrée fixe au système d'exploitation. | AMD K6-2+
SYSENTER | Cette instruction permet d'effectuer le transférer du contrôle d'un point d'entrée au système d'exploitation. | INTEL Pentium Pro+
SYSEXIT | Cette instruction permet de retourner du système d'exploitation à une application. | INTEL Pentium Pro+
SYSRET | Cette instruction permet de retourner du système d'exploitation à une application. | AMD K6-2+
TEST | Cette instruction permet d'effectuer un «Et binaire» sur une opérande cible sans modifier sa valeur. | INTEL 8088+
UCOMISD | Cette instruction permet d'effectuer une comparaison désordonnée de valeurs réels de double précision dans la partie basse d'un double mot du premier opérande et du deuxième opérande, et fixe les drapeaux ZF, PF et FC dans le registre EFLAGS selon le résultat (non-ordonnée, supérieur à, inférieur ou égal) | INTEL Pentium III+
UCOMISS | Cette instruction permet d'effectuer une comparaison désordonnée de valeurs réels de simple précision dans la partie basse d'un double mot du premier opérande et du deuxième opérande, et fixe les drapeaux ZF, PF et FC dans le registre EFLAGS selon le résultat (non-ordonnée, supérieur à, inférieur ou égal) | INTEL Pentium III+
UD | Cette instruction permet de provoquer l'exécution d'un code indéfinie. | AMD Am5k86 (SSA/5, K5)
UD2 | Cette instruction permet de provoquer l'exécution d'un code indéfinie. | INTEL Pentium Pro+
UMOV | Cette instruction permet de copier un opérande source dans une emplacement mémoire principal. | AMD Am386SXLV, Am386DXLV, 486s, IBM 486SLC2
UNPCKHPD | Cette instruction permet d'effectuer un dépaquetage de la partie haute d'un réel de double précision d'un opérande source et destination et met le résultat dans l'opérande de destination. | INTEL Pentium 4 (SSE2)+
UNPCKHPS | Cette instruction permet d'effectuer un dépaquetage de la partie haute d'un réel de simple précision d'un opérande source et destination et met le résultat dans l'opérande de destination. | INTEL Pentium III (KNI/MMX2)+
UNPCKLPD | Cette instruction permet d'effectuer un dépaquetage de la partie basse d'un réel de double précision d'un opérande source et destination et met le résultat dans l'opérande de destination. | INTEL Pentium 54 (SSE2)+
UNPCKLPS | Cette instruction permet d'effectuer un dépaquetage de la partie basse d'un réel de simple précision d'une opérande source et destination et met le résultat dans l'opérande de destination. | INTEL Pentium III (KNI/MMX2)+
VBROADCASTF128 | Cette instruction permet d'effectuer le chargement de valeurs réels de 128 bits d'une opérande source et de se diffuser dans tous les éléments de l'opérande de destination. | AVX (AMD ou INTEL)
VBROADCASTSD | Cette instruction permet d'effectuer le chargement de valeurs réels de double précision d'une opérande source et de se diffuser dans tous les éléments de l'opérande de destination. | AVX (AMD ou INTEL)
VBROADCASTSS | Cette instruction permet d'effectuer le chargement de valeurs réels de simple précision d'une opérande source et de se diffuser dans tous les éléments de l'opérande de destination. | AVX (AMD ou INTEL)
VERR | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode lecture à partir du niveau de privilège courant (CPL). | INTEL 80286+
VERW | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode écriture à partir du niveau de privilège courant (CPL). | INTEL 80286+
VEXTRACTF128 | Cette instruction permet d'effectuer l'extraction de paquet de valeurs réel de 128 bits d'une opérande source dans l'opérande de destination en tenant compte de la position d'extraction avec une opérande de destination. | AVX (AMD ou INTEL)
VFMADD132PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un premier opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire au résultat de deux ou quatres paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD132PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un premier opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire au résultat de quatre ou huit paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD132SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un premier opérande source avec la partie basse de paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire au résultat de la partie basse de paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD132SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un premier opérande source avec la partie basse de paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire au résultat de la partie basse de paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD213PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un second opérande source avec les deux ou quatres paquets de valeurs réels de double précision du premier opérande source, ajoute la précision infinie intermédiaire au résultat de deux ou quatres paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD213PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un second opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du premier opérande source, ajoute la précision infinie intermédiaire au résultat de quatre ou huit paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD213SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un second opérande source avec la partie basse de paquets de valeurs réels de double précision du premier opérande source, ajoute la précision infinie intermédiaire au résultat de la partie basse de paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD213SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de simple précision du premier opérande source, ajoute la précision infinie intermédiaire au résultat de la partie basse de paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD231PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un second opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire au résultat de deux ou quatres paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD231PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un second opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire au résultat de quatre ou huit paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD231SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un second opérande source avec la partie basse de paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire au résultat de la partie basse de paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD231SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire au résultat de la partie basse de paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADDSUB132PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un premier opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire impaire et soustrait la précision intermédiaire paire au résultat de deux ou quatres paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADDSUB132PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un premier opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire impaire et soustrait la précision intermédiaire paire au résultat de quatre ou huit paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADDSUB213PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du premier opérande source, ajoute la précision infinie intermédiaire impaire et soustrait la précision intermédiaire paire au résultat de deux ou quatres paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADDSUB213PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxème opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du premier opérande source, ajoute la précision infinie intermédiaire impaire et soustrait la précision intermédiaire paire au résultat de quatre ou huit paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADDSUB231PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire impaire et soustrait la précision intermédiaire paire au résultat de deux ou quatres paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADDSUB231PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire impaire et soustrait la précision intermédiaire paire au résultat de quatre ou huit paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUBADD132PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un premier opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire impaire et ajoute la précision intermédiaire paire au résultat de deux ou quatres paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUBADD132PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un premier opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire impaire et ajoute la précision intermédiaire paire au résultat de quatre ou huit paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUBADD213PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du premier opérande source, soustrait la précision infinie intermédiaire impaire et ajoute la précision intermédiaire paire au résultat de deux ou quatres paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUBADD213PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du premier opérande source, soustrait la précision infinie intermédiaire impaire et ajoute la précision intermédiaire paire au résultat de quatre ou huit paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUBADD231PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire impaire et ajoute la précision intermédiaire paire au résultat de deux ou quatres paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUBADD231PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire impaire et ajoute la précision intermédiaire paire au résultat de quatre ou huit paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB132PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un premier opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire au résultat de deux ou quatres paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB132PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un premier opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire au résultat de quatre ou huit paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB132SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un premier opérande source avec la partie basse de paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire au résultat de la partie basse de paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB132SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un premier opérande source avec la partie basse de paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire au résultat de la partie basse de paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB213PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du premier opérande source, soustrait la précision infinie intermédiaire au résultat de deux ou quatres paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB213PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du premier opérande source, soustrait la précision infinie intermédiaire au résultat de quatre ou huit paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB213SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de double précision du premier opérande source, soustrait la précision infinie intermédiaire au résultat de la partie basse de paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB213SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de simple précision du premier opérande source, soustrait la précision infinie intermédiaire au résultat de la partie basse de paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB231PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire au résultat de deux ou quatres paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB231PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire au résultat de quatre ou huit paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB231SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire au résultat de la partie basse de paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB231SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire au résultat de la partie basse de paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD132PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un premier opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire négative au résultat de deux ou quatres paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD132PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un premier opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire négative au résultat de quatre ou huit paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD132SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un premier opérande source avec la partie basse de paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD132SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un premier opérande source avec la partie basse de paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD213PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du premier opérande source, ajoute la précision infinie intermédiaire négative au résultat de deux ou quatres paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD213PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du premier opérande source, ajoute la précision infinie intermédiaire négative au résultat de quatre ou huit paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD213SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de double précision du premier opérande source, ajoute la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD213SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de simple précision du premier opérande source, ajoute la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD231PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire négative au résultat de deux ou quatres paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD231PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire négative au résultat de quatre ou huit paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD231SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD231SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB132PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un premier opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire négative au résultat de deux ou quatres paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB132PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un premier opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire négative au résultat de quatre ou huit paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB132SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un premier opérande source avec la partie basse de paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB132SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un premier opérande source avec la partie basse de paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB213PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du premier opérande source, soustrait la précision infinie intermédiaire négative au résultat de deux ou quatres paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB213PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du premier opérande source, soustrait la précision infinie intermédiaire négative au résultat de quatre ou huit paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB213SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de double précision du premier opérande source, soustrait la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB213SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de simple précision du premier opérande source, soustrait la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB231PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire négative au résultat de deux ou quatres paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB231PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire négative au résultat de quatre ou huit paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB231SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB231SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VINSERTF128 | Cette instruction permet d'insérer une valeur réel de 128 bits d'un opérande source dans l'emplacement d'un registre d'opérande de destination et met des 0 dans les données en dehors du masque de destination. | AVX (AMD ou INTEL)
VLDMXCSR | Cette instruction permet d'effectuer le chargement du mot de contrôle (MXCSR) d'une opérande mémoire 32 bits pour l'AVX. | AVX (AMD ou INTEL)
VMASKMOVPD | Cette instruction permet d'effectuer un chargement conditionnel des valeurs réels de double précision de paquets d'une opérande de 128 ou 256 bits avec le masque de destination et entrepose le résultat dans l'opérande de destination. | AVX (AMD ou INTEL)
VMASKMOVPS | Cette instruction permet d'effectuer un chargement conditionnel des valeurs réels de simple précision de paquets d'une opérande de 128 ou 256 bits avec le masque d'opérande et entrepose le résultat dans l'opérande de destination. | AVX (AMD ou INTEL)
VMCALL | Cette instruction permet de fournir un mécanisme invité logiciel pour appeler un service dans un moniteur VM. | INTEL VMX (Virtualisation)
VMCLEAR | Cette instruction permet d'appliquer un VMCS à une région VMCS à l'adresse physique contenu dans l'opération spécifié. | INTEL VMX (Virtualisation)
VMLAUNCH | Cette instruction permet de gérer l'entrée VM par le VMCS courant, de façon à échoué si l'état de lancement VMCS courant n'est pas effacé. Si l'instruction est un succès, il définit l'état de lancement à relancer. | INTEL VMX (Virtualisation)
VMLOAD | Cette instruction permet d'effectuer le chargement d'un sous-ensemble d'état de microprocesseur dans un VMCB spécifié par une adresse physique contenu dans le registre RAX. | AMD-V
VMMCALL | Cette instruction permet de fournir un mécanisme invité pour communiquer explicitement avec le VMM en générant un #VMEXIT. | AMD-V
VMPTRLD | Cette instruction permet de marquer le pointeur VMCS courant valide et charge celui-ci avec une adresse physique dans l'opérande d'instruction. | INTEL VMX (Virtualisation)
VMPTRST | Cette instruction permet d'entreposer le pointeur VMCS courant dans l'adresse mémoire spécifié. | INTEL VMX (Virtualisation)
VMREAD | Cette instruction permet d'effectuer la lecture du champ spécifié dans le VMCS et l'entrepose dans l'opérande de destination spécifié. | INTEL VMX (Virtualisation)
VMRESUME | Cette instruction permet de gérer l'entrée VM par le VMCS courant, de façon à échoué si l'état le lancement VMCS courant n'est pas lancé. | INTEL VMX (Virtualisation)
VMRUN | Cette instruction permet de lancer l'exécution d'un flux d'instructions invité. | AMD-V
VMSAVE | Cette instruction permet d'entreposer un sous-ensemble d'état du microprocesseur dans un VMCB spécifié par une adresse physique contenu dans le registre RAX. | AMD-V
VMWRITE | Cette instruction permet d'effectuer l'écriture du champ spécifié du VMCS spécifié par l'opérande source secondaire (registre seulement) en utilisant le contenu de l'opérande source primaire (registre ou mémoire). | INTEL VMX (Virtualisation)
VMXOFF | Cette instruction permet d'utiliser le processeur logique en dehors de l'opération VMX, de débloquer le signal INIT, de conditionnellement réactiver le A20M et d'effacer tous les rangs d'adresse du moniteur. | INTEL VMX (Virtualisation)
VMXON | Cette instruction permet d'utiliser le processeur logique dans une opération VMX avec le VMCS non courant, le signal INIT bloqué, la désactivation A20M, et en effaçant n'importe quel rang d'adresse du moniteur établit avec l'instruction MONITOR. | INTEL VMX (Virtualisation)
VPERM2F128 | Cette instruction permet d'effectuer la permutation de valeurs réel de 128 bits d'un premier opérande source utilisant un champ de 8 bits de contrôle dans les octets bas d'un second opérande source et entrepose les résultats dans l'opérande de destination. | AVX (AMD ou INTEL)
VPERMILPD | Cette instruction permet d'effectuer la permutation de valeurs réels de double précision d'un premier opérande source utilisant un champ de 8 bits de contrôle dans les octets bas d'un second opérande source et entrepose les résultats dans l'opérande de destination. | AVX (AMD ou INTEL)
VPERMILPS | Cette instruction permet d'effectuer la permutation de valeurs réels de simple précision d'un premier opérande source utilisant un champ de 8 bits de contrôle dans les octets bas d'un second opérande source et entrepose les résultats dans l'opérande de destination. | AVX (AMD ou INTEL)
VZEROALL | Cette instruction permet de mettre la valeur 0 dans tous les registres XMM ou YMM. | AVX (AMD ou INTEL)
VZEROUPPER | Cette instruction permet de mettre la valeur 0 dans chacun des 128 bits de la partie haute de tous les registres XMM ou YMM. | AVX (AMD ou INTEL)
WAIT | Cette instruction permet de faire passer le microprocesseur en mode d'attente jusqu'à ce que la ligne de teste sur la carte mère s'active. | INTEL 8088+
WBINVD | Cette instruction permet de désactiver et de vider le tampon interne du micro-processeur. | INTEL 80486+
WRMSR | Cette instruction écrit les valeurs contenues dans le MSR (Model-Specific Register) en fonction du registre d'index ECX dans la paire des registres EDX:EAX. | INTEL Pentium+
WRSHR | Cette instruction écrit les valeurs contenues dans l'opérande source dans l'entête SMM. | Cyrix Cx6x86MX
XADD | Cette instruction permet d'échanger le premier opérande avec le deuxième opérande, et ensuite effectue la somme des valeurs dans le premier opérande. | INTEL 80486+
XBTS | Cette instruction permet de prendre des bits d'un opérande source et de les mettres dans une opérande destinataire. | INTEL 80386
XCHG | Cette instruction permet d'échanger la valeur de deux opérandes. | INTEL 8088+
XGETBV | Cette instruction permet d'effectuer la lecture du registre de contrôle étendue (XCR) spécifié par le registre ECX dans les registres EDX:EAX. | INTEL SDM (Core i7)+
XLAT | Cette instruction permet de remplacer le contenu du registre AL par un octet de la «tablesource». | INTEL 8088+
XLATB | Cette instruction permet de remplacer le contenu du registre AL par un octet de la «tablesource» sans opérande. | INTEL 8088+
XOR | Cette instruction permet d'effectuer un OU exclusif BINAIRE sur les 2 opérandes spécifiés. | INTEL 8086+
XORPD | Cette instruction permet d'effectuer un ou exclusif binaire de 2 paquets de valeurs réel de double précision dans un opérande source et destination et de mettre le résultat dans l'opérande de destination. | INTEL Pentium 4 (SSE2)+
XORPS | Cette instruction permet d'effectuer un ou exclusif binaire de 4 paquets de valeurs réel de simple précision dans une opérande source et destination et de mettre le résultat dans l'opérande de destination. | INTEL Pentium III+ (KNI/MMX2)
XRSTOR | Cette instruction permet d'effectuer une restauration complète ou partiel des états actifs du processeur en utilisant les informations entreposé dans les adresses de mémoire spécifié par l'opérande. | INTEL SDM (Core i7)+
XSAVE | Cette instruction permet d'effectuer une sauvegarde complète ou partiel des états actifs du processeur en utilisant les informations entreposé dans les adresses de mémoire spécifié par l'opérande. | INTEL SDM (Core i7)+
XSETBV | Cette instruction permet d'effectuer l'écriture du registre de contrôle étendue (XCR) spécifié par les registres EDX:EAX à l'aide du registre ECX. | INTEL SDM (Core i7)+

Dernière mise à jour : Samedi, le 2 août 2014


Langage de programmation - Assembleur 80x86 - Référence, lexique et dictionnaire des instructions 80x86 - Vue par Opcode (Inline ou code machine hexadécimal)

Vu dans ... http://www.gladir.com Voici la liste des opcodes en 16 et 32 bits :

Opcode | Instruction | Description
00h (r/m8) | ADD r/m8 | Cette instruction additionne 2 quantités numérique sur 8 bits.
01h (r/m16) | ADD r/m16 | Cette instruction additionne 2 quantités numérique sur 16 bits.
02h (r/m8) | ADD r/m8 | Cette instruction additionne 2 quantités numérique sur 8 bits.
03h (r/m16) | ADD r/m16 | Cette instruction additionne 2 quantités numérique sur 16 bits.
04h (xxh) | ADD AL,xxh | Cette instruction additionne une valeur 8 bits immédiate au registre AL.
05h (xxh) (yyh) | ADD AX,yyxxh | Cette instruction additionne une valeur 16 bits immédiate au registre AX.
06h | PUSH ES | Cette instruction permet d'empiler le registre ES dans la pile.
07h | POP ES | Cette instruction permet de désempiler de la pile une mot et la met dans le registre ES.
08h (r/m8) | OR r/m8 | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandes spécifiés 8 bits.
09h (r/m16) | OR r/m16 | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandes spécifiés 16 bits.
0Ah (r/m8) | OR r/m8 | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandes spécifiés 8 bits.
0Bh (r/m16) | OR r/m16 | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandes spécifiés 16 bits.
0Ch (xxh) | OR AL,xxh | Cette instruction permet d'effectuer un OU BINAIRE sur le registre AL avec une valeur immédiate 8 bits.
0Dh (xxh) (yyh) | OR AX,yyxxh | Cette instruction permet d'effectuer un OU BINAIRE sur le registre AX avec une valeur immédiate 16 bits.
0Eh | PUSH CS | Cette instruction permet d'empiler le registre CS dans la pile.
0Fh 01h C8h | MONITOR | Cette instruction permet d'indiquer au microprocesseur quel rangé d'adresse est à surveiller par l'instruction STORE.
0Fh 01h C9h | MWAIT | Cette instruction permet d'indiquer au microprocesseur que l'état de l'alimentation de la ligne de cache est en attente d'écriture dans la plage d'adresse, mettant fin à la plupart des activités dans le noyau en le faisant.
0Fh 01h D9h | VMMCALL | Cette instruction permet de fournir un mécanisme invité pour communiquer explicitement avec le VMM en générant un #VMEXIT.
0Fh 01h DCh | STGI | Cette instruction permet de fixer les drapeaux global d'interruption (GIF). Quand le GIF est à 1, les interruptions externes sont réactivés.
0Fh 01h DDh | CLGI | Cette instruction permet d'effacer le drapeau d'interruption global (GIF).
0Fh 01h DEh | SKINIT EAX | Cette instruction permet de réinitialiser de façon sécuritaire le microprocesseur et de démarrer un logiciel de confiance comme un VMM.
0Fh 01h DFh | INVLPGA RAX, ECX | Cette instruction permet d'invalider la cartographie TLB (Translation Lookaside Buffer) pour une page virtuel et un ASID spécifié.
0Fh 01h F8h | SWAPGS | Cette instruction permet de fournir une méthode à un logiciel système pour charger un pointeur sur une structure de données système.
0Fh 01h F9h | RDTSCP | Cette instruction permet de charger la valeur courante du compteur de temps du microprocesseur dans le couple de registres EDX:EAX et la valeur du TSC_AUX dans le registre ECX.
0Fh 05h | SYSCALL | Cette instruction permet d'effectuer le transfert du contrôle d'un point d'entrée fixe au système d'exploitation.
0Fh 06h | CLTS | Cette instruction permet de mettre à 0 le drapeau de l'indicateur de tâche (Task-Switch) du registre CR0.
0Fh 07h | LOADALL | Cette instruction permet d'effectuer le chargement de tous les registres de descripteur de cache.
0Fh 07h | SYSRET | Cette instruction permet de retourner du système d'exploitation à une application.
0Fh 08h | WBINVD | Cette instruction permet de désactiver et de vider le tampon interne du micro-processeur.
0Fh 0Bh | UD2 | Cette instruction permet de provoquer l'exécution d'un code indéfinie.
0Fh 0Eh | FEMMS | Cette instruction permet d'effacer les états MMX après le passage d'instructions MMX.
0Fh 2Ah /r | CVTPI2PS xmm,mm/m64 | Cette instruction permet de convertir un entier de format double mot en une valeur réel de simple précision compacté.
0Fh 2Ch /r | CVTTPS2PI mm,xmm/m64 | Cette instruction permet de convertir une valeur réel de simple précision compacté avec tronquage en un entier de format double mot compacté.
0Fh 2Dh /r | CVTPS2PI mm,xmm/m64 | Cette instruction permet de convertir une valeur réel de simple précision compacté en un entier de format double mot.
0Fh 2Fh /r | COMISS xmm1,xmm2/m32 | Cette instruction permet de comparer deux valeurs réel de simple-précision dans la partie faible du quadruple mot de deux opérande et fixe les drapeaux de ZF, PF et FC du registre EFLAGS en fonction du résultat (non-ordonnée, supérieur à, inférieur ou égal).
0Fh 30h | WRMSR | Cette instruction écrit les valeurs contenu dans le MSR (Model-Specific Register) en fonction du registre d'index ECX dans la paire des registres EDX:EAX.
0Fh 31h | RDTSC | Cette instruction permet de charger la valeur courante du compteur de temps du microprocesseur dans le couple de registres EDX:EAX.
0Fh 32h | RDMSR | Cette instruction permet de charger le contenu du modèle de registre 64-bits (MSR) indiquer par le registre ECX dans le couple de registre EDX:EAX.
0Fh 33h | RDPMC | Cette instruction permet d'effectuer la lecture du compteur du moniteur de performance.
0Fh 34h | SYSENTER | Cette instruction permet d'effectuer le transférer du contrôle d'un point d'entrée au système d'exploitation.
0Fh 35h | SYSEXIT | Cette instruction permet de retourner du système d'exploitation à une application.
0Fh 40h /r | CMOVO reg16, reg/mem16 | Copie si débordement (OF = 1)
0Fh 41h /r | CMOVNO reg16, reg/mem16 | Copie si pas de débordement (OF = 0)
0Fh 42h /r | CMOVB reg16, reg/mem16 | Copie si retenu (CF = 1)
0Fh 43h /r | CMOVNB reg16,reg/mem16 | Copie si pas retenu (CF = 0)
0Fh 44h /r | CMOVZ reg16, reg/mem16 | Copie si drapeau du zéro (ZF = 1)
0Fh 45h /r | CMOVNZ reg16, reg/mem16 | Copie si drapeau de pas de zéro (ZF = 0)
0Fh 46h /r | CMOVBE reg16, reg/mem16 | Copie si drapeau de zéro (ZF = 1) ou drapeau de retenu (CF = 1)
0Fh 47h /r | CMOVNBE reg16, reg/mem16 | Copie si drapeau de pas de zéro (ZF = 0) et drapeau de pas de retenu (CF = 0)
0Fh 48h /r | CMOVS reg16, reg/mem16 | Copie si drapeau de signe (SF = 1)
0Fh 49h /r | CMOVNS reg16, reg/mem16 | Copie si drapeau de pas de signe (SF = 0)
0Fh 4Ah /r | CMOVP reg16, reg/mem16 | Copie si drapeau de parité (PF = 1)
0Fh 4Bh /r | CMOVNP reg16, reg/mem16 | Copie si drapeau de pas de parité (PF = 0)
0Fh 4Ch /r | CMOVL reg16, reg/mem16 | Copie si SF <> OF
0Fh 4Dh /r | CMOVNL reg16, reg/mem16 | Copie si SF = OF
0Fh 4Eh /r | CMOVLE reg16, reg/mem16 | Copie si ZF = 1 ou SF <> OF
0Fh 4Fh /r | CMOVNLE reg16, reg/mem16 | Copie si ZF = 0 et SF = OF
0Fh 54h /r | ANDPS xmmreg,r/m128 | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes 128 bits spécifiés.
0Fh 55h /r | ANDNPS xmmreg,r/m128 | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes 128 bits spécifiés et inverse chacun des bits du résultat.
0Fh 58h /r | ADDPS xmm1, xmm2/m128 | Cette instruction permet d'ajouter le paquet de réel de simple précision de xmm2/m128 à xmm1
0Fh 5Ah /r | CVTPS2PD xmm1, xmm2/m64 | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de simple précision en paquet de valeurs réel de double précision.
0Fh 5Bh /r | CVTDQ2PS xmm1, xmm2/m128 | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de simple précision.
0Fh 5Eh /r | DIVPS xmm1,xmm2/m128 | Cette instruction permet d'effectuer une division de valeur réel de simple précision de registre XMM ou d'emplacement mémoire de 128 bits.
0Fh 77h | EMMS | Cette instruction permet de fixer les mots marqués du MPU de chacun un.
0Fh A0h | PUSH FS | Cette instruction permet d'empiler le registre FS dans la pile.
0Fh A1h | POP FS | Cette instruction permet de désempiler de la pile une mot et la met dans le registre FS.
0Fh A2h | CPUID | Cette instruction retourne le code d'identification du microprocesseur.
0Fh A3h /r | BT reg/mem16, reg16 | Copie la valeur de sélection de bit dans le drapeau de retenu
0Fh A8h | PUSH GS | Cette instruction permet d'empiler le registre GS dans la pile.
0Fh A9h | POP GS | Cette instruction permet de désempiler de la pile une mot et la met dans le registre GS.
0Fh AAh | RSM | Cette instruction permet de retourner le contrôle du programme du mode de gestion système (SMM) pour le programme d'application ou la procédure du système d'exploitation ayant été interrompu lorsque le microprocesseur à reçu un signal SSM.
0Fh ABh /r | BTS reg/mem16, reg16 | Copie la valeur du bit de sélection dans le drapeau de retenu et fixe le bit de sélection.
0Fh AEh /7 | CLFLUSH mem8 | Vide la ligne de cache contenu dans mem8.
0Fh AEh E8h | LFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant le LFENCE et les instructions de chargement suivant le LFENCE.
0Fh AEh F0h | MFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant le MFENCE et les instructions de chargement et d'entreposage précédent le MFENCE.
0Fh AEh F8h | SFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant emmagasiner du SFENCE et les instructions suivant le SFENCE.
0Fh B0h /r | CMPXCHG reg/mem8, reg8 | Compare de registre AL avec un emplacement 8 bits de registre ou mémoire. S'ils sont égale, le deuxième opérande est copié dans le première opérande.
0Fh B1h /r | CMPXCHG reg/mem16, reg16 | Compare de registre AX avec un emplacement 16 bits de registre ou mémoire. S'ils sont égale, le deuxième opérande est copié dans le première opérande.
0Fh B3h /r | BTR reg/mem16, reg16 | Copie la valeur du bit de sélection dans le drapeau de retenu et efface le bit de sélection.
0Fh BAh /4 ib | BT reg/mem16, imm8 | Copie la valeur de sélection de bit dans le drapeau de retenu
0Fh BAh /5 ib | BTS reg/mem16, imm8 | Copie la valeur du bit de sélection dans le drapeau de retenu et fixe le bit de sélection.
0Fh BAh /6 ib | BTR reg/mem16, imm8 | Copie la valeur du bit de sélection dans le drapeau de retenu et efface le bit de sélection.
0Fh BAh /7 ib | BTC reg/mem16, imm8 | Copie la valeur du bit de sélection dans le drapeau de retenu et complémente le bit de sélection.
0Fh BBh /r | BTC reg/mem16, reg16 | Copie la valeur du bit de sélection dans le drapeau de retenu et complémente le bit de sélection.
0Fh BCh /r | BSF reg16, reg/mem16 | Balayage de bit vers l'avant du contenu du registre/mémoire 16 bits
0Fh BDh /r | BSR reg16, reg/mem16 | Balayage de bit vers l'arrière du contenu du registre/mémoire 16 bits
0Fh C2h /r imm8 | CMPPS xmm1,xmm2/m128,imm8 | Cette instruction permet d'effectuer une comparaison SIMD de 4 paquets de valeurs réels de simple précision d'une opérande source et d'une opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination.
0Fh C7h /1 m64 | CMPXCHG8B mem64 | Compare la paire de registres EDX:EAX à l'emplacement mémoire de 64 bits. S'ils sont égale, alors fixe le drapeau de zéro à 1 et copie ECX:EBX dans l'emplacement mémoire. Autrement, copie l'emplacement mémoire dans EDX:EAX et efface le drapeau de zéro.
0Fh C8h +rd | BSWAP reg32 | Cette instruction permet d'inverser l'ordre des octets du registre 32 bits
0Fh FFh | OIO | Cette instruction permet de provoquer l'exécution d'un code indéfinie.
10h (r/m8) | ADC r/m8 | Cette instruction additionne 2 quantités numérique sur 8 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu.
11h (r/m16) | ADC r/m16 | Cette instruction additionne 2 quantités numérique sur 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu.
12h (r/m8) | ADC r/m8 | Cette instruction additionne 2 quantités numérique sur 8 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu.
13h (r/m16) | ADC r/m16 | Cette instruction additionne 2 quantités numérique sur 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu.
14h (xxh) | ADC AL,xxh | Cette instruction additionne une valeur 8 bits immédiate au registre AL et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu.
15h (xxh) (yyh) | ADC AX,yyxxh | Cette instruction additionne une valeur 16 bits immédiate au registre AX et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu.
16h | PUSH SS | Cette instruction permet d'empiler le registre SS dans la pile.
17h | POP SS | Cette instruction permet de désempiler de la pile une mot et la met dans le registre SS.
18h (r/m8) | SBB r/m8 | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande.
19h (r/m16) | SBB r/m16 | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande.
1Ah (r/m8) | SBB r/m16 | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande.
1Bh (r/m16) | SBB r/m16 | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande.
1Ch (xxh) | SBB AL,xxh | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande.
1Dh (xxh) (yyh) | SBB AX,yyxxh | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande.
1Eh | PUSH DS | Cette instruction permet d'empiler le registre DS dans la pile.
1Fh | POP DS | Cette instruction permet de désempiler de la pile une mot et la met dans le registre DS.
20h (r/m8) | AND r/m8 | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés 8 bits.
21h (r/m16) | AND r/m16 | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés 16 bits.
22h (r/m8) | AND r/m8 | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés 8 bits.
23h (r/m16) | AND r/m16 | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés 16 bits.
24h (xxh) | AND AL,xxh | Cette instruction permet d'effectuer un ET BINAIRE sur le registre AL avec une valeur immédiate 8 bits.
25h (xxh) (yyh) | AND AX,yyxxh | Cette instruction permet d'effectuer un ET BINAIRE sur le registre AX avec une valeur immédiate 16 bits.
26h | ES: | Cette instruction permet d'indiquer un préfixe au registre segment ES.
27h | DAA | Ajuste les décimal du registre AL
2Eh | CS: | Cette instruction permet d'indiquer un préfixe au registre segment CS.
2Fh | DAS | Ajuste les décimal du registre AL après soustraction
36h | SS: | Cette instruction permet d'indiquer un préfixe au registre segment SS.
37h | AAA | Cette instruction permet de créer un nombre dépaqueté BCD
38h /r | CMP reg/mem8, reg8 | Compare le contenu d'une opérande mémoire ou d'un registre 8 bits avec un registre 8 bits.
39h /r | CMP reg/mem16, reg16 | Compare le contenu d'une opérande mémoire ou d'un registre 16 bits avec un registre 16 bits.
3Bh /r | CMP reg16, reg/mem16 | Compare le contenu d'une opérande mémoire ou d'un registre 16 bits avec un registre 16 bits.
3Ch ib | CMP AL, imm8 | Compare une valeur 8 bits immédiate avec le contenu du registre AL.
3Dh iw | CMP AX, imm16 | Compare une valeur 16 bits immédiate avec le contenu du registre AX.
3Eh | DS: | Cette instruction permet d'indiquer un préfix au registre segment DS.
3Fh | AAS | Cette instruction permet de créer un nombre dépacter BCD à partir du contenu du registre AL
40h | INC AX | Cette instruction permet d'incrémenter le registre AX.
41h | INC CX | Cette instruction permet d'incrémenter le registre CX.
42h | INC DX | Cette instruction permet d'incrémenter le registre DX.
43h | INC BX | Cette instruction permet d'incrémenter le registre BX.
44h | INC SP | Cette instruction permet d'incrémenter le registre SP.
45h | INC BP | Cette instruction permet d'incrémenter le registre BP.
46h | INC SI | Cette instruction permet d'incrémenter le registre SI.
47h | INC DI | Cette instruction permet d'incrémenter le registre DI.
48h | DEC AX | Cette instruction permet de décrémenter le registre AX.
49h | DEC CX | Cette instruction permet de décrémenter le registre CX.
4Ah | DEC DX | Cette instruction permet de décrémenter le registre DX.
4Bh | DEC BX | Cette instruction permet de décrémenter le registre BX.
4Ch | DEC SP | Cette instruction permet de décrémenter le registre SP.
4Dh | DEC BP | Cette instruction permet de décrémenter le registre BP.
4Eh | DEC SI | Cette instruction permet de décrémenter le registre SI.
4Fh | DEC DI | Cette instruction permet de décrémenter le registre DI.
50h | PUSH AX | Cette instruction permet d'empiler le registre AX dans la pile.
51h | PUSH CX | Cette instruction permet d'empiler le registre CX dans la pile.
52h | PUSH DX | Cette instruction permet d'empiler le registre DX dans la pile.
53h | PUSH BX | Cette instruction permet d'empiler le registre BX dans la pile.
54h | PUSH SP | Cette instruction permet d'empiler le registre SP dans la pile.
55h | PUSH BP | Cette instruction permet d'empiler le registre BP dans la pile.
56h | PUSH SI | Cette instruction permet d'empiler le registre SI dans la pile.
57h | PUSH DI | Cette instruction permet d'empiler le registre DI dans la pile.
58h | POP AX | Cette instruction permet de désempiler de la pile une mot et la met dans le registre AX.
59h | POP CX | Cette instruction permet de désempiler de la pile une mot et la met dans le registre CX.
5Ah | POP DX | Cette instruction permet de désempiler de la pile une mot et la met dans le registre DX.
5Bh | POP BX | Cette instruction permet de désempiler de la pile une mot et la met dans le registre BX.
5Ch | POP SP | Cette instruction permet de désempiler de la pile une mot et la met dans le registre SP.
5Dh | POP BP | Cette instruction permet de désempiler de la pile une mot et la met dans le registre BP.
5Eh | POP SI | Cette instruction permet de désempiler de la pile une mot et la met dans le registre SI.
5Fh | POP DI | Cette instruction permet de désempiler de la pile une mot et la met dans le registre DI.
61h | POPA | Cette instruction permet de désempiler de la pile respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX.
62h /r | BOUND reg16, mem16&mem16 | Test avec un index de tableau 16 bits spécifié deux valeurs 16 bits
63h /r | ARPL reg/mem16, reg16 | Ajuste le RPL du sélecteur de segment de destination au niveau inférieur du RPL du sélecteur de segment spécifié dans le registre source 16 bits.
64h | FS: | Cette instruction permet d'indiquer un préfixe au registre segment FS.
65h | GS: | Cette instruction permet d'indiquer un préfixe au registre segment GS.
66h 0Fh 2Ah /r | CVTPI2PD xmm, mm/m64 | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de double précision compacté.
66h 0Fh 2Ch /r | CVTTPD2PI mm, xmm/m128 | Cette instruction permet de convertir une valeur réel de double précision compacté avec tronquage en un entier de format double mot compacté.
66h 0Fh 2Dh /r | CVTPD2PI mm, xmm/m128 | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en double mot entier.
66h 0Fh 2Fh /r | COMISD xmm1,xmm2/m64 | Cette instruction permet de comparer deux valeurs réel de double-précision dans la partie faible du quadruple mot de deux opérande et fixe les drapeaux de ZF, PF et FC du registre EFLAGS en fonction du résultat (non-ordonnée, supérieur à, inférieur ou égal).
66h 0Fh 38h 14h /r | BLENDVPS xmm1,xmm2/m128,xmm0 | Cette instruction permet de copier le paquet de valeurs réel de simple précisions de l'opérande source dans l'opérande de destination si la condition de masque de l'opérande du troisième opérande en registre est rempli.
66h 0Fh 38h 15h /r | BLENDVPD xmm1,xmm2/m128,xmm0 | Cette instruction permet de copier le paquet de valeurs réel de double précisions de l'opérande source dans l'opérande de destination si la condition de masque de l'opérande du troisième opérande en registre est rempli.
66h 0Fh 38h DBh /r | AESIMC xmm1,xmm2/m128 | Cette instruction permet d'effectuer une transformation InvMixColumns de l'opérande source et enregistre le résultat dans l'opérande de destination.
66h 0Fh 38h DCh /r | AESENC xmm1,xmm2/m128 | Cette instruction permet d'effectuer un arrondissement d'encryptage AES en utilisant la clef arrondie pour le deuxième opérande source, opération dans une données de 128 bits du premier opérande source, et enregistre le résultat dans l'opérande de destination.
66h 0Fh 38h DDh /r | AESENCLAST xmm1,xmm2/m128 | Cette instruction permet d'effectuer le dernier arrondissement d'encryptage AES en utilisant la clef arrondie pour le deuxième opérande source, opération dans une données de 128 bits du premier opérande source, et enregistre le résultat dans l'opérande de destination.
66h 0Fh 38h DEh /r | AESDEC xmm1,xmm2/m128 | Cette instruction permet d'effectuer un arrondissement du décryptage AES en utilisant l'équivalence de Cipher inversé, avec un clef arrondie pour le deuxième opérande source, opération dans une données de 128 bits du premier opérande source, et enregistre le résultat dans l'opérande de destination.
66h 0Fh 38h DFh /r | AESDECLAST xmm1,xmm2/m128 | Cette instruction permet d'effectuer le dernier arrondissement du décryptage AES en utilisant l'équivalence de Cipher inversé, avec un clef arrondie pour le deuxième opérande source, opération dans une données de 128 bits du premier opérande source, et enregistre le résultat dans l'opérande de destination.
66h 0Fh 3Ah 0Ch /r ib | BLENDPS xmm1,xmm2/m128,imm8 | Cette instruction permet de copier le paquet de valeurs réel de simple précisions de l'opérande source dans l'opérande de destination si la condition de masque de l'opérande immédiate est rempli.
66h 0Fh 3Ah 0Dh /r ib | BLENDPD xmm1,xmm2/m128,imm8 | Cette instruction permet de copier le paquet de valeurs réel de double précisions de l'opérande source dans l'opérande de destination si la condition de masque de l'opérande immédiate est rempli.
66h 0Fh 3Ah 40h /r ib | DPPS xmm1,xmm2/m128,imm8 | Cette instruction permet d'effectuer une multiplication conditionnel d'un paquet de valeurs réel de simple précision dans l'opérande de destination avec le paquet de valeurs réel de l'opérande source et effectue un masque des bits extrait d'un opérande immédiat.
66h 0Fh 3Ah 41h /r ib | DPPD xmm1,xmm2/m128,imm8 | Cette instruction permet d'effectuer une multiplication conditionnel d'un paquet de valeurs réel de double précision dans l'opérande de destination avec le paquet de valeurs réel de l'opérande source et effectue un masque des bits extrait d'un opérande immédiat.
66h 0Fh 3Ah DFh /r ib | AESKEYGENASSIST xmm1,xmm2/m128,imm8 | Cette instruction permet d'effectuer l'expansion de clef AES Cipher, en calculant la génération des clefs arrondies pour l'encryption, en utilisant les données 128 bits spécifiés de l'opérande source et de la constante arrondie arrondie 8 bits spécifié immédiate et enregistre le résultat dans l'opérande de destination.
66h 0Fh 54h /r | ANDPD xmm1, xmm2/m128 | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 paquets d'opérandes de valeur de format réel de double précision.
66h 0Fh 55h /r | ANDNPD xmm1, xmm2/m128 | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 paquets d'opérandes de valeur de format réel de double précision et inverse chacun des bits du résultat.
66h 0Fh 58h /r | ADDPD xmm1, xmm2/m128 | Cette instruction permet d'effectuer une addition de 2 paquets de valeurs réels de double précision d'une opérande source et d'une opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de double précision.
66h 0Fh 5Ah /r | CVTPD2PS xmm1, xmm2/m128 | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en valeurs réel de simple précision et fixe à 0 le reste du paquet.
66h 0Fh 5Bh /r | CVTPS2DQ xmm1, xmm2/m128 | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de simple précision en paquet de double mots entiers.
66h 0Fh 5Eh /r | DIVPD xmm1, xmm2/m128 | Cette instruction permet d'effectuer une division de valeur réel de double précision de registre XMM ou d'emplacement mémoire de 128 bits.
66h 0Fh C2h /r ib | CMPPD xmm1,xmm2/m128,imm8 | Cette instruction permet d'effectuer une comparaison SIMD de 2 paquets de valeurs réels de double précision d'un opérande source et d'un opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination.
66h 0Fh D0h /r | ADDSUBPD xmm1, xmm2/m128 | Cette instruction permet d'effectuer une soustraction de la partie basse d'une valeur réel de double précision d'une opérande source et destination et entrepose le résultat dans une opérande de destination de valeur réel de double précision et d'effectuer une addition de la partie haute d'une valeur réel de double précision d'une opérande source et destination et entrepose le résultat dans une opérande de destination de valeur réel de double précision.
66h 0Fh E6h /r | CVTTPD2DQ xmm1, xmm2/m128 | Cette instruction permet de convertir un paquet de valeur réel de double précision avec en un paquet d'entier de format double mot tronquer et fixe à 0 le reste du paquet.
66h 60h | PUSHAD | Cette instruction permet d'empiler respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX dans la pile.
66h 61h | POPAD | Cette instruction permet de désempiler de la pile respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX.
66h 6Ch | INSD | Cette instruction permet de demander un double mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction.
66h 6Fh | OUTSD | Cette instruction permet d'envoyer un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 4 en fonction de l'état du drapeau de direction.
66h 98h | CWDE | Cette instruction est l'alternative pour convertir le mot du registre AX en un double mot contenu dans le registre EAX par extension du signe.
66h 99h | CDQ | Cette instruction permet de convertir le double mot en un quadruple mot, le résultat tient sur une taille de 64 bits.
66h 9Ch | PUSHFD | Cette instruction permet d'empiler respectivement le registre 32 bits de drapeau des indicateurs d'état dans la pile.
66h 9Dh | POPFD | Cette instruction permet de désempiler de la pile le registre 32 bits de drapeau contenant les indicateurs d'état.
66h A5h | MOVSD | Cette instruction permet de copier un double mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 4 en fonction de l'état du drapeau de direction.
66h A7h | CMPSD | Cette instruction permet d'effectuer la comparaison d'un double mot avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison.
66h ABh | STOSD | Cette instruction permet de copier le registre EAX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction.
66h ADh | LODSD | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 4 en fonction de l'état du drapeau de direction.
66h AFh | SCASD | Cette instruction permet de comparer le registre EAX avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction.
6Ch | INSB | Cette instruction permet de demander un octet du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction.
6Dh | INSW | Cette instruction permet de demander un mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction.
6Eh | OUTSB | Cette instruction permet d'envoyer un octet contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 1 en fonction de l'état du drapeau de direction.
6Fh | OUTSW | Cette instruction permet d'envoyer un mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 2 en fonction de l'état du drapeau de direction.
70h (rel8) | JO rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
71h (rel8) | JNO rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
72h (rel8) | JB/JNAE/JC rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
73h (rel8) | JNB/JAE/JNC rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
74h (rel8) | JZ/JE rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
75h (rel8) | JNZ/JNE rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
76h (rel8) | JBE/JNA rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
77h (rel8) | JNBE/JA rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
78h (rel8) | JS rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
79h (rel8) | JNS rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
7Ah (rel8) | JP/JPE rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
7Bh (rel8) | JNP/JPO rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
7Ch (rel8) | JL/JNGE rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
7Dh (rel8) | JNL/JGE rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
7Eh (rel8) | JLE/JNG rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
7Fh (rel8) | JNLE/JG rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
80h /0 ib | ADD reg/mem8, imm8 | Ajout immédiate de 8 bits à registre/mémoire 8 bits
80h /2 ib | ADC reg/mem8, imm8 | Cette instruction permet d'ajouter un immédiat de 8 bits à un registre/mémoire + CF
80h /4 ib | AND reg/mem8, imm8 | Et binaire sur le contenu du registre/mémoire 8 bits avec une valeur immédiate 8 bits
80h /7 ib | CMP reg/mem8, imm8 | Compare une valeur 8 bits immédiate avec le contenu d'une opérande mémoire ou d'un registre 8 bits.
81h /0 iw | ADD reg/mem16, imm16 | Ajout immédiate de 16 bits à registre/mémoire 16 bits
81h /2 iw | ADC reg/mem16, imm16 | Cette instruction permet d'ajouter un immédiat de 16 bits à registre/mémoire 16 bits + CF
81h /4 iw | AND reg/mem16, imm16 | Et binaire sur le contenu du registre/mémoire 16 bits avec une valeur immédiate 16 bits
81h /7 iw | CMP reg/mem16, imm16 | Compare une valeur 16 bits immédiate avec le contenu d'une opérande mémoire ou d'un registre 16 bits.
83h /0 ib | ADD reg/mem16, imm8 | Ajout entier immédiate de 8 bits à registre/mémoire 16 bits
83h /2 ib | ADC reg/mem16, imm8 | Cette instruction permet d'ajouter un immédiat de 8 bits entier à registre/mémoire 16 bits + CF
83h /4 ib | AND reg/mem16, imm8 | Et binaire sur le contenu du registre/mémoire 16 bits avec une valeur entière immédiate 8 bits
90h | NOP | Cette instruction ne fait rien.
91h | XCHG AX,CX | Cette instruction permet d'échanger les valeurs des registres AX et CX
92h | XCHG AX,DX | Cette instruction permet d'échanger les valeurs des registres AX et DX
94h | XCHG AX,SP | Cette instruction permet d'échanger les valeurs des registres AX et SP
95h | XCHG AX,BP | Cette instruction permet d'échanger les valeurs des registres AX et BP
96h | XCHG AX,SI | Cette instruction permet d'échanger les valeurs des registres AX et SI
97h | XCHG AX,DI | Cette instruction permet d'échanger les valeurs des registres AX et DI
98h | CBW | Cette instruction permet de convertir un nombre contenu dans le registre AL en un format sur 16 bits pour se retrouver dans le registre AX en appliquant une extension du signe.
99h | CWD | Cette instruction est l'alternative pour convertir le mot du registre AX en un double mot contenu dans le couple de registre DX et AX par extension du signe.
9Ah {immW2} {immW1} | CALL immW1:immW2 | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse d'appel avant de continuer.
9Bh | WAIT | Cette instruction permet de faire passer le microprocesseur en mode d'attente jusqu'à ce que la ligne de teste sur la carte mère s'active.
9Bh DBh E0h | FENI | Cette instruction permet d'autoriser les interruptions.
9Bh DBh E1h | FDISI | Cette instruction permet de désactiver les interruptions.
9Bh DBh E2h | FCLEX | Cette instruction permet d'effacer toutes les exceptions contenu dans les drapeaux de registres du coprocesseur mathématique.
9Ch | PUSHF | Cette instruction permet d'empiler respectivement le registre 16 bits de drapeau des indicateurs d'état dans la pile.
9Dh | POPF | Cette instruction permet de désempiler de la pile le registre 16 bits de drapeau contenant les indicateurs d'état.
9Eh | SAHF | Cette instruction permet de copier les bits du registre AH dans l'octet de poids faible dans le registre des drapeaux (les indicateurs d'état).
9Fh | LAHF | Cette instruction permet de transférer les bits d'indicateurs du registre d'état vers le registre AH.
A0h xxh yyh | MOV AL,[yyxxh] | ...
A1h xxh yyh | MOV AX,[yyxxh] | ...
A2h xxh yyh | MOV [yyxxh],AL | ...
A3h xxh yyh | MOV [yyxxh],AX | ...
A4h | MOVSB | Cette instruction permet de copier un octet de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 1 en fonction de l'état du drapeau de direction.
A5h | MOVSW | Cette instruction permet de copier un mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 2 en fonction de l'état du drapeau de direction.
A6h | CMPSB | Cette instruction permet d'effectuer la comparaison d'un octet avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison.
A7h | CMPSW | Cette instruction permet d'effectuer la comparaison d'un mot avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison.
A8h xxh | TEST AL,xxh | Cette instruction permet d'effectuer un test de «Et binaire» avec une valeur immédiate de 8 bits sur le registre AL et indique le résultat de la comparaison sur le registre des drapeaux.
A9h xxh yyh | TEST AX,yyxxh | Cette instruction permet d'effectuer un test de «Et binaire» avec une valeur immédiate de 16 bits sur le registre AX et indique le résultat de la comparaison sur le registre des drapeaux.
AAh | STOSB | Cette instruction permet de copier le registre AL dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction.
ABh | STOSW | Cette instruction permet de copier le registre AX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction.
ACh | LODSB | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 1 en fonction de l'état du drapeau de direction.
ADh | LODSW | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 2 en fonction de l'état du drapeau de direction.
AEh | SCASB | Cette instruction permet de comparer le registre AL avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction.
AFh | SCASW | Cette instruction permet de comparer le registre AX avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction.
B0h xxh | MOV AL,xxh | Cette instruction permet de copier une valeur immédiate de 8 bits dans le registre AL.
B1h xxh | MOV CL,xxh | Cette instruction permet de copier une valeur immédiate de 8 bits dans le registre CL.
B2h xxh | MOV DL,xxh | Cette instruction permet de copier une valeur immédiate de 8 bits dans le registre DL.
B3h xxh | MOV BL,xxh | Cette instruction permet de copier une valeur immédiate de 8 bits dans le registre BL.
B4h xxh | MOV AH,xxh | Cette instruction permet de copier une valeur immédiate de 8 bits dans le registre AH.
B5h xxh | MOV CH,xxh | Cette instruction permet de copier une valeur immédiate de 8 bits dans le registre CH.
B6h xxh | MOV DH,xxh | Cette instruction permet de copier une valeur immédiate de 8 bits dans le registre DH.
B7h xxh | MOV BH,xxh | Cette instruction permet de copier une valeur immédiate de 8 bits dans le registre BH.
B8h xxh yyh | MOV AX,yyxxh | Cette instruction permet de copier une valeur immédiate de 16 bits dans le registre AX.
B9h xxh yyh | MOV CX,yyxxh | Cette instruction permet de copier une valeur immédiate de 16 bits dans le registre CX.
BAh xxh yyh | MOV DX,yyxxh | Cette instruction permet de copier une valeur immédiate de 16 bits dans le registre DX.
BBh xxh yyh | MOV BX,yyxxh | Cette instruction permet de copier une valeur immédiate de 16 bits dans le registre BX.
BCh xxh yyh | MOV SP,yyxxh | Cette instruction permet de copier une valeur immédiate de 16 bits dans le registre SP.
BDh xxh yyh | MOV BP,yyxxh | Cette instruction permet de copier une valeur immédiate de 16 bits dans le registre BP.
BEh xxh yyh | MOV SI,yyxxh | Cette instruction permet de copier une valeur immédiate de 16 bits dans le registre SI.
BFh xxh yyh | MOV DI,yyxxh | Cette instruction permet de copier une valeur immédiate de 16 bits dans le registre DI.
C3h | RETN | Cette instruction permet de quitter une procédure ayant lieu avec un appel court (NEAR CALL).
C8h iw ib | ENTER imm16, imm8 | Crée un cadre de pile pour une procédure
C9h | LEAVE | Cette instruction permet de libérer une zone de mémoire attribué par l'instruction «ENTER» lorsqu'on utilise des procédures dans des langages de programmation de haut niveau.
CAh xxh yyh | RETF yyxxh | Cette instruction permet de quitter une procédure ayant lieu avec un appel long (FAR CALL).
CBh | RETF | Cette instruction permet de quitter une procédure ayant lieu avec un appel long (FAR CALL).
CCh | INT 03h | Cette instruction permet d'exécuter l'interruption avec le numéro 03h.
CDh xxh | INT xxh | Cette instruction permet d'exécuter l'interruption avec le numéro spécifié.
CEh | INTO | Cette instruction permet d'exécuter l'interruption numéro 4 si le drapeau de débordement (OF) est fixé sur 1.
CFh | IRET | Cette instruction permet d'effectuer un retour précédemment provoquer par une interruption.
D4h 0Ah | AAM | Cette instruction offre la possibilité de convertir le produit de la multiplication de 2 valeurs de format DCB en un format DCB.
D5h 0Ah | AAD | Cette instruction permet de convertir une valeur de format DCB non compactée.
D6h | SETALC (SALC) | Cette instruction permet de copier la valeur du drapeau de retenue dans le registre AL en la multipliant par 0FFh.
D7h | XLAT | Cette instruction permet de remplacer le contenu du registre AL par un octet de la «tablesource».
D8h /0 | FADD mem32 | Cette instruction permet d'ajouter le nombre réel de valeur positive «source» à «cible» et enregistre la somme dans «cible».
D8h /2 | FCOM mem32 | Cette instruction permet de comparer le nombre réel de valeur positive source avec le registre mathématique ST(0) et mettre les indicateurs d'état C0 à C3 avec la valeur 1.
D8h /3 | FCOMP mem32 | Cette instruction permet de comparer le nombre réel de valeur positive «source» avec le registre mathématique ST(0), mettre les indicateurs d'état C0 à C3 avec la valeur 1 et dépile le registre mathématique ST(0) de la pile de registres.
D8h /6 | FDIV mem32 | Cette instruction permet d'effectuer des divisions de nombre réel de valeur positive source par cible et enregistrer le résultat dans cible.
D8h /7 | FDIVR mem32 | Cette instruction permet d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».
D8h 06h yyh xxh imm8 | ESC [xxyy],imm8 | Cette instruction active le coprocesseur, lequel se permettra d'utiliser les méthodes d'adressage du processeur principal (CPU).
D8h (C0h+r) | FADD fpureg | Cette instruction permet d'ajouter le nombre réel de valeur positive «source» à «cible» et enregistre la somme dans «cible».
D8h (D0h+r) | FCOM fpureg | Cette instruction permet de comparer le nombre réel de valeur positive source avec le registre mathématique ST(0) et mettre les indicateurs d'état C0 à C3 avec la valeur 1.
D8h (D8h+r) | FCOMP fpureg | Cette instruction permet de comparer le nombre réel de valeur positive «source» avec le registre mathématique ST(0), mettre les indicateurs d'état C0 à C3 avec la valeur 1 et dépile le registre mathématique ST(0) de la pile de registres.
D8h (F0h+r) | FDIV fpureg | Cette instruction permet d'effectuer des divisions de nombre réel de valeur positive source par cible et enregistrer le résultat dans cible.
D8h (F8h+r) | FDIVR fpureg | Cette instruction permet d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».
D9h E0h | FCHS | Cette instruction permet d'inverser le signe du registre mathématique ST(0).
D9h E1h | FABS | Cette instruction permet de convertir le nombre réel contenu dans le registre mathématique ST(0) en sa valeur absolue.
D9h F0h | F2XM1 | Cette instruction permet de remplacer ST(0) avec 2 à la (ST(0) - 1).
D9h F6h | FDECSTP | Cette instruction permet de décrémenter le pointeur de pile de registres.
D9h FFh | FCOS | Cette instruction permet de calculer le cosinus du registre mathématique ST(0) et l'enregistrer dans le registre mathématique ST(1); ensuite met dans le registre mathématique ST(0) à la valeur 1,0.
DAh /0 | FIADD mem32 | Cette instruction permet d'ajouter le nombre réel source à cible et enregistre la somme dans cible.
DAh (C0h+i) | FCMOVB ST,STi | Cette instruction permet de déplacé des nombres réel si inférieur.
DAh (C8h+i) | FCMOVE ST,STi | Cette instruction permet de déplacé des nombres réel si égale.
DAh (D0h+i) | FCMOVBE ST,STi | Cette instruction permet de déplacé des nombres réel si inférieur ou égale.
DAh (D8h+i) | FCMOVU ST,STi | Cette instruction permet de déplacé des nombres réel si désordonné.
DBh (C0h+i) | FCMOVNB ST,STi | Cette instruction permet de déplacé des nombres réel si pas inférieur.
DBh (C8h+i) | FCMOVNE ST,STi | Cette instruction permet de déplacé des nombres réel si pas égale.
DBh (D0h+i) | FCMOVNBE ST,STi | Cette instruction permet de déplacé des nombres réel si pas inférieur ou égale.
DBh (D8h+i) | FCMOVNU ST,STi | Cette instruction permet de déplacé des nombres réel si pas désordonné.
DBh E4h | FSETPM | Cette instruction permet de faire passer le coprocesseur mathématique en mode protégé.
DBh (E8h+i) | FUCOMI ST, ST(i) | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et vérifie l'ordre des valeurs et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats.
DBh (F0h+i) | FCOMI ST, ST(i) | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats.
DCh /0 | FADD mem64 | Cette instruction permet d'ajouter le nombre réel de valeur positive «source» à «cible» et enregistre la somme dans «cible».
DCh /2 | FCOM mem64 | Cette instruction permet de comparer le nombre réel de valeur positive source avec le registre mathématique ST(0) et mettre les indicateurs d'état C0 à C3 avec la valeur 1.
DCh /3 | FCOMP mem64 | Cette instruction permet de comparer le nombre réel de valeur positive «source» avec le registre mathématique ST(0), mettre les indicateurs d'état C0 à C3 avec la valeur 1 et dépile le registre mathématique ST(0) de la pile de registres.
DCh /6 | FDIV mem64 | Cette instruction permet d'effectuer des divisions de nombre réel de valeur positive source par cible et enregistrer le résultat dans cible.
DCh /7 | FDIVR mem64 | Cette instruction permet d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».
DCh (C0h+r) | FADD fpureg,ST0 | Cette instruction permet d'ajouter le nombre réel de valeur positive «source» à «cible» et enregistre la somme dans «cible».
DCh (F0h+r) | FDIVR fpureg,ST0 | Cette instruction permet d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».
DCh (F8h+r) | FDIV fpureg,ST0 | Cette instruction permet d'effectuer des divisions de nombre réel de valeur positive source par cible et enregistrer le résultat dans cible.
DDh (C0h+r) | FFREE fpureg | Cette instruction permet de libérer le registre «cible» devant représenté un des registres de la pile.
DEh /0 | FIADD mem16 | Cette instruction permet d'ajouter le nombre réel source à cible et enregistre la somme dans cible.
DEh (C0h+r) | FADDP fpureg | Cette instruction complémentaire ajoute le nombre réel source au nombre réel cible et enregistrer la somme dans cible puis prendre le registre mathématique ST(0) et le dépile.
DEh D9h | FCOMPP | Cette instruction permet de comparer les nombres réels du registre mathématique ST(1) avec le registre mathématique ST(0), ensuite de mettre les indicateurs d'état C0 à C3 à la valeur 1 et prendre le couple de registre mathématique ST(1) et ST(0) dans la pile de registres (2 dépilages).
DEh (F0h+r) | FDIVRP fpureg | Cette instruction permet d'effectuer des divisions de nombre réel avec les registres inversés «cible» par «source» et place ST(0) dans la pile.
DEh F1h | FDIVRP | Cette instruction permet d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».
DEh (F8h+r) | FDIVP fpureg | Cette instruction permet d'effectuer des division de nombre réel et place ST(0) dans la pile.
DFh /4 | FBLD mem80 | Cette instruction charge la valeur de format DCB compactée après le registre mathématique ST(0).
DFh /6 | FBSTP mem80 | Cette instruction extrait la valeur de format DCB compactée du registre mathématique ST(0), l'enregistrer dans cible et prendre le registre mathématique ST(0) et sort de la pile.
DFh (C0h+r) | FFREEP fpureg | Cette instruction permet de libérer un des registres de la pile et d'ensuite de désempiler le registre de la pile.
DFh (E8h+i) | FUCOMIP ST, ST(i) | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et vérifie l'ordre des valeurs et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats et désempile de la pile la valeur dans le registre.
DFh (F0h+i) | FCOMIP ST, ST(i) | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats et désempile de la pile la valeur dans le registre.
E8h iw | CALL rel16off | Appel court avec une destination spécifié par une adresse 16 bits
EBh (rel8) | JMP rel8 | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié.
ECh | IN AL,DX | Cette instruction permet de lire un octet dans un port d'entrée/sortie à l'adresse spécifié par le registre DX et met le résultat dans le registre AL.
EDh | IN AX,DX | Cette instruction permet de lire un mot dans un port d'entrée/sortie à l'adresse spécifié par le registre DX et met le résultat dans le registre AX.
EEh | OUT DX,AL | Cette instruction permet de mettre un octet contenu dans le registre AL dans le port spécifié par le registre DX.
EFh | OUT DX,AX | Cette instruction permet de mettre un mot contenu dans le registre AX dans le port spécifié par le registre DX.
F0h | LOCK | Cette instruction est utilisé comme préfixe avec d'autres instructions pour amener le microprocesseur à émettre un signal de verrouillage (Lock) sur le bus lors du traitement de l'instruction suivante.
F1h | SMI | Cette instruction permet de gérer les interruptions systèmes en mode de débogage.
F1h | ICEBP | Cette instruction permet de passer en mode d'instruction ICE (In-Circuit Emulator) si le bit 12 du registre DR7 vaut 1 sinon il exécute l'interruption 1.
F2h | REPNE | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1.
F2h 0Fh 2Ah /r | CVTSI2SD xmm, r/m32 | Cette instruction permet de convertir un entier de format double mot en une valeur réel de double précision.
F2h 0Fh 2Ch /r | CVTTSD2SI r32, xmm/m64 | Cette instruction permet de convertir une valeur réel de double précision avec en un entier de format double mot tronquer.
F2h 0Fh 2Dh /r | CVTSD2SI r32, xmm/m64 | Cette instruction permet d'effectuer la conversion d'une valeur réel de simple précision en valeur entier de double mots.
F2h 0Fh 38h F0h /r | CRC32 r32, r/m8 | Cette instruction débute avec une valeur initiale dans l'opérande de destination, accumule une valeur de code CRC-32 (polynomial de 11EDC6F41h) dans l'opérande source et enregistre le résultat dans l'opérande de destination.
F2h 0Fh 38h F1h /r | CRC32 r32, r/m16 | Cette instruction débute avec une valeur initiale dans l'opérande de destination, accumule une valeur de code CRC-32 (polynomial de 11EDC6F41h) dans l'opérande source et enregistre le résultat dans l'opérande de destination.
F2h 0Fh 58h /r | ADDSD xmm1, xmm2/m128 | Cette instruction permet d'effectuer une addition de la partie basse d'une valeur réel de double précision d'une opérande source et destination et entrepose le résultat dans une opérande de destination de valeur réel de double précision.
F2h 0Fh 5Ah /r | CVTSD2SS xmm1, xmm2/m64 | Cette instruction permet d'effectuer la conversion d'une valeur réel de double précision en valeur réel de simple précision.
F2h 0Fh 5Eh /r | DIVSD xmm1, xmm2/m64 | Cette instruction permet d'effectuer une division scalaire de valeur réel de double précision de registre XMM ou d'emplacement mémoire de 128 bits.
F2h 0Fh C2h /r ib | CMPSD xmm1,xmm2/m64, imm8 | Cette instruction permet d'effectuer une comparaison de la partie basse de valeurs réelles de double précision d'un opérande source et d'un opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination.
F2h 0Fh D0h /r | ADDSUBPS xmm1, xmm2/m128 | Cette instruction permet d'effectuer une soustraction de la partie basse d'un paquet de valeur réel de simple précision d'une opérande source et destination et entrepose le résultat dans une opérande de destination de valeur réel de simple précision et d'effectuer une addition de la partie haute d'un paquet de valeur réel de simple précision d'une opérande source et destination et entrepose le résultat dans une opérande de destination de valeur réel de simple précision.
F2h 0Fh E6h | CVTPD2DQ xmm1, xmm2/m128 | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en double mot entier et fixe à 0 le reste du paquet.
F3h | REP | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions tant que CX ne vaut pas 0.
F3h 0Fh 2Ah /r | CVTSI2SS xmm,r/m32 | Cette instruction permet de convertir un entier de format double mot en une valeur réel de simple précision.
F3h 0Fh 2Ch /r | CVTTSS2SI r32,xmm/m32 | Cette instruction permet de convertir un entier de format double mot avec tronquage en une valeur réel de simple précision.
F3h 0Fh 2Dh /r | CVTSS2SI r32,xmm/m32 | Cette instruction permet de convertir une valeur réel de simple précision en un entier de format double mot.
F3h 0Fh 58h /r | ADDSS xmm1, xmm2/m32 | Cette instruction permet d'ajouter la partie basse d'une valeur réel de simple précision de xmm2/m32 to xmm1.
F3h 0Fh 5Ah /r | CVTSS2SD xmm1, xmm2/m32 | Cette instruction permet de convertir une valeur réel de simple précision en une valeur réel de double précision.
F3h 0Fh 5Bh /r | CVTTPS2DQ xmm1, xmm2/m128 | Cette instruction permet de convertir un paquet de valeur réel de simple précision avec en un paquet d'entier de format double mot tronquer.
F3h 0Fh 5Eh /r | DIVSS xmm1,xmm2/m128 | Cette instruction permet d'effectuer une division scalaire de valeur réel de simple précision de registre XMM ou d'emplacement mémoire de 128 bits.
F3h 0Fh B8h /r | POPCNT reg16, reg/mem16 | Cette instruction permet de compter le nombre de bits à 1 que possède une opérande source et place le résultat dans un registre destinataire.
F3h 0Fh C2h /r imm8 | CMPSS xmm1,xmm2/m128,imm8 | Cette instruction permet d'effectuer une comparaison de la partie basse de valeurs réels de simple précision d'une opérande source et d'une opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination.
F3h 0Fh E6h | CVTDQ2PD xmm1, xmm2/m64 | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de double précision.
F3h 90h | PAUSE | Cette instruction permet d'améliorer les performances des boucles de «SPIN», en fournissant une indication pour le microprocesseur que le code courant est dans une boucle en «SPIN».
F4h | HLT | Cette instruction permet de faire passer le microprocesseur en mode d'arrêt. Toutefois, le processeur peut quitter cet état lorsqu'une ligne matérielle RESET ou lorsqu'une interruption non-masquable (NMI) reçoit un signal.
F5h | CMC | Cette instruction offre la possibilité d'inverser la valeur de l'indicateur de retenue. Si ce dernier vaut 1, elle le met à 0 et inversement.
F6h /6 | DIV reg/mem8 | Division naturel de AX par le contenu d'un emplacement mémoire ou registre 8 bits et entrepose le quotient dans AL et restant dans AH.
F7h /6 | DIV reg/mem16 | Division naturel de DX:AX par le contenu d'un emplacement mémoire ou registre 16 bits et entrepose le quotient dans AX et restant dans DX.
F8h | CLC | Cette instruction permet de mettre l'indicateur d'état de retenu CF à 0.
F9h | STC | Cette instruction permet de fixer l'indicateur de retenue (CF) à la valeur 1.
FAh | CLI | Cette instruction met l'indicateur d'état IF à 0, soit l'interdiction des interruptions.
FBh | STI | Cette instruction permet de fixer l'indicateur d'interruption (IF) à la valeur 1.
FCh | CLD | Cette instruction met l'indicateur d'état DF à 0, soit la direction croissante.
FDh | STD | Cette instruction permet de fixer l'indicateur de direction (DF) à la valeur 1.
FEh /1 | DEC reg/mem8 | Décrémente de 1 le contenu d'un emplacement de registre ou mémoire 8 bits
FFh /1 | DEC reg/mem16 | Décrémente de 1 le contenu d'un emplacement de registre ou mémoire 16 bits
FFh /2 | CALL reg/mem16 | Appel court avec une destination spécifié par un registre/mémoire 16 bits
FFh /3 | CALL FAR mem16:16 | Appel long indirect, avec un destination spécifié par un pointeur long en mémoire.
... | ... | ...

Références

Assembleur - Référence, Edition Micro Application, Pierre Maurette, 2003, ISBN: 2-7429-3061-2.
The Undocumented PC: A programmer's Guide to I/O, CPUs, and Fixed Memory Areas - Second Edition, Edition Addison-Wesley, Frank van Gilluwe, 1997, ISBN: 0-201-47950-8.

Dernière mise à jour : Samedi, le 21 décembre 2013


Langage de programmation - Assembleur 80x86 - Lexique et dictionnaire d'instruction assembleur 80x86 - Vue par cycle d'horloge

Vu dans ... http://www.gladir.com Ce tableau indique en fonction de l'opérande le nombre de cycle d'horloge que prend le micro-processeur pour effectuer l'opération.
La taille minimum et maximum est exprimé en octets; chaque "X" représente 1 octet, il faut donc additionner la somme ou regarder le chiffre à côté.

Opérandes | Description | 8088 | 8086 | 80286 | 80386DX | Taille minimum | Taille maximum
AAA | Cette instruction permet d'adapter le résultat obtenu par l'addition de 2 valeur en format DCB. | 8 | 8 | 3 | 4 | X | X
AAD | Cette instruction permet de convertir une valeur de format DCB non compactée. | 60 | 60 | 14 | 19 | XX | XX
AAM | Cette instruction offre la possibilité de convertir le produit de la multiplication de 2 valeurs de format DCB en un format DCB. | 83 | 83 | 16 | 17 | XX | XX
AAS | Cette instruction permet d'adapter le résultat de la soustraction de nombre de format DCB. | 8 | 8 | 3 | 4 | X | X
ADC registre,registre | Cette instruction additionne 2 quantités numériques sur 8 ou 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu. | 3 | 3 | 2 | 2 | XX | XX
ADC mémoire,registre | Cette instruction additionne 2 quantités numériques sur 8 ou 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu. | 24+EA | 16+EA | 7 | 7 | XX | XXXX
ADC registre,mémoire | Cette instruction additionne 2 quantités numériques sur 8 ou 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu. | 13+EA | 9+EA | 7 | 6 | XX | XXXX
ADC registre,immédiat | Cette instruction additionne 2 quantités numériques sur 8 ou 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu. | 4 | 4 | 3 | 2 | XXX | XXXX
ADC mémoire,immédiat | Cette instruction additionne 2 quantités numériques sur 8 ou 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu. | 23+EA | 17+EA | 7 | 7 | XXX | XXXXXX
ADC accumulateur,immédiat | Cette instruction additionne 2 quantités numériques sur 8 ou 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu. | 4 | 4 | 3 | 2 | XX | XXX
ADD registre,registre | Cette instruction additionne 2 quantités numérique sur 8, 16 ou 32 bits. | 3 | 3 | 2 | 2 | XX | XXX
ADD mémoire,registre | Cette instruction additionne 2 quantités numérique sur 8, 16 ou 32 bits. | 24+EA | 16+EA | 7 | 7 | XX | XXXX
ADD registre,mémoire | Cette instruction additionne 2 quantités numérique sur 8, 16 ou 32 bits. | 13+EA | 9+EA | 7 | 6 | XX | XXXX
ADD registre,immédiat | Cette instruction additionne 2 quantités numérique sur 8, 16 ou 32 bits. | 4 | 4 | 3 | 2 | XXX | XXXX
ADD mémoire,immédiat | Cette instruction additionne 2 quantités numérique sur 8, 16 ou 32 bits. | 23+EA | 17+EA | 7 | 7 | XXX | XXXXXX
ADD accumulateur,immédiat | Cette instruction additionne 2 quantités numérique sur 8, 16 ou 32 bits. | 4 | 4 | 3 | 2 | XX | XXX
AND registre,registre | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés. | 3 | 3 | 2 | 2 | XX | XX
AND mémoire,registre | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés. | 24+EA | 16+EA | 7 | 7 | XX | XXXX
AND registre,mémoire | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés. | 13+EA | 9+EA | 7 | 6 | XX | XXXX
AND registre,immédiat | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés. | 4 | 4 | 3 | 2 | XXX | XXXX
AND mémoire,immédiat | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés. | 23+EA | 17+EA | 7 | 7 | XXX | XXXXXX
AND accumulateur,immédiat | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés. | 4 | 4 | 3 | 2 | XX | XXX
ARPL registre,registre | Cette instruction permet de contrôler et corriger le niveau de privilège du segment de code en mode protégée. | - | - | 10 | 20 | XX | XX
ARPL mémoire,registre | Cette instruction permet de contrôler et corriger le niveau de privilège du segment de code en mode protégée. | - | - | 11 | 21 | XXXX | XXXX
BOUND registre16,mém32 | Cette instruction permet de vérifier la validité pouvant exister entre avec un tableau et son indexation. | - | - | ~13 | ~10 | XX | XX
BOUND registre32,mém64 | Cette instruction permet de vérifier la validité pouvant exister entre avec un tableau et son indexation. | - | - | ~13 | ~10 | XX | XX
BSF registre,registre | Cette instruction permet d'effectuer une comparaison binaire de la droite vers la gauche. | - | - | - | 10+3nano | XXX | XXX
BSF registre,mémoire | Cette instruction permet d'effectuer une comparaison binaire de la droite vers la gauche. | - | - | - | 10+3nano | XXX | XXXXXX
BSR registre,registre | Cette instruction permet d'effectuer une comparaison binaire de la gauche vers la droite. | - | - | - | 10+3nano | XXX | XXX
BSR registre,mémoire | Cette instruction permet d'effectuer une comparaison binaire de la gauche vers la droite. | - | - | - | 10+3nano | XXX | XXXXXX
BT registre16,immédiat8 | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue. | - | - | - | 3 | XXXX | XXXXXXXX
BT mémoire16,immédiat8 | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue. | - | - | - | 6 | XXXX | XXXXXXXX
BT registre16,registre16 | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue. | - | - | - | 3 | XXX | XXXXXXX
BT mémoire16,registre16 | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue. | - | - | - | 12 | XXX | XXXXXXX
BTC registre16,immédiat8 | Cette instruction transfére une Opérande vers l'indicateur de retenue le bits spécifié et inverser la valeur du bit correspondant. | - | - | - | 3 | XXXX | XXXXXXXX
BTC mémoire16,immédiat8 | Cette instruction transfére une Opérande vers l'indicateur de retenue le bits spécifié et inverser la valeur du bit correspondant. | - | - | - | 6 | XXXX | XXXXXXXX
BTC registre16,registre16 | Cette instruction transfére une Opérande vers l'indicateur de retenue le bits spécifié et inverser la valeur du bit correspondant. | - | - | - | 3 | XXX | XXXXXXX
BTC mémoire16,registre16 | Cette instruction transfére une Opérande vers l'indicateur de retenue le bits spécifié et inverser la valeur du bit correspondant. | - | - | - | 1 | XXX | XXXXXXX
BTR registre16,immédiat8 | Cette instruction permet de transférer l'Opérande vers l'indicateur de retenue le bits spécifié puis met le bits correspondant de l'Opérande à 0. | - | - | - | 6 | XXXX | XXXXXXXX
BTR mémoire16,immédiat8 | Cette instruction permet de transférer l'Opérande vers l'indicateur de retenue le bits spécifié puis met le bits correspondant de l'Opérande à 0. | - | - | - | 8 | XXXX | XXXXXXXX
BTR registre16,registre16 | Cette instruction permet de transférer l'Opérande vers l'indicateur de retenue le bits spécifié puis met le bits correspondant de l'Opérande à 0. | - | - | - | 6 | XXX | XXXXXXX
BTR mémoire16,registre16 | Cette instruction permet de transférer l'Opérande vers l'indicateur de retenue le bits spécifié puis met le bits correspondant de l'Opérande à 0. | - | - | - | 1 | XXX | XXXXXXX
BTS registre16,immédiat8 | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue le bits spécifié puis ensuite met le bits correspondant dans Opérande à 1. | - | - | - | 6 | XXXX | XXXXXXXX
BTS mémoire16,immédiat8 | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue le bits spécifié puis ensuite met le bits correspondant dans Opérande à 1. | - | - | - | 8 | XXXX | XXXXXXXX
BTS registre16,registre16 | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue le bits spécifié puis ensuite met le bits correspondant dans Opérande à 1. | - | - | - | 6 | XXX | XXXXXXX
BTS mémoire16,registre16 | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue le bits spécifié puis ensuite met le bits correspondant dans Opérande à 1. | - | - | - | 1 | XXX | XXXXXXX
CALL Near Procedure | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse d'appel en fonction de l'instruction de segment avant de continuer. | 23 | 19 | 7+m | 7+m | XXX | XXX
CALL Far Procedure | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse d'appel avant de continuer. | 36 | 28 | 13+m | 17+m | XXXXX | XXXXX
CALL registre | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse définit par le registre et l'instruction de segment avant de continuer. | 20 | 16 | 7+m | 7+m | XX | XX
CALL mémoire16 | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse définit par l'emplacement mémoire et l'instruction de segment avant de continuer. | 29+EA | 21+EA | 11+m | 10+m | XX | XXXX
CALL mémoire32 | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse définit par l'emplacement mémoire et l'instruction de segment avant de continuer. | 53+EA | 37+EA | 11+m | 10+m | XX | XXXX
CBW | Cette instruction permet de convertir un nombre contenu dans le registre AL en un format sur 16 bits pour se retrouver dans le registre AX en appliquant une extension du signe. | 2 | 2 | 2 | 3 | X | X
CDQ | Transforme un double mot en quadruple mot | - | - | - | 2 | X | X
CLC | Cette instruction permet de mettre l'indicateur d'état de retenu CF à 0. | 2 | 2 | 2 | 2 | X | X
CLD | Cette instruction met l'indicateur d'état DF à 0, soit la direction croissante. | 2 | 2 | 2 | 2 | X | X
CLI | Cette instruction met l'indicateur d'état IF à 0, soit l'interdiction des interruptions. | 2 | 2 | 2 | 3 | X | X
CLTS | Cette instruction permet de mettre à 0 le drapeau de l'indicateur de tâche (Task-Switch) du registre CR0. | - | - | 2 | 5 | X | X
CMC | Cette instruction offre la possibilité d'inverser la valeur de l'indicateur de retenue. Si ce dernier vaut 1, elle le met à 0 et inversement. | 2 | 2 | 2 | 3 | X | X
CMP registre,registre | Cette instruction offre la possibilité essentielle de comparer 2 registres. | 3 | 2 | 2 | 2 | XX | XX
CMP mémoire,registre | Cette instruction offre la possibilité essentielle de comparer 2 registres ou emplacements de mémoire. | 13+EA | 9+EA | 7 | 5 | XX | XXXX
CMP registre,mémoire | Cette instruction offre la possibilité essentielle de comparer 2 registres ou emplacements de mémoire. | 13+EA | 9+EA | 7 | 5 | XX | XXXX
CMP registre,immédiat | Comparaison | 4 | 4 | 3 | 2 | XXX | XXXX
CMP mémoire,immédiat | Comparaison | 14+EA | 10+EA | 6 | 5 | XXX | XXXXXX
CMP accumulateur,immédiat | Comparaison | 4 | 4 | 3 | 2 | XX | XXX
CMPS destination,source | Comparaison de chaîne de caractères | 22 | 22 | 8 | 10 | X | X
CWD | Conversion d'un mot en double mot | 5 | 5 | 2 | 2 | X | X
CWDE | Conversion d'un double mot en quadruple mot | - | - | - | 3 | X | X
DAA | Cette instruction corrige après coup les retenues lors de la manipulation de valeur DCB. | 4 | 4 | 3 | 4 | X | X
DAS | Cette instruction offre l'intéressante possibilité de corrige le résultat d'une soustraction de 2 nombres de format DCB compactées. | 4 | 4 | 3 | 4 | X | X
DEC registre8 | Décrémentation | 3 | 3 | 2 | 2 | XX | XX
DEC mémoire | Décrémentation | 15+EA | 15+EA | 7 | 6 | XX | XXXX
DEC registre16/32 | Décrémentation | 3 | 3 | 2 | 2 | X | X
DIV registre8 | Division naturel | 90 | 80 | 14 | 14 | XX | XX
DIV registre16 | Division naturel | 162 | 144 | 22 | 22 | XX | XX
DIV registre32 | Division naturel | - | - | - | 8 | XX | XX
DIV mémoire8 | Division naturel | 96+EA | 86+EA | 17 | 17 | XX | XX
DIV mémoire16 | Division naturel | 176+EA | 158+EA | 25 | 25 | XX | XX
DIV mémoire32 | Division naturel | - | - | - | 41 | XX | XX
ENTER immédiat16,0 | Empiler dans la pile | - | - | 11 | 10 | XXXX | XXXX
ENTER immédiat16,1 | Empiler dans la pile | - | - | 15 | 12 | XXXX | XXXX
ESC immédiat,registre | Cette instruction active le coprocesseur, lequel se permettra d'utiliser les méthodes d'adressage du processeur principal (CPU). | 2 | 2 | 9 | 20 | XXXX | XXXX
ESC immédiat,mémoire | Cette instruction active le coprocesseur, lequel se permettra d'utiliser les méthodes d'adressage du processeur principal (CPU). | 2 | 2 | 9 | 20 | XXXX | XXXX
HLT | Arrêter le microprocesseur | 2 | 2 | 2 | 5 | X | X
IDIV registre8 | Division entière | 112 | 101 | 17 | 19 | XX | XX
IDIV registre16 | Division entière | 184 | 165 | 25 | 27 | XX | XX
IDIV registre32 | Division entière | - | - | - | 4 | XX | XX
IDIV mémoire8 | Division entière | 118+EA | 107+EA | 20 | 22 | XX | XXXX
IDIV mémoire16 | Division entière | 194+EA | 175+EA | 38 | 30 | XX | XXXX
IDIV mémoire32 | Division entière | - | - | - | 46 | XXX | XXXXX
IMUL registre8 | Multiplication entière | 98 | 80 | 13 | 9 à 14 | XX | XX
IMUL registre16 | Multiplication entière | 154 | 128 | 21 | 9 à 22 | XX | XX
IMUL registre32 | Multiplication entière | - | - | - | 9 à 38 | XXX | XXX
IMUL mémoire8 | Multiplication entière | 104 | 86 | 16 | 12 à 17 | XX | XXXX
IMUL mémoire16 | Multiplication entière | 160 | 134 | 24 | 12 à 25 | XX | XXXX
IMUL mémoire32 | Multiplication entière | - | - | - | 12 à 41 | XX | XXXX
IMUL registre8,immédiat | Multiplication entière | - | - | 21 | 9 à 14 | XXX | XXX
IMUL registre16,immédiat | Multiplication entière | - | - | 21 | 9 à 22 | XXX | XXX
IMUL registre32,immédiat | Multiplication entière | - | - | - | 9 à 38 | XXX | XXXXXX
IMUL registre8,registre8,immédiat | Multiplication entière | - | - | 21 | 9 à 14 | XXX | XXXXXX
IMUL registre16,registre16,immédiat | Multiplication entière | - | - | 21 | 9 à 22 | XXX | XXXXXX
IMUL registre32,registre32,immédiat | Multiplication entière | - | - | - | 9 à 18 | XXX | XXXXXX
IMUL registre8,mémoire8,immédiat | Multiplication entière | - | - | 24 | 12 à 17 | XXX | XXXXXX
IMUL registre16,mémoire16,immédiat | Multiplication entière | - | - | 24 | 12 à 25 | XXX | XXXXXX
IMUL registre32,mémoire32,immédiat | Multiplication entière | - | - | - | 12 à 41 | XXX | XXXXXX
IMUL registre16,registre16 | Multiplication entière | - | - | - | 9 à 22 | XXX | XXXXXX
IMUL registre32,registre32 | Multiplication entière | - | - | - | 9 à 18 | XXX | XXXXX
IMUL registre16,mémoire16 | Multiplication entière | - | - | - | 12 à 25 | XXX | XXXXX
IMUL registre32,registre32 | Multiplication entière | - | - | - | 12 à 41 | XXX | XXXXX
IN accumulateur,immédiat8 | Lecture d'un port | 14 | 10 | 5 | 12 | XX | XX
IN accumulateur,DX | Lecture d'un port | 12 | 8 | 5 | 13 | X | X
INC registre8 | Incrémentation | 3 | 3 | 2 | 2 | XX | XX
INC registre16 | Incrémentation | 3 | 3 | 2 | 2 | X | X
INC registre32 | Incrémentation | 3 | 3 | 2 | 2 | XX | XX
INC mémoire | Incrémentation | 23+EA | 15+EA | 7 | 6 | XX | XXXX
INS destination,port | Lecture d'un port vers une chaîne de caractères | - | - | 5 | 15 | X | X
INT immédiat | Appel d'une interruption | 71 | 51 | 23+m | 33 | XX | XX
INT/3 (constante) | Appel de l'interruption de point d'arrêt | 72 | 52 | 23 | 33 | X | X
INTO | Appel d'une interruption de débordement | 73 | 53 | 24+m | 35 | X | X
INTO (si pas de saut) | Appel d'une interruption de débordement | 4 | 4 | 3 | 3 | X | X
IRET | Retour d'interruption | 44 | 32 | 17+m | 22 | X | X
IRETD | Retour d'interruption en mode protégé 32 bits | - | - | - | 22 | X | X
JA label | Cette instruction saut si supérieur sur des valeurs naturel | 16 | 16 | 7+m | 7+m | XX | XX
JA label (si pas de saut) | Cette instruction saut si supérieur sur des valeurs naturel | 4 | 4 | 3 | 3 | XX | XX
JA label near | Cette instruction saut si supérieur sur des valeurs naturel | - | - | - | 7+m | XXXX | XXXX
JAE label | Cette instruction saut si Supérieur ou égal sur des valeurs naturel | 16 | 16 | 7+m | 7+m | XX | XX
JAE label (si pas de saut) | Cette instruction saut si Supérieur ou égal sur des valeurs naturel | 4 | 4 | 3 | 3 | XX | XX
JAE label near | Cette instruction saut si Supérieur ou égal sur des valeurs naturel | - | - | - | 7+m | XXXX | XXXX
JB label | Cette instruction saut si inférieur sur des valeurs naturel | 16 | 16 | 7+m | 7+m | XX | XX
JB label (si pas de saut) | Cette instruction saut si inférieur sur des valeurs naturel | 4 | 4 | 3 | 3 | XX | XX
JB label near | Cette instruction saut si inférieur sur des valeurs naturel | - | - | - | 7+m | XXXX | XXXX
JBE label | Cette instruction saut si inférieur ou égal sur des valeurs naturel | 16 | 16 | 7+m | 7+m | XX | XX
JBE label (si pas de saut) | Cette instruction saut si inférieur ou égal sur des valeurs naturel | 4 | 4 | 3 | 3 | XX | XX
JBE label near | Cette instruction saut si inférieur ou égal sur des valeurs naturel | - | - | - | 7+m | XXXX | XXXX
JC label | Cette instruction saut si indicateur de retenue à égal à 1 | 16 | 16 | 7+m | 7+m | XX | XX
JC label (si pas de saut) | Cette instruction saut si indicateur de retenue à égal à 1 | 4 | 4 | 3 | 3 | XX | XX
JC label near | Cette instruction saut si indicateur de retenue à égal à 1 | - | - | - | 7+m | XXXX | XXXX
JCXZ label | Cette instruction saut si le registre CX est égal à 0 | 18 | 16 | 7+m | 7+m | XX | XX
JCXZ label (si pas saut) | Cette instruction saut si le registre CX est égal à 0 | 6 | 6 | 4 | 5 | XX | XX
JE label | Cette instruction saut si égal | 16 | 16 | 7+m | 7+m | XX | XX
JE label (si pas de saut) | Cette instruction saut si égal | 4 | 4 | 3 | 3 | XX | XX
JE label near | Cette instruction saut si égal | - | - | - | 7+m | XXXX | XXXX
JG label | Cette instruction saut si supérieur sur des valeurs entière | 16 | 16 | 7+m | 7+m | XX | XX
JG label (si pas de saut) | Cette instruction saut si supérieur sur des valeurs entière | 4 | 4 | 3 | 3 | XX | XX
JG label near | Cette instruction saut si supérieur sur des valeurs entière | - | - | - | 7+m | XXXX | XXXX
JGE label | Cette instruction saut si supérieur ou égal sur des valeurs entière | 16 | 16 | 7+m | 7+m | XX | XX
JGE label (si pas de saut) | Cette instruction saut si supérieur ou égal sur des valeurs entière | 4 | 4 | 3 | 3 | XX | XX
JGE label near | Cette instruction saut si supérieur ou égal sur des valeurs entière | - | - | - | 7+m | XXXX | XXXX
JL label | Cette instruction saut si inférieur sur des valeurs entière | 16 | 16 | 7+m | 7+m | XX | XX
JL label (si pas de saut) | Cette instruction saut si inférieur sur des valeurs entière | 4 | 4 | 3 | 3 | XX | XX
JL label near | Cette instruction saut si inférieur sur des valeurs entière | - | - | - | 7+m | XXXX | XXXX
JLE label | Cette instruction saut si inférieur ou égal sur des valeurs entière | 16 | 16 | 7+m | 7+m | XX | XX
JLE label (si pas de saut) | Cette instruction saut si inférieur ou égal sur des valeurs entière | 4 | 4 | 3 | 3 | XX | XX
JLE label near | Cette instruction saut si inférieur ou égal sur des valeurs entière | - | - | - | 7+m | XXXX | XXXX
JMP short-label | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | 15 | 15 | 7+m | 7+m | XX | XX
JMP near-label | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | 15 | 15 | 7+m | 7+m | XXX | XXXXXXX
JMP FAR label | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | 15 | 15 | 11+m | 12+m | XXXXX | XXXXX
JMP registre16 | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | 11 | 11 | 7+m | 7+m | XX | XX
JMP registre32 | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | - | - | - | 7+m | XX | XX
JMP mémoire16 | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | 18+EA | 18+EA | 11+m | 10+m | XX | XX
JMP mémoire32 | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | - | - | - | 10+m | XX | XX
JMP mémoire32 | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | 24+EA | 15+m | 12+m | 12+m | XX | XX
JMP mémoire48 | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | - | - | - | 12+m | XX | XX
JNA label | Cette instruction saut si pas supérieur sur des valeurs naturel | 16 | 16 | 7+m | 7+m | XX | XX
JNA label (si pas de saut) | Cette instruction saut si pas supérieur sur des valeurs naturel | 4 | 4 | 3 | 3 | XX | XX
JNA label near | Cette instruction saut si pas supérieur sur des valeurs naturel | - | - | - | 7+m | XXXX | XXXX
JNAE label | Cette instruction saut si pas supérieur ou égal sur des valeurs naturel | 16 | 16 | 7+m | 7+m | XX | XX
JNAE label (si pas saut) | Cette instruction saut si pas supérieur ou égal sur des valeurs naturel | 4 | 4 | 3 | 3 | XX | XX
JNAE label near | Cette instruction saut si pas supérieur ou égal sur des valeurs naturel | - | - | - | 7+m | XXXX | XXXX
JNB label | Cette instruction saut si pas inférieur sur des valeurs naturel | 16 | 16 | 7+m | 7+m | XX | XX
JNB label (si pas de saut) | Cette instruction saut si pas inférieur sur des valeurs naturel | 4 | 4 | 3 | 3 | XX | XX
JNB label near | Cette instruction saut si pas inférieur sur des valeurs naturel | - | - | - | 7+m | XXXX | XXXX
JNBE label | Cette instruction saut si pas inférieur ou égal sur des valeurs naturel | 16 | 16 | 7+m | 7+m | XX | XX
JNBE label (si pas saut) | Cette instruction saut si pas inférieur ou égal sur des valeurs naturel | 4 | 4 | 3 | 3 | XX | XX
JNBE label near | Cette instruction saut si pas inférieur ou égal sur des valeurs naturel | - | - | - | 7+m | XXXX | XXXX
JNC label | Cette instruction saut si l'indicateur de retenue est égal à 0 | 16 | 16 | 7+m | 7+m | XX | XX
JNC label (si pas de saut) | Cette instruction saut si l'indicateur de retenue est égal à 0 | 4 | 4 | 3 | 3 | XX | XX
JNC label near | Cette instruction saut si l'indicateur de retenue est égal à 0 | - | - | - | 7+m | XXXX | XXXX
JNE label | Cette instruction saut si pas égal | 16 | 16 | 7+m | 7+m | XX | XX
JNE label (si pas de saut) | Cette instruction saut si pas égal | 4 | 4 | 3 | 3 | XX | XX
JNE label near | Cette instruction saut si pas égal | - | - | - | 7+m | XXXX | XXXX
JNG label | Cette instruction saut si pas supérieur sur des valeurs entières | 16 | 16 | 7+m | 7+m | XX | XX
JNG label (si pas de saut) | Cette instruction saut si pas supérieur sur des valeurs entières | 4 | 4 | 3 | 3 | XX | XX
JNG label near | Cette instruction saut si pas supérieur sur des valeurs entières | - | - | - | 7+m | XXXX | XXXX
JNGE label | Cette instruction saut si pas supérieur ou égal sur des valeurs entières | 16 | 16 | 7+m | 7+m | XX | XX
JNGE label (si pas saut) | Cette instruction saut si pas supérieur ou égal sur des valeurs entières | 4 | 4 | 3 | 3 | XX | XX
JNGE label near | Cette instruction saut si pas supérieur ou égal sur des valeurs entières | - | - | - | 7+m | XXXX | XXXX
JNL label | Cette instruction saut si pas inférieur sur des valeurs entières | 16 | 16 | 7+m | 7+m | XX | XX
JNL label (si pas de saut) | Cette instruction saut si pas inférieur sur des valeurs entières | 4 | 4 | 3 | 3 | XX | XX
JNL label near | Cette instruction saut si pas inférieur sur des valeurs entières | - | - | - | 7+m | XXXX | XXXX
JNLE label | Cette instruction saut si pas inférieur ou égal sur des valeurs entières | 16 | 16 | 7+m | 7+m | XX | XX
JNLE label (si pas saut) | Cette instruction saut si pas inférieur ou égal sur des valeurs entières | 4 | 4 | 3 | 3 | XX | XX
JNLE label near | Cette instruction saut si pas inférieur ou égal sur des valeurs entières | - | - | - | 7+m | XXXX | XXXX
JNO label | Cette instruction saut si pas de débordement | 16 | 16 | 7+m | 7+m | XX | XX
JNO label (si pas de saut) | Cette instruction saut si pas de débordement | 4 | 4 | 3 | 3 | XX | XX
JNO label near | Cette instruction saut si pas de débordement | - | - | - | 7+m | XXXX | XXXX
JNP label | Cette instruction saut si pas de parité | 16 | 16 | 7+m | 7+m | XX | XX
JNP label (si pas de saut) | Cette instruction saut si pas de parité | 4 | 4 | 3 | 3 | XX | XX
JNP label near | Cette instruction saut si pas de parité | - | - | - | 7+m | XXXX | XXXX
JNS label | Cette instruction saut si pas de signe | 16 | 16 | 7+m | 7+m | XX | XX
JNS label (si pas de saut) | Cette instruction saut si pas de signe | 4 | 4 | 3 | 3 | XX | XX
JNS label near | Cette instruction saut si pas de signe | - | - | - | 7+m | XXXX | XXXX
JNZ label | Cette instruction saut si pas zéro | 16 | 16 | 7+m | 7+m | XX | XX
JNZ label (si pas de saut) | Cette instruction saut si pas zéro | 4 | 4 | 3 | 3 | XX | XX
JNZ label near | Cette instruction saut si pas zéro | - | - | - | 7+m | XXXX | XXXX
JO label | Cette instruction saut si débordement | 16 | 16 | 7+m | 7+m | XX | XX
JO label (si pas de saut) | Cette instruction saut si débordement | 4 | 4 | 3 | 3 | XX | XX
JO label near | Cette instruction saut si débordement | - | - | - | 7+m | XXXX | XXXX
JPO label | Cette instruction saut si parité impaire | 16 | 16 | 7+m | 7+m | XX | XX
JPO label (si pas de saut) | Cette instruction saut si parité impaire | 4 | 4 | 3 | 3 | XX | XX
JPO label near | Cette instruction saut si parité impaire | - | - | - | 7+m | XXXX | XXXX
JP label | Cette instruction saut si parité | 16 | 16 | 7+m | 7+m | XX | XX
JP label (si pas de saut) | Cette instruction saut si parité | 4 | 4 | 3 | 3 | XX | XX
JP label near | Cette instruction saut si parité | - | - | - | 7+m | XXXX | XXXX
JPE label | Cette instruction saut si parité paire | 16 | 16 | 7+m | 7+m | XX | XX
JPE label (si pas de saut) | Cette instruction saut si parité paire | 4 | 4 | 3 | 3 | XX | XX
JPE label near | Cette instruction saut si parité paire | - | - | - | 7+m | XXXX | XXXX
JS label | Cette instruction saut si signé | 16 | 16 | 7+m | 7+m | XX | XX
JS label (si pas de saut) | Cette instruction saut si signé | 4 | 4 | 3 | 3 | XX | XX
JS label near | Cette instruction saut si signé | - | - | - | 7+m | XXXX | XXXX
JZ label | Cette instruction saut si zéro | 16 | 16 | 7+m | 7+m | XX | XX
JZ label (si pas de saut) | Cette instruction saut si zéro | 4 | 4 | 3 | 3 | XX | XX
JZ label near | Cette instruction saut si zéro | - | - | - | 7+m | XXXX | XXXX
LAHF | Cette instruction permet de transférer les bits d'indicateurs du registre d'état vers le registre AH. | 4 | 4 | 2 | 2 | X | X
LAR registre16,registre16 | Cette instruction permet de charger le registre des indicateurs d'un descripteur. | - | - | 14 | 15 | XXX | XXX
LAR registre32,registre32 | Cette instruction permet de charger le registre des indicateurs d'un descripteur. | - | - | - | 15 | XXX | XXX
LAR registre16,mémoire16 | Cette instruction permet de charger le registre des indicateurs d'un descripteur. | - | - | 16 | 16 | XXX | XXXXXXX
LAR registre32,mémoire32 | Cette instruction permet de charger le registre des indicateurs d'un descripteur. | - | - | - | 16 | XXX | XXXXXXX
LDS destination,source | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment DS et dans un registre d'offset spécifié. | 16+EA | 16+EA | 7 | 7 | XX | XXXX
LEA destination,source | Cette instruction permet de copier l'offset d'une adresse de mémoire contenu dans un registre spécifié. | 2+EA | 2+EA | 3 | 2 | XX | XXXX
LEAVE | Cette instruction permet de libérer une zone de mémoire attribué par l'instruction «ENTER» lorsqu'on utilise des procédures dans des langages de programmation de haut niveau. | - | - | 5 | 4 | X | X
LES destination,mémoire | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment ES et dans un registre d'offset spécifié. | 24+EA | 16+EA | 7 | 7 | XX | XXXX
LFS destination,mémoire | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment FS et dans un registre d'offset spécifié. | - | - | - | 7 | XXXXX | XXXXXXX
LGDT source | Cette instruction permet de charger un descripteur de tables globale. | - | - | 11 | 11 | XXXXX | XXXXX
LGS destination,mémoire | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment GS et dans un registre d'offset spécifié. | - | - | - | 7 | XXXXX | XXXXXXX
LIDT source | Cette instruction permet de charger un descripteur de tables d'interruption. | - | - | 12 | 11 | XXXXX | XXXXX
LIDT registre16 | Cette instruction permet de charger un descripteur de tables d'interruption. | - | - | 17 | 20 | XXX | XXX
LLDT mémoire16 | Cette instruction permet de charger un descripteur de tables local. | - | - | 19 | 24 | XXXXX | XXXXX
LMSW registre16 | Cette instruction permet de copier 4 des bits d'une opérande vers les 4 bits de registre de contrôle CR0. | - | - | 3 | 10 | XXX | XXX
LMSW mémoire16 | Cette instruction permet de copier 4 des bits d'une opérande vers les 4 bits de registre de contrôle CR0. | - | - | 6 | 13 | XXXXX | XXXXX
LOCK | Cette instruction est utilisé comme préfixe avec d'autres instructions pour amener le microprocesseur à émettre un signal de vérouillage (Lock) sur le bus lors du traitement de l'instruction suivante. | 2 | 2 | 0 | 0 | X | X
LODS source | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction. | 16 | 12 | 5 | 5 | X | X
LOOP label | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0. | 17 | 17 | 8+m | 11+m | XX | XX
LOOP pas de saut | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0. | 5 | 5 | 4 | ? | XX | XX
LOOPE label | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1. | 18 | 18 | 8+m | 11+m | XX | XX
LOOPE pas de saut | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1. | 6 | 6 | 4 | ? | XX | XX
LOOPNE label | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0. | 19 | 19 | 8+m | 11+m | XX | XX
LOOPNE pas de saut | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0. | 5 | 5 | 4 | ? | XX | XX
LOOPNZ label | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0. | 19 | 19 | 8+m | 11+m | XX | XX
LOOPNZ pas de saut | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0. | 5 | 5 | 4 | ? | XX | XX
LOOPZ label | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1. | 18 | 18 | 8+m | 11+m | XX | XX
LOOPZ pas de saut | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1. | 6 | 6 | 4 | ? | XX | XX
LSL registre16,registre16 | Cette instruction permet de charger la limite de segment d'un descripteur de segment spécifié avec l'opérande source dans l'opérande de destination et fixe le drapeau ZF du regsistre EFLAGS. | - | - | 14 | 20 à 25 | XXX | XXX
LSL registre32,registre32 | Cette instruction permet de charger la limite de segment d'un descripteur de segment spécifié avec l'opérande source dans l'opérande de destination et fixe le drapeau ZF du regsistre EFLAGS. | - | - | - | 20 à 25 | XXX | XXX
LSL registre16,mémoire16 | Cette instruction permet de charger la limite de segment d'un descripteur de segment spécifié avec l'opérande source dans l'opérande de destination et fixe le drapeau ZF du regsistre EFLAGS. | - | - | 16 | 21 à 26 | XXXXX | XXXXX
LSL registre32,mémoire32 | Cette instruction permet de charger la limite de segment d'un descripteur de segment spécifié avec l'opérande source dans l'opérande de destination et fixe le drapeau ZF du regsistre EFLAGS. | - | - | - | 21 à 26 | XXXXX | XXXXX
LSS destination,mémoire | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment SS (Segment de pile) et dans un registre d'offset spécifié. | - | - | - | 7 | XXXXX | XXXXXXX
LTR registre16 | Cette instruction permet de charger l'opérande source dans le champ du sélecteur de segment du registre de tâche. | - | - | 17 | 23 | XXX | XXX
LTR mémoire16 | Cette instruction permet de charger l'opérande source dans le champ du sélecteur de segment du registre de tâche. | - | - | 18 | 27 | XXXXX | XXXXX
MOV registre,registre | Cette instruction permet de copier opérande source dans une opérande destinataire. | 2 | 2 | 2 | 2 | XX | XX
MOV mémoire,registre | Cette instruction permet de copier opérande source dans une opérande destinataire. | 13+EA | 9+EA | 3 | 2 | XX | XX
MOV registre,mémoire | Cette instruction permet de copier opérande source dans une opérande destinataire. | 12+EA | 8+EA | 5 | 4 | XX | XXXX
MOV mémoire,immédiat | Cette instruction permet de copier opérande source dans une opérande destinataire. | 14+EA | 10+EA | 3 | 2 | XXX | XXXXXX
MOV registre,immédiat | Cette instruction permet de copier opérande source dans une opérande destinataire. | 4 | 4 | 2 | 2 | XX | XXX
MOV mémoire,accumulateur | Cette instruction permet de copier opérande source dans une opérande destinataire. | 14 | 10 | 3 | 2 | XXX | XXX
MOV accumulateur,mémoire | Cette instruction permet de copier opérande source dans une opérande destinataire. | 14 | 10 | 5 | 4 | XXX | XXX
MOV registre segment,reg16 | Cette instruction permet de copier opérande source dans une opérande destinataire. | 2 | 2 | 2 | 2 | XX | XX
MOV RegistreSeg,mémoire | Cette instruction permet de copier opérande source dans une opérande destinataire. | 12+EA | 8+EA | 5 | 5 | XX | XXXX
MOV registre16,SegRegistre | Cette instruction permet de copier opérande source dans une opérande destinataire. | 2 | 2 | 2 | 2 | XX | XX
MOV mémoire16,segregistre | Cette instruction permet de copier opérande source dans une opérande destinataire. | 13+EA | 9+EA | 3 | 2 | XX | XXXX
MOV Reg32,controlRegistre | Cette instruction permet de copier opérande source dans une opérande destinataire. | - | - | - | 6 | XXX | XXX
MOV Registre32,DebugReg | Cette instruction permet de copier opérande source dans une opérande destinataire. | - | - | - | 10 | XXX | XXX
MOV DebugReg,Registre32 | Cette instruction permet de copier opérande source dans une opérande destinataire. | - | - | - | 22/14 | XXX | XXX
MOV registr32,teste registre | Cette instruction permet de copier opérande source dans une opérande destinataire. | - | - | - | 22/16 | XXX | XXX
MOV TestReg,Registre32 | Cette instruction permet de copier opérande source dans une opérande destinataire. | - | - | - | 12 | XXX | XXX
MOV destination,source | Cette instruction permet de copier opérande source dans une opérande destinataire. | 26 | 18 | 5 | 7 | X | X
MOVSX registre,registre | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires avec l'extension des signes.. | - | - | - | 3 | XXX | XXX
MOVSX registre,mémoire | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires avec l'extension des signes. | - | - | - | 6 | XXX | XXXXXXX
MOVZX registre,registre | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires par des 0. | - | - | - | 3 | XXX | XXX
MOVZX registre,mémoire | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires par des 0. | - | - | - | 6 | XXX | XXXXXXX
MUL registre8 | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). | 77 | 70 | 13 | 9 à 14 | XX | XX
MUL registre16 | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). | 118 | 113 | 21 | 9 à 22 | XX | XX
MUL registre32 | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). | - | - | - | 9 à 38 | XX | XXXX
MUL mémoire8 | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). | 83+EA | 76+EA | 16 | 12 à 17 | XX | XXXX
MUL mémoire16 | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). | 139+EA | 124+EA | 24 | 12 à 25 | XX | XXXX
MUL mémoire32 | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). | - | - | - | 12 à 21 | XX | XXXX
NEG registre | Cette instruction permet d'effectuer le complément à 2 d'une opérande. | 3 | 3 | 2 | 2 | XX | XX
NEG mémoire | Cette instruction permet d'effectuer le complément à 2 d'une opérande. | 24+EA | 16+EA | 7 | 6 | XX | XXXX
NOP | Cette instruction ne fait rien. | 3 | 3 | 3 | 3 | X | X
NOT registre | Cette instruction permet d'inverser la valeur de chacun des bits d'une opérande. | 3 | 3 | 2 | 2 | XX | XX
NOT mémoire | Cette instruction permet d'inverser la valeur de chacun des bits d'une opérande. | 24+EA | 16+EA | 7 | 6 | XX | XXXX
OR registre,registre | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandessp écifiés. | 3 | 3 | 2 | 2 | XX | XX
OR mémoire,registre | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandessp écifiés. | 24+EA | 16+EA | 7 | 7 | XX | XXXX
OR registre,méoire | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandessp écifiés. | 13+EA | 9+EA | 7 | 6 | XX | XXXX
OR registre,immédiat | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandessp écifiés. | 4 | 4 | 3 | 2 | XX | XXX
OR mémoire8,immmédiat8 | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandessp écifiés. | 17+EA | 17+EA | 7 | 7 | XXX | XXXXXX
OR mémoire16,immédiat16 | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandessp écifiés. | 25+EA | 25+EA | 7 | 7 | XXX | XXXXXX
OR accumulateur,immédiat | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandessp écifiés. | 4 | 4 | 3 | 2 | XX | XXX
OUT immédiat8,accumulateur | Cette instruction permet d'envoyer un octet, un mot ou un double mot sur le port d'entrée/sortie. | 14 | 10 | 3 | 10 | XX | XX
OUT DX,accumulateur | Cette instruction permet d'envoyer un octet, un mot ou un double mot sur le port d'entrée/sortie. | 12 | 8 | 3 | 11 | X | X
OUTS port,source | Cette instruction permet d'envoyer un octet, un mot ou un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | - | - | 5 | 14 | X | X
POP registre16 | Cette instruction permet de désempiler de la pile une mot ou un double mot et la met dans une opérande. | 12 | 8 | 5 | 4 | X | X
POP registre32 | Cette instruction permet de désempiler de la pile une mot ou un double mot et la met dans une opérande. | - | - | - | 4 | XX | XX
POP mémoire16 | Cette instruction permet de désempiler de la pile une mot ou un double mot et la met dans une opérande. | 25+EA | 17+EA | 5 | 5 | XX | XXXX
POP mémoire32 | Cette instruction permet de désempiler de la pile une mot ou un double mot et la met dans une opérande. | - | - | - | 5 | XXX | XXXXX
POP RegistreSegment | Cette instruction permet de désempiler de la pile une mot ou un double mot et la met dans une opérande. | 12 | 8 | 5 | 7 | X | X
POPA | Cette instruction permet de désempiler de la pile respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX. | - | - | 19 | 24 | X | X
POPAD | Cette instruction permet de désempiler de la pile respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX. | - | - | - | 24 | XX | XX
POPF | Cette instruction permet de désempiler de la pile le registre 16 bits de drapeau contenant les indicateurs d'état. | 12 | 8 | 5 | 5 | X | X
POPFD | Cette instruction permet de désempiler de la pile le registre 32 bits de drapeau contenant les indicateurs d'état. | - | - | - | 5 | XX | XX
PUSH registre16 | Cette instruction permet d'empiler une mot ou un double mot dans la pile. | 15 | 11 | 3 | 2 | X | X
PUSH registre32 | Cette instruction permet d'empiler une mot ou un double mot dans la pile. | - | - | - | 2 | XX | XX
PUSH mémoire16 | Cette instruction permet d'empiler une mot ou un double mot dans la pile. | 24+EA | 16+EA | 5 | 5 | XX | XXXX
PUSH mémoire32 | Cette instruction permet d'empiler une mot ou un double mot dans la pile. | - | - | - | 5 | XXX | XXXXX
PUSH RegistreSegment | Cette instruction permet d'empiler une mot ou un double mot dans la pile. | 14 | 10 | 3 | 2 | X | X
PUSH Immédiat | Cette instruction permet d'empiler une mot ou un double mot dans la pile. | - | - | 3 | 2 | XX | XXX
PUSHA | Cette instruction permet d'empiler respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX dans la pile. | - | - | 17 | 18 | X | X
PUSHAD | Cette instruction permet d'empiler respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX dans la pile. | - | - | - | 18 | XX | XX
PUSHF | Cette instruction permet d'empiler respectivement le registre 16 bits de drapeau des indicateurs d'état dans la pile. | 14 | 10 | 3 | 4 | X | X
PUSHFD | Cette instruction permet d'empiler respectivement le registre 32 bits de drapeau des indicateurs d'état dans la pile. | - | - | - | 4 | XX | XX
RCL registre,1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | 2 | 2 | 2 | 9 | XX | XX
RCL mémoire,1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | 23+EA | 15+EA | 7 | 10 | XX | XXXX
RCL registre,CL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | 8+4n | 8+4n | 5+n | 9 | XX | XX
RCL mémoire,CL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | 28+EA+4n | 20+EA+4n | 8+n | 10 | XX | XXXX
RCL registre,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | - | - | 5+n | 9 | XXX | XXX
RCL mémoire,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | - | - | 8+n | 10 | XXX | XXXXX
RCR registre,1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | 2 | 2 | 2 | 9 | XX | XX
RCR mémoire,1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | 23+EA | 15+EA | 7 | 10 | XX | XXXX
RCR registre,CL | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | 8+4n | 8+4n | 5+n | 9 | XX | XX
RCR m‚moire,CL | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | 28+EA+4n | 20+EA+4n | 8+n | 10 | XX | XXXX
RCR registre,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | - | - | 5+n | 9 | XXX | XXX
RCR mémoire,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | - | - | 8+n | 10 | XXX | XXXXX
REP | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions tant que CX ne vaut pas 0. | 2 | 2 | 2 | 2 | X | X
REPE | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0. | 2 | 2 | 2 | 2 | X | X
REPNE | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1. | 2 | 2 | 2 | 2 | X | X
REPNZ | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1. | 2 | 2 | 2 | 2 | X | X
REPZ | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0. | 2 | 2 | 2 | 2 | X | X
RETF | Cette instruction permet de quitter une procédure ayant lieu avec un appel long (FAR CALL). | 34 | 26 | 15+m | 18+m | X | X
RETF immédiat | Cette instruction permet de quitter une procédure ayant lieu avec un appel long (FAR CALL). | 33 | 25 | 15+m | 18+m | XXX | XXX
RETN | Cette instruction permet de quitter une procédure ayant lieu avec un appel court (NEAR CALL). | 20 | 16 | 11+m | 10+m | X | X
RETN immédiat8 | Cette instruction permet de quitter une procédure ayant lieu avec un appel court (NEAR CALL). | 24 | 20 | 11+m | 10+m | XXX | XXX
ROL registre,1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | 2 | 2 | 2 | 3 | XX | XX
ROL mémoire,1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | 23+EA | 15+EA | 7 | 7 | XX | XXXX
ROL registre,CL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | 8+4n | 8+4n | 5+n | 3 | XX | XX
ROL mémoire,CL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | 28+EA+4n | 20+EA+4n | |8+n | 7 | XX | XXXX
ROL registre,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | - | - | 5+n | 3 | XXX | XXX
ROL mémoire,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | - | - | 8+n | 7 | XXX | XXXXX
ROR registre,1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | 2 | 2 | 2 | 3 | XX | XX
ROR mémoire,1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | 23+EA | 15+EA | 7 | 7 | XX | XXXX
ROR registre,CL | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | 8+4n | 8+4n | 5+n | 3 | XX | XX
ROR mémoire,CL | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | 28+EA+4n | 20+EA+4n | 8+n | 7 | XX | XXXX
ROR registre,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | - | - | 5+n | 3 | XXX | XXX
ROR mémoire,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | - | - | 8+n | 7 | XXX | XXXXX
SAHF | Cette instruction permet de copier les bits du registre AH dans l'octet de poids faible dans le registre des drapeaux (les indicateurs d'état). | 4 | 4 | 2 | 3 | X | X
SAL registre,1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | 2 | 2 | 2 | 3 | XX | XX
SAL mémoire,1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | 23+EA | 15+EA | 7 | 7 | XX | XXXX
SAL registre,CL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | 8+4n | 8+4n | 5+n | 3 | XX | XX
SAL mémoire,CL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | 28+EA+4n | 20+EA+4n | 8+n | 7 | XX | XXXX
SAL registre,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | - | - | 5+n | 3 | XXX | XXX
SAL mémoire,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | - | - | 8+n | 7 | XXX | XXXXX
SAR registre,1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | 2 | 2 | 2 | 3 | XX | XX
SAR mémoire,1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | 23+EA | 15+EA | 7 | 7 | XX | XXXX
SAR registre,CL | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | 8+4n | 8+4n | 5+n | 3 | XX | XX
SAR mémoire,CL | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | 28+EA+4n | 20+EA+4n | 8+n | 7 | XX | XXXX
SAR registre,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | - | - | 5+n | 3 | XXX | XXX
SAR mémoire,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | - | - | 8+n | 7 | XXX | XXXXX
SBB registre,registre | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande. | 3 | 3 | 2 | 2 | XX | XX
SBB mémoire,registre | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande. | 24+EA | 16+EA | 7 | 6 | XX | XXXX
SBB registre,mémoire | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande. | 13+EA | 9+EA | 7 | 7 | XX | XXXX
SBB registre,immédiat | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande. | 4 | 4 | 3 | 2 | XXX | XXXX
SBB mémoire,immédiat | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande. | 25+EA | 17+EA | 7 | 7 | XXX | XXXXXX
SBB accumulateur,immédiat | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande. | 4 | 4 | 3 | 2 | XX | XXX
SCAS chaine | Cette instruction permet de comparer un octet, un mot ou un double mot avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | 15 | 15 | 7 | 7 | X | X
SETAE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETAE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETB registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETB mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETBE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETBE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETC registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETC mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETG registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETG mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETGE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETGE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETL registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETL mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETLE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETLE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNA registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNA mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNAE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNAE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNB registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNB mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNC registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNC mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNG registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNG mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNGE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNGE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNL registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNL mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNLE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNLE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNO registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNO mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNP registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNP mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNS registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNS mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNZ registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNZ mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETO registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETO mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETP registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETP mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETPE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETPE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETPO registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETPO mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETS registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETS mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETZ registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETZ mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SGDT mémoire64 | Cette instruction permet d'entreposer le sélecteur de segment dans le registre GDTR (registre de table global de descripteur) dans l'opérande de destination. | - | - | 11 | 9 | XXXXX | XXXXX
SHL registre,1 | Décalage de bits à gauche | 2 | 2 | 2 | 3 | XX | XX
SHL mémoire,1 | Décalage de bits à gauche | 23+EA | 15+EA | 7 | 7 | XX | XXXX
SHL registre,CL | Décalage de bits à gauche | 8+4n | 8+4n | 5+n | 3 | XX | XX
SHL mémoire,CL | Décalage de bits à gauche | 28+EA+4n | 20+EA+4n | 8+n | 7 | XX | XXXX
SHL registre,immédiat8 | Décalage de bits à gauche | - | - | 5+n | 3 | XXX | XXX
SHL mémoire,immédiat8 | Décalage de bits à gauche | - | - | 8+n | 7 | XXX | XXXXX
SHLD reg16,reg16,immédiat8 | Décalage de bits à gauche | - | - | - | 3 | XXX | XXX
SHLD reg32,reg32,immédiat8 | Décalage de bits à gauche | - | - | - | 3 | XXXX | XXXX
SHLD mém16,reg16,immédiat8 | Décalage de bits à gauche | - | - | - | 7 | XXXXXX | XXXXXX
SHLD mém32,reg32,immédiat8 | Décalage de bits à gauche | - | - | - | 7 | XXXXXX | XXXXXX
SHLD registre16,reg16,CL | Décalage de bits à gauche | - | - | - | 3 | XXX | XXX
SHLD registre32,reg32,CL | Décalage de bits à gauche | - | - | - | 3 | XXX | XXX
SHLD mémoire16,reg16,CL | Décalage de bits à gauche | - | - | - | 7 | XXXXX | XXXXX
SHLD mémoire32,reg32,CL | Décalage de bits à gauche | - | - | - | 7 | XXXXX | XXXXX
SHR registre,1 | Décalage de bits à droite | 2 | 2 | 2 | 3 | XX | XX
SHR mémoire,1 | Décalage de bits à droite | 23+EA | 15+EA | 7 | 7 | XX | XXXX
SHR registre,CL | Décalage de bits à droite | 8+4n | 8+4n | 5+n | 3 | XX | XX
SHR mémoire,CL | Décalage de bits à droite | 28+EA+4n | 20+EA+4n | 8+n | 7 | XX | XXXX
SHR registre,immédiat8 | Décalage de bits à droite | - | - | 5+n | 3 | XXX | XXX
SHR mémoire,immédiat8 | Décalage de bits à droite | - | - | 8+n | 7 | XXX | XXXXX
SHRD reg16,reg16,immédiat8 | Décalage de bits à droite | - | - | - | 3 | XXX | XXX
SHRD reg32,reg32,immédiat8 | Décalage de bits à droite | - | - | - | 3 | XXXX | XXXX
SHRD mém16,reg16,immédiat8 | Décalage de bits à droite | - | - | - | 7 | XXXXXX | XXXXXX
SHRD mém32,reg32,immédiat8 | Décalage de bits à droite | - | - | - | 7 | XXXXXX | XXXXXX
SHRD registre16,reg16,CL | Décalage de bits à droite | - | - | - | 3 | XXX | XXX
SHRD registre|2,reg|2,CL | Décalage de bits à droite | - | - | - | 3 | XXX | XXX
SHRD mémoire16,reg16,CL | Décalage de bits à droite | - | - | - | 7 | XXXXX | XXXXX
SHRD mémoire32,reg32,CL | Décalage de bits à droite | - | - | - | 7 | XXXXX | XXXXX
SIDT mémoire64 | Cette instruction permet d'entreposer le registre de descripteur de table d'interruption (IDTR) dans l'opérande de destination. | - | - | 12 | 9 | XXXXX | XXXXX
SLDT registre16 | Cette instruction permet d'entreposer le sélecteur de segment dans le registre LDTR (registre de table local de descripteur) dans l'opérande de destination. | - | - | 2 | 2 | XXX | XXX
SLDT mémoire16 | Cette instruction permet d'entreposer le sélecteur de segment dans le registre LDTR (registre de table local de descripteur) dans l'opérande de destination. | - | - | 2 | 2 | XXXXX | XXXXX
SMSW registre16 | Cette instruction permet d'entreposer le mot des états (soit les bits de 0 à 15 du registre de contrôle CR0) à partir du registre de tâche (TR) dans l'opérande cible. | - | - | 2 | 10 | XXX | XXX
SMSW mémoire16 | Cette instruction permet d'entreposer le mot des états (soit les bits de 0 à 15 du registre de contrôle CR0) à partir du registre de tâche (TR) dans l'opérande cible. | - | - | 3 | 3 | XXXXX | XXXXX
STC | Cette instruction permet de fixer l'indicateur de retenue (CF) à la valeur 1. | 2 | 2 | 2 | 2 | X | X
STD | Cette instruction permet de fixer l'indicateur de direction (DF) à la valeur 1. | 2 | 2 | 2 | 2 | X | X
STI | Cette instruction permet de fixer l'indicateur de direction (DF) à la valeur 1. | 2 | 2 | 2 | 2 | X | X
STOS destination | Cette instruction permet de copier un octet, un mot ou un double mot dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | 15 | 11 | 3 | 4 | X | X
STR registre16 | Cette instruction permet d'entreposer le sélecteur de segment à partir du registre de tâche (TR) à l'opérande cible | - | - | 2 | 2 | XXX | XXX
STR mémoire16 | Cette instruction permet d'entreposer le sélecteur de segment à partir du registre de tâche (TR) à l'opérande cible | - | - | 3 | 2 | XXXXX | XXXXX
SUB registre,registre | Soustraction | 3 | 3 | 2 | 2 | XX | XX
SUB mémoire,registre | Soustraction | 24+EA | 16+EA | 7 | 6 | XX | XXXX
SUB registre,mémoire | Soustraction | 13+EA | 9+EA | 7 | 7 | XX | XXXX
SUB registre,immédiat | Soustraction | 4 | 4 | 3 | 2 | XXX | XXXX
SUB mémoire,immédiat | Soustraction | 25+EA | 17+EA | 7 | 7 | XXX | XXXXXX
SUB accumulateur,immédiat | Soustraction | 4 | 4 | 3 | 2 | XX | XXX
TEST registre,registre | Teste et binaire | 3 | 3 | 2 | 1 | XX | XX
TEST registre,mémoire | Teste et binaire | 13+EA | 9+EA | 6 | 5 | XX | XXXX
TEST mémoire,registre | Teste et binaire | 13+EA | 9+EA | 6 | 5 | XX | XXXX
TEST registre,immédiat | Teste et binaire | 5 | 5 | 3 | 2 | XXX | XXXX
TEST mémoire,immédiat | Teste et binaire | 11+EA | 11+EA | 6 | 5 | XXX | XXXXXX
TEST accumulateur,immédiat | Teste et binaire | 4 | 4 | 3 | 2 | XX | XXX
VERR registre16 | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode lecture à partir du niveau de privilège courant (CPL). | - | - | 14 | 10 | XXX | XXX
VERR mémoire16 | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode lecture à partir du niveau de privilège courant (CPL). | - | - | 16 | 11 | XXXXX | XXXXX
VERW registre16 | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode écriture à partir du niveau de privilège courant (CPL). | - | - | 14 | 15 | XXX | XXX
VERW mémoire16 | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode écriture à partir du niveau de privilège courant (CPL). | - | - | 16 | 16 | XXXXX | XXXXX
WAIT | Cette instruction permet de faire passer le microprocesseur en mode d'attente jusqu'à ce que la ligne de teste sur la carte mère s'active. | 4 | 4 | 3 | 6 | X | X
XCHG registre,registre | Échange les deux éléments | 4 | 4 | 3 | 3 | XX | XX
XCHG mémoire,registre | Échange les deux éléments | 25+EA | 17+EA | 5 | 5 | XX | XXXX
XCHG registre,mémoire | Échange les deux éléments | 25+EA | 17+EA | 5 | 5 | XX | XXXX
XCHG accumulateur,registre | Échange les deux éléments | 3 | 3 | 3 | 3 | X | X
XCHG registre,accumulateur | Échange les deux éléments | 3 | 3 | 3 | 3 | X | X
XLAT | Cette instruction permet de remplacer le contenu du registre AL par un octet de la «tablesource». | 11 | 11 | 5 | 5 | X | X
XLATB | Cette instruction permet de remplacer le contenu du registre AL par un octet de la «tablesource» sans opérande. | 11 | 11 | 5 | 5 | X | X
XOR registre,registre | Ou exclusif | 3 | 3 | 2 | 2 | XX | XX
XOR mémoire,registre | Ou exclusif | 24+EA | 16+EA | 7 | 6 | XX | XXXX
XOR registre,mémoire | Ou exclusif | 13+EA | 9+EA | 7 | 7 | XX | XXXX
XOR registre,immédiat | Ou exclusif | 4 | 4 | 3 | 2 | XXX | XXXX
XOR mémoire,immédiat | Ou exclusif | 25+EA | 17+EA | 7 | 7 | XXX | XXXXXX
XOR accumulateur,immédiat | Ou exclusif | 4 | 4 | 3 | 2 | XX | XXX

Dernière mise à jour : Samedi, le 2 août 2014


Langage de programmation - Assembleur 80x86 - Référence, lexique et dictionnaire des instructions 80x86 - Vue par drapeaux du EFLAGS

Vu dans ... http://www.gladir.com Voici la liste des instructions en se basant sur leur affectation des drapeaux du registres «EFLAGS»:

Instruction | Description | OF | SF | ZF | AF | PF | CF | TF | IF | DF | NT | RF
AAA | Cette instruction permet d'adapter le résultat obtenu par l'addition de 2 valeur en format DCB. | — | — | — | TM | — | M |  |  |  |  |
AAD | Cette instruction permet de convertir une valeur de format DCB non compactée. | — | M | M | — | M | — |  |  |  |  |
AAM | Cette instruction offre la possibilité de convertir le produit de la multiplication de 2 valeurs de format DCB en un format DCB. | — | M | M | — | M | — |  |  |  |  |
AAS | Cette instruction permet d'adapter le résultat de la soustraction de nombre de format DCB. | — | — | — | TM | — | M |  |  |  |  |
ADC | Cette instruction additionne 2 quantités numériques sur 8 ou 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF (CARRY FLAG), à la somme obtenu. | M | M | M | M | M | TM |  |  |  |  |
ADD | Cette instruction additionne 2 quantités numérique sur 8, 16 ou 32 bits. | M | M | M | M | M | M |  |  |  |  |
AND | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés. | 0 | M | M | — | M | 0 |  |  |  |  |
ARPL | Cette instruction permet de contrôler et corriger le niveau de privilège du segment de code en mode protégée. |  |  | M |  |  |  |  |  |  |  |
BOUND | Cette instruction permet de vérifier la validité pouvant exister entre avec un tableau et son indexation. |  |  |  |  |  |  |  |  |  |  |
BSF | Cette instruction permet d'effectuer une comparaison binaire de la droite vers la gauche. | — | — | M | — | — | — |  |  |  |  |
BSR | Cette instruction permet d'effectuer une comparaison binaire de la gauche vers la droite. | — | — | M | — | — | — |  |  |  |  |
BSWAP | Cette instruction permet d'inverse l'ordre des 4 octets d'un registre de taille de 32 bits. |  |  |  |  |  |  |  |  |  |  |
BT | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue. | — | — | — | — | — | M |  |  |  |  |
BTC | Cette instruction transfère une Opérande vers l'indicateur de retenue le bits spécifié et inverser la valeur du bit correspondant. | — | — | — | — | — | M |  |  |  |  |
BTR | Cette instruction permet de transférer l'Opérande vers l'indicateur de retenue le bits spécifié puis met le bits correspondant de l'Opérande à 0. | — | — | — | — | — | M |  |  |  |  |
BTS | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue le bits spécifié puis ensuite met le bits correspondant dans Opérande à 1. | — | — | — | — | — | M |  |  |  |  |
CALL | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse d'appel avant de continuer. |  |  |  |  |  |  |  |  |  |  |
CBW | Cette instruction permet de convertir un nombre contenu dans le registre AL en un format sur 16 bits pour se retrouver dans le registre AX en appliquant une extension du signe. |  |  |  |  |  |  |  |  |  |  |
CLC | Cette instruction permet de mettre l'indicateur d'état de retenu CF à 0. |  |  |  |  |  | 0 |  |  |  |  |
CLD | Cette instruction met l'indicateur d'état DF à 0, soit la direction croissante. |  |  |  |  |  |  |  |  | 0 |  |
CLI | Cette instruction met l'indicateur d'état IF à 0, soit l'interdiction des interruptions. |  |  |  |  |  |  |  | 0 |  |  |
CLTS | Cette instruction permet de mettre à 0 le drapeau de l'indicateur de tâche (Task-Switch) du registre CR0. |  |  |  |  |  |  |  |  |  |  |
CMC | Cette instruction offre la possibilité d'inverser la valeur de l'indicateur de retenue. Si ce dernier vaut 1, elle le met à 0 et inversement. |  |  |  |  |  | M |  |  |  |  |
CMOVcc | Cette instruction copie des données d'une source (valeur) à une destination (registre) à la condition que la condition demandé soit remplie. | T | T | T |  | T | T |  |  |  |  |
CMP | Cette instruction offre la possibilité essentielle de comparer 2 registres ou emplacements de mémoire. | M | M | M | M | M | M |  |  |  |  |
CMPS | Cette instruction permet d'effectuer la comparaison d'un octet, d'un mot ou double mot spécifié avec l'opérande source et destination spécifié et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison. | M | M | M | M | M | M |  |  | T |  |
CMPXCHG | Cette instruction compare la destination avec l'accumulateur (AL, AX ou EAX) et les échanges si la condition est vrai. | M | M | M | M | M | M |  |  |  |  |
CMPXCHG8B | Cette instruction compare un nombre de 64 bits et les échanges si la condition est vrai. |  |  | M |  |  |  |  |  |  |  |
COMISD | Cette instruction permet de comparer deux valeurs réel de double-précision dans la partie faible du quadruple mot de deux opérande et fixe les drapeaux de ZF, PF et FC du registre EFLAGS en fonction du résultat (non-ordonnée, supérieur à, inférieur ou égal). | 0 | 0 | M | 0 | M | M |  |  |  |  |
COMISS | Cette instruction permet de comparer deux valeurs réel de simple-précision dans la partie faible du quadruple mot de deux opérande et fixe les drapeaux de ZF, PF et FC du registre EFLAGS en fonction du résultat (non-ordonnée, supérieur à, inférieur ou égal). | 0 | 0 | M | 0 | M | M |  |  |  |  |
CPUID | Cette instruction retourne le code d'identification du microprocesseur. |  |  |  |  |  |  |  |  |  |  |
CWD | Cette instruction est l'alternative pour convertir le mot du registre AX en un double mot contenu dans le couple de registre DX et AX par extension du signe. |  |  |  |  |  |  |  |  |  |  |
DAA | Cette instruction corrige après coup les retenues lors de la manipulation de valeur DCB. | — | M | M | TM | M | TM |  |  |  |  |
DAS | Cette instruction offre l'intéressante possibilité de corrige le résultat d'une soustraction de 2 nombres de format DCB compactées. | — | M | M | TM | M | TM |  |  |  |  |
DEC | Cette instruction décrément de 1 le registre ou l'adresse mémoire spécifié. | M | M | M | M | M |  |  |  |  |  |
DIV | Cette instruction permet d'effectuer une division non-signée (nombre naturel). | — | — | — | — | — | — |  |  |  |  |
ENTER | Cette instruction permet de créer les structures de paramètres nécessaires aux procédures des langages de haut niveau. |  |  |  |  |  |  |  |  |  |  |
ESC | Cette instruction active le coprocesseur, lequel se permettra d'utiliser les méthodes d'adressage du processeur principal (CPU). |  |  |  |  |  |  |  |  |  |  |
FCMOVcc | Cette instruction permet de déplacé des nombres réel (virgule flottante) si la condition en question est satisfaite. |  |  | T |  | T | T |  |  |  |  |
FCOM | Cette instruction permet de comparer le nombre réel de valeur positive source avec le registre mathématique ST(0) et mettre les indicateurs d'état C0 à C3 avec la valeur 1. |  |  | M |  | M | M |  |  |  |  |
FCOMI | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats. |  |  | M |  | M | M |  |  |  |  |
FCOMIP | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats et désempile de la pile la valeur dans le registre. |  |  | M |  | M | M |  |  |  |  |
FUCOMI | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et vérifie l'ordre des valeurs et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats. |  |  | M |  | M | M |  |  |  |  |
FUCOMIP | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et vérifie l'ordre des valeurs et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats et désempile de la pile la valeur dans le registre. |  |  | M |  | M | M |  |  |  |  |
HLT | Cette instruction permet de faire passer le microprocesseur en mode d'arrêt. Toutefois, le processeur peut quitter cet état lorsqu'une ligne matérielle RESET ou lorsqu'une interruption non-masquable (NMI) reçoit un signal. |  |  |  |  |  |  |  |  |  |  |
IDIV | Cette instruction permet d'effectuer une division signée (nombre entier). | — | — | — | — | — | — |  |  |  |  |
IMUL | Cette instruction permet d'effectuer une multiplication signée (nombre entier). | M | — | — | — | — | M |  |  |  |  |
IN | Cette instruction permet de demander un octet, un mot ou un double mot provenant du port d'entrée/sortie et le retourne dans le registre accumulateur (AL, AX, EAX). |  |  |  |  |  |  |  |  |  |  |
INC | Cette instruction permet d'incrémenter un registre ou un emplacement mémoire. | M | M | M | M | M |  |  |  |  |  |
INS | Cette instruction permet de demander un octet, un mot ou un double mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. |  |  |  |  |  |  |  |  | T |  |
INT | Cette instruction permet d'exécuter l'interruption avec le numéro spécifié. |  |  |  |  |  |  | 0 |  |  | 0 |
INTO | Cette instruction permet d'exécuter l'interruption numéro 4 si le drapeau de débordement (OF) est fixé sur 1é | T |  |  |  |  |  | 0 |  |  | 0 |
INVD | Cette instruction permet de désactiver et de vider le tampon interne du micro-processeur. |  |  |  |  |  |  |  |  |  |  |
INVLPG | Cette instruction permet d'invalider les transferts du TLB (Translation Lookaside Buffer) du micro-processeur |  |  |  |  |  |  |  |  |  |  |
IRET | Cette instruction permet d'effectuer un retour précédemment provoquer par une interruption. | R | R | R | R | R | R | R | R | R | T |
Jcc | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié. | T | T | T |  | T | T |  |  |  |  |
JCXZ | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié si le registre CX vaut 0. |  |  |  |  |  |  |  |  |  |  |
JMP | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. |  |  |  |  |  |  |  |  |  |  |
LAHF | Cette instruction permet de transférer les bits d'indicateurs du registre d'état vers le registre AH. |  |  |  |  |  |  |  |  |  |  |
LAR | Cette instruction permet de charger le registre des indicateurs d'un descripteur. |  |  | M |  |  |  |  |  |  |  |
LDS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment DS et dans un registre d'offset spécifié. |  |  |  |  |  |  |  |  |  |  |
LEA | Cette instruction permet de copier l'offset d'une adresse de mémoire contenu dans un registre spécifié. |  |  |  |  |  |  |  |  |  |  |
LEAVE | Cette instruction permet de libérer une zone de mémoire attribué par l'instruction «ENTER» lorsqu'on utilise des procédures dans des langages de programmation de haut niveau. |  |  |  |  |  |  |  |  |  |  |
LES | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment ES et dans un registre d'offset spécifié. |  |  |  |  |  |  |  |  |  |  |
LFS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment FS et dans un registre d'offset spécifié. |  |  |  |  |  |  |  |  |  |  |
LGDT | Cette instruction permet de charger un descripteur de tables globale. |  |  |  |  |  |  |  |  |  |  |
LGS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment GS et dans un registre d'offset spécifié. |  |  |  |  |  |  |  |  |  |  |
LIDT | Cette instruction permet de charger un descripteur de tables d'interruption. |  |  |  |  |  |  |  |  |  |  |
LLDT | Cette instruction permet de charger un descripteur de tables local. |  |  |  |  |  |  |  |  |  |  |
LMSW | Cette instruction permet de copier 4 des bits d'une opérande vers les 4 bits de registre de contrôle CR0. |  |  |  |  |  |  |  |  |  |  |
LOCK | Cette instruction est utilisé comme préfixe avec d'autres instructions pour amener le microprocesseur à émettre un signal de vérouillage (Lock) sur le bus lors du traitement de l'instruction suivante. |  |  |  |  |  |  |  |  |  |  |
LODS | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction. |  |  |  |  |  |  |  |  | T |  |
LOOP | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0. |  |  |  |  |  |  |  |  |  |  |
LOOPE | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1. |  |  | T |  |  |  |  |  |  |  |
LOOPNE | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0. |  |  | T |  |  |  |  |  |  |  |
LSL | Cette instruction permet de charger la limite de segment d'un descripteur de segment spécifié avec l'opérande source dans l'opérande de destination et fixe le drapeau ZF du registre EFLAGS. |  |  | M |  |  |  |  |  |  |  |
LSS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment SS (Segment de pile) et dans un registre d'offset spécifié. |  |  |  |  |  |  |  |  |  |  |
LTR | Cette instruction permet de charger l'opérande source dans le champ du sélecteur de segment du registre de tâche. |  |  |  |  |  |  |  |  |  |  |
MONITOR | Cette instruction permet d'indiquer au microprocesseur quel rangé d'adresse est à serveiller par l'instruction STORE. |  |  |  |  |  |  |  |  |  |  |
MOV | Cette instruction permet de copier opérande source dans une opérande destinataire. |  |  |  |  |  |  |  |  |  |  |
MOV control, debug, test | Cette instruction permet de copier opérande source dans une opérande destinataire. | — | — | — | — | — | — |  |  |  |  |
MOVS | Cette instruction permet de copier un élément de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction. |  |  |  |  |  |  |  |  | T |  |
MOVSX | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires avec l'extension des signes. |  |  |  |  |  |  |  |  |  |  |
MOVZX | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires par des 0. |  |  |  |  |  |  |  |  |  |  |
MUL | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). | M | — | — | — | — | M |  |  |  |  |
MWAIT | Cette instruction permet d'indiquer au microprocesseur que l'état de l'alimentation de la ligne de cache est en attente d'écriture dans la plage d'adresse, mettant fin à la plupart des activités dans le noyau en le faisant. |  |  |  |  |  |  |  |  |  |  |
NEG | Cette instruction permet d'effectuer le complément à 2 d'une opérande. | M | M | M | M | M | M |  |  |  |  |
NOP | Cette instruction ne fait rien. |  |  |  |  |  |  |  |  |  |  |
NOT | Cette instruction permet d'inverser la valeur de chacun des bits d'une opérande. |  |  |  |  |  |  |  |  |  |  |
OR | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandessp écifiés. | 0 | M | M | — | M | 0 |  |  |  |  |
OUT | Cette instruction permet d'envoyer un octet, un mot ou un double mot sur le port d'entrée/sortie. |  |  |  |  |  |  |  |  |  |  |
OUTS | Cette instruction permet d'envoyer un octet, un mot ou un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. |  |  |  |  |  |  |  |  | T |  |
POP | Cette instruction permet de désempiler de la pile une mot ou un double mot et la met dans une opérande. |  |  |  |  |  |  |  |  |  |  |
POPA | Cette instruction permet de désempiler de la pile respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX. |  |  |  |  |  |  |  |  |  |  |
POPF | Cette instruction permet de désempiler de la pile le registre 16 bits de drapeau contenant les indicateurs d'état. | R | R | R | R | R | R | R | R | R | R |
PUSH | Cette instruction permet d'empiler une mot ou un double mot dans la pile. |  |  |  |  |  |  |  |  |  |  |
PUSHA | Cette instruction permet d'empiler respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX dans la pile. |  |  |  |  |  |  |  |  |  |  |
PUSHF | Cette instruction permet d'empiler respectivement le registre 16 bits de drapeau des indicateurs d'état dans la pile. |  |  |  |  |  |  |  |  |  |  |
RCL 1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | M |  |  |  |  | TM |  |  |  |  |
RCL compteur | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | — |  |  |  |  | TM |  |  |  |  |
RCR 1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | M |  |  |  |  | TM |  |  |  |  |
RCR compteur | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | — |  |  |  |  | TM |  |  |  |  |
RDMSR | Cette instruction permet de charger le contenu du modèle de registre 64-bits (MSR) indiquer par le registre ECX dans le couple de registre EDX:EAX. |  |  |  |  |  |  |  |  |  |  |
RDPMC | Cette instruction permet d'effectuer la lecture du compteur du moniteur de performance. |  |  |  |  |  |  |  |  |  |  |
RDTSC | Cette instruction permet de charger la valeur courante du compteur de temps du microprocesseur dans le couple de registres EDX:EAX. |  |  |  |  |  |  |  |  |  |  |
REP | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions tant que CX ne vaut pas 0. |  |  |  |  |  |  |  |  |  |  |
REPE | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0. |  |  |  |  |  |  |  |  |  |  |
REPNE | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1. |  |  |  |  |  |  |  |  |  |  |
RET | Cette instruction permet de quitter une procédure. |  |  |  |  |  |  |  |  |  |  |
ROL 1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | M |  |  |  |  | M |  |  |  |  |
ROL compteur | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | — |  |  |  |  | M |  |  |  |  |
ROR 1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | M |  |  |  |  | M |  |  |  |  |
ROR compteur | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | — |  |  |  |  | M |  |  |  |  |
RSM | Cette instruction permet de retourner le contrôle du programme du mode de gestion système (SMM) pour le programme d'application ou la procédure du système d'exploitation ayant été interrompu lorsque le microprocesseur à reçu un signal SSM. | M | M | M | M | M | M | M | M | M | M | M
SAHF | Cette instruction permet de copier les bits du registre AH dans l'octet de poids faible dans le registre des drapeaux (les indicateurs d'état). |  | R | R | R | R | R |  |  |  |  |
SAL 1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | M | M | M | — | M | M |  |  |  |  |
SAL compteur | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | — | M | M | — | M | M |  |  |  |  |
SAR 1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | M | M | M | — | M | M |  |  |  |  |
SAR compteur | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | — | M | M | — | M | M |  |  |  |  |
SBB | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande. | M | M | M | M | M | TM |  |  |  |  |
SCAS | Cette instruction permet de comparer un octet, un mot ou un double mot avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | M | M | M | M | M | M |  |  | T |  |
SETcc | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | T | T | T |  | T | T |  |  |  |  |
SGDT | Cette instruction permet d'entreposer le sélecteur de segment dans le registre GDTR (registre de table global de descripteur) dans l'opérande de destination. |  |  |  |  |  |  |  |  |  |  |
SHL 1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | M | M | M | — | M | M |  |  |  |  |
SHL compteur | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | — | M | M | — | M | M |  |  |  |  |
SHLD | Cette instruction permet d'effectuer une rotation des bits d'un double mot vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | — | M | M | — | M | M |  |  |  |  |
SHR 1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | M | M | M | — | M | M |  |  |  |  |
SHR compteur | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | — | M | M | — | M | M |  |  |  |  |
SHRD | Cette instruction permet d'effectuer une rotation des bits d'un double mot vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | — | M | M | — | M | M |  |  |  |  |
SIDT | Cette instruction permet d'entreposer le registre de descripteur de table d'interruption (IDTR) dans l'opérande de destination. |  |  |  |  |  |  |  |  |  |  |
SLDT | Cette instruction permet d'entreposer le sélecteur de segment dans le registre LDTR (registre de table local de descripteur) dans l'opérande de destination. |  |  |  |  |  |  |  |  |  |  |
SMSW | Cette instruction permet d'entreposer le mot des états (soit les bits de 0 à 15 du registre de contrôle CR0) à partir du registre de tâche (TR) dans l'opérande cible. |  |  |  |  |  |  |  |  |  |  |
STC | Cette instruction permet de fixer l'indicateur de retenue (CF) à la valeur 1. |  |  |  |  |  | 1 |  |  |  |  |
STD | Cette instruction permet de fixer l'indicateur de direction (DF) à la valeur 1. |  |  |  |  |  |  |  |  | 1 |  |
STI | Cette instruction permet de fixer l'indicateur d'interruption (IF) à la valeur 1. |  |  |  |  |  |  |  | 1 |  |  |
STOS | Cette instruction permet de copier un octet, un mot ou un double mot dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. |  |  |  |  |  |  |  |  | T |  |
STR | Cette instruction permet d'entreposer le sélecteur de segment à partir du registre de tâche (TR) à l'opérande cible |  |  |  |  |  |  |  |  |  |  |
SUB | Cette instruction permet de soustraire une valeur à une opérande. | M | M | M | M | M | M |  |  |  |  |
TEST | Cette instruction permet d'effectuer un «Et binaire» sur une opérande cible sans modifier sa valeur. | 0 | M | M | — | M | 0 |  |  |  |  |
UCOMISD | Cette instruction permet d'effectuer une comparaison désordonnée de valeurs réels de double précision dans la partie basse d'un double mot du premier opérande et du deuxième opérande, et fixe les drapeaux ZF, PF et FC dans le registre EFLAGS selon le résultat (non-ordonnée, supérieur à, inférieur ou égal) | 0 | 0 | M | 0 | M | M |  |  |  |  |
UCOMISS | Cette instruction permet d'effectuer une comparaison désordonnée de valeurs réels de simple précision dans la partie basse d'un double mot du premier opérande et du deuxième opérande, et fixe les drapeaux ZF, PF et FC dans le registre EFLAGS selon le résultat (non-ordonnée, supérieur à, inférieur ou égal) | 0 | 0 | M | 0 | M | M |  |  |  |  |
UD2 | Cette instruction permet de provoquer l'exécution d'un code indéfinie. |  |  |  |  |  |  |  |  |  |  |
VERR | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode lecture à partir du niveau de privilège courant (CPL). |  |  | M |  |  |  |  |  |  |  |
VERW | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode écriture à partir du niveau de privilège courant (CPL). |  |  | M |  |  |  |  |  |  |  |
WAIT | Cette instruction permet de faire passer le microprocesseur en mode d'attente jusqu'à ce que la ligne de teste sur la carte mère s'active. |  |  |  |  |  |  |  |  |  |  |
WBINVD | Cette instruction permet de désactiver et de vider le tampon interne du micro-processeur. |  |  |  |  |  |  |  |  |  |  |
WRMSR | Cette instruction écrit les valeurs contenu dans le MSR (Model-Specific Register) en fonction du registre d'index ECX dans la paire des registres EDX:EAX. |  |  |  |  |  |  |  |  |  |  |
XADD | Cette instruction permet d'échanger le premier opérande avec le deuxième opérande, et ensuite effectue la somme des valeurs dans le première opérande. | M | M | M | M | M | M |  |  |  |  |
XCHG | Cette instruction permet d'échanger la valeur de deux opérandes. |  |  |  |  |  |  |  |  |  |  |
XLAT | Cette instruction permet de remplacer le contenu du registre AL par un octet de la «tablesource». |  |  |  |  |  |  |  |  |  |  |
XOR | Cette instruction permet d'effectuer un OU exclusif BINAIRE sur les 2 opérandes spécifiés. | 0 | M | M | — | M | 0 |  |  |  |  |

Légende

Cette case vide permet d'indiquer que l'instruction n'affecte pas le drapeau.
— Ce symbole permet d'indiquer une instruction fixant une valeur indéfini.
0 Ce chiffre permet d'indiquer une instruction fixant la valeur du drapeau à 0.
1 Ce chiffre permet d'indiquer une instruction fixant la valeur du drapeau à 1.
M Cette lettre permet d'indiquer une instruction de modification de drapeau.
R Cette lettre permet d'indiquer une instruction restaurant la valeur du drapeau.
T Cette lettre permet d'indiquer une instruction de test de drapeau.

Références

Assembleur - Référence, Edition Micro Application, Pierre Maurette, 2003, ISBN: 2-7429-3061-2.
The Undocumented PC: A programmer's Guide to I/O, CPUs, and Fixed Memory Areas - Second Edition, Edition Addison-Wesley, Frank van Gilluwe, 1997, ISBN: 0-201-47950-8.
Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 1: Basic Architecture, Order Number: 253665-032US, Septembre 2009, volume I, A-1.

Dernière mise à jour : Samedi, le 21 décembre 2013


Langage de programmation - Assembleur 80x86 - Référence, lexique et dictionnaire des instructions 80x86 - Vue par microprocesseur (CPU)

Vu dans ... http://www.gladir.com Voici la liste des instructions d'origines des 8086 et 8088 :

Instruction | Signification | Description
AAA | ASCII adjust AL after addition | Cette instruction permet d'adapter le résultat obtenu par l'addition de 2 valeur en format DCB.
AAD | ASCII adjust AX before division | Cette instruction permet de convertir une valeur de format DCB non compactée.
AAM | ASCII adjust AX after multiplication | Cette instruction offre la possibilité de convertir le produit de la multiplication de 2 valeurs de format DCB en un format DCB.
AAS | ASCII adjust AL after subtraction | Cette instruction permet d'adapter le résultat de la soustraction de nombre de format DCB.
ADC | Add with carry | Cette instruction additionne 2 quantités numériques sur 8 ou 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu.
ADD | Add | Cette instruction additionne 2 quantités numérique sur 8, 16 ou 32 bits.
AND | And | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés.
CALL | Call procedure | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse d'appel avant de continuer.
CBW | Convert byte to word | Cette instruction permet de convertir un nombre contenu dans le registre AL en un format sur 16 bits pour se retrouver dans le registre AX en appliquant une extension du signe.
CLC | Clear carry flag | Cette instruction permet de mettre l'indicateur d'état de retenu CF à 0.
CLD | Clear direction flag | Cette instruction met l'indicateur d'état DF à 0, soit la direction croissante.
CLI | Clear interrupt flag | Cette instruction met l'indicateur d'état IF à 0, soit l'interdiction des interruptions.
CMC | Complement carry flag | Cette instruction offre la possibilité d'inverser la valeur de l'indicateur de retenue. Si ce dernier vaut 1, elle le met à 0 et inversement.
CMP | Compare operands | Cette instruction offre la possibilité essentielle de comparer 2 registres ou emplacements de mémoire.
CMPS | Compare String | Cette instruction permet d'effectuer la comparaison d'un octet, d'un mot ou double mot spécifié avec l'opérande source et destination spécifié et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison.
CMPSB | Compare String Byte | Cette instruction permet d'effectuer la comparaison d'un octet avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison.
CMPSW | Compare String Word | Cette instruction permet d'effectuer la comparaison d'un mot avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison.
CWD | Convert word to doubleword | Cette instruction est l'alternative pour convertir le mot du registre AX en un double mot contenu dans le couple de registre DX et AX par extension du signe.
DAA | Decimal adjust AL after addition | Cette instruction corrige après coup les retenues lors de la manipulation de valeur DCB.
DAS | Decimal adjust AL after subtraction | Cette instruction offre l'intéressante possibilité de corrige le résultat d'une soustraction de 2 nombres de format DCB compactées.
DEC | Decrement by 1 | Cette instruction décrément de 1 le registre ou l'adresse mémoire spécifié.
DIV | Unsigned divide | Cette instruction permet d'effectuer une division non-signée (nombre naturel).
ESC | Escape | Cette instruction active le coprocesseur, lequel se permettra d'utiliser les méthodes d'adressage du processeur principal (CPU).
HLT | Halt | Cette instruction permet de faire passer le microprocesseur en mode d'arrêt. Toutefois, le processeur peut quitter cet état lorsqu'une ligne matérielle RESET ou lorsqu'une interruption non-masquable (NMI) reçoit un signal.
IDIV | Integer divide | Cette instruction permet d'effectuer une division signée (nombre entier).
IMUL | Integer multiply | Cette instruction permet d'effectuer une multiplication signée (nombre entier).
IN | Input from port | Cette instruction permet de demander un octet, un mot ou un double mot provenant du port d'entrée/sortie et le retourne dans le registre accumulateur (AL, AX, EAX).
INC | Increment by 1 | Cette instruction permet d'incrémenter un registre ou un emplacement mémoire.
INT | Interrupt | Cette instruction permet d'exécuter l'interruption avec le numéro spécifié.
INTO | Interrupt if overflow | Cette instruction permet d'exécuter l'interruption numéro 4 si le drapeau de débordement (OF) est fixé sur 1é
IRET | Return from interrupt | Cette instruction permet d'effectuer un retour précédemment provoquer par une interruption.
Jcc | Jump if condition | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
JMP | Jump | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié.
LAHF | Load flags into AH register | Cette instruction permet de transférer les bits d'indicateurs du registre d'état vers le registre AH.
LDS | Load pointer using DS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment DS et dans un registre d'offset spécifié.
LEA | Load Effective Address | Cette instruction permet de copier l'offset d'une adresse de mémoire contenu dans un registre spécifié.
LES | Load ES with pointer | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment ES et dans un registre d'offset spécifié.
LOCK | Assert BUS LOCK# signal | Cette instruction est utilisé comme préfixe avec d'autres instructions pour amener le microprocesseur à émettre un signal de verrouillage (Lock) sur le bus lors du traitement de l'instruction suivante.
LODS | Load String | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction.
LODSB | Load String Byte | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 1 en fonction de l'état du drapeau de direction.
LODSW | Load String Word | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 2 en fonction de l'état du drapeau de direction.
LOOP | Loop | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0.
LOOPE | Loop equal | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1.
LOOPNE | Loop not equal | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0.
MOV | Move | Cette instruction permet de copier opérande source dans une opérande destinataire.
MOVS | Move String | Cette instruction permet de copier un élément de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction.
MOVSB | Move Byte from string to string | Cette instruction permet de copier un octet de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 1 en fonction de l'état du drapeau de direction.
MOVSW | Move Word from string to string | Cette instruction permet de copier un mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 2 en fonction de l'état du drapeau de direction.
MUL | Unsigned multiply | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel).
NEG | Negation | Cette instruction permet d'effectuer le complément à 2 d'une opérande.
NOP | No operation | Cette instruction ne fait rien.
NOT | Not | Cette instruction permet d'inverser la valeur de chacun des bits d'une opérande.
OR | Or | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandes spécifiés.
OUT | Output to port | Cette instruction permet d'envoyer un octet, un mot ou un double mot sur le port d'entrée/sortie.
POP | Pop data from stack | Cette instruction permet de désempiler de la pile une mot ou un double mot et la met dans une opérande.
POPF | Pop data into Flags register | Cette instruction permet de désempiler de la pile le registre 16 bits de drapeau contenant les indicateurs d'état.
PUSH | Push data onto stack | Cette instruction permet d'empiler une mot ou un double mot dans la pile.
PUSHF | Push flags onto stack | Cette instruction permet d'empiler respectivement le registre 16 bits de drapeau des indicateurs d'état dans la pile.
RCL 1 | Rotate left (with carry) | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré.
RCR 1 | Rotate right (with carry) | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré.
REP | Repeat | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions tant que CX ne vaut pas 0.
REPE | Repeat equal | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0.
REPNE | Repeat not equal | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1.
RET | Return from procedure | Cette instruction permet de quitter une procédure.
RETF | Return from far procedure | Cette instruction permet de quitter une procédure ayant lieu avec un appel long (FAR CALL).
RETN | Return from near procedure | Cette instruction permet de quitter une procédure ayant lieu avec un appel court (NEAR CALL).
ROL 1 | Rotate left | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré.
ROR 1 | Rotate right | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré.
SAHF | Store AH into flags | Cette instruction permet de copier les bits du registre AH dans l'octet de poids faible dans le registre des drapeaux (les indicateurs d'état).
SAL 1 | Shift Arithmetically left | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF).
SAR 1 | Shift Arithmetically right | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF).
SBB | Subtraction with borrow | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande.
SCAS | String Compare String | Cette instruction permet de comparer un octet, un mot ou un double mot avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction.
SCASB | String Compare String Byte | Cette instruction permet de comparer le registre AL avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction.
SCASW | String Compare String Word | Cette instruction permet de comparer le registre AX avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction.
SEG | Segment | Cette directive permet de demander la partie segment de l'adresse d'une opérande.
SETALC | Set AL Carry | Cette instruction permet de copier la valeur du drapeau de retenue dans le registre AL en la multipliant par 0FFh.
SHL 1 | Shift left | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF).
SHR 1 | Shift right | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF).
STC | Set carry flag | Cette instruction permet de fixer l'indicateur de retenue (CF) à la valeur 1.
STD | Set direction flag | Cette instruction permet de fixer l'indicateur de direction (DF) à la valeur 1.
STI | Set interrupt flag | Cette instruction permet de fixer l'indicateur d'interruption (IF) à la valeur 1.
STOS | Store in string | Cette instruction permet de copier un octet, un mot ou un double mot dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction.
STOSB | Store in string Byte | Cette instruction permet de copier le registre AL dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction.
STOSW | Store in string Word | Cette instruction permet de copier le registre AX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction.
SUB | Subtraction | Cette instruction permet de soustraire une valeur à une opérande.
TEST | Test | Cette instruction permet d'effectuer un «Et binaire» sur une opérande cible sans modifier sa valeur.
WAIT | Wait | Cette instruction permet de faire passer le microprocesseur en mode d'attente jusqu'à ce que la ligne de teste sur la carte mère s'active.
XCHG | Exchange | Cette instruction permet d'échanger la valeur de deux opérandes.
XLAT | Table look-up translation | Cette instruction permet de remplacer le contenu du registre AL par un octet de la «tablesource».
XOR | Exclusive OR | Cette instruction permet d'effectuer un OU exclusif BINAIRE sur les 2 opérandes spécifiés.

80186 et 80188

Voici la liste des instructions ajouter au 80186 et 80188 :

Instruction | Signification | Description
BOUND | Bounds | Cette instruction permet de vérifier la validité pouvant exister entre avec un tableau et son indexation.
ENTER | Enter stack frame | Cette instruction permet de créer les structures de paramètres nécessaires aux procédures des langages de haut niveau.
INS | Input from port to string | Cette instruction permet de demander un octet, un mot ou un double mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction.
INSB | Input from port to string Byte | Cette instruction permet de demander un octet du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction.
INSW | Input from port to string Word | Cette instruction permet de demander un mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction.
LEAVE | Leave stack frame | Cette instruction permet de libérer une zone de mémoire attribué par l'instruction «ENTER» lorsqu'on utilise des procédures dans des langages de programmation de haut niveau.
OUTS | Output string to port | Cette instruction permet d'envoyer un octet, un mot ou un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction.
OUTSB | Output String Byte to port | Cette instruction permet d'envoyer un octet contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 1 en fonction de l'état du drapeau de direction.
OUTSW | Output String Word to port | Cette instruction permet d'envoyer un mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 2 en fonction de l'état du drapeau de direction.
POPA | Pop All | Cette instruction permet de désempiler de la pile respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX.
PUSHA | Push All | Cette instruction permet d'empiler respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX dans la pile.

80286

Voici la liste des instructions ajouter au 80286 :

Instruction | Signification | Description
ARPL | Adjust RPL field of selector | Cette instruction permet de contrôler et corriger le niveau de privilège du segment de code en mode protégée.
CLTS | Clear task-switched flag in register CR0 | Cette instruction permet de mettre à 0 le drapeau de l'indicateur de tâche (Task-Switch) du registre CR0.
LAR | Load access rights byte | Cette instruction permet de charger le registre des indicateurs d'un descripteur.
LGDT | Load global descriptor table | Cette instruction permet de charger un descripteur de tables globale.
LIDT | Load interrupt descriptor table | Cette instruction permet de charger un descripteur de tables d'interruption.
LLDT | Load local descriptor table | Cette instruction permet de charger un descripteur de tables local.
LMSW | Load machine status word | Cette instruction permet de copier 4 des bits d'une opérande vers les 4 bits de registre de contrôle CR0.
LOADALL | Load all CPU registers | Cette instruction permet d'effectuer le chargement de tous les registres de descripteur de cache.
LSL | Load segment limit | Cette instruction permet de charger la limite de segment d'un descripteur de segment spécifié avec l'opérande source dans l'opérande de destination et fixe le drapeau ZF du registre EFLAGS.
LTR | Load task register | Cette instruction permet de charger l'opérande source dans le champ du sélecteur de segment du registre de tâche.
SGDT | Store global descriptor table | Cette instruction permet d'entreposer le sélecteur de segment dans le registre GDTR (registre de table global de descripteur) dans l'opérande de destination.
SIDT | Store interrupt descriptor table | Cette instruction permet d'entreposer le registre de descripteur de table d'interruption (IDTR) dans l'opérande de destination.
SLDT | Store local descriptor table | Cette instruction permet d'entreposer le sélecteur de segment dans le registre LDTR (registre de table local de descripteur) dans l'opérande de destination.
SMSW | Store machine status word | Cette instruction permet d'entreposer le mot des états (soit les bits de 0 à 15 du registre de contrôle CR0) à partir du registre de tâche (TR) dans l'opérande cible.
STR | Store task register | Cette instruction permet d'entreposer le sélecteur de segment à partir du registre de tâche (TR) à l'opérande cible
VERR | Verify a segment for reading | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode lecture à partir du niveau de privilège courant (CPL).
VERW | Verify a segment for writing | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode écriture à partir du niveau de privilège courant (CPL).

80386

Voici la liste des instructions ajouter au 80386 :

Instruction | Signification | Description
BSF | Bit scan forward | Cette instruction permet d'effectuer une comparaison binaire de la droite vers la gauche.
BSR | Bit scan reverse | Cette instruction permet d'effectuer une comparaison binaire de la gauche vers la droite.
BT | Bit test | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue.
BTC | Bit test and complement | Cette instruction transfère une Opérande vers l'indicateur de retenue le bits spécifié et inverser la valeur du bit correspondant.
BTR | Bit test and reset | Cette instruction permet de transférer l'Opérande vers l'indicateur de retenue le bits spécifié puis met le bits correspondant de l'Opérande à 0.
BTS | Bit test and set | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue le bits spécifié puis ensuite met le bits correspondant dans Opérande à 1.
CDQ | Convert double-word to quad-word | Cette instruction permet de convertir le double mot en un quadruple mot, le résultat tient sur une taille de 64 bits.
CMPSD | Compare string double-word | Cette instruction permet d'effectuer la comparaison d'un double mot avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison.
CWDE | Compare string double-word | Cette instruction est l'alternative pour convertir le mot du registre AX en un double mot contenu dans le registre EAX par extension du signe.
INSD | Input from port to string double-word | Cette instruction permet de demander un double mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction.
IRETD | Interrupt Return Doubleword | Cette instruction permet d'effectuer un retour 32-bits précédemment provoquer par une interruption.
JECXZ | Jump if register ECX is zero | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié si le registre ECX vaut 0.
LFS | Load pointer using FS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment FS et dans un registre d'offset spécifié.
LGS | Load pointer using GS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment GS et dans un registre d'offset spécifié.
LODSD | Load String Doubleword | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 4 en fonction de l'état du drapeau de direction.
LOOPD | Loop Double | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0.
LOOPED | Loop Equal Double | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0 et si le drapeau ZF vaut 1.
LOOPNED | Loop Not Equal Double | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0 et si le drapeau ZF vaut 0.
LOOPNZD | Loop Not Zero Double | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0 et si le drapeau ZF vaut 0.
LOOPZD | Loop Zero Double | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0 et si le drapeau ZF vaut 1.
LSS | Load pointer using SS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment SS (Segment de pile) et dans un registre d'offset spécifié.
MOVSD | Move String Doubleword | Cette instruction permet de copier un double mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 4 en fonction de l'état du drapeau de direction.
MOVSX | Move with sign-extend | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires avec l'extension des signes.
MOVZX | Move with zero-extend | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires par des 0.
OUTSD | Output String Doubleword | Cette instruction permet d'envoyer un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 4 en fonction de l'état du drapeau de direction.
POPAD | Pop all double-word | Cette instruction permet de désempiler de la pile respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX.
POPFD | Pop data into EFLAGS register | Cette instruction permet de désempiler de la pile le registre 32 bits de drapeau contenant les indicateurs d'état.
PUSHAD | Push all double-word | Cette instruction permet d'empiler respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX dans la pile.
PUSHFD | Push EFLAGS | Cette instruction permet d'empiler respectivement le registre 32 bits de drapeau des indicateurs d'état dans la pile.
SCASD | Scan string double-word | Cette instruction permet de comparer le registre EAX avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction.
SETcc | Set byte to one on condition | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0.
SHLD | Shift left double-word | Cette instruction permet d'effectuer une rotation des bits d'un double mot vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF).
SHRD | Shift right double-word | Cette instruction permet d'effectuer une rotation des bits d'un double mot vers la droite en réinsérant le bit dans l'indicateur de retenue (CF).
STOSD | Store string double-word | Cette instruction permet de copier le registre EAX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction.

80486

Voici la liste des instructions ajouter au 80486 :

Instruction | Signification | Description
BSWAP | Byte Swap | Cette instruction permet d'inverse l'ordre des 4 octets d'un registre de taille de 32 bits.
CMPXCHG | CoMPare and eXCHanGe | Cette instruction compare la destination avec l'accumulateur (AL, AX ou EAX) et les échanges si la condition est vrai.
INVD | Invalidate Internal Caches | Cette instruction permet de désactiver et de vider le tampon interne du micro-processeur.
INVLPG | Invalidate TLB Entry | Cette instruction permet d'invalider les transferts du TLB (Translation Lookaside Buffer) du micro-processeur
WBINVD | Write Back and Invalidate Cache | Cette instruction permet de désactiver et de vider le tampon interne du micro-processeur.
XADD | Exchange and Add | Cette instruction permet d'échanger le premier opérande avec le deuxième opérande, et ensuite effectue la somme des valeurs dans le première opérande.

Cyrix 6x86MX (EMMX)

Voici la liste des instructions ajouter au Cyrix 6x86MX (EMMX):

Instruction | Signification | Description
PADDSIW | Packed Add with Saturation | Cette instruction permet d'effectuer l'addition du mot de format entier de l'opérande source au mot de format entier de l'opérande de destination et écrit le résultat dans le registre MMX.
PAVEB | Packed Average Bits | Cette instruction permet d'effectuer le calcul de la moyenne des paquets spécifiés.
PDISTIB | Packed Distribution | Cette instruction permet d'effectuer le calcul de la distance entre des octets de deux opérandes, le résultat de l'addition d'octet de l'opérande de destination et la saturation du résultat.
PMACHRIW | Packed Multiply and Accumulate with Rounding | Cette instruction permet d'effectuer une multiplication de 2 opérandes sources en utilisant la méthode décrite par PMULHRW et accumule le résultat avec la valeur dans un registre de destination en utilisant un arrondissement arithmétique.
PMAGW | Packed Magnitude | Cette instruction permet d'effectuer la comparaison de la valeur absolue d'un paquet de mots de l'opérande source et de l'ensemble des mots de destination et fixe l'opérande de destination avec la valeur de la plus large magnitude.
PMULHRIW | Packed Multiply High with Rounding, result to Implied Register | Cette instruction permet de retourner le résultat d'une matrice de 16x16 bits avec un arrondissement LSB avant de tronquer les 16 bits et place ce résultat dans un registre MMX.
PMULHRW | Packed Multiply High with Rounding | Cette instruction permet de retourner le résultat d'une matrice de 16x16 bits avec un arrondissement LSB avant de tronquer les 16 bits.
PMVGEZB | Packed Conditional Move Great Zero Byte | Cette instruction permet de copier l'octet de paquet correspondant de l'opérande source dans l'opérande de destination si l'octet de l'opérande destination est supérieur à 0 et effectue se traitement pour chacun des 8 octets du paquet.
PMVLZB | Packed Conditional Move Less Zero Byte | Cette instruction permet de copier l'octet de paquet correspondant de l'opérande source dans l'opérande de destination si l'octet de l'opérande destination est inférieur à 0 et effectue se traitement pour chacun des 8 octets du paquet.
PMVNZB | Packed Conditional Move Not Zero Byte | Cette instruction permet de copier l'octet de paquet correspondant de l'opérande source dans l'opérande de destination si l'octet de l'opérande destination ne vaut pas 0 et effectue se traitement pour chacun des 8 octets du paquet.
PMVZB | Packed Conditional Move Zero Byte | Cette instruction permet de copier l'octet de paquet correspondant de l'opérande source dans l'opérande de destination si l'octet de l'opérande destination vaut 0 et effectue se traitement pour chacun des 8 octets du paquet.
PSUBSIW | Packed Subtract with Saturation | Cette instruction permet d'effectuer la soustraction du mot de format entier de l'opérande source au mot de format entier de l'opérande de destination et écrit le résultat dans le registre MMX.

Pentium

Voici la liste des instructions ajouter au Pentium:

Instruction | Signification | Description
CMPXCHG8B | CoMPare and eXCHanGe 8 bytes | Cette instruction compare un nombre de 64 bits et les échanges si la condition est vrai.
CPUID | CPU IDentification | Cette instruction retourne le code d'identification du microprocesseur.
RDMSR | ReaD from Model-Specific Register | Cette instruction permet de charger le contenu du modèle de registre 64-bits (MSR) indiquer par le registre ECX dans le couple de registre EDX:EAX.
RDTSC | ReaD Time Stamp Counter | Cette instruction permet de charger la valeur courante du compteur de temps du microprocesseur dans le couple de registres EDX:EAX.
RSM | Resume operation of interrupted program | Cette instruction permet de retourner le contrôle du programme du mode de gestion système (SMM) pour le programme d'application ou la procédure du système d'exploitation ayant été interrompu lorsque le microprocesseur à reçu un signal SSM.
WRMSR | WRite to Model-Specific Register | Cette instruction écrit les valeurs contenu dans le MSR (Model-Specific Register) en fonction du registre d'index ECX dans la paire des registres EDX:EAX.

Pentium MMX

Voici la liste des instructions ajouter au Pentium MMX:

Instruction | Signification | Description
EMMS | Empty MMX State | Cette instruction fixe les mots marqués du MPU de chacun un.
MOVD | Move Doubleword | Cette instruction permet de copier l'opérande dans un registre XMM ou vice-versa.
MOVQ | Move Quadword | Cette instruction permet de copier un quadruple mot d'une opérande source vers une opérande destination dans le cas des registres XMM.
PACKSSDW | Pack with Signed Saturation DoubleWord | Cette instruction permet de compacté 8 paquets de double mots en mots.
PACKSSDW | Pack with Signed Saturation DoubleWord | Cette instruction permet de compacté 8 paquets de double mots en mots.
PACKSSWB | Pack with Signed Saturation Word Byte | Cette instruction permet de compacté 8 paquets d'entier en octets.
PACKUSWB | Pack with Signed Saturation Unsigned Word Byte | Cette instruction permet de compacté 8 paquets de mots en octets.
PADDB | Packed Add Byte | Cette instruction permet d'effectuer une addition scalaire sur un paquet de 8 octets.
PADDD | Packed Add Double | Cette instruction permet d'effectuer une addition scalaire sur un paquet de 2 double mots.
PADDSB | Packed Add with Saturation Byte | Cette instruction permet d'effectuer une addition scalaire avec saturation sur un paquet de 8 octets signés.
PADDSW | Packed Add with Saturation Word | Cette instruction permet d'effectuer une addition scalaire avec saturation sur un paquet de 4 entiers.
PADDUSB | Packed Add Unsigned with Saturation Byte | Cette instruction permet d'effectuer une addition scalaire avec saturation sur un paquet de 8 octets.
PADDUSW | Packed Add Unsigned with Saturation Word | Cette instruction permet d'effectuer une addition scalaire avec saturation sur un paquet de 4 mots.
PADDW | Packed Add Word | Cette instruction permet d'effectuer une addition scalaire sur un paquet de 4 mots.
PAND | Bitwise Logical AND | Cette instruction permet d'effectuer un «ET BINAIRE» d'un quadruple mot d'une opérande source avec une opérande destination dans le cas des registres XMM.
PANDN | Bitwise Logical AND | Cette instruction permet d'effectuer un «ET BINAIRE» et une «NEGATION» de chacun des bits d'un quadruple mot d'une opérande source avec une opérande destination dans le cas des registres XMM.
PCMPEQB | Packed Compare for Equal Byte | Cette instruction permet d'effectuer une comparaison sur un paquet d'octets et fixe la valeur de chacun d'eux à FFh s'ils sont égales sinon à 00h.
PCMPEQD | Packed Compare for Equal Byte | Cette instruction permet d'effectuer une comparaison sur un paquet de double mots et fixe la valeur de chacun d'eux à FFFFFFFFh s'ils sont égales sinon à 00000000h.
PCMPEQW | Packed Compare for Equal Word | Cette instruction permet d'effectuer une comparaison sur un paquet de mots et fixe la valeur de chacun d'eux à FFFFh s'ils sont égales sinon à 0000h.
PCMPGTB | Packed Compare for Greater Than Byte | Cette instruction permet d'effectuer une comparaison sur un paquet d'octets et fixe la valeur de chacun d'eux à FFh si l'opérande destinataire est supérieur à l'opérande source sinon à 00h.
PCMPGTD | Packed Compare for Greater Than Doubleword | Cette instruction permet d'effectuer une comparaison sur un paquet de double mots et fixe la valeur de chacun d'eux à FFFFFFFFFh si l'opérande destinataire est supérieur à l'opérande source sinon à 00000000h.
PCMPGTW | Packed Compare for Greater Than Word | Cette instruction permet d'effectuer une comparaison sur un paquet de mots et fixe la valeur de chacun d'eux à FFFFFh si l'opérande destinataire est supérieur à l'opérande source sinon à 0000h.
PMADDWD | Packed Multiply and Add Word | Cette instruction permet d'effectuer une multiplication de 2 registres MMX contenant dans un paquet de mots d'un emplacement/mémoire.
PMULHW | Packed Multiply and Add Word | Cette instruction permet d'effectuer la multiplication de la partie haute de chacun des mots des 2 paquets d'opérandes.
PMULLW | Packed Multiply and Add Word | Cette instruction permet d'effectuer la multiplication de la partie basse de chacun des mots des 2 paquets d'opérandes.
POR | Bitwise Logical OR | Cette instruction permet d'effectuer un «OU BINAIRE» d'un quadruple mot d'une opérande source avec une opérande destination dans le cas des registres XMM.
PSLLD | Packed Shift Left Logical Doubleword | Cette instruction permet d'effectuer le décalage de bits vers la gauche d'un paquet de double mots.
PSLLQ | Packed Shift Left Logical Quadword | Cette instruction permet d'effectuer le décalage de bits vers la gauche d'un quadruple mot.
PSLLW | Packed Shift Left Logical Word | Cette instruction permet d'effectuer le décalage de bits vers la gauche d'un paquet de mots.
PSRAD | Packed Shift Right Arithmetic Doubleword | Cette instruction permet d'effectuer le décalage arithmétique de bits vers la droite d'un paquet de double mots.
PSRAW | Packed Shift Right Arithmetic Word | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un paquet de mots.
PSRLD | Packed Shift Right Logical Doubleword | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un paquet de double mots.
PSRLQ | Packed Shift Right Logical Quadword | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un quadruple mot.
PSRLW | Packed Shift Right Logical Word | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un paquet de mots.
PSUBB | Packed Subtract Byte | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des octets d'un paquet contenu dans des opérandes de 64 bits.
PSUBD | Packed Subtract Byte | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PSUBSB | Packed Subtract with Saturation Byte | Cette instruction permet d'effectuer la soustraction avec saturation de la valeur de chacun des octets signés d'un paquet contenu dans des opérandes de 64 bits.
PSUBSW | Packed Subtract with Saturation Word | Cette instruction permet d'effectuer la soustraction du mot de format entier de l'opérande source au mot de format entier de l'opérande de destination et écrit le résultat dans l'opérande destinataire.
PSUBUSB | Packed Subtract with Saturation Unsigned Byte | Cette instruction permet d'effectuer la soustraction avec saturation de la valeur de chacun des octets d'un paquet contenu dans des opérandes de 64 bits.
PSUBUSW | Packed Subtract Unsigned with Saturation Word | Cette instruction permet d'effectuer la soustraction avec saturation de la valeur de chacun des mots d'un paquet contenu dans des opérandes de destinations.
PSUBW | Packed Subtract Words | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des mots d'un paquet contenu dans des opérandes de 64 bits.
PUNPCKHBW | Unpack High Bytes to Words | Cette instruction permet de décompacter des octets en mots dans le haut d'un paquets de 64 bits.
PUNPCKHDQ | Unpack High Dwords to Qwords | Cette instruction permet de décompacter des doubles mots en quadruples mots dans le haut d'un paquets de 64 bits.
PUNPCKHWD | Unpack High Words to Dwords | Cette instruction permet de décompacter des mots en double mots dans le haut d'un paquets de 64 bits.
PUNPCKLBW | Unpack Low Bytes to Words | Cette instruction permet de décompacter des octets en mots dans le bas d'un paquets de 64 bits.
PUNPCKLDQ | Unpack Low Dwords to Qwords | Cette instruction permet de décompacter des doubles mots en quadruples mots dans le bas d'un paquets de 64 bits.
PUNPCKLWD | Unpack Low Words to Dwords | Cette instruction permet de décompacter des mots en double mots dans le bas d'un paquets de 64 bits.
PXOR | Bitwise Logical Exclusive OR | Cette instruction permet d'effectuer un ou exclusif binaire d'un quadruple mot d'une opérande source avec une opérande destination dans le cas des registres XMM.
RDPMC | Read the Performance Monitoring Counter | Cette instruction permet d'effectuer la lecture du compteur du moniteur de performance.

Pentium Pro

Voici la liste des instructions ajouter au Pentium Pro:

Instruction | Description
CMOV | Cette instruction copie des données d'une source (valeur) à une destination (registre) à la condition que la condition demandé soit remplie.
FCOMI | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats.
FCOMIP | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats et désempile de la pile la valeur dans le registre.
FUCOMI | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et vérifie l'ordre des valeurs et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats.
FUCOMIP | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et vérifie l'ordre des valeurs et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats et désempile de la pile la valeur dans le registre.
FCMOV | Cette instruction permet de déplacé des nombres réel (virgule flottante) si la condition en question est satisfaite.
SYSENTER | Cette instruction permet d'effectuer le transférer du contrôle d'un point d'entrée au système d'exploitation.
SYSEXIT | Cette instruction permet de retourner du système d'exploitation à une application.
UD2 | Cette instruction permet de provoquer l'exécution d'un code indéfinie.

AMD K6-2

Voici la liste des instructions ajouter au AMD K6-2:

Instruction | Description
FEMMS | Cette instruction permet d'effacer les états MMX après le passage d'instructions MMX.
PAVGUSB | Cette instruction permet d'effectuer le calcul de la moyenne de paquets de 8 octets spécifiés.
PF2ID | Cette instruction permet de convertir un double mots d'un format réel à un format d'entier 32 bits.
PFACC | Cette instruction permet d'effectuer l'accumulation de double mots.
PFADD | Cette instruction permet d'effectuer l'addition de double mots.
PFCMPEQ | Cette instruction permet d'effectuer la comparaison d'égalité d'un paquet de double mots contenu dans des opérandes de 64 bits.
PFCMPGE | Cette instruction permet d'effectuer la comparaison d'égalité ou de supériorité d'un paquet de double mots contenu dans des opérandes de 64 bits.
PFCMPGT | Cette instruction permet d'effectuer la comparaison de supériorité d'un paquet de double mots contenu dans des opérandes de 64 bits.
PFMAX | Cette instruction permet de retourner la valeur maximal de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFMIN | Cette instruction permet de retourner la valeur minimal de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFMUL | Cette instruction permet d'effectuer la multiplication de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFRCP | Cette instruction permet d'effectuer la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFRCPIT1 | Cette instruction permet d'effectuer la première étape d'itération de la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFRCPIT2 | Cette instruction permet d'effectuer la deuxième étape d'itération de la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFRSQIT1 | Cette instruction permet d'effectuer la première étape d'itération de la racine carré de la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFRSQRT | Cette instruction permet d'effectuer la racine carré approximative de la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFSUB | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFSUBR | Cette instruction permet d'effectuer la soustraction inversé de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PI2FD | Cette instruction permet de convertir un paquet de format d'entier 32 bits à double mots d'un format réel.
PMULHRW | Cette instruction permet de retourner le résultat d'une matrice de 16x16 bits avec un arrondissement LSB avant de tronquer les 16 bits.
PREFETCH | Cette instruction permet d'effectuer le chargement de l'entrée d'une séquence d'alignement de mémoire de 64 bits de l'adresse mémoire spécifié dans le cache de données L1 du microprocesseur.
PREFETCHW | Cette instruction permet d'effectuer le chargement de l'entrée d'une séquence d'alignement de mémoire de 64 bits de l'adresse mémoire spécifié dans le cache de données L1 du microprocesseur dans un état de modification.
SYSCALL | Cette instruction permet d'effectuer le transfert du contrôle d'un point d'entrée fixe au système d'exploitation.
SYSRET | Cette instruction permet de retourner du système d'exploitation à une application.

Pentium III (SSE)

Voici la liste des instructions ajouter au Pentium III (SSE):

Instruction | Description
ADDPS | Cette instruction permet d'effectuer une addition SIMD de 4 paquets de valeurs réels de simple précision d'une opérande source et d'une opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de simple précision.
ADDSS | Cette instruction permet d'effectuer une addition de la partie basse d'une valeur réel de simple précision d'une opérande source et destination et entrepose le résultat dans une opérande de destination de valeur réel de simple précision.
ANDNPS | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes 128 bits spécifiés et inverse chacun des bits du résultat.
ANDPS | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes 128 bits spécifiés.
CMPPS | Cette instruction permet d'effectuer une comparaison SIMD de 4 paquets de valeurs réels de simple précision d'une opérande source et d'une opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination.
CMPSS | Cette instruction permet d'effectuer une comparaison de la partie basse de valeurs réels de simple précision d'une opérande source et d'une opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination.
COMISS | Cette instruction permet de comparer deux valeurs réel de simple-précision dans la partie faible du quadruple mot de deux opérande et fixe les drapeaux de ZF, PF et FC du registre EFLAGS en fonction du résultat (non-ordonnée, supérieur à, inférieur ou égal).
CVTPI2PS | Cette instruction permet de convertir un entier de format double mot en une valeur réel de simple précision compacté.
CVTPS2PI | Cette instruction permet de convertir une valeur réel de simple précision compacté en un entier de format double mot.
CVTSI2SS | Cette instruction permet de convertir un entier de format double mot en une valeur réel de simple précision.
CVTSS2SI | Cette instruction permet de convertir une valeur réel de simple précision en un entier de format double mot.
CVTTPS2PI | Cette instruction permet de convertir une valeur réel de simple précision compacté avec tronquage en un entier de format double mot compacté.
CVTTSS2SI | Cette instruction permet de convertir un entier de format double mot avec tronquage en une valeur réel de simple précision.
DIVPS | Cette instruction permet d'effectuer une division de valeur réel de simple précision de registre XMM ou d'emplacement mémoire de 128 bits.
DIVSS | Cette instruction permet d'effectuer une division scalaire de valeur réel de simple précision de registre XMM ou d'emplacement mémoire de 128 bits.
LDMXCSR | Cette instruction permet d'effectuer le chargement du mot de contrôle et d'état du flux d'extension SIMD d'une opérande mémoire 32 bits.
MASKMOVQ | Cette instruction permet d'entreposer les octets sélectionner de l'opérande source dans un emplacement mémoire de 64 bits.
MAXPS | Cette instruction permet de retourner la valeur maximal de chacune des paires de valeur entre l'opérande source et l'opérande de destination.
MAXSS | Cette instruction permet de retourner la valeur maximal entre l'opérande source et destination.
MINPS | Cette instruction permet de retourner la valeur minimal de chacune des paires de valeur entre l'opérande source et l'opérande de destination.
MINSS | Cette instruction permet de retourner la valeur minimal entre l'opérande source et destination.
MOVAPS | Cette instruction permet de copier le contenu de 4 paquets alignés de valeurs réel de simple précision (4 x 32 bits).
MOVHLPS | Cette instruction permet de copier le contenu du haut d'un paquet de valeurs réel de simple précision dans sa partie basse.
MOVHPS | Cette instruction permet de copier le contenu du haut de deux paquets de valeurs réel de simple précision dans une opérande de destination.
MOVLHPS | Cette instruction permet de copier le contenu du bas d'un paquet de valeurs réel de simple précision dans sa partie haute.
MOVLPS | Cette instruction permet de copier le contenu du bas de deux paquets de valeurs réel de simple précision dans un opérande de destination.
MOVMSKPS | Cette instruction permet de copier les bits de signes de quatre paquets de valeurs réels de simple précision d'un registre XMM dans les 4 bits les plus bas d'un registre 32 bits. Les autres bits du registres 32 bits sont fixés à 0.
MOVNTPS | Cette instruction permet de copier le contenu de 4 paquets alignés de valeurs réel de simple précision sans utiliser la méthode temporel pour minimiser la pollution du cache.
MOVNTQ | Cette instruction permet de copier une valeur 64 bits sans utiliser la méthode temporel pour minimiser la pollution du cache.
MOVSS | Cette instruction permet de copier une valeur réel de simple précision d'une opérande source vers une opérande de destination.
MOVUPS | Cette instruction permet de copier le contenu de 4 paquets désalignés de valeurs réel de simple précision (4 x 32 bits).
MULPS | Cette instruction permet d'effectuer la multiplication de chacune des paires de valeur de l'opérande source et l'opérande de destination.
MULSS | Cette instruction permet d'effectuer la multiplication scalaire de l'opérande source et l'opérande de destination.
ORPS | Cette instruction permet d'effectuer un OU BINAIRE de 128 bits sur les 2 opérandes spécifiés.
PAVGB | Cette instruction permet d'effectuer le calcul de la moyenne des paquets d'octets spécifiés.
PAVGW | Cette instruction permet d'effectuer le calcul de la moyenne des paquets des mots spécifiés.
PEXTRW | Cette instruction permet de copier le mot de l'opérande source spécifié par un compteur d'opérande dans l'opérande de destination.
PINSRW | Cette instruction permet d'effectuer une copie d'un mot d'un opérande source et de l'insérer dans l'opérande de destination de l'emplacement spécifié par un compteur d'opérande.
PMAXSW | Cette instruction permet de retourner la valeur maximal de chacun des mots (entier) des paquets contenu dans deux opérandes.
PMAXUB | Cette instruction permet de retourner la valeur maximal de chacun des octets des paquets contenu dans deux opérandes.
PMINSW | Cette instruction permet de retourner la valeur minimal de chacun des mots des paquets contenu dans deux opérandes.
PMINUB | Cette instruction permet de retourner la valeur minimal de chacun des octets des paquets contenu dans deux opérandes.
PMOVMSKB | Cette instruction permet de copiés les masques de chacun des octets d'un paquet contenu dans une opérande.
PMULHUW | Cette instruction permet d'effectuer la multiplication de la partie haute de chacun des entiers des 2 paquets d'opérandes.
PREFETCH0 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T0 du microprocesseur. Alias de PREFETCHT0.
PREFETCH1 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T1 du microprocesseur. Alias de PREFETCHT1.
PREFETCH2 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T2 du microprocesseur. Alias de PREFETCHT2.
PREFETCHNTA | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données NTA du microprocesseur.
PREFETCHT0 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T0 du microprocesseur. Alias de PREFETCH0.
PREFETCHT1 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T1 du microprocesseur. Alias de PREFETCH1.
PREFETCHT2 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T2 du microprocesseur. Alias de PREFETCH2.
PSADBW | Cette instruction permet d'effectuer le calcul la valeur de absolue de la différence des octets de paquet contenu dans une opérande source et destination.
PSHUFW | Cette instruction permet de copier une double mots d'un opérande source avec emplacement spécifié par un opérande immédiate dans un opérande de destination.
RCPPS | Cette instruction permet d'effectuer le calcul de la réciproque d'un paquet de valeurs de réel de simple précision.
RCPSS | Cette instruction permet d'effectuer le calcul de la réciproque d'une valeur de réel de simple précision.
RSQRTPS | Cette instruction permet de calculer la réciproque approximative de la racine carré d'un paquet de simple précision.
RSQRTSS | Cette instruction permet de calculer la réciproque approximative de la racine carré d'un scalaire de simple précision.
SFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant emmagasiner du SFENCE et les instructions suivant le SFENCE.
SHUFPS | Cette instruction permet de copier 4 paquets de valeurs de format réel de simple précision dans une opérande destinataire dans la partie basse d'un quadruple mot de celle-ci et copie 2 des 4 paquets de valeurs de format réel de simple précision dans l'opérande source dans la partie haute d'un quadruple mot de l'opérande destinataire.
SQRTPS | Cette instruction permet d'effectuer le calcul de la racine carré d'un paquet de valeur de simple précision réel de l'opérande source et de mettre son résultat dans l'opérande de destination sous forme d'un réel de simple précision.
SQRTSS | Cette instruction permet d'effectuer le calcul de la racine carré d'une valeur de simple précision réel de l'opérande source et de mettre son résultat dans l'opérande de destination sous forme d'un réel de simple précision.
STMXCSR | Cette instruction permet de copier le MXCSR dans un emplacement mémoire de 32 bits.
SUBPS | Cette instruction permet d'effectuer une soustraction de 4 paquets de valeurs réels de simple précision d'une opérande source et d'une opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de simple précision.
SUBSS | Cette instruction permet d'effectuer une soustraction de la partie basse d'une valeur réel de simple précision d'une opérande source et destination et entrepose le résultat dans une opérande de destination de valeur réel de simple précision.
UCOMISD | Cette instruction permet d'effectuer une comparaison désordonnée de valeurs réels de double précision dans la partie basse d'un double mot du premier opérande et du deuxième opérande, et fixe les drapeaux ZF, PF et FC dans le registre EFLAGS selon le résultat (non-ordonnée, supérieur à, inférieur ou égal)
UCOMISS | Cette instruction permet d'effectuer une comparaison désordonnée de valeurs réels de simple précision dans la partie basse d'un double mot du premier opérande et du deuxième opérande, et fixe les drapeaux ZF, PF et FC dans le registre EFLAGS selon le résultat (non-ordonnée, supérieur à, inférieur ou égal)
UNPCKHPS | Cette instruction permet d'effectuer un dépaquetage de la partie haute d'un réel de simple précision d'un opérande source et destination et met le résultat dans l'opérande de destination.
UNPCKLPS | Cette instruction permet d'effectuer un dépaquetage de la partie basse d'un réel de simple précision d'une opérande source et destination et met le résultat dans l'opérande de destination.
XORPS | Cette instruction permet d'effectuer un ou exclusif binaire de 4 paquets de valeurs réel de simple précision dans une opérande source et destination et de mettre le résultat dans l'opérande de destination.

Pentium 4 (SSE2)

Voici la liste des instructions ajouter au Pentium 4 (SSE2):

Instruction | Description
ADDPD | Cette instruction permet d'effectuer une addition de 2 paquets de valeurs réels de double précision d'un opérande source et d'un opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de double précision.
ADDSD | Cette instruction permet d'effectuer une addition de la partie basse d'une valeur réel de double précision d'un opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de double précision.
ANDNPD | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 paquets d'opérandes de valeur de format réel de double précision et inverse chacun des bits du résultat.
ANDPD | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 paquets d'opérandes de valeur de format réel de double précision.
CLFLUSH | Cette instruction permet de vider la ligne de cache d'une adresse linéaire.
CMPPD | Cette instruction permet d'effectuer une comparaison SIMD de 2 paquets de valeurs réels de double précision d'un opérande source et d'un opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination.
COMISD | Cette instruction permet de comparer deux valeurs réel de double-précision dans la partie faible du quadruple mot de deux opérande et fixe les drapeaux de ZF, PF et FC du registre EFLAGS en fonction du résultat (non-ordonnée, supérieur à, inférieur ou égal).
CVTDQ2PD | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de double précision.
CVTDQ2PS | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de simple précision.
CVTPD2DQ | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en double mot entier et fixe à 0 le reste du paquet.
CVTPD2PI | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en double mot entier.
CVTPD2PS | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en valeurs réel de simple précision et fixe à 0 le reste du paquet.
CVTPI2PD | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de double précision compacté.
CVTPS2DQ | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de simple précision en paquet de doubles mots entiers.
CVTPS2PD | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de simple précision en paquet de valeurs réel de double précision.
CVTSD2SI | Cette instruction permet d'effectuer la conversion d'une valeur réel de simple précision en valeur entier de double mots.
CVTSD2SS | Cette instruction permet d'effectuer la conversion d'une valeur réel de double précision en valeur réel de simple précision.
CVTSS2SD | Cette instruction permet de convertir une valeur réel de simple précision en une valeur réel de double précision.
CVTTPD2DQ | Cette instruction permet de convertir un paquet de valeur réel de double précision avec en un paquet d'entier de format double mot tronquer et fixe à 0 le reste du paquet.
CVTTPD2PI | Cette instruction permet de convertir une valeur réel de double précision compacté avec tronquage en un entier de format double mot compacté.
CVTTPS2DQ | Cette instruction permet de convertir un paquet de valeur réel de simple précision avec en un paquet d'entier de format double mot tronquer.
CVTTSD2SI | Cette instruction permet de convertir une valeur réel de double précision avec en un entier de format double mot tronquer.
DIVPD | Cette instruction permet d'effectuer une division de valeur réel de double précision de registre XMM ou d'emplacement mémoire de 128 bits.
DIVSD | Cette instruction permet d'effectuer une division scalaire de valeur réel de double précision de registre XMM ou d'emplacement mémoire de 128 bits.
LFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant le LFENCE et les instructions de chargement suivant le LFENCE.
MASKMOVDQU | Cette instruction permet d'entreposer les octets sélectionnés par l'opérande source dans une emplacement mémoire de 128 bits.
MAXPD | Cette instruction permet de retourner la valeur maximal de chacune des paires de valeur entre l'opérande source et l'opérande de destination de nombre réel de double précision.
MAXSD | Cette instruction permet de retourner la valeur maximal entre l'opérande source et destination de nombre réel de simple précision.
MFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant le MFENCE et les instructions de chargement et d'entreposage précédent le MFENCE.
MINPD | Cette instruction permet de retourner la valeur minimal de chacune des paires de valeur entre l'opérande source et l'opérande de destination de nombre réel de double précision.
MINSD | Cette instruction permet de retourner la valeur minimal entre l'opérande source et destination de nombre réel de simple précision.
MOVAPD | Cette instruction permet de copier le contenu de 2 paquets alignés de valeurs réel de double précision.
MOVHPD | Cette instruction permet de copier le contenu du haut de deux paquets de valeurs réel de double précision dans une opérande de destination.
MOVLPD | Cette instruction permet de copier le contenu du bas de deux paquets de valeurs réel de double précision dans un opérande de destination.
MOVMSKPD | Cette instruction permet de copier les bits de signes de deux paquets de valeurs réels de double précision d'un registre XMM dans les 2 bits les plus bas d'un registre 32 bits. Les autres bits du registres 32 bits sont fixés à 0.
MOVNTI | Cette instruction permet de copier une valeur 32 ou 64 bits dans un emplacement mémoire afin de minimiser la pollution du cache dans un processus léger.
MOVNTDQ | Cette instruction permet de copier le contenu de double quadruple mots d'un opérande source vers un opérande de destination sans utiliser la méthode temporel pour minimiser la pollution du cache.
MOVNTPD | Cette instruction permet de copier le contenu de valeur réel de double précision d'un opérande source vers un opérande de destination sans utiliser la méthode temporel pour minimiser la pollution du cache.
MOVSD | Cette instruction permet de copier un scalaire de valeur de double précision d'un opérande source vers un opérande destination.
MOVUPD | Cette instruction permet de copier le contenu de 2 paquets désalignés de valeurs réel de double précision.
MULPD | Cette instruction permet d'effectuer la multiplication de chacune des paires de valeur de double précision de l'opérande source et l'opérande de destination.
MULSD | Cette instruction permet d'effectuer la multiplication scalaire de valeurs réel de double précision de l'opérande source et l'opérande de destination.
ORPD | Cette instruction permet d'effectuer un OU BINAIRE de 128 bits sur les 2 opérandes réels de double précisions spécifiés.
PAUSE | Cette instruction permet d'améliorer les performances des boucles de «SPIN», en fournissant une indication pour le microprocesseur que le code courant est dans une boucle en «SPIN».
SHUFPD | Cette instruction permet de copier 4 paquets de valeurs de format réel de double précision dans un opérande destinataire dans la partie basse d'un quadruple mot de celle-ci et copie 2 des 4 paquets de valeurs de format réel de simple précision dans l'opérande source dans la partie haute d'un quadruple mot de l'opérande destinataire.
SQRTPD | Cette instruction permet d'effectuer le calcul de la racine carré d'un paquet de valeur de double précision réel de l'opérande source et de mettre son résultat dans l'opérande de destination sous forme d'un réel de double précision.
SQRTSD | Cette instruction permet d'effectuer le calcul de la racine carré d'une valeur de double précision réel de l'opérande source et de mettre son résultat dans l'opérande de destination sous forme d'un réel de double précision.
SUBPD | Cette instruction permet d'effectuer une soustraction de 2 paquets de valeurs réels de double précision d'un opérande source et d'un opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de double précision.
SUBSD | Cette instruction permet d'effectuer une soustraction de la partie basse d'une valeur réel de double précision d'un opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de double précision.
UCOMISD | Cette instruction permet d'effectuer une comparaison désordonnée de valeurs réels de double précision dans la partie basse d'un double mot du premier opérande et du deuxième opérande, et fixe les drapeaux ZF, PF et FC dans le registre EFLAGS selon le résultat (non-ordonnée, supérieur à, inférieur ou égal)
UNPCKHPD | Cette instruction permet d'effectuer un dépaquetage de la partie haute d'un réel de double précision d'un opérande source et destination et met le résultat dans l'opérande de destination.
UNPCKLPD | Cette instruction permet d'effectuer un dépaquetage de la partie basse d'un réel de double précision d'un opérande source et destination et met le résultat dans l'opérande de destination.
XORPD | Cette instruction permet d'effectuer un ou exclusif binaire de 2 paquets de valeurs réel de double précision dans un opérande source et destination et de mettre le résultat dans l'opérande de destination.

Pentium 4 (SSE3)

Voici la liste des instructions ajouter au Pentium 4 (SSE3):

Instruction | Description
LDDQU | Cette instruction permet de copier un quadruple mot d'une opérande source vers une opérande destination.
MONITOR | Cette instruction permet d'indiquer au microprocesseur quel rangé d'adresse est à serveiller par l'instruction STORE.
MWAIT | Cette instruction permet d'indiquer au microprocesseur que l'état de l'alimentation de la ligne de cache est en attente d'écriture dans la plage d'adresse, mettant fin à la plupart des activités dans le noyau en le faisant.

VMX

Voici la liste des instructions ajouter pour la virtualisation par INTEL sous le nom VMX :

Instruction | Description
INVEPT | Cette instruction permet d'invalider la cartographie dans translation des tampons (TLB) et des caches de pagination structuré dérivé des tables de pages étendue (EPT).
INVVPID | Cette instruction permet d'invalider la cartographie dans translation des tampons (TLB) et des caches de pagination structuré basé sur l'identificateur de processeur virtuel (VPID).
VMCALL | Cette instruction permet de fournir un mécanisme invité logiciel pour appeler un service dans un moniteur VM.
VMCLEAR | Cette instruction permet d'appliquer un VMCS à une région VMCS à l'adresse physique contenu dans l'opération spécifié.
VMLAUNCH | Cette instruction permet de gérer l'entrée VM par le VMCS courant, de façon à échoué si l'état de lancement VMCS courant n'est pas effacé. Si l'instruction est un succès, il définit l'état de lancement à relancer.
VMPTRLD | Cette instruction permet de marquer le pointeur VMCS courant valide et charge celui-ci avec une adresse physique dans l'opérande d'instruction.
VMPTRST | Cette instruction permet d'entreposer le pointeur VMCS courant dans l'adresse mémoire spécifié.
VMREAD | Cette instruction permet d'effectuer la lecture du champ spécifié dans le VMCS et l'entrepose dans l'opérande de destination spécifié.
VMRESUME | Cette instruction permet de gérer l'entrée VM par le VMCS courant, de façon à échoué si l'état le lancement VMCS courant n'est pas lancé.
VMWRITE | Cette instruction permet d'effectuer l'écriture du champ spécifié du VMCS spécifié par l'opérande source secondaire (registre seulement) en utilisant le contenu de l'opérande source primaire (registre ou mémoire).
VMXOFF | Cette instruction permet d'utiliser le processeur logique en dehors de l'opération VMX, de débloquer le signal INIT, de conditionnellement réactiver le A20M et d'effacer tous les rangs d'adresse du moniteur.
VMXON | Cette instruction permet d'utiliser le processeur logique dans une opération VMX avec le VMCS non courant, le signal INIT bloqué, la désactivation A20M, et en effaçant n'importe quel rang d'adresse du moniteur établit avec l'instruction MONITOR.

AMD-V

Voici la liste des instructions ajouter au AMD-V:

Instruction | Description
CLGI | Cette instruction permet d'effacer les drapeaux global d'interruption (GIF). Quand le GIF est à 0, toutes les interruptions externes sont désactivés.
SKINIT | Cette instruction permet de réinitialiser de façon sécuritaire le microprocesseur et de démarrer un logiciel de confiance comme un VMM.
STGI | Cette instruction permet de fixer les drapeaux global d'interruption (GIF). Quand le GIF est à 1, les interruptions externes sont réactivés.
VMLOAD | Cette instruction permet d'effectuer le chargement d'un sous-ensemble d'état de microprocesseur dans un VMCB spécifié par une adresse physique contenu dans le registre RAX.
VMMCALL | Cette instruction permet de fournir un mécanisme invité pour communiquer explicitement avec le VMM en générant un #VMEXIT.
VMRUN | Cette instruction permet de lancer l'exécution d'un flux d'instructions invité.
VMSAVE | Cette instruction permet d'entreposer un sous-ensemble d'état du microprocesseur dans un VMCB spécifié par une adresse phyisque contenu dans le registre RAX.

x86-64

Voici la liste des instructions ajouter au x86-64:

Instruction | Description
CMPXCHG16B | Cette instruction permet de comparer un nombre de 128 bits et les échanges si la condition est vrai.
CMPSQ | Cette instruction permet d'effectuer la comparaison d'un quadruple mot avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison.
INVLPGA | Cette instruction permet d'invalider la cartographie TLB (Translation Lookaside Buffer) pour une page virtual et un ASID spécifié.
IRETQ | Cette instruction permet d'effectuer un retour 64-bits précédemment provoquer par une interruption.
LODSQ | Cette instruction permet de copier un élément de l'adresse DS:(R)SI dans le registre accumulateur et incrémente/décrémente le registre (R)SI de 8 en fonction de l'état du drapeau de direction.
PUSHFQ | Cette instruction permet d'empiler respectivement le registre 64 bits de drapeau (RFLAGS) des indicateurs d'état dans la pile.
RDTSCP | Cette instruction permet de charger la valeur courante du compteur de temps du microprocesseur dans le couple de registres EDX:EAX et la valeur du TSC_AUX dans le registre ECX.
MOVSQ | Cette instruction permet de copier un quadruple mot de l'adresse DS:(R)SI dans l'adresse ES:(R)DI et incrémente/décrémente les registres (R)DI et (R)SI de 8 en fonction de l'état du drapeau de direction.
MOVSXD | Cette instruction permet de copier un registre de taille inférieur dans un registre 64 bits en remplissant les bits supplémentaires avec l'extension des signes.
POPFQ | Cette instruction permet de désempiler de la pile le registre 64 bits de drapeau (RFLAGS) contenant les indicateurs d'état.
STOSQ | Cette instruction permet de copier le registre RAX dans la cellule mémoire à l'adresse ES:[(R)DI] et incrémente/décrémente le registre (R)DI de 8 en fonction de l'état du drapeau de direction.
SWAPGS | Cette instruction permet de fournir une méthode à un logiciel système pour charger un pointeur sur une structure de données système.

AMD K10 (SSE4a)

Voici la liste des instructions ajouter au AMD K10 (SSE4a):

Instruction | Description
LZCNT | Cette instruction permet de compter le nombre de bits à 0 dans un registre 16, 32 ou 64 bits contenu dans l'opérande source.
POPCNT | Cette instruction permet de compter le nombre de bits à 1 que possède une opérande source et place le résultat dans un registre destinataire.

Références

Assembleur - Référence, Edition Micro Application, Pierre Maurette, 2003, ISBN: 2-7429-3061-2.
The Undocumented PC: A programmer's Guide to I/O, CPUs, and Fixed Memory Areas - Second Edition, Edition Addison-Wesley, Frank van Gilluwe, 1997, ISBN: 0-201-47950-8.

Dernière mise à jour : Samedi, le 21 décembre 2013


Langage de programmation - Assembleur 80x86 - Références des ports d'entrée/sortie 80x86

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Port(s) | Description | Prérequis
0000h | Ce port permet de manipuler le registre d'adresse du Canal 0 d'un contrôleur 8237A. | PC, XT, PC Junior, AT, PS/2
0001h | Ce port permet de manipuler le registre de compteur de mot du Canal 0 d'un contrôleur 8237A. | PC, XT, PC Junior, AT, PS/2
0002h | Ce port permet de manipuler le registre d'adresse du Canal 1 d'un contrôleur 8237A. | PC, XT, PC Junior, AT, PS/2
0003h | Ce port permet de manipuler le registre de compteur de mot du Canal 1 d'un contrôleur 8237A. | PC, XT, PC Junior, AT, PS/2
0004h | Ce port permet de manipuler le registre d'adresse du Canal 2 d'un contrôleur 8237A. | PC, XT, PC Junior, AT, PS/2
0005h | Ce port permet de manipuler le registre de compteur de mot du Canal 2 d'un contrôleur 8237A. | PC, XT, PC Junior, AT, PS/2
0006h | Ce port permet de manipuler le registre d'adresse du Canal 3 d'un contrôleur 8237A. | PC, XT, PC Junior, AT, PS/2
0007h | Ce port permet de manipuler le registre de compteur de mot du Canal 3 d'un contrôleur 8237A. | PC, XT, PC Junior, AT, PS/2
0008h | Ce port permet de manipuler le registre de commande et d'état d'un contrôleur 8237A. | PC, XT, PC Junior, AT, PS/2
0009h | Ce port permet de manipuler le registre de requête d'un contrôleur 8237A. | PC, XT, PC Junior, AT, PS/2
000Ah | Ce port permet de manipuler le registre de masque d'un contrôleur 8237A. | PC, XT, PC Junior, AT, PS/2
000Bh | Ce port permet de manipuler le registre de mode d'un contrôleur 8237A. | PC, XT, PC Junior, AT, PS/2
000Ch | Ce port permet d'effacer l'échange FLIP/FLOP entre le MSB/LSB d'un contrôleur 8237A. | PC, XT, PC Junior, AT, PS/2
000Dh | Ce port permet d'effacer le registre principal ou de lire le registre temporaire d'un contrôleur 8237A. | PC, XT, PC Junior, AT, PS/2
000Eh | Ce port permet d'effacer le registre de masque d'un contrôleur 8237A. | PC, XT, PC Junior, AT, PS/2
000Fh | Ce port permet de manipuler le registre de multiple masques d'un contrôleur 8237A. | PC, XT, PC Junior, AT, PS/2
0010h à 001Fh | Ces ports permettent de manipuler le DMA 1 du contrôleur 8237A. | AT
0010h à 001Fh | Ces ports permettent de manipuler le DMA 1 du contrôleur 8237A en mode de compatibilité. | PS/2
001Eh | Ce port permet de changer le registre d'index de l'ensemble de puce Oak (OAK Port Addr Ptr). | Ensemble de puce OTI-051, OTI-052 et OTI-053 d'Oak
001Fh | Ce port permet de manipuler le registre de données de l'ensemble de puce Oak (OAK Data Register). | Ensemble de puce OTI-051, OTI-052 et OTI-053 d'Oak
0020h | Ce port permet de manipuler le registre de commande du contrôleur d'interruption 1 du contrôleur 8259A. | PC, XT, PC Junior, AT, PS/2
0021h | Ce port permet de manipuler le registre de masque d'IRQ (Interrupt Request) du contrôleur d'interruption 1 du contrôleur 8259A. | PC, XT, PC Junior, AT, PS/2
0022h | Ce port permet de fixer le registre d'index de l'ensemble de puce ou du microprocesseur Cyrix. | Ensemble de puce, Microprocesseur Cyrix
0023h | Ce port permet de manipuler le registre de données de l'ensemble de puce ou du microprocesseur Cyrix. | Ensemble de puce, Microprocesseur Cyrix
0030h à 003Fh | Ces ports permettent de manipuler le contrôleur d'interruption programmable du contrôleur 8259A en mode eslave. | AT, PS/2
0040h | Ce port permet de manipuler le compteur de diviseur à l'aide du canal 0 du contrôleur 8253. | PC, XT, PC Junior, AT, PS/2
0041h | Ce port permet de manipuler le compteur de rafraichissement de la mémoire vive (RAM) à l'aide du canal 1 du contrôleur 8253. | PC, XT, PC Junior, AT, PS/2
0042h | Ce port permet de manipuler les fonctions cassettes et du PC Speaker à l'aide du canal 1 du contrôleur 8253. | PC, XT, PC Junior, AT, PS/2
0043h | Ce port permet de manipuler le mode de contrôle du contrôleur 8253. | PC, XT, PC Junior, AT, PS/2
0044h | Ce port permet de manipuler le minuterie étendue du contrôleur 8254. | PS/2
0047h | Ce port permet de manipuler le contrôleur d'octet à l'aide du canal 3 du contrôleur 8254. | AT, PS/2
0048h à 005Fh | Ce port permet de manipuler la minuterie programmable du contrôleur 8254. | AT
0060h | Ce port permet de manipuler le registre A en entrée et sortie du contrôleur 8255A destiné au clavier. | PC, XT
0060h | Ce port permet de manipuler le registre A en sortie du contrôleur 8255A destiné au clavier. | PC Junior
0060h | Ce port permet de manipuler le registre A en entrée et sortie du contrôleur 8042 destiné au clavier. | AT, PS/2
0061h | Ce port permet de manipuler le registre B de sortie du contrôleur 8255A destiné au clavier. | PC, XT, PC Junior
0061h | Ce port permet de manipuler le port système du 8042 pour être compatible au registre B de sortie du contrôleur 8255A destiné au clavier. | AT, PS/2
0062h | Ce port permet de manipuler le registre C d'entrée du contrôleur 8255A. | PC, XT, PC Junior
0063h | Ce port permet de manipuler le registre de commande et de mode du contrôleur 8255A. | PC, XT, PC Junior
0064h | Ce port permet de manipuler le registre de commande et de mode du contrôleur 8042 destiné au clavier. | AT, PS/2
0065h à 006Fh | Ces port permettent de manipuler le contrôleur 8042 destiné au clavier. | AT
0070h | Ce port permet de manipuler le registre d'index de la CMOS RAM/RTC. | AT, PS/2
0071h | Ce port permet de manipuler le registre de données de la CMOS RAM/RTC. | AT, PS/2
0074h | Ce port permet de manipuler la partie faible de l'adressage étendu CMOS RAM. | PS/2
0075h | Ce port permet de manipuler la partie forte de l'adressage étendu CMOS RAM. | PS/2
0076h | Ce port permet de manipuler le registre de données étendu CMOS RAM. | PS/2
0078h | Ce port permet d'effectuer la coordonnée horizontal de la souris. | Amstrad PC1512
007Ah | Ce port permet d'effectuer la coordonnée vertical de la souris. | Amstrad PC1512
0080h à 009Fh | Ces ports permettent de manipuler le registre de page du DMA du contrôleur 74LS612. | AT
0090h | Ce port permet de manipuler le contrôle l'arbitrage central. | PS/2
0091h | Ce port permet de manipuler la confirmation de sélection de carte. | PS/2
0092h | Ce port permet de manipuler le registre A du contrôle de système. | PS/2
0093h | Ce port est réservé. | PS/2
0094h | Ce port permet de manipuler la configuration de la carte système. | PS/2
0096h à 0097h | Ces port permettent de manipuler le canal de sélection. | PS/2
00A0h | Ce port permet de manipuler le registre de masque NMI. | PC
00A0h à 00A1h | Ce port permet de manipuler le contrôleur d'interruption 2 du contrôleur 8259A. | AT, PS/2
00C0h à 00DFh | Ce port permet de manipuler le contrôleur DMA 2 du contrôleur 8237A-5. | AT, PS/2
00E0h | Ce port permet de manipuler le registre d'index de la CMOS RAM/RTC. | Certain XT disposant CMOS (Wyse XT, Amdek System/88)
00E1h | Ce port permet de manipuler le registre de données de la CMOS RAM/RTC. | Certain XT disposant CMOS (Wyse XT, Amdek System/88)
00F0h | Ce port permet de manipuler le contrôleur de disque. | PC Junior
00F2h | Ce port permet de manipuler le contrôle du contrôleur de disque. | PC Junior
00F4h | Ce port permet de manipuler le registre d'état du contrôleur de disque. | PC Junior
00F5h | Ce port permet de manipuler le registre de données du contrôleur de disque. | PC Junior
00F0h à 00FFh | Ce port permet de manipuler le coprocesseur mathématique. | AT, PS/2
0100h | Ce port permet de manipuler le registre de position 0 de l'octet d'identificateur d'adaptateur (LSB). | PS/2
0101h | Ce port permet de manipuler le registre de position 1 de l'octet d'identificateur d'adaptateur (MSB). | PS/2
0102h | Ce port permet de manipuler le registre de position 2 de l'octet de sélection de données 1. | PS/2
0102h | Ce port permet de mettre en mode dormance la carte vidéo VGA lors de l'ajustement. | AT avec carte vidéo Paradise PVGA1A ou PVGA1B
0103h | Ce port permet de manipuler le registre de position 3 de l'octet de sélection de données 2. | PS/2
0104h | Ce port permet de manipuler le registre de position 4 de l'octet de sélection de données 3. | PS/2
0105h | Ce port permet de manipuler le registre de position 5 de l'octet de sélection de données 4. | PS/2
0106h | Ce port permet de manipuler le registre de position 6 du sous-adresse de l'extension (LSB). | PS/2
0107h | Ce port permet de manipuler le registre de position 7 du sous-adresse de l'extension (MSB). | PS/2
0110h à 01EFh | Ces ports permettent de manipuler le canal d'entrée/sortie du système. | PC, XT, PC Junior, AT, PS/2
0168h | Ce port permet de manipuler le registre de données du disque dur numéro 3. | AT, PS/2
0169h | Ce port permet de manipuler le registre d'erreur du disque dur numéro 3. | AT, PS/2
016Ah | Ce port permet de manipuler le registre de compteur de secteur du disque dur numéro 3. | AT, PS/2
016Bh | Ce port permet de manipuler le registre de numéro de secteur du disque dur numéro 3. | AT, PS/2
016Ch | Ce port permet de manipuler le registre de la partie basse du cylindre du disque dur numéro 3. | AT, PS/2
016Dh | Ce port permet de manipuler le registre de la partie haute du cylindre du disque dur numéro 3. | AT, PS/2
016Eh | Ce port permet de manipuler le registre de tête du disque dur numéro 3. | AT, PS/2
016Fh | Ce port permet de manipuler le registre d'état du disque dur numéro 3. | AT, PS/2
0170h | Ce port permet de manipuler le registre de données du disque dur numéro 1. | AT, PS/2
0171h | Ce port permet de manipuler le registre d'erreur du disque dur numéro 1. | AT, PS/2
0172h | Ce port permet de manipuler le registre de compteur de secteur du disque dur numéro 1. | AT, PS/2
0173h | Ce port permet de manipuler le registre de numéro de secteur du disque dur numéro 1. | AT, PS/2
0174h | Ce port permet de manipuler le registre de la partie basse du cylindre du disque dur numéro 1. | AT, PS/2
0175h | Ce port permet de manipuler le registre de la partie haute du cylindre du disque dur numéro 1. | AT, PS/2
0176h | Ce port permet de manipuler le registre de tête du disque dur numéro 1. | AT, PS/2
0177h | Ce port permet de manipuler le registre d'état du disque dur numéro 1. | AT, PS/2
0180h à 184h | Ces ports permettent de manipuler la carte numéris. | Bus PCI
01E8h | Ce port permet de manipuler le registre de données du disque dur numéro 2. | AT, PS/2
01E9h | Ce port permet de manipuler le registre d'erreur du disque dur numéro 2. | AT, PS/2
01EAh | Ce port permet de manipuler le registre de compteur de secteur du disque dur numéro 2. | AT, PS/2
01EBh | Ce port permet de manipuler le registre de numéro de secteur du disque dur numéro 2. | AT, PS/2
01ECh | Ce port permet de manipuler le registre de la partie basse du cylindre du disque dur numéro 2. | AT, PS/2
01EDh | Ce port permet de manipuler le registre de la partie haute du cylindre du disque dur numéro 2. | AT, PS/2
01EEh | Ce port permet de manipuler le registre de tête du disque dur numéro 2. | AT, PS/2
01EFh | Ce port permet de manipuler le registre d'état du disque dur numéro 2. | AT, PS/2
01F0h | Ce port permet de manipuler le registre de données du disque dur numéro 0. | AT, PS/2
01F1h | Ce port permet de manipuler le registre d'erreur du disque dur numéro 0. | AT, PS/2
01F2h | Ce port permet de manipuler le registre de compteur de secteur du disque dur numéro 0. | AT, PS/2
01F3h | Ce port permet de manipuler le registre de numéro de secteur du disque dur numéro 0. | AT, PS/2
01F4h | Ce port permet de manipuler le registre de la partie basse du cylindre du disque dur numéro 0. | AT, PS/2
01F5h | Ce port permet de manipuler le registre de la partie haute du cylindre du disque dur numéro 0. | AT, PS/2
01F6h | Ce port permet de manipuler le registre de tête du disque dur numéro 0. | AT, PS/2
01F7h | Ce port permet de manipuler le registre d'état du disque dur numéro 0. | AT, PS/2
0200h à 020Fh | Ces ports permettent de manipuler l'adaptateur de manette de jeux. | PC, XT, PC Junior, AT
0201h | Ce port permet de demander l'état des positions des manettes de jeux. | PC, XT, PC Junior, AT
0210h à 028Fh | Ces ports permettent de manipuler les entrées/sorties de la carte de son SoundBlaster avec la puce CT-DSP-1321. | SoundBlaster
0210h | Ce port permet de manipuler le loquet d'expansion du bus de données lorsqu'on écrit sur le port ou de vérifier les données du bus d'expansion lorsqu'on lit le port. | XT
0211h | Ce port permet de tester le loquet et d'effacer l'attente lorsqu'on écrit sur le port ou d'effectuer la lecture de l'adresse de données MSB lorsqu'on lit le port. | XT
0212h | Ce port permet d'effectuer la lecture de l'adresse de données LSB lorsqu'on lit le port. | XT
0213h | Ce port permet de fixer l'état de l'unité d'expansion: 0 = Active, 1 = désactive. | XT
0214h | Ce port permet d'écrire des données sur le loquet d'expansion lorsqu'on écrit sur le port et d'effectuer la lecture de données sur le loquet d'expansion lorsqu'on lit le port. | XT
0215h | Ce port permet d'effectuer la lecture de l'adresse MSB lors de la première lecture, et d'effectuer la lecture de l'adresse LSB lors de la seconde lecture. | XT
220h à 026Fh | Ces ports permettent sont réservés pour les canal d'entrée/sortie. | PC, XT, PC Junior, AT, PS/2
260h à 027Fh | Ces ports permettent de manipuler la carte réseau compatible NE2000. | Carte réseau NE2000
0274h | Ce port permet de manipuler les périphériques systèmes Plug&Play. | Plug&Play
0278h | Ce port permet d'effectuer la lecture des données du port parallèle 2 (LPT2). | PC, XT, PC Junior, AT, PS/2
0279h | Ce port permet d'effectuer la lecture de l'état du port parallèle 2 (LPT2). | PC, XT, PC Junior, AT, PS/2
027Ah | Ce port permet de manipuler le registre de contrôle du port parallèle 2 (LPT2). | PC, XT, PC Junior, AT, PS/2
0280h à 02AFh | Ces ports permettent sont réservés pour les canal d'entrée/sortie. | PC, XT, PC Junior, AT, PS/2
02A2h à 02A3h | Ces ports permettent de manipuler l'horloge du contrôleur MSM5821RS. | PC, XT, PC Junior, AT, PS/2
02B0h à 02DFh | Ces ports permettent de manipuler la carte vidéo EGA secondaire. | EGA
02C0h à 02DFh | Ces ports permettent de manipuler le CMOS du contrôleur RTC-58321 ou MM58167. | Certain XT avec CMOS
02E0h | Ce port permet d'effectuer l'alternation entre les adaptateurs EGA et VGA. | EGA/VGA
02E1h | Ce port permet de manipuler le GPIB de l'unité 0. | AT
02E2h à 02E3h | Ces ports permettent d'effectuer la lecture des données de l'unité 0. | AT
02E8h à 02EFh | Ces ports permettent de manipuler le port de communication série 4 (COM4). | PC, XT, PC Junior, AT, PS/2
02F8h à 02FFh | Ces ports permettent de manipuler le port de communication série 2 (COM2). | PC, XT, PC Junior, AT, PS/2
02FDh | Ce port permet d'effectuer la lecture de l'état du registre de la ligne du port série 2. | PC, XT, PC Junior, AT
02FEh | Ce port permet d'effectuer la lecture de l'état du registre de Modem 2. | PC, XT, PC Junior, AT
0300h à 031Fh | Ces ports permettent de manipuler une carte prototype ou Numéris. | PC, XT, PC Junior, AT
0320h | Ce port permet de manipuler le contrôleur de disque dur MFM. | PC, XT (MFM)
0321h | Ce port permet de demander l'état du contrôleur de disque dur MFM lorsqu'on lit le port ou d'effectuer une réinitialisation du contrôleur lorsqu'on écrit sur le port. | PC, XT (MFM)
0322h | Ce port permet d'écrire la sélection de générateur de pulsion du contrôleur de disque dur MFM. | PC, XT (MFM)
0323h | Ce port permet d'écrire la palette du DMA et le registre de masque d'interruption du contrôleur de disque dur MFM. | PC, XT (MFM)
0324h | Ce port permet de demander l'état d'attention du contrôleur de disque dur MFM. | PC, XT (MFM)
0330h à 331h | Ces ports permettent de manipuler les fonctionnalités MIDI de la carte de son. | SoundBlaster
0360h à 036Fh | Ces ports permettent de manipuler la carte réseau PC. | AT
0370h | Ce port permet de manipuler le carte accélératrice de bande magnétique. | PC
0372h | Ce port permettent de manipuler la sortie digital de l'unité de disquette. | PC, XT, AT, PS/2
0374h | Ce port permettent de manipuler l'état du contrôleur de l'unité de disquette. | PC, XT, AT, PS/2
0375h | Ce port permettent de manipuler les données du contrôleur de l'unité de disquette. | PC, XT, AT, PS/2
0376h | Ce port permettent de manipuler les données du contrôleur de l'unité de disquette. | PC, XT, AT, PS/2
0377h | Ce port permettent de manipuler l'entrée digital de l'unité de disquette. | PC, XT, AT, PS/2
0378h à 037Fh | Ces ports permettent de manipuler le port parallèle 1 d'imprimante (LPT1). | PC, XT, PC Junior, AT
0378h à 037Bh | Ces ports permettent de manipuler le port parallèle 2 d'imprimante (LPT2). | PS/2
0380h à 038Ch | Ces ports permettent de manipuler la communication SDLC. | PC, XT, PC Junior, AT
0380h à 0389h | Ces ports permettent de manipuler la communication BSC secondaire. | PC, XT, PC Junior
0380h à 03A9h | Ces ports permettent de manipuler la carte de son. | AT
0390h à 0393h | Ces ports permettent de manipuler l'unité d'allocation de l'unité 0. | PC, XT, PC Junior, AT
03B4h à 03B5h | Ces ports permettent de manipuler le sous-système vidéo. | PS/2
03B4h/03B5h | Ces port permettent de manipuler le CRTC de la carte vidéo monochrome. | MDA, HGC, EGA, VGA, SVGA
03BAh | Ces ports permettent de manipuler le sous-système vidéo. | PS/2
03BCh à 03BFh | Ces ports permettent de manipuler le port parallèle 1 d'imprimante (LPT1). | PS/2
03C0h à 03CFh | Ces ports permettent de manipuler la carte vidéo EGA primaire. | EGA
03C0h à 03DAh | Ces ports permettent de manipuler le système vidéo et la DAC. | PS/2
03C4h/03C5h | Ces port permettent de manipuler le TS (Timing Sequencer) de la carte vidéo principal. | VGA et Super VGA
03D0h | Ce port est une redirection vers le port 03D4h du contrôleur 6845. | CGA, EGA, VGA
03D1h | Ce port est une redirection vers le port 03D5h du contrôleur 6845. | CGA, EGA, VGA
03D2h | Ce port est une redirection vers le port 03D4h du contrôleur 6845. | CGA, EGA, VGA
03D3h | Ce port est une redirection vers le port 03D5h du contrôleur 6845. | CGA, EGA, VGA
03D4h/03D5h | Ces port permettent de manipuler le CRTC de la carte vidéo couleur. | CGA, PC Junior, EGA, VGA, SVGA
03D6h | Ce port est une redirection vers le port 03D4h du contrôleur 6845. | CGA, EGA, VGA
03D6h | Ces port permettent de passer en mode plein écran. | OS/2
03D7h | Ce port est une redirection vers le port 03D5h du contrôleur 6845. | CGA, EGA, VGA
03D8h | Ce port permet de manipuler le registre de contrôle de mode et de couleur du contrôleur 6845. | CGA et Super CGA (Graphic Solutions d'ATI), EGA, VGA
03D9h | Ce port permet de manipuler le registre de sélection de palette de couleur du contrôleur 6845 des cartes vidéo couleur. | CGA, EGA, VGA, Graphic Solutions d'ATI
03DAh | Ce port permet de manipuler le registre d'état du contrôleur 6845 de la carte vidéo couleur. | CGA, PC Junior, EGA, VGA
03DBh | Ce port permet d'effacer le loquet du crayon lumineux du contrôleur 6845. | CGA, EGA
03DCh | Ce port permet de réinitialiser le loquet du crayon lumineux du contrôleur 6845. | CGA, EGA
03DDh | Ce port permet de programmer le registre de spécification graphique de la carte vidéo Graphic Solutions | Graphic Solutions d'ATI
03DEh/03DFh | Ces ports permettent de manipuler les services complémentaires et les extensions des Super VGA. | Super VGA
03DFh | Ce port permet de manipuler la page CRT/CPU. | PC Junior
03DFh | Ce port permet de manipuler les différents mode d'affichage d'écran de texte en 132 colonnes. | Graphic Solutions d'ATI
03E8h à 03EFh | Ces ports permettent de manipuler le port de communication série 3 (COM3). | PC, XT, PC Junior, AT
03F0h à 03F7h | Ces ports permettent de manipuler le contrôleur de disquette. | PC, XT, AT
03F8h à 03FFh | Ces ports permettent de manipuler le port de communication série 1 (COM1). | PC, XT, PC Junior, AT
03FDh | Ce port permet d'effectuer la lecture de l'état du registre de la ligne du port série 1. | PC, XT, PC Junior, AT
03FEh | Ce port permet d'effectuer la lecture de l'état du registre de Modem 1. | PC, XT, PC Junior, AT
04D0h à 04D1h | Ces ports permettent de manipuler le bus PCI. | Bus PCI
0534h à 0537h | Ces ports permettent de manipuler les fonctionnalités audio de la carte de son. | Bus PCI
06E2h à 06E3h | Ces ports permettent d'effectuer la lecture de données de l'unité 1. | AT
0778h à 077Fh | Ces ports permettent de manipuler le port parallèle d'imprimante 1 (LPT1). | Certain PC
0790h à 0793h | Ces ports permettent de manipuler les unités d'allocation de l'unité 1. | PC, XT, PC Junior, AT
0AE2h à 0AE3h | Ces ports permettent d'effectuer la lecture de données de l'unité 2. | AT
0B90h à 0B93h | Ces ports permettent de manipuler les unités d'allocation de l'unité 2. | PC, XT, PC Junior, AT
0CF8h à 0CFFh | Ces ports permettent de manipuler le bus PCI. | Bus PCI
0EE2h à 0EE3h | Ces ports permettent d'effectuer la lecture de données de l'unité 3. | AT
1390h à 1393h | Ces ports permettent de manipuler les unités d'allocation de l'unité 3. | PC, XT, PC Junior, AT
22E1h | Ce port permet de manipuler le GPIB de l'unité 1. | AT
2390h à 2393h | Ces ports permettent de manipuler les unités d'allocation de l'unité 4. | PC, XT, PC Junior, AT
3220h à 3227h | Ces ports permettent de manipuler le port de communication série 3 (COM3). | PS/2
3228h à 322Fh | Ces ports permettent de manipuler le port de communication série 4 (COM4). | PS/2
4220h à 4227h | Ces ports permettent de manipuler le port de communication série 5 (COM5). | PS/2
4228h à 422Fh | Ces ports permettent de manipuler le port de communication série 6 (COM6). | PS/2
42E1h | Ce port permet de manipuler le GPIB de l'unité 2. | AT
46E8h | Ce port permet de de désactiver le module. | AT avec carte vidéo Paradise PVGA1A ou PVGA1B
5220h à 5227h | Ces ports permettent de manipuler le port de communication série 7 (COM7). | PS/2
5228h à 522Fh | Ces ports permettent de manipuler le port de communication série 8 (COM8). | PS/2
62E1h | Ce port permet de manipuler le GPIB de l'unité 3. | AT
82E1h | Ce port permet de manipuler le GPIB de l'unité 4. | AT
A2E1h | Ce port permet de manipuler le GPIB de l'unité 5. | AT
C2E1h | Ce port permet de manipuler le GPIB de l'unité 6. | AT
D800h à D8FFh | Ces ports permettent de manipuler le contrôleur SCSI sur un bus PCI. | SCSI
E000h à E03Fh | Ces ports permettent de manipuler la carte réseau sur un bus PCI. | Bus PCI
E2E1h | Ce port permet de manipuler le GPIB de l'unité 7. | AT
E800h à E80Fh | Ces ports permettent de manipuler le contrôleur E-IDE dual de disque dur. | Certains PC

Dernière mise à jour : Samedi, le 2 août 2014


Langage de programmation - Assembleur 80x86 - Lexique et dictionnaire d'instruction assembleur 80x86 - Instruction OUT

Assembleur 80x86

OUT
INTEL 8088+ Output

Syntaxe

OUT adresse,accumulateur

Paramètres

Nom | Description
adresse | Ce paramètre permet d'indiquer l'adresse du port d'entrée/sortie. Il peut s'agir d'une valeur entre 0 et FFFFh. Voir Référence des ports d'entrée/sortie 80x86 pour plus de détails.
accumulateur | Ce paramètre permet d'indiquer la valeur envoyer dans le port d'entrée/sortie. Il peut s'agir d'un des 3 registres AL, AX ou EAX. Même avec les microprocesseurs 64 bits, il n'est pas possible d'envoyer une valeur plus grande que 32 bits.

Description

Cette instruction permet d'envoyer un octet, un mot ou un double mot sur le port d'entrée/sortie.

Algorithme

SI ((PE = 1) ET ((CPL > IOPL) ET (VM = 1))) ALORS * Mode protégé avec CPL > IOPL ou mode virtual 8086
SI (n'importe quel permission de bit d'E/S pour un port d'E/S à un accès = 1) ALORS
EXCEPTION #GP(0)
SINON
Port(adresse) ← accumulateur
FIN SI
SINON
Port(adresse) ← accumulateur
FIN SI

Mnémonique

Instruction | Opcode | Description
OUT imm8, AL | E6h ib | Met un octet contenu dans le registre AL dans le port spécifié par la valeur immédiate de 8 bits.
OUT imm8, AX | E7h ib | Met un mot contenu dans le registre AX dans le port spécifié par la valeur immédiate de 8 bits.
OUT imm8, EAX | E7h ib | Met un double mot contenu dans le registre EAX dans le port spécifié par la valeur immédiate de 8 bits.
OUT DX, AL | EEh | Met un octet contenu dans le registre AL dans le port spécifié par le registre DX.
OUT DX, AX | EFh | Met un mot contenu dans le registre AX dans le port spécifié par le registre DX.
OUT DX, EAX | EFh | Met un double mot contenu dans le registre EAX dans le port spécifié par le registre DX.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) |  | X |  | Un ou plusieurs bits de permission d'entrée/sortie sont fixer par le TSS pour un accès au port.
 |  |  | X | Le CPL est plus grand que le IOPL et une ou plusieurs bits de permission sont fixer par le TSS pour un accès au port.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction

Exemple

Cette exemple permet d'effectuer une commande de fin d'interruption (Port 0020h):

  1. MOV AL,20h
  2. OUT 20h,AL

Voir également

Référence des ports d'entrée/sortie 80x86
Instruction assembleur 80x86 - Instruction IN
Instruction assembleur 80x86 - Instruction INS
Instruction assembleur 80x86 - Instruction OUTS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 824
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 181.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 24 à 26.

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Dernière mise à jour : Lundi, le 1 septembre 2014


Langage de programmation - Assembleur 80x86 - Lexique et dictionnaire d'instruction assembleur 80x86 - Instruction IN

Assembleur 80x86

IN
INTEL 8088+ INput

Syntaxe

IN accumulateur,imm
IN accumulateur,DX

Description

Cette instruction permet de demander un octet ou un mot provenant du port d'entrée/sortie et le retourne dans le registre accumulateur (AL, AX, EAX).

Algorithme

SI ((PE = 1) ET ((CPL > IOPL) ET (VM = 1))) ALORS * Mode protégé avec CPL > IOPL ou mode virtual 8086
SI (n'importe quel permission de bit d'E/S pour un port d'E/S à un accès = 1) ALORS
EXCEPTION #GP(0)
SINON
accumulateur ← Port(adresse)
FIN SI
SINON
accumulateur ← Port(adresse)
FIN SI

Mnémonique

Instruction | Opcode | Description
IN AL, imm8 | E4h ib | Lit un octet dans un port d'entrée/sortie à l'adresse spécifié par l'imm8 et met le résultat dans le registre AL.
IN AX, imm8 | E5h ib | Lit un mot dans un port d'entrée/sortie à l'adresse spécifié par l'imm8 et met le résultat dans le registre AX.
IN EAX, imm8 | E5h ib | Lit un double mot dans un port d'entrée/sortie à l'adresse spécifié par l'imm8 et met le résultat dans le registre EAX.
IN AL, DX | ECh | Lit un octet dans un port d'entrée/sortie à l'adresse spécifié par le registre DX et met le résultat dans le registre AL.
IN AX, DX | EDh | Lit un mot dans un port d'entrée/sortie à l'adresse spécifié par le registre DX et met le résultat dans le registre AX.
IN EAX, DX | EDh | Lit un mot dans un port d'entrée/sortie à l'adresse spécifié par le registre DX et met le résultat dans le registre EAX.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) |  | X |  | Un ou plusieurs bits de permission d'entrée/sortie sont fixer par le TSS pour un accès au port.
 |  |  | X | Le CPL est plus grand que le IOPL et une ou plusieurs bits de permission sont fixer par le TSS pour un accès au port.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction

Voir également

Référence des ports d'entrée/sortie 80x86
Instruction assembleur 80x86 - Instruction OUT

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 812
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 117.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 568 à 569.

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Dernière mise à jour : Lundi, le 1 septembre 2014


Langage de programmation - Assembleur 80x86 - Références des ports d'entrée/sortie des 80x86 - Port 0070h/0071h - CMOS

Port d'entrée/sortie 80x86

0070h/0071h
AT, PS/2 CMOS RAM/RTC (MC146818)

Description

Les ports d'Entrée/Sortie 0070h et 0071h sont reliés au spécification du CMOS, le port 0070h donne accès à un registre, tandis que le 0071h est attribué à une commande de lecture ou d'écriture. Voici donc leur rôle :

Registre | Description
00h | Ce registre permet d'indiquer les secondes de l'horloge sur pile de l'ordinateur.
01h | Ce registre permet d'indiquer les secondes de l'alarme.
02h | Ce registre permet d'indiquer les minutes de l'horloge sur pile de l'ordinateur.
03h | Ce registre permet d'indiquer les minutes de l'alarme.
04h | Ce registre permet d'indiquer les heures de l'horloge sur pile de l'ordinateur.
05h | Ce registre permet d'indiquer les heures de l'alarme.
06h | Ce registre permet d'indiquer le jour de la semaine sur pile de l'ordinateur :
 | Valeur | Description
 | 01h | Cette valeur permet d'indiquer le Dimanche.
 | 02h | Cette valeur permet d'indiquer le Lundi.
 | 03h | Cette valeur permet d'indiquer le Mardi.
 | 04h | Cette valeur permet d'indiquer le Mercredi.
 | 05h | Cette valeur permet d'indiquer le Jeudi.
 | 06h | Cette valeur permet d'indiquer le Vendredi.
 | 07h | Cette valeur permet d'indiquer le Samedi.
07h | Ce registre permet d'indiquer le jour du mois sur pile de l'ordinateur.
08h | Ce registre permet d'indiquer le mois sur pile de l'ordinateur :
 | Valeur | Description
 | 01h | Cette valeur permet d'indiquer le mois de Janvier.
 | 02h | Cette valeur permet d'indiquer le mois de Février.
 | 03h | Cette valeur permet d'indiquer le mois de Mars.
 | 04h | Cette valeur permet d'indiquer le mois d'Avril.
 | 05h | Cette valeur permet d'indiquer le mois de Mai.
 | 06h | Cette valeur permet d'indiquer le mois de Juin.
 | 07h | Cette valeur permet d'indiquer le mois de Juillet.
 | 08h | Cette valeur permet d'indiquer le mois d'Août.
 | 09h | Cette valeur permet d'indiquer le mois de Septembre.
 | 0Ah | Cette valeur permet d'indiquer le mois d'Octobre en mode binaire.
 | 0Bh | Cette valeur permet d'indiquer le mois de Novembre en mode binaire.
 | 0Ch | Cette valeur permet d'indiquer le mois de Décembre en mode binaire.
 | 10h | Cette valeur permet d'indiquer le mois d'Octobre en mode BCD.
 | 11h | Cette valeur permet d'indiquer le mois de Novembre en mode BCD.
 | 12h | Cette valeur permet d'indiquer le mois de Décembre en mode BCD.
09h | Ce registre permet d'indiquer l'année sur pile de l'ordinateur.
0Ah | Ce registre permet d'indiquer le registre d'état A de la CMOS RAM/RTC :
 | Bit | Description
 | 0 à 3 | Ces bits permettant d'indiquer les impulsions de sorties. Par défaut, fixé à 0110b = 1,024 kHz, 976,562 microsecondes :
 |  | Valeur | Description
 |  | 0000b | Cette valeur permet d'indiquer qu'il n'y aucune impulsions.
 |  | 0011b | Cette valeur permet d'indiquer qu'il y 122 microsecondes d'impulsions.
 |  | 0110b | Cette valeur permet d'indiquer qu'il y 976,562 microsecondes d'impulsions.
 |  | 1111b | Cette valeur permet d'indiquer qu'il y 500 microsecondes d'impulsions.
 | 4 à 6 | Ces bits permettant d'indiquer les impulsions d'entrée. Par défaut, fixé à 010b = 32,768 kHz
 | 7 | Ce bit permet d'indiquer si une mise-à-jour est nécessaire :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer qu'il n'y a pas de mise-à-jour de l'horloge.
 |  | 1 | Cette valeur permet d'indiquer qu'il y a une mise-à-jour de l'horloge.
0Bh | Ce registre permet d'indiquer le registre d'état B de la CMOS RAM/RTC.
 | Bit | Description
 | 0 | Ce bit permet d'indiquer l'état de l'heure d'été :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer que l'heure d'été n'est pas activé.
 |  | 1 | Cette valeur permet d'indiquer que l'heure d'été est activé.
 | 1 | Ce bit permet d'indiquer le format de l'heure :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer que l'heure est sur une base de 12 heures avec un AM et PM.
 |  | 1 | Cette valeur permet d'indiquer que l'heure est sur une base de 24 heures.
 | 2 | Ce bit permet d'indiquer le format de données :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer que les données sont encodés en format BCD.
 |  | 1 | Cette valeur permet d'indiquer que les données sont encodés en format binaire.
 | 3 | Ce bit permet d'indiquer le signal de fréquence rectangulaire :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer qu'il n'y a pas de signal de fréquence rectangulaire.
 |  | 1 | Cette valeur permet d'indiquer qu'il y a un signal de fréquence rectangulaire.
 | 4 | Ce bit permet d'indiquer si les données de l'horloge sont mise-à-jour et l'interruption est exécuté :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer que les données ne sont pas mise-à-jour et que l'interruption n'est pas exécuté.
 |  | 1 | Cette valeur permet d'indiquer que les données sont mise-à-jour et que l'interruption est exécuté.
 | 5 | Ce bit permet d'indiquer si l'interruption d'alarme est autorisé :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer que l'interruption d'alarme n'est pas autorisé.
 |  | 1 | Cette valeur permet d'indiquer que l'interruption d'alarme est autorisé.
 | 6 | Ce bit permet d'indiquer si l'interruption périodique est autorisé :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer que l'interruption périodique n'est pas autorisé.
 |  | 1 | Cette valeur permet d'indiquer que l'interruption périodique est autorisé.
 | 7 | Ce bit permet d'indiquer que la date et l'heure sont réinitialisés :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer qu'il n'y a pas de réinitialisation.
 |  | 1 | Cette valeur permet d'indiquer qu'il y a une réinitialisation.
0Ch | Ce registre permet d'indiquer le registre d'état C de la CMOS RAM/RTC.
 | Bit | Description
 | 0 à 3 | Ces bits ont toujours la valeur 0.
 | 4 | Ce bit permet d'indiquer la mise-à-jour de l'horloge après l'interruption :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer qu'il n'y pas d'événement de mise-à-jour.
 |  | 1 | Cette valeur permet d'indiquer qu'il a mise-à-jour de l'horloge après l'interruption.
 | 5 | Ce bit permet d'indiquer l'interruption d'alarme programmable :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer qu'il n'y pas d'événement d'interruption d'alarme.
 |  | 1 | Cette valeur permet d'indiquer qu'il y a un événement d'interruption d'alarme.
 | 6 | Ce bit permet d'indiquer l'interruption périodique :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer qu'il n'y pas d'événement d'interruption périodique.
 |  | 1 | Cette valeur permet d'indiquer qu'il y a un événement d'interruption périodique.
 | 7 | Ce bit permet d'indiquer l'interruption :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer qu'il n'y pas d'événement d'interruption.
 |  | 1 | Cette valeur permet d'indiquer qu'il y a un événement d'interruption.
0Dh | Ce registre permet d'indiquer le registre d'état D de la CMOS RAM/RTC :
 | Bit | Description
 | 0 à 6 | Ces bits ont toujours la valeur 0.
 | 7 | Ce bit permet d'indiquer l'état du fonctionnement de l'horloge :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer que l'horloge fonctionne normalement.
 |  | 1 | Cette valeur permet d'indiquer que l'horloge ne fonctionne pas correctement, problème d'alimentation. Il s'agit la plupart du temps d'une batterie n'ayant plus aucune charge.
0Eh | Ce registre permet d'indiquer l'état de diagnostique de la CMOS RAM/RTC :
 | Bit | Description
 | 0 à 1 | Ces bits sont réservés
 | 2 | Ce bit permet d'indiquer l'état de l'analyse de l'heure :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer que l'heure est correcte.
 |  | 1 | Cette valeur permet d'indiquer que l'heure est invalide.
 | 3 | Ce bit permet d'indiquer l'état de l'analyse du contrôleur de disque dur :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer que le contrôleur de disque dur est correcte.
 |  | 1 | Cette valeur permet d'indiquer que le contrôleur de disque dur ou le disque dur lui-même n'est pas correctement initialisé.
 | 4 | Ce bit permet d'indiquer l'analyse de la taille de la mémoire par défaut :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer que la taille de la mémoire est correcte.
 |  | 1 | Cette valeur permet d'indiquer que la taille de la mémoire ne correspond pas aux entrées.
 | 5 | Ce bit permet d'indiquer l'état de la configuration :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer que la configuration est correcte.
 |  | 1 | Cette valeur permet d'indiquer que la configuration est incorrecte ou endommagé.
 | 6 | Ce bit permet d'indiquer que le résultat du test de sommation de vérification :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer que la sommation est incorrecte.
 |  | 1 | Cette valeur permet d'indiquer que la sommation est normal.
 | 7 | Ce bit permet d'indiquer l'état d'alimentation du MC146818 :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer qu'il fonctionne correctement.
 |  | 1 | Cette valeur permet d'indiquer que l'heure a été interrompu.
0Fh | Ce registre permet d'indiquer l'état de redémarrage de la CMOS RAM/RTC :
 | Valeur | Description
 | 00h | Cette valeur permet d'indiquer une réinitialisation logiciel ou redémarrage non demandé.
 | 01h | Cette valeur permet d'indiquer un redémarrage après que la taille de la mémoire est identifié.
 | 02h | Cette valeur permet d'indiquer un redémarrage après que la mémoire a été testé.
 | 03h | Cette valeur permet d'indiquer un redémarrage avec une erreur de mémoire.
 | 04h | Cette valeur permet d'indiquer un redémarrage avec une requête de redémarrage de chargement.
 | 05h | Cette valeur permet d'indiquer une requête «JMP DWORD» avec une initialisation d'interruption (INT).
 | 06h | Cette valeur permet d'indiquer un test 7 de mode protégé passé.
 | 07h | Cette valeur permet d'indiquer un test 7 de mode protégé échoué.
 | 08h | Cette valeur permet d'indiquer un test 1 de mode protégé échoué.
 | 09h | Cette valeur permet d'indiquer une requête de déplacement de bloc lors de redémarrage.
 | 0Ah | Cette valeur permet d'indiquer une requête «JMP DWORD» sans initialisation d'interruption (INT).
10h | Ce registre permet d'indiquer le type d'unité de disquette :
 | Bit | Description
 | 0 à 3 | Ce bit permet d'indiquer le type d'unité de disquette «A:» :
 |  | Valeur | Description
 |  | 0000b | Cette valeur permet d'indiquer qu'il n'y a pas d'unité de disquette d'installé.
 |  | 0001b | Cette valeur permet d'indiquer une unité de disquette 5 1/4" 360 Ko.
 |  | 0010b | Cette valeur permet d'indiquer une unité de disquette 5 1/4" 1,2 Mo.
 |  | 0011b | Cette valeur permet d'indiquer une unité de disquette 3 1/2" 720 Ko.
 |  | 0100b | Cette valeur permet d'indiquer une unité de disquette 3 1/2" 1,44 Mo.
 |  | 0101b | Cette valeur permet d'indiquer une unité de disquette 3 1/2" 2,88 Mo.
 | 4 à 7 | Ce bit permet d'indiquer le type d'unité de disquette «B:» :
 |  | Valeur | Description
 |  | 0000b | Cette valeur permet d'indiquer qu'il n'y a pas d'unité de disquette d'installé.
 |  | 0001b | Cette valeur permet d'indiquer une unité de disquette 5 1/4" 360 Ko.
 |  | 0010b | Cette valeur permet d'indiquer une unité de disquette 5 1/4" 1,2 Mo.
 |  | 0011b | Cette valeur permet d'indiquer une unité de disquette 3 1/2" 720 Ko.
 |  | 0100b | Cette valeur permet d'indiquer une unité de disquette 3 1/2" 1,44 Mo.
 |  | 0101b | Cette valeur permet d'indiquer une unité de disquette 3 1/2" 2,88 Mo.
11h | Ce registre permet d'indiquer la vitesse de répétition du clavier avec un BIOS AMI :
 | Bit | Description
 | 0 à 4 | Ces bits permettent d'indiquer taux de répétition d'une touche clavier :
 |  | Valeur | Description
 |  | 00000b | Cette valeur permet d'indiquer un taux de répétition de 30,0 caractères par seconde
 |  | 00001b | Cette valeur permet d'indiquer un taux de répétition de 26,7 caractères par seconde
 |  | 00010b | Cette valeur permet d'indiquer un taux de répétition de 24,0 caractères par seconde
 |  | 00011b | Cette valeur permet d'indiquer un taux de répétition de 21,8 caractères par seconde
 |  | 00100b | Cette valeur permet d'indiquer un taux de répétition de 20,0 caractères par seconde
 |  | 00101b | Cette valeur permet d'indiquer un taux de répétition de 18,5 caractères par seconde
 |  | 00110b | Cette valeur permet d'indiquer un taux de répétition de 17,1 caractères par seconde
 |  | 00111b | Cette valeur permet d'indiquer un taux de répétition de 16,0 caractères par seconde
 |  | 01000b | Cette valeur permet d'indiquer un taux de répétition de 15,0 caractères par seconde
 |  | 01001b | Cette valeur permet d'indiquer un taux de répétition de 13,3 caractères par seconde
 |  | 01010b | Cette valeur permet d'indiquer un taux de répétition de 12,0 caractères par seconde
 |  | 01011b | Cette valeur permet d'indiquer un taux de répétition de 10,9 caractères par seconde
 |  | 01100b | Cette valeur permet d'indiquer un taux de répétition de 10,0 caractères par seconde
 |  | 01101b | Cette valeur permet d'indiquer un taux de répétition de 9,2 caractères par seconde
 |  | 01110b | Cette valeur permet d'indiquer un taux de répétition de 8,6 caractères par seconde
 |  | 01111b | Cette valeur permet d'indiquer un taux de répétition de 8,0 caractères par seconde
 |  | 10000b | Cette valeur permet d'indiquer un taux de répétition de 7,5 caractères par seconde
 |  | 10001b | Cette valeur permet d'indiquer un taux de répétition de 6,7 caractères par seconde
 |  | 10010b | Cette valeur permet d'indiquer un taux de répétition de 6,0 caractères par seconde
 |  | 10011b | Cette valeur permet d'indiquer un taux de répétition de 5,5 caractères par seconde
 |  | 10100b | Cette valeur permet d'indiquer un taux de répétition de 5,0 caractères par seconde
 |  | 10101b | Cette valeur permet d'indiquer un taux de répétition de 4,6 caractères par seconde
 |  | 10110b | Cette valeur permet d'indiquer un taux de répétition de 4,3 caractères par seconde
 |  | 10111b | Cette valeur permet d'indiquer un taux de répétition de 4,0 caractères par seconde
 |  | 11000b | Cette valeur permet d'indiquer un taux de répétition de 3,7 caractères par seconde
 |  | 11001b | Cette valeur permet d'indiquer un taux de répétition de 3,3 caractères par seconde
 |  | 11010b | Cette valeur permet d'indiquer un taux de répétition de 3,0 caractères par seconde
 |  | 11011b | Cette valeur permet d'indiquer un taux de répétition de 2,7 caractères par seconde
 |  | 11100b | Cette valeur permet d'indiquer un taux de répétition de 2,5 caractères par seconde
 |  | 11101b | Cette valeur permet d'indiquer un taux de répétition de 2,3 caractères par seconde
 |  | 11110b | Cette valeur permet d'indiquer un taux de répétition de 2,1 caractères par seconde
 |  | 11111b | Cette valeur permet d'indiquer un taux de répétition de 2,0 caractères par seconde
 | 5 à 6 | Ces bits permettent d'indiquer délai de répétition d'une touche clavier :
 |  | Valeur | Description
 |  | 00b | Cette valeur permet d'indiquer une 250 millisecondes
 |  | 01b | Cette valeur permet d'indiquer une 500 millisecondes
 |  | 10b | Cette valeur permet d'indiquer une 750 millisecondes
 |  | 11b | Cette valeur permet d'indiquer une 1000 millisecondes
 | 7 | Ce bit permet d'indiquer la programmation taux de répétition d'une touche clavier est activé ou désativé.
12h | Ce registre permet d'indiquer le type d'unité de disque dur.
13h | Ce registre permet d'indiquer le drapeau de configuration système et démarrage avec un BIOS AMI :
 | Bit | Description
 | 0 | Ce bit permet d'indiquer si la touche NumLock est activé ou désactivé au démarrage.
 | 1 | Ce bit permet d'indiquer si une attente après la touche F1 après n'importe quel message d'erreur est activé ou désactivé au démarrage.
 | 2 | Ce bit permet d'indiquer qu'elle type de disque dur 47 dans la région de la RAM est utilisé : 0000h:0300h ou 1 Ko dans la région haute du DOS.
 | 3 | Ce bit permet d'indiquer si un déclencheur d'affichage de l'utilitaire SETUP est activé ou désactivé.
 | 4 | Ce bit permet d'indiquer si une vérification d'erreur de parité de mémoire est activé ou désactivé.
 | 5 | Ce bit permet d'indiquer si un tic sonore lors du test de mémoire est activé ou désactivé.
 | 6 | Ce bit permet d'indiquer si un test de la mémoire au delà du 1 Mo est activé ou désactivé.
 | 7 | Ce bit permet d'indiquer si le support de la souris est activé ou désactivé.
14h | Ce registre permet d'indiquer l'octet d'équipement :
 | Bit | Description
 | 0 | Ce bit permet d'indiquer si au moins une unité de disquette est installé :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer qu'il n'y a pas d'unité de disquette d'installé.
 |  | 1 | Cette valeur permet d'indiquer qu'il y a au moins une unité de disquette d'installé.
 | 1 | Ce bit permet d'indiquer si un coprocesseur mathématique est installé :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer qu'il n'y a pas de coprocesseur mathématique d'installé.
 |  | 1 | Cette valeur permet d'indiquer qu'il y a un coprocesseur mathématique d'installé.
 | 2 à 3 | Ces bits sont réservés.
 | 4 à 5 | Ces bits permettent d'indiquer l'affichage primaire :
 |  | Valeur | Description
 |  | 00b | Cette valeur permet d'indiquer qu'il n'y a pas d'affichage primaire.
 |  | 01b | Cette valeur permet d'indiquer que l'affichage primaire est 40 caractères par ligne en mode couleur (CGA).
 |  | 10b | Cette valeur permet d'indiquer que l'affichage primaire est 80 caractères par ligne en mode couleur (CGA).
 |  | 11b | Cette valeur permet d'indiquer que l'affichage primaire est monochrome.
 | 6 à 7 | Ces bits permettent d'indiquer le nombre d'unité de disquette :
 |  | Valeur | Description
 |  | 00b | Cette valeur permet d'indiquer qu'il y a qu'un seul unité de disquette.
 |  | 01b | Cette valeur permet d'indiquer qu'il y a deux unités de disquette.
 |  | 10b | Cette valeur permet d'indiquer qu'il y a trois unités de disquette.
 |  | 11b | Cette valeur permet d'indiquer qu'il y a quatre unités de disquette.
15h | Ce registre permet d'indiquer l'octet de poids faible de la taille de la mémoire conventionnel en KiloOctets.
16h | Ce registre permet d'indiquer l'octet de poids fort de la taille de la mémoire conventionnel en KiloOctets.
17h | Ce registre permet d'indiquer l'octet de poids faible de la taille de la mémoire étendue en accord avec la valeur du SETUP du BIOS en KiloOctets.
18h | Ce registre permet d'indiquer l'octet de poids fort de la taille de la mémoire étendue en accord avec la valeur du SETUP du BIOS en KiloOctets.
19h | Ce registre permet d'indiquer l'octet d'extension de l'unité de disque «C:». Utilisé par les AT seulement.
1Ah | Ce registre permet d'indiquer l'octet d'extension de l'unité de disque «D:». Utilisé par les AT seulement.
1Bh | Ce registre permet d'indiquer l'octet de poids faible du nombre de cylindres de l'unité de disque «C:» avec une définition utilisateur.
1Ch | Ce registre permet d'indiquer l'octet de poids fort du nombre de cylindres de l'unité de disque «C:» avec une définition utilisateur.
1Dh | Ce registre permet d'indiquer le nombre de têtes de l'unité de disque «C:» avec une définition utilisateur.
1Eh | Ce registre permet d'indiquer l'octet de poids faible du cylindres de précompensation d'écriture de l'unité de disque «C:» avec une définition utilisateur.
1Fh | Ce registre permet d'indiquer l'octet de poids fort du cylindres de précompensation d'écriture de l'unité de disque «C:» avec une définition utilisateur.
20h | Ce registre permet d'indiquer l'octet de contrôle de l'unité de disque «C:» avec une définition utilisateur.
21h | Ce registre permet d'indiquer l'octet de poids faible de la zone Landing de l'unité de disque «C:» avec une définition utilisateur.
22h | Ce registre permet d'indiquer l'octet de poids faible de la zone Landing de l'unité de disque «C:» avec une définition utilisateur.
23h | Ce registre permet d'indiquer le nombre de secteurs de l'unité de disque «C:» avec une définition utilisateur.
24h | Ce registre permet d'indiquer l'octet de poids faible du nombre de cylindres de l'unité de disque «D:» avec une définition utilisateur.
25h | Ce registre permet d'indiquer l'octet de poids fort du nombre de cylindres de l'unité de disque «D:» avec une définition utilisateur.
26h | Ce registre permet d'indiquer le nombre de têtes de l'unité de disque «D:» avec une définition utilisateur.
27h | Ce registre permet d'indiquer l'octet de poids faible du cylindres de précompensation d'écriture de l'unité de disque «D:» avec une définition utilisateur.
28h | Ce registre permet d'indiquer l'octet de poids fort du cylindres de précompensation d'écriture de l'unité de disque «D:» avec une définition utilisateur.
29h | Ce registre permet d'indiquer l'octet de contrôle de l'unité de disque «D:» avec une définition utilisateur.
2Ah | Ce registre permet d'indiquer l'octet de poids faible de la zone Landing de l'unité de disque «D:» avec une définition utilisateur.
2Bh | Ce registre permet d'indiquer l'octet de poids faible de la zone Landing de l'unité de disque «D:» avec une définition utilisateur.
2Ch | Ce registre permet d'indiquer le nombre de secteurs de l'unité de disque «D:» avec une définition utilisateur.
2Dh | Ce registre permet d'indiquer le drapeau d'opérations système avec un BIOS AMI :
 | Bit | Description
 | 0 | Ce bit permet d'indiquer si la fonction d'échangeur Turbo est activé ou désactivé.
 | 1 | Ce bit permet d'indiquer si le pont d'opération rapide A20 est activé ou désactivé.
 | 2 | Ce bit permet d'indiquer si le cache interne est activé ou désactivé.
 | 3 | Ce bit permet d'indiquer si le cache interne est activé ou désactivé.
 | 4 | Ce bit permet d'indiquer si le démarrage rapide du CPU est haut ou bas.
 | 5 | Ce bit permet d'indiquer si le séquence de démarrage est activé ou désactivé.
 | 6 | Ce bit permet d'indiquer si le positionnement de la disquette sur un secteur de démarrage est activé ou désactivé.
 | 7 | Ce bit permet d'indiquer si le processeur Weitek est présent ou absent.
2Eh | Ce registre permet d'indiquer l'octet de la partie basse de la somme de vérification.
2Fh | Ce registre permet d'indiquer l'octet de la partie haute de la somme de vérification.
30h | Ce registre permet d'indiquer l'octet de poids faible de la taille de la mémoire étendue en accord avec la valeur du POST.
31h | Ce registre permet d'indiquer l'octet de poids fort de la taille de la mémoire étendue en accord avec la valeur du POST.
32h | Ce registre permet d'indiquer le siècle sur pile de l'ordinateur en format BCD.
33h | Ce registre permet d'indiquer les informations d'ajustement :
 | Bit | Description
 | 0 | Ce bit permet d'indiquer si le test de cache de POST a réussis ou échoué.
 | 1 à 5 | Ces bits sont réservés.
 | 6 | Ce bit permet d'indiquer le drapeau d'initialisation de message du SETUP.
 | 7 | Ce bit permet d'indiquer si la cartouche d'extension BIOS de 128 Ko est installé :
 |  | Valeur | Description
 |  | 0 | Cette valeur permet d'indiquer qu'il n'y a pas de cartouche BIOS d'extension de 128 Ko d'installé.
 |  | 1 | Cette valeur permet d'indiquer qu'il y a une cartouche BIOS d'extension de 128 Ko d'installé.
34h | Ce registre permet d'indiquer les options de BIOS et de drapeau de Shadow avec un BIOS AMI :
 | Bit | Description
 | 0 | Ce bit permet d'indiquer d'activer ou désactiver le Shadow sur l'adaptateur de ROM à l'adresse DC00h d'une taille de 16 Ko.
 | 1 | Ce bit permet d'indiquer d'activer ou désactiver le Shadow sur l'adaptateur de ROM à l'adresse D800h d'une taille de 16 Ko.
 | 2 | Ce bit permet d'indiquer d'activer ou désactiver le Shadow sur l'adaptateur de ROM à l'adresse D400h d'une taille de 16 Ko.
 | 3 | Ce bit permet d'indiquer d'activer ou désactiver le Shadow sur l'adaptateur de ROM à l'adresse D000h d'une taille de 16 Ko.
 | 4 | Ce bit permet d'indiquer d'activer ou désactiver le Shadow sur l'adaptateur de ROM à l'adresse CC00h d'une taille de 16 Ko.
 | 5 | Ce bit permet d'indiquer d'activer ou désactiver le Shadow sur l'adaptateur de ROM à l'adresse C800h d'une taille de 16 Ko.
 | 6 | Ce bit permet d'indiquer que l'option de vérification de mot de passe est activé ou désactivé.
 | 7 | Ce bit permet d'indiquer d'activer ou désactiver la protection du secteur de démarrage contre les virus.
35h à 3Ch | Ces registres permettent d'indiquer les paramètres de type 49 de disque dur.
35h | Ce registre permet d'indiquer les options supplémentaire de BIOS et de drapeau de Shadow avec un BIOS AMI :
 | Bit | Description
 | 0 | Ce bit permet d'indiquer d'activer ou désactiver le test de coprocesseur mathématique.
 | 1 | Ce bit permet d'indiquer d'activer ou désactiver le Shadow sur l'adaptateur de ROM à l'adresse C400h d'une taille de 16 Ko.
 | 2 | Ce bit permet d'indiquer d'activer ou désactiver le Shadow sur l'adaptateur de ROM à l'adresse C000h d'une taille de 16 Ko.
 | 3 | Ce bit permet d'indiquer d'activer ou désactiver le Shadow sur l'adaptateur de ROM à l'adresse F000h d'une taille de 16 Ko.
 | 4 | Ce bit permet d'indiquer d'activer ou désactiver le Shadow sur l'adaptateur de ROM à l'adresse EC00h d'une taille de 16 Ko.
 | 5 | Ce bit permet d'indiquer d'activer ou désactiver le Shadow sur l'adaptateur de ROM à l'adresse E800h d'une taille de 16 Ko.
 | 6 | Ce bit permet d'indiquer d'activer ou désactiver le Shadow sur l'adaptateur de ROM à l'adresse E400h d'une taille de 16 Ko.
 | 7 | Ce bit permet d'indiquer d'activer ou désactiver le Shadow sur l'adaptateur de ROM à l'adresse E000h d'une taille de 16 Ko.
36h | Ce registre permet d'indiquer les informations de l'ensemble de puces sur certains avec un BIOS AWARD.
37h | Ce registre permet d'indiquer les options de couleurs et paramètre du mot de passe avec un BIOS AWARD.
38h à 3Dh | Ces registres permettent d'indiquer le mot de passe encrypté avec un BIOS AMI.
3Dh à 3Fh | Ces registres sont réservés.

Remarques

  • Le contenu des 64 registres du CMOS RAM/RTC sont conservés sur batterie, si bien que lorsque l'ordinateur est fermé, leur contenu est conservé et l'horloge contenu d'avancer normalement.

    Le BIOS utilise les registres 10h à 18h pour ses besoins interne lors de son passage de mode protégé vers le mode réel.

    L'interruption 1Ah utilise les fonctionnalités d'alarme et de l'heure de la journées. Voir Langage de programmation - Assembleur 80x86 - Interruption 1Ah.

    Le bit 5 du registre d'état de diagnostique est fixé durant le test de démarrage. Ce bit est fixé s'il n'y a pas d'unité de disquette trouvé ou que l'affichage ne correspond pas au ajustement d'affichage indiquer dans l'échangeur.

    Tous les registres envoyés par le port 70h ont les bits 6 et 7 d'effacé quand le bit 7 du port 70h est fixé pour active (1)/désactivé (0) le NMI.

    Quand un masque d'interruption NMI est utilisé pour le port 70h, le port 71h doit être imméditament lue après ou le RTC sera tenu dans un inconnu ou instable. Ceci peut affecté le chien de garde de la minuterie PS/2 ou le dépassement de délai d'un canal système.

Exemple

L'exemple suivant permet de retourner dans la paire de registres DX:AX le tic d'horloge de 18,2 par seconde identique à celle retourner par l'Interruption 1Ah, Fonction 00h en utilisant uniquement le contenu des cellules de mémoire du CMOS RAM/RTC :

  1. XOR AX,AX
  2. XOR DX,DX
  3. OUT 70h,AL
  4. IN  AL,71h
  5. MOV BL,AL
  6. MOV BH,AL
  7. AND BL,0Fh
  8. MOV CL,4
  9. SHR BH,CL
  10. MOV AL,10
  11. MUL BH
  12. ADD BL,AL
  13. MOV AL,18
  14. MUL BL
  15. MOV SI,AX
  16. MOV AL,2
  17. OUT 70h,AL
  18. IN  AL,71h
  19. MOV BL,AL
  20. MOV BH,AL
  21. AND BL,0Fh
  22. MOV CL,4
  23. SHR BH,CL
  24. MOV AL,10
  25. MUL BH
  26. ADD BL,AL
  27. MOV AL,182
  28. MUL BL
  29. MOV BX,6
  30. MUL BX
  31. ADD AX,SI
  32. ADC DX,0
  33. MOV SI,AX
  34. MOV DI,DX
  35. MOV AL,4
  36. OUT 070h,AL
  37. IN  AL,071h
  38. MOV BL,AL
  39. MOV BH,AL
  40. AND BL,0Fh
  41. MOV CL,4
  42. SHR BH,CL
  43. MOV AL,10
  44. MUL BH
  45. ADD BL,AL
  46. MOV AL,182
  47. MUL BL
  48. MOV BX,360
  49. MUL BX
  50. ADD AX,SI
  51. ADC DX,DI

Voir également

Langage de programmation - Assembleur 80x86 - Références des ports d'entrée/sortie 80x86 - Registre de données de la CMOS étendue (PS/2)
Langage de programmation - Assembleur 80x86 - Références des ports d'entrée/sortie 80x86 - Registre de données de la CMOS RAM/RTC (Certain XT disposant CMOS (Wyse XT, Amdek System/88)
Interruption 15h: Fonction 01h: Écrit dans la RAM non-volatile (Amstrad PC1512)
Interruption 15h: Fonction 02h: Lecture dans la RAM non-volatile (Amstrad PC1512)

Références

ABIOS for IBM PS/2 Computers and Compatibles - The Complete Guide to ROM-Based System Software for OS/2, Edition Addison-Wesley, Phoenix Technologies Ltd., 1987, ISBN: 0-201-51805-8, page 525 à 528.
Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 399 à 403.
The Indispensable PC Hardware Book - Fourth Edition, Edition Addison-Wesley, Hans-Peter Messmer, 2002, ISBN: 0-201-59616-4, page 604.

PARTAGER CETTE PAGE SUR
Dernière mise à jour : Samedi, le 2 août 2014


 alarm.c

#include
#include

#define MAX_ALARMS 20
typedef struct time_stamp
{
  int status;
  int hour;
  int min;
  int sec;
  char message[128];

} TIME_STAMP, *TIME_STAMP_PTR; //time_stamp

TIME_STAMP alarm_request;

int hour, min, sec;
int alarm_flag;
int min_index;

  char str[16];
  int local_flag = 1, x71h1=0, x71h2=0, x71h3;
  char old_0A1h_mask, old_70h_A_mask;

  int hour, min, secs;

void interrupt new0x70isr(void)
{

  alarm_flag = 1;
  asm {
   PUSH AX
   PUSH BX
   IN AL,70h   // Read existing port 70h
   MOV BX,AX

   MOV AL,0Ch  // Set up "Read status register C"
   OUT 70h,AL  //
   MOV AL,8Ch  //
   OUT 70h,AL  //
   IN AL,71h
   MOV AX,BX   //  Restore port 70h
   OUT 70h,AL  //

   MOV AL,20h   // Set up "EOI" value
   OUT 0A0h,AL  // Notify Secondary PIC
   OUT 020h,AL  // Notify Primary PIC

   POP BX
   POP AX

  } // asm */

} // new0x70isr

void beep(char msg[])
{
  int i;
  char msg1[128];

  strcpy(msg1, msg);
  for(i=0; i < 4; i++)
   {
     printf("\nALARM  ALARM ALARM\n");
     printf("%s",msg1);
     putchar(7);
     putchar(7);
     putchar(7);
     sleep(1);
   } //for
}//beep

int request_alarm(void)
{
  int i, found;
  int hour, min, sec;
  char string[128];
  unsigned char bcd_secs, bcd_min, bcd_hour;

  TIME_STAMP_PTR stptr;

  printf("\nEnter alarm time(hour:min:sec):");
  fgets(string, 128, stdin);
  sscanf(string, "%d:%d:%d", &hour, &min, &sec);
  printf("\nEnter alarm message:");
  fgets(string, 128, stdin);

  printf("hour = %d, min = %d, secs = %d\n", hour, min, sec);

  stptr = &alarm_request;
  if (stptr->status == 1)
  {
      fprintf(stderr, "Alarm exists\n");
      return -1;

  } //
  // (stptr->status == 0)

  stptr->status = 1;
  stptr->hour = hour;
  stptr->min = min;
  stptr->sec = sec;
  strcpy(stptr->message, string);

  bcd_secs = (sec/10)*16 + (sec % 10);
  bcd_min = (min/10)*16 + (min % 10);
  bcd_hour = (hour/10)*16 + (hour % 10);

  printf("hour = %x, min = %x, secs = %x\n",
        bcd_hour, bcd_min, bcd_secs);

 asm {
   PUSH AX
;
   IN AL,70h   // Set up "Write into alarm sec"
   MOV AL,01h  //
   OUT 70h,AL  //
   MOV AL,81h  //
   OUT 70h,AL  //
   IN AL,71h   //
   MOV AL,bcd_secs // set up alarm sec
   OUT 71h,AL  // Write into status register A
   IN AL,71h   // Read to confirm write
;
   IN AL,70h   // Set up "Write into alarm min"
   MOV AL,03h  //
   OUT 70h,AL  //
   MOV AL,83h  //
   OUT 70h,AL  //
   IN AL,71h   //
   MOV AL,bcd_min // set up alarm min
   OUT 71h,AL  // Write into status register A
   IN AL,71h   // Read to confirm write
;
   IN AL,70h   // Set up "Write into alarm hour"
   MOV AL,05h  //
   OUT 70h,AL  //
   MOV AL,85h  //
   OUT 70h,AL  //
   IN AL,71h   //
   MOV AL,bcd_hour // set up alarm hour
   OUT 71h,AL  // Write into status register A
   IN AL,71h   // Read to confirm write

   IN AL,70h  // Set up "Read into status resister C"
   MOV AL,0Ch // Required for for "Write into port 71h"
   OUT 70h,AL
   IN AL,70h
   MOV AL,8Ch //
   OUT 70h,AL
   IN AL,71h  // Read status register C
              // (we do nothing with it)

   IN AL,70h  // Set up "Read into status resister C"
   MOV AL,0Dh // Required for for "Write into port 71h"
   OUT 70h,AL
   IN AL,70h
   MOV AL,8Dh
   OUT 70h,AL
   IN AL,71h  // Read status register D
              // (we do nothing with it)

   POP AX
   } // asm

  return 1;

} //request_alarm

int  convert_to_binary(int x)
{
 int i;
 int temp, scale, result;

  temp =0;
  scale = 1;
  for(i=0; i < 4; i++)
   {
     temp = temp + (x % 2)*scale;
     scale *= 2;
     x = x >> 1;
   } // for

  result = temp;
  temp = 0;

  scale = 1;
  for(i=0; i < 4; i++)
   {
     temp = temp + (x % 2)*scale;
     scale *= 2;
     x = x >> 1;
   } // for

  temp *= 10;
  result = temp + result;
  return result;

} // convert_to_binary

void readclk(char str[])
{
  int i;

  hour = min = sec = 0;

  asm {
   PUSH AX
   MOV AL,0
   OUT 70h,AL
   IN AL,71h
   MOV BYTE PTR sec,AL
;
   MOV AL,2
   OUT 70h,AL
   IN AL,71h
   MOV BYTE PTR min,AL
;
   MOV AL,4
   OUT 70h,AL
   IN AL,71h
   MOV BYTE PTR hour,AL
;
   POP AX
  } // asm

  sec = convert_to_binary(sec);
  min = convert_to_binary(min);
  hour = convert_to_binary(hour);

  sprintf(str,"%2d:%2d:%2d", hour, min, sec);

} // readclk

int main()
{
  char str[16];
  int flag = 1;
  void interrupt (*old0x70isr)(void);

  alarm_flag = 0;

  old0x70isr = getvect(0x70);
  setvect(0x70, new0x70isr);

  asm {
   CLI         // Disable interrupts
   PUSH AX     // Interrupt may occur while updating

   IN AL,0A1h  // Make sure IRQ8 is not masked
   MOV old_0A1h_mask,AL
   AND AL,0FEh // Set bit 0 of port 0A1 to zero
   OUT 0A1h,AL //

   IN AL,70h   // Set up "Write into status register A"
   MOV AL,0Ah  //
   OUT 70h,AL  //
   MOV AL,8Ah  //
   OUT 70h,AL  //
   IN AL,71h   //
   MOV BYTE PTR x71h1,AL  // Save old value
   MOV old_70h_A_mask,AL
   AND AL,11110000b // Change only Rate
   OR AL,0110b // Make sure it is Rate =0110 (1Khz)
   OUT 71h,AL  // Write into status register A
   IN AL,71h   // Read to confirm write

   IN AL,70h  // Set up "Write into status register B"
   MOV AL,0Bh //
   OUT 70h,AL //
   MOV AL,8Bh //
   OUT 70h,AL //
   IN AL,71h  //
   MOV BYTE PTR x71h2,AL // Save Old value
   AND AL,8Fh // Mask out PI,AI,UI
   OR AL,20h  // Enable update interrupts (AI=1) only
   OUT 71h,AL // Write into status register  B
   IN AL,71h  // Read to confirm write
   MOV byte ptr x71h3,AL // Save old value

   IN AL,021h  // Make sure IRQ2 is not masked
   AND AL,0FBh // Write 0 to bit 2 of port 21h
   OUT 021h,AL // Write to port 21h

   IN AL,70h  // Set up "Read into status resister C"
   MOV AL,0Ch // Required for for "Write into port 71h"
   OUT 70h,AL
   IN AL,70h
   MOV AL,8Ch //
   OUT 70h,AL
   IN AL,71h  // Read status register C
              // (we do nothing with it)

   IN AL,70h  // Set up "Read into status resister C"
   MOV AL,0Dh // Required for for "Write into port 71h"
   OUT 70h,AL
   IN AL,70h
   MOV AL,8Dh
   OUT 70h,AL
   IN AL,71h  // Read status register D
              // (we do nothing with it)

   STI
   POP AX

  } // asm

  printf("x71h1 = %x, x71h2 = %x, x72h3  = %x\n", x71h1, x71h2, x71h3);

  while(flag)
  {
    putchar(13);
    readclk(str);
    printf(str);
    if (alarm_flag != 0)
    {
      beep(alarm_request.message);
      alarm_flag = 0;
      alarm_request.status = 0;
    } // if
    printf(" Enter either t for Terminate or r for Request alarm:");
      asm {
          PUSH AX
          MOV AH,1
          INT 16h
          PUSHF
          POP AX
          AND AX,64 /* isolate zf */
          MOV flag,AX
          POP AX
        } // asm
      if (flag == 0)
      {
        int c = 0;
         asm {
          MOV AH,0
          INT 16h
          MOV BYTE PTR c,AH
        }  // asm
        if (c != 20)
          flag = 1;
        if ( c == 19 ) //
           request_alarm();

      }// if

  } // while

    asm {
        MOV AL,old_0A1h_mask
        OUT 0A1h,AL

        IN AL,70h  // restore A status register
        MOV AL,0Ah
        OUT 70h,AL
        MOV AL,8Ah
        OUT 70h,AL
        IN AL,71h
        MOV AL,old_70h_A_mask
        OUT 71h,AL
        IN AL,71h

    } // asm
    setvect(0x70, old0x70isr);

}  // main


Langage de programmation - Assembleur 80x86 - Référence global de la mémoire des compatibles IBM PC

Voici une référence des adresses mémoire exploité par le système d'exploitation DOS ou compatible. Vous remarquerez que les adresses ne sont pas diviser en Segment:Offset mais plutôt en adresse physique en mémoire. Vous devrez conserver les 4 chiffres du haut pour le segment et garder le dernier du bas pour l'offset. A NOTER toutefois que bien que je ne voulais pas copier des auteurs de livre et ne pas respect leurs droits, il devient parfois difficile de ne pas avoir des similitudes pour une raison fort simple, il y a trop d'auteurs ( Aide-Mémoire de Les Interruptions Du MS-DOS de Philippe Mercier, La Bible du PC – Programmation Système de Michaël Tischer, Le Livre d'Or PC de Martin Althaus, Turbo Pascal 7 utile de François Gervais, les livres de Microsoft Press,...) ayant traiter de se sujet lors des années 1980, 1990 et ils ont carrément épuiser toutes les possibilités de dire les termes... J'ose croire que si un de ses auteurs parcours cette page, il se persuadera pas de m'actionner parce qu'il y a deux ou trois mots pareils à son livre.

Adresse | Longueur | Description
00000h à 003FCh | 1 Ko | Table des vecteurs d'interruption
00400h à 004FFh | 256 octets | Ces adresses sont utilisées par la ROM BIOS (sans oublier ceux des cartes vidéo EGA ou postérieur) ainsi que par de nombreuses applications DOS afin de pouvoir reconnaître correctement le matériel installer et d'agir en conséquence. Il est cependant peut flexible sur de nombreux aspect.
00400h à 00401h | 2 octets (1 mot) | On utilise cette adresse de base (port d'entrée/sortie) pour le COM1 ou désigne régulièrement la souris série affectant du même coup le COM3.
00402h à 00403h | 2 octets (1 mot) | On utilise cette adresse de base (port d'entrée/sortie) pour désigné le COM2
00404h à 00405h | 2 octets (1 mot) | On utilise cette adresse de base (port d'entrée/sortie) pour désigné le COM3
00406h à 00407h | 2 octets (1 mot) | On utilise cette adresse de base (port d'entrée/sortie) pour désigné le COM4
00408h à 00409h | 2 octets (1 mot) | On utilise cette adresse de base (port d'entrée/sortie) pour désigné le LPT1
0040Ah à 0040Bh | 2 octets (1 mot) | On utilise cette adresse de base (port d'entrée/sortie) pour désigné le LPT2
0040Ch à 0040Dh | 2 octets (1 mot) | On utilise cette adresse de base (port d'entrée/sortie) pour désigné le LPT3
0040Eh à 0040Fh | 2 octets (1 mot) | On utilise cette adresse de base (port d'entrée/sortie) pour désigné le LPT4
00410h à 00411h | 2 octets (1 mot) | Ce mot contient divers informations sur l'équipement de la machine actuellement installé.
Bits | Description
0 | Contient la valeur 1 advenant qu'il y ait au moins une unité de disquette installé sur la machine.
1 | Contient la valeur 1 si un coprocesseur mathématique est installé sur la machine.
2 et 3 | Lors des premiers PC, on utilisait ces bits pour indiquer la mémoire RAM disponible par le système sur la carte mère des PC et XT uniquement.
4 et 5 | Indique la carte vidéo installé exploiter au démarrage de la machine :
Valeur | Description
00b | Carte vidéo adaptateur spécial comme les cartes EGA, VGA ou PGA...
01b | Mode texte 40x25 en 16 couleurs
10b | Mode texte 80x25 en 16 couleurs
11b | Mode texte 80x25 en monochrome
6 et 7 | Indique le nombre d'unité de disquette installé:
Valeur | Description
00b | 1 lecteur
01b | 2 lecteurs
10b | 3 lecteurs
11b | 4 lecteurs
8 à 10 | Indique le nombre de ports série de format RS-232 installé.
12 | Aura la valeur 1 si une manette de jeux est installé
13 | Vaudra 1 si les modèle d'imprimante pour port série est installé.
14 et 15 | Indique le nombre d'imprimante connecté
00412h | 1 octet | Auto-test : Cet octet sert à stocker certaines informations pendant l'auto-test du système, étant effectué au cours de l'opération de démarrage du système (avant que le système d'exploitation ne soit lancer), y compris lors d'un démarrage à chaud. Il est utilisé par la suite par les routines du BIOS pour détecter la frappe de certaines touches mais il ne présente aucun intérêt pratique pour le programmeur.
00413h à 00414h | 2 octets (Mot) | La taille mémoire exprimée en Kilo-octets : A cet adresse de la mémoire figure un mot indiquant la capacité (RAM) de la mémoire conventionnel (celle se trouvant sous la barre des 1 Mo) en Ko. Cette donnée est également calculés au cours de l'opération de lancement du système et elle peut être lue à l'aide de l'interruption 12h du BIOS.
00415h à 00416h | 2 octets (Mot) | Tester: Une fois de plus, ces 2 octets sont exploités uniquement pendant l'opération du démarrage du système pour tester l'électronique. Ils n'ont plus aucune signification par la suite.
00417h | 1 octet | Premier ensemble d'État du clavier : Cet octet est appelé "octet d'état du clavier" puisqu'il indique l'état du clavier et de certaines touches spéciales. On pourra lire le contenu de cet octet grâce à la fonction 02h de l'INTERRUPTION 16h (clavier du BIOS). En accédant à cet octet, il est autre possible d'activer ou de désactiver les modes INSERT ou majuscules (CAPS) sur les BIOS AT ou postérieur. Seuls les 4 bits de plus fort poids de cet octet sont utiles à cet effet et il préférable d'éviter d'affecter les 4 bits inférieurs.
Bits | Description
0 | Vaut 1 si la touche Shift droite est actionnée
1 | Vaut 1 si la touche Shift gauche est actionnée
2 | Vaut 1 si une/des touches Ctrl sont actionnées
3 | Vaut 1 si la touche Alt est actionnée
4 | Vaut 1 si la touche Scroll Lock activée
5 | Vaut 1 si la touche Num Lock est activée
6 | Vaut 1 si la touche Caps Lock est activée
7 | Vaut 1 si le mode INSERT activé
00418h | 1 octet | Deuxième ensemble d'État du clavier: La signification de cet octet se rapproche drôlement de celle de l'octet de l'adresse 00417h avec cependant la différence que ce n'est pas l'état des modes INSERT ou majuscules étant mentionné mais davantage la position, "enfoncée" ou "non enfoncée", des touches correspondantes
Bits | Description
0 | Vaut si 1 la touche Ctrl gauche est enfoncée (à partir du AT ou postérieur)
1 | Vaut si 1 la touche Alt gauche est enfoncée (à partir du AT ou postérieur)
2 | Vaut si 1 la touche SysReq est enfoncée (à partir du AT ou postérieur)
3 | Vaut si 1 si le mode Pause est activé
4 | Vaut si 1 la touche Break est enfoncée
5 | Vaut si 1 la touche Num Lock est enfoncée
6 | Vaut si 1 la touche Caps Lock est enfoncée
7 | Vaut si 1 la touche INSERT est enfoncée
00419h | 1 octet | ALT+Code ASCII: Cet octet est utilisé lorsqu'on enfonce une combinaison de touche ALT+Code ASCII. Il conserva donc la valeur tapée lorsqu'on enfonce la touche ALT suivie d'un code ASCII.
0041Ah | 2 octets (1 mot) | Cet octet contient l'adresse du prochain caractère à extraire à partir du tampon clavier, il s'agit de l'adresse de début.
0041Ch | 2 octets (1 mot) | Cet octet contient l'adresse du dernier caractère (fin) du tampon clavier.
0041Eh | 32 octets (16 mots) | Tampon clavier: C'est dans cette zone de mémoire qu'est situé le véritable tampon clavier. Comme chaque caractère stocké dans le tampon clavier occupe 2 octets, sa taille est de 32 octets. Il pourra donc recevoir 16 touches au maximum. Pour un caractère ASCII normal, c'est d'abord le code ASCII du caractère, suivi de sa correspondance au niveau du code clavier, étant mémorisé ici. Le code clavier spécifier est le numéro de la touche ayant produit le caractère ASCII. Toutefois, si le caractère figurent dans le tampon clavier et que celui-ci possède un code étendu (par exemple une touche de déplacement), alors le premier octet contiendra 0 et le deuxième octet indiquera le code de la touche étendue. Le tampon lui-même est conçu comme une sorte de mémoire en anneau dans lequel on en insère tant qu'elle n'est pas pleine. L'adresse du prochain caractère à lire dans le tampon clavier est fournie par le mot à l'adresse 0041Ah. Lorsqu'un caractère est lu, ce pointeur est avancée de 2 octets vers la fin du tampon. Si un caractère a été lu dans la dernière cellule de mémoire du tampon, le pointeur est à nouveau fixé sur le début du tampon. Il en va exactement de même avec le pointeur placé à l'adresse 0041Ch, indiquant la fin du tampon clavier. Lorsqu'un nouveau caractère est entré, il est stocké, dans le tampon clavier, à l'endroit désigné par ce pointeur. Il est ensuite augmenté de 2 pour se rapprocher de la fin du tampon. Si un nouveau caractère vient d'être inséré dans le dernier emplacement tampon, le pointeur est à nouveau fixé sur le début tampon. La rapport entre le pointeur de début et le pointeur de fin du tampon est ainsi d'une grande importance pour juger de l'état du tampon. Deux situations revêtent à cet égard une signification particulière. Il s'agit tout d'abord du cas où les 2 pointeurs contiennent la même adresse. Ce terme exprime tout simplement qu'il n'y a pour le moment aucun caractère dans le tampon clavier. Le second cas est celui où on tente d'ajouter un caractère au-delà de la "fin" du tampon clavier. Cela supposerait que le pointeur de fin fût augmenté de 2 pour "rattraper" le pointeur de début. Ou par conséquent que le tampon clavier est plein et qu'il ne peut plus recevoir d'autres caractères. Si le début (0041Ah) = Fin(0041Ch), le tampon est vide.
00450h | 1 octet | Position X du curseur sur la page 0
00451h | 1 octet | Position Y du curseur sur la page 0
00452h | 1 octet | Position X du curseur sur la page 1
00453h | 1 octet | Position Y du curseur sur la page 1
00454h | 1 octet | Position X du curseur sur la page 2
00455h | 1 octet | Position Y du curseur sur la page 2
00456h | 1 octet | Position X du curseur sur la page 3
00457h | 1 octet | Position Y du curseur sur la page 3
00458h | 1 octet | Position X du curseur sur la page 4
00459h | 1 octet | Position Y du curseur sur la page 4
0045Ah | 1 octet | Position X du curseur sur la page 5
0045Bh | 1 octet | Position Y du curseur sur la page 5
0045Ch | 1 octet | Position X du curseur sur la page 6
0045Dh | 1 octet | Position Y du curseur sur la page 6
0045Eh | 1 octet | Position X du curseur sur la page 7
0045Fh | 1 octet | Position Y du curseur sur la page 7
0A0000h à 0AFFFFh | 64 Ko | Adresse de la mémoire graphique des modes supérieur au carte CGA.
0B0000h à 0B7FFFh | 32 Ko | Adresse de la mémoire vidéo des cartes monochromes ou des modes émuler correspondant à celui-ci.
0B8000h à 0BFFFFh | 32 Ko | Adresse de la mémoire vidéo des cartes couleurs CGA et de leur mode vidéo ainsi que de tous les modes texte couleurs.
C00F9h | 20 octets | Chaîne de caractère signature du BIOS ayant la forme «ATI Technologies Inc» du fabricant ATI.
C0110h | 29 octets | Chaîne de caractère signature du BIOS ayant la forme «ATI VGA EDGE-16, BIOS V5-1.01» du fabricant ATI.
C0110h | 21 octets | Chaîne de caractère signature du BIOS ayant la forme «VGA1024, BIOS V5-1.01» du fabricant ATI.
C011Eh | 7 octets | Chaîne de caractère signature du BIOS ayant la forme «V5-1.01» du fabricant ATI d'une carte VGA1024.
C0126h | 7 octets | Chaîne de caractère signature du BIOS ayant la forme «V5-1.01» du fabricant ATI d'une carte VGA EDGE-16.
C0181h | 9 octets | Chaîne de caractère signature du BIOS ayant la forme «IT - VGA2» du fabricant Inform Tech.
C94F9h | 23 octets | Chaîne de caractère signature du BIOS ayant la forme «Super BIOS II Formatter» du fabricant Western digital.
0E0000h à 0EFFFFh | 64 Ko | Cette banque de mémoire est souvent utiliser pour la mémoire EMS ou ces émulateurs. Sur certains XT on le retrouvera pour la ROM supplémentaire.
E0013h | Chaîne de caractère signature du BIOS ayant la forme «ROM DIAGNOSTICS (C) 1987, American Megatrends Inc.» du fabricant American Megatrends.
0F0000h à 0FFFFFh | Pouvant aller jusqu'à 64 Ko de mémoire. | Ces adresses sont utiliser pour la ROM BIOS de la carte mère.
F0004h à 0F0010h | 12 octets | Chaîne de caractère signature du BIOS ayant la forme «AAAAMMMMIIII» du fabricant American Megatrends.
F0005h | Chaîne de caractère signature du BIOS ayant la forme «Copyright 1984,1985 Phoenix Software Associates Ltd.» du fabricant WYSE dans ses machines Amdek System/88.
F0010h à 0F0017h | 8 octets | Chaîne de caractère signature du BIOS ayant la forme «07/07/91» du fabricant American Megatrends.
F0020h | Chaîne de caractère signature du BIOS ayant la forme «American Megatrends Inc.» du fabricant American Megatrends.
F0100h | Chaîne de caractère signature du BIOS ayant la forme «ROM BIOS (C) 1990 American Megatrends Inc.» du fabricant American Megatrends.
F0150h | Chaîne de caractère signature du BIOS ayant la forme «386DX-OP-PIc-25-F1-ZZ» du fabricant American Megatrends.
F0723h | Chaîne de caractère signature du BIOS ayant la forme «Real Time Clock Battery Problem Detected» du fabricant WYSE dans ses machines Amdek System/88.
F079Ch | Chaîne de caractère signature du BIOS ayant la forme «Invalid Configuration information - please run SETUP program» du fabricant WYSE dans ses machines Amdek System/88.
F1B20h | Chaîne de caractère signature du BIOS ayant la forme «American Megatrends Inc.» du fabricant American Megatrends.
F2004h | Chaîne de caractère signature du BIOS ayant la forme «WYSE COPR. IBM Compatible» du fabricant WYSE dans ses machines Amdek System/88.
F39C1h | Chaîne de caractère signature du BIOS ayant la forme «Non-System disk or disk error» du fabricant WYSE dans ses machines Amdek System/88.
F3F37h | Chaîne de caractère signature du BIOS ayant la forme «Rom Bios Ver 2.14» du fabricant WYSE dans ses machines Amdek System/88.
FB000h | 6 octets | Chaîne de caractère signature du BIOS ayant la forme «Zenith» du fabricant Zenith.
FC02Bh | 5 octets | Chaîne de caractère signature du BIOS ayant la forme «Tandy» du fabricant Tandy.
FC050h | 8 octets | Chaîne de caractère signature du BIOS ayant la forme «OLIVETTI» du fabricant Olivetti.
FC2FFh | 6 octets | Chaîne de caractère signature du BIOS ayant la forme «Zenith» du fabricant Zenith.
FD900h | Double mot | Adresse de l'interruption 16h du Conterm Max.
FE004h | 6 octets | Chaîne de caractère signature du BIOS ayant la forme «Tandon» du fabricant Tandon.
FE00Eh | 3 octets | Chaîne de caractère signature du BIOS ayant la forme «IBM» du fabricant IBM.
FE719h | Double mot | Adresse de l'interruption 18h de la ROM Bios Phoenix version 2.14 (1984, 1985)
FE739h | Double mot | Adresse de l'interruption 14h de la ROM Bios Phoenix version 2.14 (1984, 1985)
FE82Eh | Double mot | Adresse de l'interruption 16h de la ROM Bios Phoenix version 2.14 (1984, 1985)
FEFD2h | Double mot | Adresse de l'interruption 17h de la ROM Bios Phoenix version 2.14 (1984, 1985)
FF841h | Double mot | Adresse de l'interruption 12h de la ROM Bios Phoenix version 2.14 (1984, 1985)
FF859h | Double mot | Adresse de l'interruption 11h de la ROM Bios Phoenix version 2.14 (1984, 1985)
FFA0Ah | Double mot | Adresse de l'interruption 02h de la ROM Bios Phoenix version 2.14 (1984, 1985)
FFF23h | Double mot | Adresse de l'interruption 06h, 07h et 0Ah de la ROM Bios Phoenix version 2.14 (1984, 1985)
FFF54h | Double mot | Adresse de l'interruption 05h de la ROM Bios Phoenix version 2.14 (1984, 1985)
FFFC2h | 4 octets | Chaîne de caractère signature du BIOS ayant la forme «WANG» du fabricant Wang.
FFFF0h | Variable | Point d'entrée de la combinaison de touche Ctrl+Alt+Delete lors du démarrage à froid de tous bon compatible.
FFFFEh | 1 octets | Signature de modèle de PC
Code | Description
055h (85) | Conterm Max du fabricant du même nom.
0FCh (252) | PC AT ou postérieur
0FDh (253) | PC Junior d'IBM.
0FEh (254) | PC XT
0FFh (255) | IBM PC ou compatible

Dernière mise à jour : Samedi, le 2 août 2014


Langage de programmation - Assembleur 80x86 - Référence global de la mémoire des compatibles IBM PC - Cellule 00410h à 00411h

-<²+
Équipement

Cellule 00410h à 00411h
PC, XT, PC Junior, AT, PS/2

Description

Ce mot contient divers informations sur l'équipement de la machine actuellement installé.

Lecture/Écriture

Bits | Description
0 | Contient la valeur 1 advenant qu'il y ait au moins une unité de disquette installé sur la machine.
1 | Contient la valeur 1 si un coprocesseur mathématique est installé sur la machine.
2 et 3 | Lors des premiers PC, on utilisait ces bits pour indiquer la mémoire RAM disponible par le système sur la carte mère des PC et XT uniquement.
4 et 5 | Indique la carte vidéo installé exploiter au démarrage de la machine :
 | Valeur | Description
 | 00b | Carte vidéo adaptateur spécial comme les cartes EGA, VGA ou PGA...
 | 01b | Mode texte 40x25 en 16 couleurs
 | 10b | Mode texte 80x25 en 16 couleurs
 | 11b | Mode texte 80x25 en monochrome
6 et 7 | Indique le nombre d'unité de disquette installé:
 | Valeur |  | Description
 | 00b |  | 1 lecteur
 | 01b |  | 2 lecteurs
 | 10b |  | 3 lecteurs
 | 11b |  | 4 lecteurs
8 à 10 | Indique le nombre de ports série de format RS-232 installé.
12 | Aura la valeur 1 si une manette de jeux est installé
13 | Vaudra 1 si les modèle d'imprimante pour port série est installé.
14 et 15 | Indique le nombre d'imprimante connecté

Exemples

Voici un exemple, en Turbo Pascal, permettant de demander l'équipement installé à l'aide de cette cellule :

  1. Program Mem00410;
  2.
  3. Var
  4.  Equip:Word Absolute $0040:$0010;
  5.
  6. BEGIN
  7.  If (Equip AND $0002) shr 1 = 1 Then Begin
  8.   WriteLn('Coprocesseur mathématique présent');
  9.  End
  10.   Else
  11.  Begin
  12.   WriteLn('Coprocesseur mathématique non installé');
  13.  End;
  14.  WriteLn('Nombre de port RS-232 : ',(Equip AND $0E00) shr 9);
  15.  WriteLn('Nombre de port parallèle : ',(Equip AND $C000) shr 14);
  16.  WriteLn('Nombre de manette de jeu : ',(Equip AND $1000) shr 12);
  17. END.

Voici un exemple, en Turbo C, permettant de demander l'équipement installé à l'aide de cette cellule :

  1. #include <stdio.h>
  2. #include <stdlib.h>
  3. #include <dos.h>
  4.
  5. int main() {
  6.  int Equip;
  7.  Equip = peek(0x0040,0x0010);
  8.  if((Equip & 0x0002) >> 1) {
  9.   printf("Coprocesseur mathématique présent\n");
  10.  } else {
  11.   printf("Coprocesseur mathématique non installé\n");
  12.  }
  13.  printf("Nombre de port RS-232 : %i\n",(Equip & 0x0E00)>> 9);
  14.  printf("Nombre de port parallèle : %i\n",(Equip & 0xC000) >> 14);
  15.  printf("Nombre de manette de jeu : %i\n",(Equip & 0x1000)>> 12);
  16.  return 0;
  17. }

Voici un exemple, en Turbo Basic, permettant de demander l'équipement installé à l'aide de cette cellule :

  1. DEF SEG=0
  2. Equip = PEEK(&H0410)+(PEEK(&H0411)*256)
  3. IF (Equip AND &H0002) = &H0002 Then
  4.  PRINT "Coprocesseur mathématique présent"
  5. ELSE
  6.  PRINT "Coprocesseur mathématique non installé"
  7. END IF
  8. PRINT "Nombre de port RS-232 : "; (Equip AND &H0E00) / 512
  9. PRINT "Nombre de port parallèle : "; (32768-(Equip AND &HC000)) / 16384
  10. PRINT "Nombre de manette de jeu : "; (Equip AND &H1000) / 4096

Voir également

Langage de programmation - Assembleur 80x86 - Interruption 11h: Demande la configuration

Dernière mise à jour : Samedi, le 2 août 2014


Jeu d'instructions x86 — Wikipédia

Jeu d'instructions x86

Un article de Wikipédia, l'encyclopédie libre.
(Redirigé depuis Jeu d'instruction x86)
Le jeu d'instructions du x86 a subi de nombreux changements au cours du temps. La plupart d'entre eux ne sont que des ajouts au jeu d'instructions initial afin d'apporter de nouvelles fonctionnalités.

Sommaire

[masquer]
  • 1 Jeu d'instructions sur les entiers
    • 1.1 Instructions originales des 8086/8088
    • 1.2 Ajouts aux processeurs spécifiques
      • 1.2.1 Ajouts aux processeurs 80186/80188
      • 1.2.2 Ajouts au processeur 80286
      • 1.2.3 Ajouts au processeur 80386
      • 1.2.4 Ajouts au processeur 80486
      • 1.2.5 Ajouts au processeur Pentium
      • 1.2.6 Ajouts au processeur Pentium Pro
      • 1.2.7 Ajouts au processeur AMD K7
      • 1.2.8 Ajouts au processeur Pentium III
      • 1.2.9 Ajouts au processeur Pentium 4
      • 1.2.10 Ajouts au processeur Pentium 4 supportant les fonctionnalités SSE3
      • 1.2.11 Ajouts au processeur Pentium 4 6x2
      • 1.2.12 Ajouts au processeurs x86-64
  • 2 x87 : Instructions d'unité de calcul en virgule flottante
    • 2.1 Instructions du processeur x87 original
    • 2.2 Ajouts aux processeurs spécifiques
      • 2.2.1 Ajouts au processeur 80287
      • 2.2.2 Ajouts au processeur 80387
      • 2.2.3 Ajouts au processeur Pentium Pro
      • 2.2.4 Ajouts au processeur Pentium 4 supportant le SSE3
  • 3 Instructions SIMD
    • 3.1 Instructions MMX
    • 3.2 Instructions MMX+ étendues
    • 3.3 Instructions 3DNow!
    • 3.4 Instructions 3DNow!+
    • 3.5 Instructions SSE
      • 3.5.1 Instructions SSE SIMD en virgule flottante
      • 3.5.2 Instructions SSE SIMD sur les entiers
    • 3.6 Instructions SSE2
      • 3.6.1 Instructions SSE2 SIMD en virgule flottante
      • 3.6.2 Instructions SSE2 SIMD sur les entiers
    • 3.7 Instructions SSE3
      • 3.7.1 Instructions SSE3 SIMD en virgule flottante
      • 3.7.2 Instructions SSE3 SIMD portant sur les entiers
    • 3.8 Instructions SSSE3
    • 3.9 Instructions SSE4
      • 3.9.1 Ajouts aux architectures Intel Penryn
      • 3.9.2 Ajouts aux architectures Intel Nehalem
      • 3.9.3 Ajouts aux architectures Intel Westmere
      • 3.9.4 Ajouts aux architectures Intel Sandy Bridge
  • 4 Voir aussi
    • 4.1 Articles connexes
    • 4.2 Liens externes

Jeu d'instructions sur les entiers

Ceci est le jeu d'instructions complet pour les processeurs 8086-8088 et la plupart, si ce n'est toutes ces instructions sont accessibles en mode 32 bits. Elles opèrent alors sur les registres et valeurs 32 bits (eax, ebx, etc.) en lieu et place de leur contrepartie en 16 bits (ax, bx, etc.).

Instructions originales des 8086/8088

Nom | Sens | Traduction | Notes
AAA | ASCII Adjust AL after Addition | Ajuste le registre AL après addition (mode ASCII) | Utilisé avec le codage BCD non compacté
AAD | ASCII Adjust AX after Division | Ajuste le registre AX après division (mode ASCII) | Utilisé avec le codage BCD non compacté, bogué dans le jeu d'instruction original, mais « réparé » dans le NEC V20, causant de nombreuses incompatibilités
AAM | ASCII Adjust AX after Multiplication | Ajuste le registre AX après multiplication (mode ASCII) | Utilisé avec le codage BCD non compacté
AAS | ASCII Adjust AL after Subtraction | Ajuste le registre AL après soustraction (mode ASCII) | Utilisé avec le codage BCD non compacté
ADC | Add with Carry | Ajoute deux entiers, plus le drapeau de retenue | Le résultat remplace le premier opérande
ADD | Add | Ajoute deux entiers | Le résultat remplace le premier opérande
AND | Logical AND | Effectue un ET logique des opérandes | Le résultat remplace le premier opérande
CALL | Call Procedure | Appelle une procédure |
CBW | Convert Byte to Word | Convertit un octet en mot | Le registre AL est étendu à AX
CLC | Clear Carry Flag | Met le drapeau de retenue à zéro |
CLD | Clear Direction Flag | Met le drapeau de direction à zéro |
CLI | Clear Interrupt Flag | Met le drapeau d'interruption à zéro |
CMC | Complement Carry Flag | Inverse le drapeau de retenue |
CMP | Compare | Compare deux entiers (de façon arithmétique) | Positionne les drapeaux en fonction de la différence entre les opérandes
CMPSzz | Compare Strings | Compare un octet/mot de deux chaînes | Mnémoniques : CMPS, CMPSB, CMPSW
CWD | Convert Word to Doubleword | Convertit un mot en double mot | Le registre AX est étendu à DX:AX
DAA | Decimal Adjust AL after Addition | Ajuste le registre AL après addition (mode décimal) | Utilisé avec le codage BCD compacté
DAS | Decimal Adjust AL after Subtraction | Ajuste le registre AL après soustraction (mode décimal) | Utilisé avec le codage BCD compacté
DEC | Decrement by 1 | Décrémente un entier | Ôte un de l'opérande
DIV | Unsigned Divide | Divise par un entier non signé | Le dividende est le registre AX/DX:AX, le quotient est écrit dans AL/AX et le reste dans AH/DX
ESC | Escape |  | Utilisé avec l'unité de calcul en virgule flottante
HLT | Halt | Entre en état d'arrêt jusqu'à réception d'une interruption | Permet de réduire la consommation de puissance du processeur. Alias : HALT
IDIV | Signed Divide | Divise par un entier signé | Le dividende est le registre AX/DX:AX, le quotient est écrit dans AL/AX et le reste dans AH/DX
IMUL | Signed Multiply | Multiplie par un entier signé | Le facteur est le registre AL/AX et le produit est écrit dans AX/DX:AX
IN | Input from Port | Lit depuis un port | La destination est le registre AL/AX
INC | Increment by 1 | Incrémente un entier | Ajoute un à l'opérande
INT | Call to Interrupt Procedure | Appelle l'interruption identifiée par l'opérande |
INTO | Call to Interrupt Procedure if Overflow | Appelle l'interruption de débordement si le drapeau de débordement est à un |
IRET | Interrupt Return | Revient d'une interruption |
Jcc | Jump if Condition Is Met | Saute si une condition est vérifiée | Mnémoniques : JA, JAE, JB, JBE, JC, JCXZ, JE, JG, JGE, JL, JLE, JNA, JNAE, JNB, JNBE, JNC, JNE, JNG, JNGE, JNL, JNLE, JNO, JNP, JNS, JNZ, JO, JP, JPE, JPO, JS, JZ
JMP | Jump | Saute (inconditionnel) |
LAHF | Load Flags into AH | Copie le registre des drapeaux dans le registre AH |
LDS | Load DS with Far Pointer | Charge un pointeur de type far (lointain) dans le registre DS (segment) et l'opérande (décalage) |
LEA | Load Effective Address | Charge l'adresse du second opérande dans le premier |
LES | Load ES with Far Pointer | Charge un pointeur de type far (lointain) dans le registre ES (segment) et l'opérande (décalage) |
LOCK | Assert LOCK# Signal Prefix | Préfixe verrouillant les bus pour les prochaines instructions | Utilisé pour les plates-formes multiprocesseurs.
LODSzz | Load String | Copie un octet/mot d'une chaîne | La destination est le registre AL/AX. Mnémoniques : LODS, LODSB, LODSW
LOOPcc | Loop According to Counter | Décrémente le compteur et saute si une condition est vérifiée | Le compteur est le registre CX. Mnémoniques : LOOP, LOOPE, LOOPNE, LOOPNZ, LOOPZ
MOV | Move | Copie le second opérande dans le premier |
MOVSzz | Move from String to String | Copie un octet/mot d'une chaîne vers une autre | Mnémoniques : MOVS, MOVSB, MOVSW
MUL | Unsigned Multiply | Multiplie par un entier non signé | Le facteur est le registre AL/AX et le produit est écrit dans AX/DX:AX
NEG | Two's Complement Negation | Calcule l'opposé de l'opérande (négation par complément à deux) | Le résultat remplace l'opérande
NOP | No Operation | Ne fait rien |
NOT | One's Complement Negation | Effectue un NON logique (négation par complément à un) | Le résultat remplace l'opérande
OR | Logical Inclusive OR | Effectue un OU logique inclusif des opérandes | Le résultat remplace le premier opérande
OUT | Output to Port | Écrit vers un port | La source est le registre AX/AL
POP | Pop a Value from the Stack | Dépile vers le registre opérande |
POPF | Pop Flags Register from the Stack | Dépile vers le registre des drapeaux |
PUSH | Push a Value onto the Stack | Empile le registre opérande |
PUSHF | Push Flags Register onto the Stack | Empile le registre des drapeaux |
RCL | Rotate through Carry Left | Effectue une rotation à gauche via par le drapeau de retenue |
RCR | Rotate through Carry Right | Effectue une rotation à droite via par le drapeau de retenue |
REPcc | Repeat String Operation Prefix | Préfixe de répétition d'une opération sur une chaîne | Mnémoniques : REP, REPE, REPNE, REPNZ, REPZ
RET | Return from Procedure | Revient d'une procédure appelée avec décalage seul | L'adresse de retour (décalage) est sur la pile. Un opérande optionnel peut indiquer le nombre d'octets supplémentaire à dépiler.
RETF | Return from Far Procedure | Revient d'une procédure appelée avec segment et décalage | L'adresse de retour (segment et décalage) est sur la pile. Un opérande optionnel peut indiquer le nombre d'octets supplémentaire à dépiler.
ROL | Rotate Left | Effectue une rotation vers la gauche |
ROR | Rotate Right | Effectue une rotation vers la droite |
SAHF | Store AH into Flags | Copie le registre AH dans le registre des drapeaux |
SAL | Shift Arithmectically Left | Décalage arithmétique vers la gauche | Même instruction que SHL
SALC | Set AL from Carry Flag | Copie la valeur 0xFF dans le registre AL si CF vaut 1, ou 0x00 sinon | Initialement non documenté. Alias : SETALC
SAR | Shift Arithmectically Right | Décalage arithmétique vers la droite | À ne pas confondre avec SHR
SBB | Integer Subtraction with Borrow | Soustrait deux entiers, ajoute le drapeau de retenue | Le résultat remplace le premier opérande
SCASzz | Scan String | Compare un octet/mot d'une chaîne | La référence est le registre AL/AX. Mnémoniques : SCAS, SCASB, SCASW
SHL | Shift Left | Décalage logique à gauche | Même instruction que SAL
SHR | Shift Right | Décalage logique à droite | À ne pas confondre avec SAR
STC | Set Carry Flag | Met le drapeau de retenue à un |
STD | Set Direction Flag | Met le drapeau de direction à un |
STI | Set Interrupt Flag | Met le drapeau d'interruption à un |
STOSzz | Store in String | Copie dans un octet/mot d'une chaîne | La source est le registre AL/AX. Mnémoniques : STOS, STOSB, STOSW
SUB | Subtract | Soustrait deux entiers | Le résultat remplace le premier opérande
TEST | Logical Compare | Compare deux opérandes (de façon logique) | Positionne les drapeaux en fonction du résultat du ET logique entre les opérandes
WAIT | Wait | Attend tant que la broche BUSY du processeur est inactive | Utilisé avec l'unité de calcul en virgule flottante
XCHG | Exchange | Permute le contenu des deux opérandes |
XLAT | Table Look-up Translation | Translation de donnée entre des tables | Alias : XLATB
XOR | Logical Exclusive OR | Effectue un OU logique exclusif des opérandes | Le résultat remplace le premier opérande

Ajouts aux processeurs spécifiques

Ajouts aux processeurs 80186/80188

BOUND, ENTER, INSB, INSW, LEAVE, OUTSB, OUTSW, POPA, PUSHA, PUSHW

Ajouts au processeur 80286

ARPL, CLTS, LAR, LGDT, LIDT, LLDT, LMSW, LOADALL, LSL, LTR, SGDT, SIDT, SLDT, SMSW, STR, VERR, VERW

Ajouts au processeur 80386

BSF, BSR, BT, BTC, BTR, BTS, CDQ, CMPSD, CWDE, INSD, IRETD, IRETDF, IRETF, JECXZ, LFS, LGS, LSS, LODSD, LOOPD, LOOPED, LOOPNED, LOOPNZD, LOOPZD, MOVSD, MOVSX, MOVZX, OUTSD, POPAD, POPFD, PUSHAD, PUSHD, PUSHFD, SCASD, SETA, SETAE, SETB, SETBE, SETC, SETE, SETG, SETGE, SETL, SETLE, SETNA, SETNAE, SETNB, SETNBE, SETNC, SETNE, SETNG, SETNGE, SETNL, SETNLE, SETNO, SETNP, SETNS, SETNZ, SETO, SETP, SETPE, SETPO, SETS, SETZ, SHLD, SHRD, STOSD

Ajouts au processeur 80486

BSWAP, CMPXCHG, CPUID, INVD, INVLPG, RSM, WBINVD, XADD

Ajouts au processeur Pentium

CMPXCHG8B, RDMSR, RDPMC*, RDTSC, WRMSR

  • RDPMC a été introduit avec le processeur Pentium Pro et le processeur Pentium MMX

Ajouts au processeur Pentium Pro

CMOVA, CMOVAE, CMOVB, CMOVB, CMOVE, CMOVG, CMOVGE, CMOVL, CMOVLE, CMOVNA, CMOVNAE, CMOVNB, CMOVNBE, CMOVNC, CMOVNE, CMOVNG, CMOVNGE, CMOVNL, CMOVNLE, CMOVNO, CMOVNP, CMOVNS, CMOVNZ, CMOVO, CMOVP, CMOVPE, CMOVPO, CMOVS, CMOVZ, SYSENTER, SYSEXIT, UD2

Ajouts au processeur AMD K7

  • SYSCALL - Fonctionnalité spécifique au processeur AMD équivalente à l'instruction SYSENTER.
  • SYSRET - Fonctionnalité spécifique au processeur AMD équivalente à l'instruction SYSEXIT.
Cette liste est incomplète ou mal ordonnée. Votre aide est la bienvenue !

Ajouts au processeur Pentium III

Fonctionnalités SSE

MASKMOVQ, MOVNTPS, MOVNTQ, PREFETCH0, PREFETCH1, PREFETCH2, PREFETCHNTA, SFENCE (Mise en cache et ordonnancement mémoire (Memory Ordering))

Ajouts au processeur Pentium 4

Fonctionnalités SSE2

CLFLUSH, LFENCE, MASKMOVDQU, MFENCE, MOVNTDQ, MOVNTI, MOVNTPD, PAUSE (for Cacheability)

Ajouts au processeur Pentium 4 supportant les fonctionnalités SSE3

Processeur supportant l'Hyper-Threading

Fonctionnalités SSE3

MONITOR, MWAIT (Pour la synchronisation des threads)

Ajouts au processeur Pentium 4 6x2

VMPTRLD, VMPTRST, VMCLEAR, VMREAD, VMWRITE, VMCALL, VMLAUNCH, VMRESUME, VMXOFF, VMXON (instructions VMX)

Ajouts au processeurs x86-64[

CMPXCHG16B

x87 : Instructions d'unité de calcul en virgule flottante

Instructions du processeur x87 original

F2XM1, FABS, FADD, FADDP, FBLD, FBSTP, FCHS, FCLEX, FCOM, FCOMP, FCOMPP, FDECSTP, FDISI, FDIV, FDIVP, FDIVR, FDIVRP, FENI, FFREE, FIADD, FICOM, FICOMP, FIDIV, FIDIVR, FILD, FIMUL, FINCSTP, FINIT, FIST, FISTP, FISUB, FISUBR, FLD, FLD1, FLDCW, FLDENV, FLDENVW, FLDL2E, FLDL2T, FLDLG2, FLDLN2, FLDPI, FLDZ, FMUL, FMULP, FNCLEX, FNDISI, FNENI, FNINIT, FNOP, FNSAVE, FNSAVEW, FNSTCW, FNSTENV, FNSTENVW, FNSTSW, FPATAN, FPREM, FPTAN, FRNDINT, FRSTOR, FRSTORW, FSAVE, FSAVEW, FSCALE, FSQRT, FST, FSTCW, FSTENV, FSTENVW, FSTP, FSTSW, FSUB, FSUBP, FSUBR, FSUBRP, FTST, FWAIT, FXAM, FXCH, FXTRACT, FYL2X, FYL2XP1

Ajouts aux processeurs spécifiques

Ajouts au processeur 80287

FSETPM

Ajouts au processeur 80387

FCOS, FLDENVD, FNSAVED, FNSTENVD, FPREM1, FRSTORD, FSAVED, FSIN, FSINCOS, FSTENVD, FUCOM, FUCOMP, FUCOMPP

Ajouts au processeur Pentium Pro

FCMOVB, FCMOVBE, FCMOVE, FCMOVNB, FCMOVNBE, FCMOVNE, FCMOVNU, FCMOVU, FCOMI, FCOMIP, FUCOMI, FUCOMIP, FXRSTOR, FXSAVE

Ajouts au processeur Pentium 4 supportant le SSE3

Fonctionnalité SSE3

FISTTP (conversion x87 vers entier)

Instructions SIMD

Instructions MMX

Ajouts au processeur Pentium MMX

EMMS, MOVD, MOVQ, PABSB, PABSW, PABSD, PACKSSDW, PACKSSWB, PACKUSWB, PADDB, PADDD, PADDSB, PADDSW, PADDUSB, PADDUSW, PADDW, PAND, PANDN, PCMPEQB, PCMPEQD, PCMPEQW, PCMPGTB, PCMPGTD, PCMPGTW, PMADDWD, PMULHW, PMULLW, POR, PSLLD, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLQ, PSRLW, PSUBB, PSUBD, PSUBQ, PSUBSB, PSUBSW, PSUBUSB, PSUBUSW, PSUBW, PUNPCKHBW, PUNPCKHDQ, PUNPCKHWD, PUNPCKLBW, PUNPCKLDQ, PUNPCKLWD, PXOR

Instructions MMX+ étendues

Ajouts au processeur 6x86MX de Cyrix ; Supportés sur les autres processeurs, i.e. Extended MMX sur Athlon 64

Cette section est vide, insuffisamment détaillée ou incomplète. Votre aide est la bienvenue !

Instructions 3DNow!

Ajouts au processeur K6-2

FEMMS, PAVGUSB, PF2ID, PFACC, PFADD, PFCMPEQ, PFCMPGE, PFCMPGT, PFMAX, PFMIN, PFMUL, PFRCP, PFRCPIT1, PFRCPIT2, PFRSQIT1, PFRSQRT, PFSUB, PFSUBR, PI2FD, PMULHRW, PREFETCH, PREFETCHW

Instructions 3DNow!

Ajout au processeur Athlon

PF2IW, PFNACC, PFPNACC, PI2FW, PSWAPD

Instructions SSE

Ajouts au processeur Pentium III

Voir aussi les instructions sur les entiers ajoutées au processeur Pentium III

Instructions SSE SIMD en virgule flottante

ADDPS, ADDSS, ANDNPS, ANDPS, CMPPS, CMPSS, COMISS, CVTPI2PS, CVTPS2PI, CVTSI2SS, CVTSS2SI, CVTTPS2PI, CVTTSS2SI, DIVPS, DIVSS, LDMXCSR, MAXPS, MAXSS, MINPS, MINSS, MOVAPS, MOVHLPS, MOVHPS, MOVLHPS, MOVLPS, MOVMSKPS, MOVNTPS, MOVSS, MOVUPS, MULPS, MULSS, ORPS, RCPPS, RCPSS, RSQRTPS, RSQRTSS, SHUFPS, SQRTPS, SQRTSS, STMXCSR, SUBPS, SUBSS, UCOMISS, UNPCKHPS, UNPCKLPS, XORPS

Instructions SSE SIMD sur les entiers

PAVGB, PAVGW, PEXTRW, PINSRW, PMAXSW, PMAXUB, PMINSW, PMINUB, PMOVMSKB, PSADBW, PSHUFW

Instructions SSE2

Ajouts au processeur Pentium 4

Voir aussi les instructions sur les entiers ajoutées au processeur Pentium 4

Instructions SSE2 SIMD en virgule flottante

ADDPD, ADDSD, ANDNPD, ANDPD, CMPPD, CMPSD*, COMISD, CVTDQ2PD, CVTDQ2PS, CVTPD2DQ, CVTPD2PI, CVTPD2PS, CVTPI2PD, CVTPS2DQ, CVTPS2PD, CVTSD2SI, CVTSD2SS, CVTSI2SD, CVTSS2SD, CVTTPD2DQ, CVTTPD2PI, CVTPS2DQ, CVTTSD2SI, DIVPD, DIVSD, MAXPD, MAXSD, MINPD, MINSD, MOVAPD, MOVHPD, MOVLPD, MOVMSKPD, MOVSD*, MOVUPD, MULPD, MULSD, ORPD, SHUFPD, SQRTPD, SQRTSD, SUBPD, SUBSD, UCOMISD, UNPCKHPD, UNPCKLPD, XORPD

  • Les instructions CMPSD et MOVSD ont le même nom que les instructions portant sur les chaînes CMPSD (CMPS) et MOVSD (MOVS). Toutefois il convient de faire la différence entre les instructions portant sur les scalaires en virgules flottantes à double-précision alors que les dernières se réfèrent aux instructions portant sur des double-mots de chaînes de caractères (instructions portant sur des entiers).

Instructions SSE2 SIMD sur les entiers

MOVDQ2Q, MOVDQA, MOVDQU, MOVQ2DQ, PADDQ, PMULUDQ, PSHUFHW, PSHUFLW, PSHUFD, PSLLDQ, PSRLDQ, PUNPCKHQDQ, PUNPCKLQDQ

Instructions SSE3

Ajouts au processeur Pentium 4 supportant le SSE3

Voir aussi les instructions portant sur les entiers et les virgules flottantes ajoutées au processeurs Pentium 4 avec support SSE3

Instructions SSE3 SIMD en virgule flottante

  • ADDSUBPD, ADDSUBPS (Arithmétique sur les nombres complexes)
  • HADDPD, HADDPS, HSUBPD, HSUBPS (Pour les graphismes)

Instructions SSE3 SIMD portant sur les entiers

  • MOVDDUP, MOVSHDUP, MOVSLDUP (Arithmétique sur les nombres complexes)
  • LDDQU (Pour l'encodage vidéo)

Instructions SSSE3

Ajouts au processeur Core 2

  • PSIGNW, PSIGND, PSIGNB
  • PSHUFB
  • PMULHRSW, PMADDUBSW
  • PHSUBW, PHSUBSW, PHSUBD
  • PHADDW, PHADDSW, PHADDD
  • PALIGNR
  • PABSW, PABSD, PABSB

Instructions SSE4

Ajouts aux architectures Intel Penryn et Nehalem

  • PMULLD, PMULDQ
  • DPPS, DPPD
  • BLENDPS, BLENDPD, BLENDVPS, BLENDVPD, PBLENDVB, PBLENDDW
  • PMINSB, PMAXSB, PMINUW, PMAXUW, PMINUD, PMAXUD, PMINSD, PMAXSD
  • ROUNDPS, ROUNDSS, ROUNDPD, ROUNDSD
  • INSERTPS, PINSRB, PINSRD, PINSRQ, EXTRACTPS, PEXTRB, PEXTRD, PEXTRW, PEXTRQ
  • PMOVSXBW, PMOVZXBW, PMOVSXBD, PMOVZXBD, PMOVSXBQ, PMOVZXBQ, PMOVSXWD, PMOVZXWD, PMOVSXWQ, PMOVZXWQ, *PMOVSXDQ, PMOVZXDQ
  • PTEST
  • PCMPEQQ, PCMPGTQ
  • PACKUSDW
  • PCMPESTRI, PCMPESTRM, PCMPISTRI, PCMPISTRM
  • CRC32
  • POPCNT

Ajouts aux architectures Intel

  • 47 instructions SSE4

Ajouts aux architectures Intel

  • 3 instructions SSE4

Ajouts aux architectures Intel

  • des instructions pour AES

Ajouts aux architectures Intel

  • instruction Advanced Vector Extensions

Voir aussi

Articles connexes

  • Jeu d'instructions
  • x86

Liens externes

  • (en) Documentation gratuite sur l'architecture IA-32 d'Intel, documentation officielle d'Intel, contient toutes les instructions et diverses documentations.
  • (en) Référence NASM sur le jeu d'instruction x86


 Elément du langage

  • Introduction
    Les remarques
    Les opérateurs
    Type de données élémentaire
    Référence des registres
    Référence des instructions par catégories
    Référence, lexique et dictionnaire des instructions 80x86
    • Vue par Opcode (Inline ou code machine hexadécimal)
      Vue par cycle d'horloge
      Vue par drapeaux du EFLAGS
      Vue par microprocesseur (CPU)
    Les symboles prédéfinies
    Les directives conditionnelles

 Programmation

  • Le premier programme, le programme «Bonjour!»
    Détection
    • Carte vidéo
      Carte de son
      BIOS SCSI
      CMOS de XT
      DESQview
    Application
    • Stationnement de voiture (AVOSRISQUE)
    Mathématique
    • Triangle Pascal
      Valeur absolue (ABS)
    Temps
    • Année bissextile

 Annexe

  • Composantes
    • EMS/EMM
      MPU : Coprocesseur mathématique
      XMS
    Références des interruptions
    • Interruption 00h à 07h : Processeur
      Interruption 08h à 0Fh : Périphériques (IRQ0 à IRQ7)
      Interruption 10h : Gestionnaire de l'affichage vidéo
      Interruption 11h : Demande la configuration
      Interruption 12h : Demande la taille de la mémoire conventionnel
      Interruption 13h : Interface de gestion d'accès aux disques
      Interruption 14h : Interface de gestion AUX/FOSSIL
      Interruption 15h : Extension d'Entrée/Sortie
      Interruption 16h : Interface de gestion du clavier
      Interruption 17h : Interface de gestion d'imprimante
      Interruption 18h : Appel du BASIC en ROM
      Interruption 19h : Redémarrage de l'ordinateur
      Interruption 1Ah : Interface de gestion du temps
      Interruption 1Bh : Pour le clavier quand la touche Break actionnée
      Interruption 1Ch : Routine d'horloge
      Interruption 1Dh : Pointeur vers les paramètres de la table vidéo
      Interruption 1Eh : Paramètre disquette
      Interruption 1Fh : Caractères graphiques vidéo
      Interruption 20h : Terminer un programme
      Interruption 21h : Service DOS
      Interruption 22h : Routine pour terminer un programme
      Interruption 23h : Touche Break actionnée
      Interruption 24h : Erreur critique
      Interruption 25h : Lecture absolue
      Interruption 26h : Écriture absolue
      Interruption 27h : Terminer en TSR
      Interruption 28h : DOS en attente
      Interruption 29h : Sortie rapide de la console
      Interruption 2Ah : Interface de service réseau
      Interruption 2Bh : Expansion futur du DOS
      Interruption 2Eh : EXEC du prompt de COMMAND
      Interruption 2Fh : Interruption Multiplexe
      Interruption 33h : Interface du pilote de souris
      Interruption 41h : Paramètres du premier disque dur
      Interruption 4Bh : Gestionnaire virtuel
      Interruption 59h : Interface de gestion du GSS Computer Graphics Interface
      Interruption 5Ch : Gestionnaire BIOS Réseau (NetBIOS)
      Interruption 67h : Gestionnaire EMS/EMM
      Interruption 7Ah : Gestionnaire Novell Netware (API)
      Interruption 80h : Appel au noyau Linux (API)
      Interruption 80h à F0h : Interpréteur BASIC
    Port d'Entrée/Sortie
    Références des adresses de cellule mémoire du «PC IBM»
    Téléchargement
    Système d'exploitation - Linux - Références de commandes et de programmes - as
    Bibliographie
Dernière mise à jour : Vendredi, le 15 août 2014


Système d'exploitation DOS

Voici le premier programme comme on l'appel dans le jargon, le programme «Bonjour!» permettant d'afficher le petit message «Bonjour!» à l'écran sous un système d'exploitation DOS ou compatible :

  1. .MODEL small
  2.    .STACK 100h
  3.    .DATA
  4. MessageBonjour DB 'Bonjour!',13,10,'$'
  5.    .CODE
  6.    .startup
  7.    MOV  AX,@data
  8.    MOV  DS,AX
  9.    MOV  AH,9
  10.    MOV  DX,OFFSET MessageBonjour
  11.    INT  21h
  12.    MOV  AX,4C00h
  13.    INT  21h
  14.    END

Il affichera donc le message suivant :

Bonjour!

Si par exemple vous utilisez le Turbo Assembleur version 5.0, vous n'aurez que les trois commandes suivantes a effectuer pour voir le résultat en supposant que le programme s'appel «bonjour.asm» :

TASM bonjour.asm
TLINK bonjour.obj
bonjour.exe

Système d'exploitation Linux

Si vous êtes sous un système d'exploitation Linux, avec une distribution Ubuntu par exemple, vous pouvez également des applications consoles en assembleurs facilement avec l'utilitaire de développement «nasm» comme le montre le programme d'exemple suivant :

  1. section .text
  2.     global _start
  3. _start:
  4.         MOV EDX,len
  5.         MOV ECX,msg
  6.         MOV EBX,1
  7.         MOV EAX,4
  8.         INT 80h
  9.         MOV EAX,1
  10.         INT 80h
  11. section .data
  12. msg DB 'Bonjour!',0Ah
  13. len EQU $ - msg

Il affichera donc le message suivant en mode console:

Bonjour!

Si vous avez l'utilitaire «nasm» d'installer sous votre distribution Linux et que le programme se nomme «bonjourasm.asm», vous pourrez le créer et l'exécuter avec les commandes suivantes :

nasm -f elf bonjourasm.asm
ld bonjourasm.o -o bonjourasm
./bonjourasm

Dernière mise à jour : Vendredi, le 4 mars 2016


Voici une petite application ayant pour but d'effectuer la gestion d'un stationnement de voiture.

Le code source Turbo Assembleur de l'application :

  1. ;\Source\Chantal\Samples\Stationn.mnt\AvosRisq.Asm
  3. ;+------------------------------------------------------------------------
  4. ;| |
  5. ;| AVOSRISQUES Inc. |
  6. ;| |
  7. ;| Malte Genesis/Samples de gestion de liste |
  8. ;| Édition Chantal/IV - Version 1.1 |
  9. ;| 1998/11/30 |
  10. ;| |
  11. ;| Tous droits réservés par les Chevaliers de Malte (C) |
  12. ;| |
  13. ;+-----------------------------------------------------------------------|
  14. ;
  15. ;
  16. ;Nom des programmeurs
  17. ;====================
  18. ;
  19. ; Sylvain Maltais
  20. ; ...? Bien il y en qu'un!
  21. ;
  22. ;
  23. ;Description
  24. ;===========
  25. ;
  26. ; Ce fichier contient le listing d'un fichier de gestion de parc de
  27. ; voiture par l'entremise d'une liste symétrique. A titre de démonstration
  28. ; il est limité à la gestion de 7 voitures dans le parc et de 3 dans la
  29. ; rue.
  30. ;
  31. ;
  32. ;Remarque
  33. ;========
  34. ;
  35. ; þ Je dédis ce listing au «MonsterBook», alias l'Oeuvre inhumaine afin
  36. ; que son honneur soit laver ainsi qu'aux vieux CPU 8088 et 8086 dont
  37. ; l'arrogance de certain permet de les juger dépasser pour les tâches
  38. ; classique.
  40. .8086
  41. .MODEL TPASCAL
  43. Include \Source\Chantal\Library\Compiler\Assemble.ur\Dialect. Inc
  44. Include \Source\Chantal\Library\System\Dos\Constant.Mac
  45. Include \Source\Chantal\Library\Memories\Real\RBufHead.Mac
  47. Public AvosRisque
  49. errHdl Equ 0FFh ; Mauvais handle, erreur d'ouverture de fichier
  51. ; ------------------- Constantes d'AVOSRISQUES Inc. -------------------
  52. MaximumVoitureParc Equ 7 ; Nombre maximal de voiture dans le parc
  53. MaximumVoitureRue Equ 3 ; Nombre maximal de voiture dans la rue
  55. ; ------------ Enregistrement utilisée pour AVOSRISQUES Inc. ------------
  56. InfoAuto STRUC
  57. Marque DB 26 DUP (?) ; Marque de la voiture
  58. Couleur DB 16 DUP (?) ; Couleur de la voiture
  59. Annee DW ? ; Année: 19xx
  60. Immat DB 16 DUP (?) ; Immat
  61. ENDS
  63. Extrn MemAlloc:Far
  64. Extrn Free:Far
  66. .DATA
  68. String DB 255 DUP (?) ; Variable de retour de fonction
  69. NomFichier DB 82 DUP (?) ; Nom du fichier par défaut
  70. InfoParc RBuf ? ; Contient les données de la liste AVOSRISQUES
  71. ; dans le parc
  72. InfoRue RBuf ? ; Contient les données de la liste AVOSRISQUES
  73. ; dans la rue
  74. TempAuto InfoAuto ? ; Enregistrement temporaire d'auto
  76. .CODE
  78. RawTxtY DW 0, 80, 160, 240, 320, 400, 480, 560, 640, 720, 800, 880 ; 0 à 11
  79. DW 960, 1040, 1120, 1200, 1280, 1360, 1440, 1520, 1600, 1680, 1760, 1840 ; 12 à 23
  80. DW 1920, 2000, 2080, 2160, 2240, 2320, 2400, 2480, 2560, 2640, 2720, 2800 ; 24 à 35
  81. DW 2880, 2960, 3040, 3120, 3200, 3280, 3360, 3440, 3520, 3600, 3680, 3760 ; 36 à 47
  82. DW 3840, 3920, 4000, 4080, 4160, 4240, 4320, 4400, 4480, 4560, 4640, 4720 ; 48 à 63
  84. ; ------------------ Définition utilisé pour le vidéo ------------------
  85. SegVideo DW 0B800h ; Segment vidéo
  86. MaxYTxts DB 24 ; Position maximale d'affichage vertical
  87. NmYTxts DB 25 ; Nombre de ligne affichable
  88. NmXTxts DB 80 ; Nombre de colonne affichable
  90. ; ------------------ Message utilisé dans ce programme -----------------
  91. Pres1 DB 18,"Travail Pratique 4"
  92. Pres2 DB 8,"fait par"
  93. Pres3 DB 15,"Sylvain Maltais"
  94. Pres4 DB 48,"Tous droits réservés par les Gladir.com"
  95. Pres5 DB 10,"1998/11/06"
  96. Pres6 DB 11,"Description"
  97. Pres7 DB 11,"-----------"
  98. Pres8 DB 56,"Ce programme permet de gérée un stationnement de voiture"
  99. Pres9 DB 40,"aussi bien dans le parc que dans la rue."
  100. Titre DB 38,"PARC DE STATIONNEMENT AVOSRISQUES inc."
  101. Item1 DB 21,"1. Arrivée d'une auto"
  102. Item2 DB 20,"2. Départ d'une auto"
  103. Item3 DB 26,"3. Consultation d'une auto"
  104. Item4 DB 25,"4. Informations générales"
  105. Item5 DB 20,"5. Fin de la journée"
  106. StrFull DB 57,"Chaîne pleine! Arrêtez dans mettre et presser sur «ENTER»"
  107. StrLettreAttendu DB 46,"Une lettre valide entre 'A' et 'Z' est attendu"
  108. StrChiffreAttendu DB 46,"Un chiffre valide entre '0' et '9' est attendu"
  109. PresseUneTouche DB 35,"Presse une touche pour continuer..."
  110. PrendDessin DB 40,"Répondez par la lettre «O» ou «N» S.V.P.!"
  111. TitreDepartAuto DB 20,"Départ d'une voiture"
  112. TitreArriveeAuto DB 18,"Arrivée d'une auto"
  113. TitreConsultationAuto DB 26,"Consultation d'une voiture"
  114. TitreInformation DB 11,"Information"
  115. SaisieDonnee DB 16,"Saisie de donnée"
  116. FinJourneeStr DB 14,"Fin de journée"
  117. QuesPrinc DB 13,"Votre choix ?"
  118. QuestionMat DB 36,"Entrez le matricule de la voiture ? "
  119. QuestionMarque DB 29,"Entrez la marque du véhicule ?"
  120. QuestionCouleur DB 30,"Entrez la couleur du véhicule ?"
  121. QuestionAnnee DB 27,"Entrez l'année du véhicule ?"
  122. EntrezNom DB 25,"Entrez le nom du fichier:"
  123. AutreFichier DB 46,"Désirez-vous charger un autre fichier (O/N) ? "
  124. QuesNewVoiture DB 54,"Désirez-vous faire entrer une nouvelle voiture (O/N) ?"
  125. Pres10 DB 45,"Voulez-vous poursuivre le traîtement (O/N) ? "
  126. QuesConsultNewVoiture DB 51,"Désirez-vous consulter une nouvelle voiture (O/N) ?"
  127. QuesDepartNewVoiture DB 54,"Désirez-vous faire partir une nouvelle voiture (O/N) ?"
  128. SauveMsg DB 47,"Sauvegarde des voitures du parc dans un fichier"
  129. ParcEtRuePlein DB 35,"Parc de stationnement et rue plein!"
  130. VoitureExistante DB 50,"La voiture est déja dans le parc de stationnement!"
  131. VoitureIntrouvable DB 20,"Voiture introuvable!"
  132. VoitureExistePas DB 58,"Aucune voiture ne se trouve dans le parc de stationnement!"
  133. ImpossibleCree DB 31,"Impossible de créer le fichier!"
  134. AnneeInvalid DB 44,"Année invalide! Dois être entre 1900 et 1999"
  135. ChoixInvalid DB 45,"Choix invalide! Entrez 1, 2, 3, 4 ou 5 S.V.P."
  136. StrMarque DB 7, "Marque:"
  137. StrCouleur DB 8, "Couleur:"
  138. StrAnnee DB 6, "Année:"
  139. InfoParcUsed DB 40,"Nombre d'autos stationnées dans le parc:"
  140. InfoParcFree DB 36,"Nombre de places libre dans le parc:"
  141. InfoRueUsed DB 37,"Nombre d'autos attendant dans la rue:"
  142. InfoRueFree DB 39,"Nombre de places de libres dans la rue:"
  143. InfoVoitureParc DB 45,"Voici la liste de(s) voiture(s) dans le parc:"
  144. EnteteParc1 DB 63,"Marque Couleur Annee Immatriculation"
  145. EnteteParc2 DB 64,"------------------------- --------------- ----- ----------------"
  146. TuteurAnnee DB "9999"
  147. AccepteTous DB 'þ'
  149. ; ----- Module incluant les routines de gestion de liste symétrique ----
  150. Include \Source\Chantal\Library\Memories\Real\RBuf.Mac
  152. ;+--------------------------------------------------------------------
  153. ;| Procédure ClrScr |
  154. ;+-------------------------------------------------------------------|
  155. ;
  156. ;
  157. ; Description
  158. ; ===========
  159. ;
  160. ; Cette procédure est utilisé pour effacer l'écran de mode texte.
  161. ;
  162. ;
  163. ; Entrée
  164. ; ======
  165. ;
  166. ; AH = Attribut utilisé pour effacer l'écran
  167. ;
  168. ;
  169. ; Sortie
  170. ; ======
  171. ;
  172. ; Registres détruit AX, CX, DI, ES et les drapeaux
  174. ClrScr Proc Near
  175. PUSH BX
  176. CLD
  177. MOV ES,SegVideo
  178. XOR DI,DI
  179. MOV BL,NmYTxts
  180. XOR BH,BH
  181. SHL BX,1
  182. MOV CX,Word Ptr RawTxtY[BX]
  183. MOV AL,' '
  184. REP STOSW
  185. POP BX
  186. EndProc
  188. ;+----------------------------------------------------------------------
  189. ;| Procédure BarTxtHor |
  190. ;+---------------------------------------------------------------------|
  191. ;
  192. ;
  193. ; Description
  194. ; ===========
  195. ;
  196. ; Cette procédure permet de tracer une barre de texte dans une écran en
  197. ; mode texte dans l'intervalle (X1,Y)-(X2,Y).
  198. ;
  199. ;
  200. ; Entrée
  201. ; ======
  202. ;
  203. ; AL = Caractère utilisé pour afficher la barre d'écran de texte
  204. ; AH = Attribut utilisé pour afficher la barre d'écran de texte
  205. ; BL = Coordonnée texte Y
  206. ; DL = Coordonnée texte X1
  207. ; DH = Coordonnée texte X2
  208. ;
  209. ;
  210. ; Sortie
  211. ; ======
  212. ;
  213. ; Registres détruit AX, BX, CX, DX, DI, ES et les drapeaux
  215. BarTxtHor Proc Near
  216. XOR BH,BH
  217. SHL BX,1
  218. MOV DI,Word Ptr RawTxtY[BX]
  219. MOV BL,DL
  220. ADD DI,BX
  221. SHL DI,1
  222. MOV ES,SegVideo
  223. XOR CH,CH
  224. MOV CL,DH
  225. SUB CL,DL
  226. INC CL
  227. CLD
  228. REP STOSW
  229. EndProc
  231. ;+--------------------------------------------------------------------
  232. ;| Procédure _PutTxtXY |
  233. ;+-------------------------------------------------------------------|
  234. ;
  235. ;
  236. ; Description
  237. ; ===========
  238. ;
  239. ; Cette procédure permet l'affichage d'un message texte à partir du
  240. ; segment de donnée à un endroit (X,Y) en texte définit respectivement
  241. ; par les registres BH et BL.
  242. ;
  243. ;
  244. ; Entrée
  245. ; ======
  246. ;
  247. ; BL = Coordonnée texte Y ( XX??h )
  248. ; BH = Coordonnée texte X ( ??YYh )
  249. ; DS = Segment utilisé pour l'affichage du message (String Pascal)
  250. ; SI = Offset utilisé pour l'affichage du message (String Pascal)
  251. ; AH = Attribut (couleur) utilisé pour l'affichage du message
  252. ;
  253. ;
  254. ; Sortie
  255. ; ======
  256. ;
  257. ; Registres détruit CX, DX, DI, ES et les drapeaux
  259. _PutTxtXY Proc Near
  260. PUSH AX
  261. PUSH BX
  262. PUSH SI
  263. MOV CL,BH
  264. XOR BH,BH
  265. SHL BX,1
  266. MOV DI,Word Ptr RawTxtY[BX] ; DI:=RawTxtY[Y shl 1]
  267. MOV BL,CL
  268. ADD DI,BX
  269. SHL DI,1
  270. MOV ES,SegVideo
  271. MOV CL,DS:[SI]
  272. XOR CH,CH
  273. JCXZ @2
  274. INC SI
  275. @1: LODSB
  276. STOSW
  277. LOOP @1
  278. @2:
  279. POP SI
  280. POP BX
  281. POP AX
  282. EndProc
  284. ;+--------------------------------------------------------------------
  285. ;| Procédure PutTxtXY |
  286. ;+-------------------------------------------------------------------|
  287. ;
  288. ;
  289. ; Description
  290. ; ===========
  291. ;
  292. ; Cette procédure permet l'affichage d'un message texte à partir du
  293. ; segment de code à un endroit (X,Y) en texte définit respectivement
  294. ; par les registres BH et BL.
  295. ;
  296. ;
  297. ; Entrée
  298. ; ======
  299. ;
  300. ; BL = Coordonnée texte Y ( XX??h )
  301. ; BH = Coordonnée texte X ( ??YYh )
  302. ; CS = Segment utilisé pour l'affichage du message (String Pascal)
  303. ; SI = Offset utilisé pour l'affichage du message (String Pascal)
  304. ; AH = Attribut (couleur) utilisé pour l'affichage du message
  305. ;
  306. ;
  307. ; Sortie
  308. ; ======
  309. ;
  310. ; Registres détruit CX, DX, DI, ES et les drapeaux
  312. PutTxtXY Proc Near
  313. PUSH DS
  314. _MOV_DS_CS
  315. CALL _PutTxtXY
  316. POP DS
  317. EndProc
  319. ;+------------------------------------------------------------------
  320. ;| Procédure PutTxtY |
  321. ;+-----------------------------------------------------------------|
  322. ;
  323. ;
  324. ; Description
  325. ; ===========
  326. ;
  327. ; Cette procédure permet l'affichage d'un message texte centrer à
  328. ; l'écran à partir du segment de code à une ligne en texte Y définit
  329. ; par le registres BL.
  330. ;
  331. ;
  332. ; Entrée
  333. ; ======
  334. ;
  335. ; BL = Coordonnée texte Y
  336. ; CS = Segment utilisé pour l'affichage du message (String Pascal)
  337. ; SI = Offset utilisé pour l'affichage du message (String Pascal)
  338. ; AH = Attribut (couleur) utilisé pour l'affichage du message
  339. ;
  340. ;
  341. ; Sortie
  342. ; ======
  343. ;
  344. ; Registres détruit BX, CX, DX, DI, ES et les drapeaux
  346. PutTxtY Proc Near
  347. MOV BH,NmXTxts
  348. SUB BH,CS:[SI]
  349. SHR BH,1
  350. CALL PutTxtXY
  351. EndProc
  353. ;+------------------------------------------------------------------
  354. ;| Procédure SetChr |
  355. ;+-----------------------------------------------------------------|
  356. ;
  357. ;
  358. ; Description
  359. ; ===========
  360. ;
  361. ; Cette procédure permet l'affichage d'un caractère à la position
  362. ; texte (X,Y) définit respectivement par les registres DL et DH.
  363. ;
  364. ;
  365. ; Entrée
  366. ; ======
  367. ;
  368. ; DL = Coordonnée texte X
  369. ; DH = Coordonnée texte Y
  370. ; AL = Code du caractère à afficher
  371. ;
  372. ;
  373. ; Sortie
  374. ; ======
  375. ;
  376. ; Registres drapeaux détruit
  378. SetChr Proc Near ; (DL,DH) AL=Char
  379. PUSH BX
  380. PUSH DI
  381. PUSH ES
  382. MOV BL,DH
  383. XOR BH,BH
  384. SHL BX,1
  385. MOV DI,Word Ptr RawTxtY[BX]
  386. MOV BL,DL
  387. ADD DI,BX
  388. SHL DI,1
  389. MOV ES,SegVideo
  390. STOSB
  391. POP ES
  392. POP DI
  393. POP BX
  394. EndProc
  396. ;+------------------------------------------------------------------
  397. ;| Procédure SetCurPos |
  398. ;+-----------------------------------------------------------------|
  399. ;
  400. ;
  401. ; Description
  402. ; ===========
  403. ;
  404. ; Cette procédure permet de fixer la coordonnée d'écran de texte du
  405. ; curseur clignotant à la position (X,Y) définit respectivement par
  406. ; les registres DL et DH.
  407. ;
  408. ;
  409. ; Entrée
  410. ; ======
  411. ;
  412. ; DL = Coordonnée texte X
  413. ; DH = Coordonnée texte Y
  414. ;
  415. ;
  416. ; Sortie
  417. ; ======
  418. ;
  419. ; Registre détruit AX, BX, CX, DX, SI, DI et les registres de drapeaux
  421. SetCurPos Proc Near ; (DL,DH)
  422. MOV AH,02h
  423. XOR BX,BX
  424. INT 010h
  425. RET
  426. endp
  428. ;+-----------------------------------------------------------------
  429. ;| Fonction OpenFile |
  430. ;+----------------------------------------------------------------|
  431. ;
  432. ;
  433. ; Description
  434. ; ===========
  435. ;
  436. ; Cette fonction permet d'ouvrir un fichier de type Handle avec le
  437. ; mode spécifiée par le registre BL (lecture, écriture ou combiné).
  438. ;
  439. ;
  440. ; Entrée
  441. ; ======
  442. ;
  443. ; DS = Segment du nom du fichier (Format String Pascal)
  444. ; DI = Offset du nom de fichier (Format String Pascal)
  445. ; BL = Mode d'accès (lecture=0, écriture=1 ou combiné=2).
  446. ;
  447. ;
  448. ; Retour
  449. ; ======
  450. ;
  451. ; AL = Handle alloué
  452. ; = FFh (errHdl) si une erreur s'est produit
  454. OpenFile Proc Near
  455. MOV AX,3D40h
  456. OR AL,BL
  457. MOV BL,DS:[DI]
  458. XOR BH,BH
  459. INC BX
  460. MOV DS:[DI+BX],BH
  461. MOV DX,DI
  462. INC DX
  463. INT 21h
  464. JNC @OF2
  465. MOV AL,errHdl
  466. @OF2:
  467. EndProc
  469. ;+-----------------------------------------------------------------
  470. ;| Fonction DelFile |
  471. ;+----------------------------------------------------------------|
  472. ;
  473. ;
  474. ; Description
  475. ; ===========
  476. ;
  477. ; Cette fonction permet d'effacer un fichier par l'entremise de la
  478. ; technique des Handle du système d'exploitation DOS.
  479. ;
  480. ;
  481. ; Entrée
  482. ; ======
  483. ;
  484. ; DS = Segment du nom du fichier (Format String Pascal)
  485. ; DI = Offset du nom de fichier (Format String Pascal)
  486. ;
  487. ;
  488. ; Retour
  489. ; ======
  490. ;
  491. ; AX = 0 tous va bien
  492. ; <> 0 une erreur s'est produit
  494. DelFile Proc Near
  495. MOV BL,DS:[DI]
  496. INC DI
  497. MOV BH,0
  498. MOV DS:[DI+BX],BH
  499. MOV DX,DI
  500. MOV AX,04100h
  501. INT 021h
  502. JC @DF2
  503. XOR AX,AX
  504. @DF2:
  505. DEC DI
  506. EndProc
  508. ;+----------------------------------------------------------------
  509. ;| Fonction NewFile |
  510. ;+---------------------------------------------------------------|
  511. ;
  512. ;
  513. ; Description
  514. ; ===========
  515. ;
  516. ; Cette fonction permet de créer un fichier par l'entremise de la
  517. ; technique des Handle du système d'exploitation DOS.
  518. ;
  519. ;
  520. ; Entrée
  521. ; ======
  522. ;
  523. ; DS = Segment du nom du fichier (Format String Pascal)
  524. ; DI = Offset du nom de fichier (Format String Pascal)
  525. ;
  526. ;
  527. ; Retour
  528. ; ======
  529. ;
  530. ; AL = Handle
  531. ; = FFh (errHdl) s'est qu'une erreur de création s'est produite
  533. NewFile Proc Near
  534. MOV BL,DS:[DI]
  535. XOR BH,BH
  536. INC BX
  537. MOV DS:[DI+BX],BH
  538. MOV DX,DI
  539. INC DX
  540. XOR CX,CX
  541. MOV AH,03Ch
  542. INT 021h
  543. JNC @NF2
  544. MOV AL,errHdl
  545. @NF2:
  546. EndProc
  548. ;+-----------------------------------------------------------------
  549. ;| Fonction FileSize |
  550. ;+----------------------------------------------------------------|
  551. ;
  552. ;
  553. ; Description
  554. ; ===========
  555. ;
  556. ; Cette fonction permet de connaître la taille d'un fichier ouvert
  557. ; par l'entremise de la technique des «Handles» du système
  558. ; d'exploitation DOS.
  559. ;
  560. ;
  561. ; Entrée
  562. ; ======
  563. ;
  564. ; BL = Handle
  565. ;
  566. ;
  567. ; Retour
  568. ; ======
  569. ;
  570. ; DX:AX = Taille du fichier en 32 bits
  572. FileSize Proc Near
  573. CMP BL,errHdl
  574. JE @FS1
  575. XOR BH,BH
  576. MOV AX,04202h
  577. XOR CX,CX
  578. XOR DX,DX
  579. INT 021h
  580. JNC @FS1
  581. MOV AX,0FFFFh
  582. MOV DX,AX
  583. @FS1:
  584. EndProc
  586. ;+-------------------------------------------------------------------
  587. ;| Procédure Rewind |
  588. ;+------------------------------------------------------------------|
  589. ;
  590. ;
  591. ; Description
  592. ; ===========
  593. ;
  594. ; Cette procédure permet de place le pointeur fichier de type Handle
  595. ; au début du dit fichier spécifier par le Handle.
  596. ;
  597. ;
  598. ; Entrée
  599. ; ======
  600. ;
  601. ; BL = Handle
  602. ;
  603. ;
  604. ; Sortie
  605. ; ======
  606. ;
  607. ; Registre détruit AX, BX, DX, SI, DI, ES
  609. Rewind Proc Near
  610. PUSH CX
  611. MOV AX,4200h
  612. XOR BH,BH
  613. CMP BL,errHdl
  614. JE @FinRewind
  615. XOR DX,DX
  616. XOR CX,CX
  617. INT 21h
  618. JC @ErrRewind
  619. XOR AX,AX
  620. @ErrRewind:
  621. @FinRewind:
  622. POP CX
  623. EndProc
  625. ;+-------------------------------------------------------------------
  626. ;| Procédure _GetRec |
  627. ;+------------------------------------------------------------------|
  628. ;
  629. ;
  630. ; Description
  631. ; ===========
  632. ;
  633. ; Cette procédure permet de lire un enregistrement dans un fichier de
  634. ; type Handle à la position courante.
  635. ;
  636. ;
  637. ; Entrée
  638. ; ======
  639. ;
  640. ; BL = Handle
  641. ; CX = Taille de l'enregistrement
  642. ; ES = Segment de l'enregistrement
  643. ; DI = Offset de l'enregistrement
  644. ;
  645. ;
  646. ; Sortie
  647. ; ======
  648. ;
  649. ; Registre détruit AX, BX, DX, SI, DI, ES
  651. _GetRec Proc Near
  652. PUSH CX
  653. CLD
  654. XOR AX,AX
  655. PUSH CX
  656. MOV DX,DI
  657. SHR CX,1
  658. REP STOSW
  659. ADC CX,CX
  660. REP STOSB
  661. POP CX
  662. MOV AX,3F00h
  663. XOR BH,BH
  664. CMP BL,errHdl
  665. JE @1GR
  666. PUSH DS
  667. _MOV_DS_ES
  668. INT 021h
  669. POP DS
  670. JNC @1GR
  671. XOR AX,AX
  672. @1GR:
  673. POP CX
  674. EndProc
  676. ;+---------------------------------------------------------------------
  677. ;| Procédure _SetRec |
  678. ;+--------------------------------------------------------------------|
  679. ;
  680. ;
  681. ; Description
  682. ; ===========
  683. ;
  684. ; Cette procédure permet d'écrire un enregistrement dans un fichier de
  685. ; type Handle à la position courante.
  686. ;
  687. ;
  688. ; Entrée
  689. ; ======
  690. ;
  691. ; BL = Handle
  692. ; CX = Taille de l'enregistrement
  693. ; DS = Segment de l'enregistrement
  694. ; SI = Offset de l'enregistrement
  695. ;
  696. ;
  697. ; Sortie
  698. ; ======
  699. ;
  700. ; Registre détruit AX, BX, DX, SI, DI, ES
  702. _SetRec Proc Near
  703. PUSH ES
  704. PUSH DI
  705. PUSH BX
  706. MOV BL,Handle
  707. XOR BH,BH
  708. CMP BL,errHdl
  709. JE @ErrSetRec
  710. MOV DX,SI
  711. MOV AX,04000h
  712. INT 021h
  713. @ErrSetRec:
  714. JC @FinSetRec
  715. XOR AX,AX
  716. @FinSetRec:
  717. POP BX
  718. POP DI
  719. POP ES
  720. EndProc
  722. ;+----------------------------------------------------------------------
  723. ;| Procédure CloseFile |
  724. ;+---------------------------------------------------------------------|
  725. ;
  726. ;
  727. ; Description
  728. ; ===========
  729. ;
  730. ; Cette procédure permet de fermer un fichier de type Handle du système
  731. ; d'exploitation DOS.
  732. ;
  733. ;
  734. ; Entrée
  735. ; ======
  736. ;
  737. ; BL = Handle
  738. ;
  739. ;
  740. ; Sortie
  741. ; ======
  742. ;
  743. ; Registre détruit AX, BX, CX, DX, SI, DI, ES
  745. CloseFile Proc Near
  746. MOV AX,03E00h
  747. XOR BH,BH
  748. INT 021h
  749. EndProc
  751. ;+----------------------------------------------------------------------
  752. ;| Fonction ReadKey |
  753. ;+---------------------------------------------------------------------|
  754. ;
  755. ;
  756. ; Description
  757. ; ===========
  758. ;
  759. ; Cette fonction permet de lire le dernier caractère avec son scan code
  760. ; enfoncé au clavier. Si aucun caractère n'attend dans le tampon, il
  761. ; attend après l'utilisateur afin de retourner l'action de l'utilisateur.
  762. ;
  763. ;
  764. ; Entrée
  765. ; ======
  766. ;
  767. ; Aucun
  768. ;
  769. ;
  770. ; Sortie
  771. ; ======
  772. ;
  773. ; Registre détruit BX, CX, DX, SI, DI, ES
  774. ;
  775. ;
  776. ; Retour
  777. ; ======
  778. ;
  779. ; AL = Code de caractère
  780. ; AH = Scan Code
  782. ReadKey Proc Near
  783. XOR AX,AX
  784. INT 16h
  785. EndProc
  787. ;+----------------------------------------------------------------------
  788. ;| Procédure ErrMsg |
  789. ;+---------------------------------------------------------------------|
  790. ;
  791. ;
  792. ; Description
  793. ; ===========
  794. ;
  795. ; Cette procédure permet d'afficher un message d'erreur sur la dernière
  796. ; ligne de couleur rouge.
  797. ;
  798. ;
  799. ; Entrée
  800. ; ======
  801. ;
  802. ; DS = Segment du message d'erreur (Format String Pascal)
  803. ; SI = Offset du message d'erreur (Format String Pascal)
  805. ErrMsg Proc Near
  806. MOV BL,MaxYTxts
  807. MOV DX,0+(79 shl 8)
  808. MOV AX,04F20h
  809. CALL BarTxtHor
  810. MOV AH,4Eh
  811. MOV BX,(2 shl 8)+24
  812. CALL PutTxtXY
  813. EndProc
  815. ;+-------------------------------------------------------------------
  816. ;| Procédure Msg |
  817. ;+------------------------------------------------------------------|
  818. ;
  819. ;
  820. ; Description
  821. ; ===========
  822. ;
  823. ; Cette procédure permet d'afficher un message sur la ligne réservée
  824. ; au message utilisateur.
  825. ;
  826. ;
  827. ; Entrée
  828. ; ======
  829. ;
  830. ; DS = Segment du message (Format String Pascal)
  831. ; SI = Offset du message (Format String Pascal)
  833. Msg Proc Near
  834. MOV BL,MaxYTxts
  835. DEC BL
  836. MOV DX,0+(79 shl 8)
  837. MOV AX,02F20h
  838. CALL BarTxtHor
  839. MOV AH,2Eh
  840. MOV BX,(2 shl 8)+24-1
  841. CALL PutTxtXY
  842. MOV DH,MaxYTxts
  843. DEC DH
  844. MOV DL,2
  845. ADD DL,CS:[SI]
  846. CALL SetCurPos
  847. EndProc
  849. ;+-----------------------------------------------------------------
  850. ;| Procédure CLireChaine |
  851. ;+----------------------------------------------------------------|
  852. ;
  853. ;
  854. ; Description
  855. ; ===========
  856. ;
  857. ; Cette procédure permet d'interroger l'utilisateur en acceptant
  858. ; n'importe quel caractère mettant le contenu de sa réponse dans le
  859. ; segment de code.
  860. ;
  861. ;
  862. ; Entrée
  863. ; ======
  864. ;
  865. ; CS = Segment du message de l'usager (Format String Pascal)
  866. ; SI = Offset du message de l'usager (Format String Pascal)
  867. ; CL = Longueur maximal de la chaîne entrable par l'utilisateur
  868. ; DL = Position X de départ
  869. ; DH = Position Y de départ
  871. CLireChaine Proc Near
  872. MOV DI,Offset AccepteTous
  873. endp
  875. ;+-----------------------------------------------------------------
  876. ;| Procédure CLireChaine |
  877. ;+----------------------------------------------------------------|
  878. ;
  879. ;
  880. ; Description
  881. ; ===========
  882. ;
  883. ; Cette procédure permet d'interroger l'utilisateur en acceptant
  884. ; que les caractères conforme au tuteur mettant le contenu de sa
  885. ; réponse dans le segment de code.
  886. ;
  887. ;
  888. ; Entrée
  889. ; ======
  890. ;
  891. ;* CS = Segment du message de l'usager (Format String Pascal)
  892. ; SI = Offset du message de l'usager (Format String Pascal)
  893. ;* CS = Segment du tuteur
  894. ; DI = Offset du tuteur
  895. ; CL = Longueur maximal de la chaîne entrable par l'utilisateur
  896. ; DL = Position X de départ
  897. ; DH = Position Y de départ
  899. _CLireChaine Proc Near
  900. PUSH DS
  901. _MOV_DS_CS
  902. CALL _LireChaine
  903. POP DS
  904. EndProc
  906. ;+-----------------------------------------------------------------
  907. ;| Procédure LireChaine |
  908. ;+----------------------------------------------------------------|
  909. ;
  910. ;
  911. ; Description
  912. ; ===========
  913. ;
  914. ; Cette procédure permet d'interroger l'utilisateur en acceptant
  915. ; n'importe quel caractère mettant le contenu de sa réponse dans le
  916. ; segment de donnée.
  917. ;
  918. ;
  919. ; Entrée
  920. ; ======
  921. ;
  922. ; DS = Segment du message de l'usager (Format String Pascal)
  923. ; SI = Offset du message de l'usager (Format String Pascal)
  924. ; CL = Longueur maximal de la chaîne entrable par l'utilisateur
  925. ; DL = Position X de départ
  926. ; DH = Position Y de départ
  928. LireChaine Proc Near
  929. MOV DI,Offset AccepteTous
  930. endp
  932. ;+-----------------------------------------------------------------
  933. ;| Procédure _LireChaine |
  934. ;+----------------------------------------------------------------|
  935. ;
  936. ;
  937. ; Description
  938. ; ===========
  939. ;
  940. ; Cette procédure permet d'interroger l'utilisateur en acceptant
  941. ; que les caractères conforme au tuteur mettant le contenu de sa
  942. ; réponse dans le segment de donnée.
  943. ;
  944. ;
  945. ; Entrée
  946. ; ======
  947. ;
  948. ; DS = Segment du message de l'usager (Format String Pascal)
  949. ; SI = Offset du message de l'usager (Format String Pascal)
  950. ; CS = Segment du tuteur
  951. ; DI = Offset du tuteur
  952. ; CL = Longueur maximal de la chaîne entrable par l'utilisateur
  953. ; DL = Position X de départ
  954. ; DH = Position Y de départ
  956. _LireChaine Proc Near
  957. Local OldPos:Word,Buffer:Word,Max:Byte,Tuteur:Word
  958. MOV Buffer,SI
  959. MOV Tuteur,DI
  960. DEC CL
  961. MOV Max,CL
  962. MOV Byte Ptr DS:[SI],0 ; Initialise le tampon
  963. MOV OldPos,DX
  964. DEC DL
  965. PUSH DX
  966. MOV BL,DH
  967. MOV DH,DL
  968. ADD DH,Max
  969. MOV AX,07F20h
  970. CALL BarTxtHor
  971. POP DX
  972. ReLire:
  973. CALL SetCurPos
  974. CALL ReadKey
  975. CMP AL,13
  976. JE FinLecture
  977. CMP AL,8
  978. JE BackCaract
  979. CMP AL,' '
  980. JB Relire
  981. JMP InsereCaract
  982. BackCaract:
  983. MOV BX,Buffer
  984. CMP Byte Ptr DS:[BX],0
  985. JE Relire
  986. DEC Byte Ptr DS:[BX]
  987. MOV DX,OldPos
  988. ADD DL,DS:[BX]
  989. DEC DL
  990. MOV AL,' '
  991. CALL SetChr
  992. JMP ReLire
  993. FinLecture:
  994. MOV SI,Buffer
  995. RET
  996. InsereCaract:
  997. MOV DI,Tuteur
  998. MOV DX,OldPos
  999. MOV BX,Buffer
  1000. MOV CL,DS:[BX]
  1001. CMP CL,Max
  1002. JA ChainePleine
  1003. CMP Byte Ptr CS:[DI],'þ'
  1004. JE Tous
  1005. XCHG DI,AX
  1006. ADD AL,DS:[BX]
  1007. ADC AH,0
  1008. XCHG DI,AX
  1009. CMP Byte Ptr CS:[DI],'A'
  1010. JE TestLettre
  1011. CMP Byte Ptr CS:[DI],'9'
  1012. JE TestChiffre
  1013. JMP Tous
  1014. TestChiffre:
  1015. CMP AL,'0'
  1016. JB ChiffreAttendu
  1017. CMP AL,'9'
  1018. JA ChiffreAttendu
  1019. JMP Tous
  1020. TestLettre:
  1021. AND AL,NOT 020h
  1022. CMP AL,'A'
  1023. JB LettreAttendu
  1024. CMP AL,'Z'
  1025. JA LettreAttendu
  1026. Tous:
  1027. ADD DL,DS:[BX]
  1028. INC Byte Ptr DS:[BX]
  1029. ADD BL,DS:[BX]
  1030. ADC BH,0
  1031. MOV DS:[BX],AL
  1032. PUSH DX
  1033. DEC DL
  1034. CALL SetChr
  1035. POP DX
  1036. JMP ReLire
  1037. ChiffreAttendu:
  1038. MOV SI,Offset StrChiffreAttendu
  1039. JMP @LEM
  1040. LettreAttendu:
  1041. MOV SI,Offset StrLettreAttendu
  1042. JMP @LEM
  1043. ChainePleine:
  1044. MOV SI,Offset StrFull
  1045. @LEM:
  1046. CALL ErrMsg
  1047. ResetLire:
  1048. MOV DX,OldPos
  1049. DEC DL
  1050. MOV BX,Buffer
  1051. ADD DL,DS:[BX]
  1052. JMP Relire
  1053. endp
  1055. ;+----------------------------------------------------------
  1056. ;| Procédure InitTitre |
  1057. ;+---------------------------------------------------------|
  1058. ;
  1059. ;
  1060. ; Description
  1061. ; ===========
  1062. ;
  1063. ; Cette procédure initialise l'écran comme avec «ClrScr» et
  1064. ; affiche un titre à la ligne spécifier par le registre BL.
  1065. ;
  1066. ;
  1067. ; Entrée
  1068. ; ======
  1069. ;
  1070. ; BL = Position vertical du titre
  1071. ; CS = Segment du Titre
  1072. ; SI = Offset du Titre
  1074. InitTitre Proc Near
  1075. MOV AH,017h
  1076. CALL ClrScr
  1077. PUSH AX
  1078. MOV AX,0720h
  1079. MOV DX,0+(79 shl 8)
  1080. MOV BL,24
  1081. CALL BarTxtHor
  1082. POP AX
  1083. MOV AH,01Eh
  1084. CALL PutTxtY
  1085. EndProc
  1087. ;+-----------------------------------------------------------------
  1088. ;| Procédure RBGetCurrAuto |
  1089. ;+----------------------------------------------------------------|
  1090. ;
  1091. ;
  1092. ; Propriétaire: RBuf
  1093. ;
  1094. ;
  1095. ; Description
  1096. ; ===========
  1097. ;
  1098. ; Cette procédure permet de charger dans le segment de donnée
  1099. ; la voiture courante d'une liste symétrique.
  1100. ;
  1101. ;
  1102. ; Entrée
  1103. ; ======
  1104. ;
  1105. ; ES:DI = Adresse de la structure «RBuf»
  1107. RBGetCurrAuto Proc Near
  1108. PUSH DS
  1109. PUSH ES
  1110. PUSH DI
  1111. CALL RBGetCurrBuf
  1112. CMP CX,TYPE InfoAuto
  1113. JNE @CorruptionMemoire
  1114. _MOV_ES_DS
  1115. MOV DI,Offset TempAuto
  1116. MOV DS,DX
  1117. XCHG SI,AX
  1118. CLD
  1119. REP MOVSB
  1120. @CorruptionMemoire:
  1121. POP DI
  1122. POP ES
  1123. POP DS
  1124. EndProc
  1126. ;+-------------------------------------------------------------------
  1127. ;| Fonction ICompare |
  1128. ;+------------------------------------------------------------------|
  1129. ;
  1130. ;
  1131. ; Description
  1132. ; ===========
  1133. ;
  1134. ; Cette fonction compare deux chaînes de caractères en ne tenant pas
  1135. ; compte des majuscules/minuscules et indique si elles sont identique
  1136. ; (1) ou différente (0).
  1137. ;
  1138. ;
  1139. ; Entrée
  1140. ; ======
  1141. ;
  1142. ; DS:SI = Source
  1143. ; ES:DI = Destination
  1144. ; CX = Longueur
  1145. ;
  1146. ;
  1147. ; Sortie
  1148. ; ======
  1149. ;
  1150. ; Registre détruit AX, BX, CX, DX et les registres drapeaux
  1151. ;
  1152. ;
  1153. ; Retour
  1154. ; ======
  1155. ;
  1156. ; AX = 0 pour des chaînes de caractères différente
  1157. ; = 1 pour des chaînes de caractères identique
  1159. ICompare Proc Near
  1160. PUSH SI
  1161. PUSH DI
  1162. JCXZ @@97
  1163. CLD
  1164. @@99:
  1165. CMPSB
  1166. JNE @@98
  1167. LOOP @@99
  1168. JMP @@100
  1169. @@98:
  1170. DEC SI
  1171. LODSB
  1172. MOV AH,ES:[DI-1]
  1173. OR AX,2020h
  1174. CMP AH,'a'
  1175. JB @@97
  1176. CMP AH,'z'
  1177. JA @@97
  1178. CMP AL,'a'
  1179. JB @@97
  1180. CMP AL,'z'
  1181. JA @@97
  1182. SUB AL,AH
  1183. OR AL,AL
  1184. JNZ @@97
  1185. LOOP @@99
  1186. JMP @@0
  1187. @@100:
  1188. JZ @@0
  1189. @@97:
  1190. MOV CL,1
  1191. @@0:
  1192. XCHG AX,CX
  1193. XOR AL,1
  1194. MOV AH,0
  1195. POP DI
  1196. POP SI
  1197. EndProc
  1199. ;+------------------------------------------------------------------
  1200. ;| Fonction RBSearchAuto |
  1201. ;+-----------------------------------------------------------------|
  1202. ;
  1203. ;
  1204. ; Description
  1205. ; ===========
  1206. ;
  1207. ; Cette fonction recherche dans une liste symétrique de format
  1208. ; «RBuf» l'immatriculation de la voiture spécifiée par les registres
  1209. ; d'adressages DS:SI.
  1210. ;
  1211. ;
  1212. ; Entrée
  1213. ; ======
  1214. ;
  1215. ; DS:SI = Adresse de l'immatriculation
  1216. ; ES:DI = Adresse de la structure «RBuf»
  1217. ;
  1218. ;
  1219. ; Sortie
  1220. ; ======
  1221. ;
  1222. ; Registre détruit AX, BX, CX, DX, SI et DI et les registres drapeaux
  1223. ;
  1224. ;
  1225. ; Retour
  1226. ; ======
  1227. ;
  1228. ; AX = 0 voiture introuvable
  1229. ; > 0 position dans la liste
  1231. RBSearchAuto Proc Near
  1232. XOR AX,AX
  1233. MOV CX,ES:[DI].RBuf.NB
  1234. JCXZ @FinSearch
  1235. CALL RBSetPtrHome
  1236. @Next:
  1237. PUSH CX
  1238. PUSH ES
  1239. PUSH DI
  1240. CALL RBGetCurrBuf
  1241. XCHG DI,AX
  1242. ADD DI,Offset InfoAuto.Immat
  1243. MOV ES,DX
  1244. MOV CL,ES:[DI]
  1245. XOR CH,CH
  1246. XOR AX,AX
  1247. CMP CL,DS:[SI]
  1248. JNE @SkipCompare
  1249. INC CX
  1250. CALL ICompare
  1251. @SkipCompare:
  1252. POP DI
  1253. POP ES
  1254. OR AX,AX
  1255. JNZ @FinTrouve
  1256. CALL RBNext
  1257. POP CX
  1258. LOOP @Next
  1259. XOR AX,AX
  1260. JMP @FinSearch
  1261. @FinTrouve:
  1262. POP AX
  1263. @FinSearch:
  1264. EndProc
  1266. ;+------------------------------------------------------------------
  1267. ;| Fonction Menu |
  1268. ;+-----------------------------------------------------------------|
  1269. ;
  1270. ;
  1271. ; Description
  1272. ; ===========
  1273. ;
  1274. ; Cette procédure affiche un menu avec 5 options et permet à
  1275. ; l'utilisateur de choisir un des options. Il retourne ensuite comme
  1276. ; valeur de retour cette option sous forme de lettre '1' à '5'.
  1277. ;
  1278. ;
  1279. ; Entrée
  1280. ; ======
  1281. ;
  1282. ; DS:SI = Adresse de l'immatriculation
  1283. ; ES:DI = Adresse de la structure «RBuf»
  1284. ;
  1285. ;
  1286. ; Sortie
  1287. ; ======
  1288. ;
  1289. ; Registre détruit AX, BX, CX, DX, SI et DI et les registres drapeaux
  1290. ;
  1291. ;
  1292. ; Retour
  1293. ; ======
  1294. ;
  1295. ; AL = Caractère correspondant à l'option
  1297. Menu Proc Near
  1298. MOV SI,Offset Titre
  1299. MOV BL,0
  1300. CALL InitTitre
  1301. MOV SI,Offset Item1
  1302. MOV BX,(5 shl 8)+5
  1303. MOV AH,01Bh
  1304. CALL PutTxtXY
  1305. MOV SI,Offset Item2
  1306. INC BX
  1307. INC BX
  1308. CALL PutTxtXY
  1309. MOV SI,Offset Item3
  1310. INC BX
  1311. INC BX
  1312. CALL PutTxtXY
  1313. MOV SI,Offset Item4
  1314. INC BX
  1315. INC BX
  1316. CALL PutTxtXY
  1317. MOV SI,Offset Item5
  1318. INC BX
  1319. INC BX
  1320. CALL PutTxtXY
  1321. MOV SI,Offset QuesPrinc
  1322. MOV BX,17
  1323. MOV AH,01Fh
  1324. CALL PutTxtXY
  1325. @MenuRestart:
  1326. MOV DX,(17 shl 8)+15
  1327. CALL SetCurPos
  1328. CALL ReadKey
  1329. CMP AL,'1'
  1330. JB @MenuErr
  1331. CMP AL,'5'
  1332. JA @MenuErr
  1333. RET
  1334. @MenuErr:
  1335. MOV SI,Offset ChoixInvalid
  1336. CALL ErrMsg
  1337. JMP @MenuRestart
  1338. endp
  1340. ;+--------------------------------------------------------------------
  1341. ;| Fonction Val |
  1342. ;+-------------------------------------------------------------------|
  1343. ;
  1344. ;
  1345. ; Description
  1346. ; ===========
  1347. ;
  1348. ; Cette fonction retourne la valeur entière d'une chaîne de caractère
  1349. ; de format numérique.
  1350. ;
  1351. ;
  1352. ; Remarque
  1353. ; ========
  1354. ;
  1355. ; þ S'il les caractères contenu dans la chaîne ne sont pas des lettres
  1356. ; aussi bien dire qu'il retournera n'importe quel valeur...
  1357. ;
  1358. ;
  1359. ; Entrée
  1360. ; ======
  1361. ;
  1362. ; DS:SI = Chaîne de caractères contenant les nombres
  1363. ;
  1364. ;
  1365. ; Retour
  1366. ; ======
  1367. ;
  1368. ; AX = Valeur numérique contenu dans la chaîne
  1370. ValTab10 DW 1, 10, 100, 1000, 10000
  1372. Val Proc Near
  1373. PUSH DI
  1374. XOR DI,DI
  1375. MOV CL,DS:[SI]
  1376. XOR CH,CH
  1377. ADD SI,CX
  1378. STD
  1379. XOR BX,BX
  1380. @Val:
  1381. LODSB
  1382. SUB AL,'0'
  1383. XOR AH,AH
  1384. MUL ValTab10[BX]
  1385. ADD DI,AX
  1386. INC BX
  1387. INC BX
  1388. LOOP @Val
  1389. XCHG AX,DI
  1390. POP DI
  1391. EndProc
  1393. ;+----------------------------------------------------------------------
  1394. ;| Fonction LireOuiNon |
  1395. ;+---------------------------------------------------------------------|
  1396. ;
  1397. ;
  1398. ; Description
  1399. ; ===========
  1400. ;
  1401. ; Cette fonction demande à l'utilisateur de répondre par une lettre O
  1402. ; ou N en majuscule ou minuscule il ne fait pas la différence.
  1403. ; Toutefois si vous répondez une autre lettre que ces 2 alors il repose
  1404. ; la question à l'utilisateur en lui affichant un message pour lui faire
  1405. ; comprendre sa grossière erreur de concentration.
  1406. ;
  1407. ;
  1408. ; Entrée
  1409. ; ======
  1410. ;
  1411. ; Aucun
  1412. ;
  1413. ;
  1414. ; Retour
  1415. ; ======
  1416. ;
  1417. ; AL = Caractère correspondant à O ou N seulement
  1419. LireOuiNon Proc Near
  1420. @ReLireOuiNon:
  1421. CALL ReadKey
  1422. AND AL,NOT 20h
  1423. CMP AL,'O'
  1424. JE @FinOuiNon
  1425. CMP AL,'N'
  1426. JE @FinOuiNon
  1427. MOV SI,Offset PrendDessin
  1428. CALL ErrMsg
  1429. JMP @ReLireOuiNon
  1430. @FinOuiNon:
  1431. EndProc
  1433. ;+--------------------------------------------------------------------
  1434. ;| Procédure ArriveeAuto |
  1435. ;+-------------------------------------------------------------------|
  1436. ;
  1437. ;
  1438. ; Description
  1439. ; ===========
  1440. ;
  1441. ; Cette procédure demande à l'utilisateur d'entrée une voiture s'il
  1442. ; existe de la place dans le parc ou la rue et vérifie que son
  1443. ; immatriculation ne corresponde pas déjà à une voiture existante dans
  1444. ; le parc.
  1445. ;
  1446. ;
  1447. ; Entrée
  1448. ; ======
  1449. ;
  1450. ; Aucun
  1451. ;
  1452. ;
  1453. ; Sortie
  1454. ; ======
  1455. ;
  1456. ; Registre détruit AX, BX, CX, DX, SI, DI et les drapeaux
  1458. ArriveeAuto Proc Near
  1459. @ArriveeAuto:
  1460. MOV SI,Offset TitreArriveeAuto
  1461. MOV BL,0
  1462. CALL InitTitre
  1463. MOV SI,Offset QuestionMat
  1464. MOV BX,5
  1465. MOV AH,01Bh
  1466. CALL PutTxtXY
  1467. MOV AX,InfoParc.NB
  1468. ADD AX,InfoRue.NB
  1469. CMP AX,MaximumVoitureParc+MaximumVoitureRue
  1470. JAE @ParcEtRuePlein
  1471. MOV DX,37+(5 shl 8)
  1472. MOV CL,15
  1473. MOV SI,Offset TempAuto.Immat
  1474. CALL LireChaine
  1475. CMP InfoParc.NB,0
  1476. JE @LectureDonnee
  1477. MOV DI,Offset InfoParc
  1478. MOV SI,Offset TempAuto.Immat
  1479. _MOV_ES_DS
  1480. CALL RBSearchAuto
  1481. OR AX,AX
  1482. JZ @LectureDonnee
  1483. MOV SI,Offset VoitureExistante
  1484. CALL ErrMsg
  1485. JMP @ArriveeAutre
  1486. @ParcEtRuePlein:
  1487. MOV SI,Offset ParcEtRuePlein
  1488. CALL ErrMsg
  1489. MOV SI,Offset PresseUneTouche
  1490. CALL Msg
  1491. CALL ReadKey
  1492. RET
  1493. @LectureDonnee:
  1494. MOV SI,Offset QuestionMarque
  1495. MOV BX,7
  1496. MOV AH,01Bh
  1497. CALL PutTxtXY
  1498. MOV DX,37+(7 shl 8)
  1499. MOV CL,25
  1500. MOV SI,Offset TempAuto.Marque
  1501. CALL LireChaine
  1502. MOV SI,Offset QuestionCouleur
  1503. MOV BX,8
  1504. MOV AH,01Bh
  1505. CALL PutTxtXY
  1506. MOV DX,37+(8 shl 8)
  1507. MOV CL,15
  1508. MOV SI,Offset TempAuto.Couleur
  1509. CALL LireChaine
  1510. MOV SI,Offset QuestionAnnee
  1511. MOV BX,9
  1512. MOV AH,01Bh
  1513. CALL PutTxtXY
  1514. @RelireAnnee:
  1515. MOV DX,37+(9 shl 8)
  1516. MOV CL,4
  1517. MOV SI,Offset String
  1518. MOV DI,Offset TuteurAnnee
  1519. CALL _LireChaine
  1520. CALL Val
  1521. CMP AX,1900
  1522. JB @MauvaiseAnnee
  1523. CMP AX,1999
  1524. JNA @AnneeValide
  1525. @MauvaiseAnnee:
  1526. MOV SI,Offset AnneeInvalid
  1527. CALL ErrMsg
  1528. JMP @RelireAnnee
  1529. @AnneeValide:
  1530. MOV TempAuto.Annee,AX
  1531. MOV CX,TYPE InfoAuto
  1532. _MOV_ES_DS
  1533. CMP InfoParc.NB,MaximumVoitureParc
  1534. JNE @Parc
  1535. MOV DI,Offset InfoRue
  1536. JMP @SkipParc
  1537. @Parc:
  1538. MOV DI,Offset InfoParc
  1539. @SkipParc:
  1540. MOV SI,Offset TempAuto
  1541. CALL RBAdd
  1542. @ArriveeAutre:
  1543. MOV SI,Offset QuesNewVoiture
  1544. CALL Msg
  1545. CALL LireOuiNon
  1546. CMP AL,'N'
  1547. JE @FinArrivee
  1548. JMP @ArriveeAuto
  1549. @FinArrivee:
  1550. EndProc
  1552. ;+--------------------------------------------------------------------
  1553. ;| Fonction AChiffre |
  1554. ;+-------------------------------------------------------------------|
  1555. ;
  1556. ;
  1557. ; Description
  1558. ; ===========
  1559. ;
  1560. ; Cette fonction retourne une valeur numérique contenu par le registre
  1561. ; BX dans une chaîne de caractères nommé «String».
  1562. ;
  1563. ;
  1564. ; Entrée
  1565. ; ======
  1566. ;
  1567. ; BL = Valeur
  1568. ;
  1569. ;
  1570. ; Sortie
  1571. ; ======
  1572. ;
  1573. ; Registre détruit AX, BX, CX, DX, SI, DI et les drapeaux
  1574. ;
  1575. ;
  1576. ; Retour
  1577. ; ======
  1578. ;
  1579. ; String = Contient une chaîne de caractères numérique contenant la valeur
  1580. ; du registre BX
  1582. AChiffre Proc Near
  1583. CLD
  1584. MOV DI,Offset String
  1585. PUSH DS
  1586. POP ES
  1587. CMP BX,10000
  1588. JAE @10000
  1589. CMP BX,1000
  1590. JAE @1000
  1591. CMP BX,100
  1592. JAE @100
  1593. CMP BX,10
  1594. JAE @10
  1595. MOV AL,1
  1596. MOV AH,BL
  1597. ADD AH,'0'
  1598. STOSW
  1599. JMP @FinChiffre
  1600. @10:
  1601. MOV AL,2
  1602. STOSB
  1603. XCHG AX,BX
  1604. @Dump10:
  1605. MOV DL,10
  1606. DIV DL
  1607. ADD AL,'0'
  1608. ADD AH,'0'
  1609. STOSW
  1610. JMP @FinChiffre
  1611. @100:
  1612. MOV AL,3
  1613. STOSB
  1614. XCHG AX,BX
  1615. @Dump100:
  1616. MOV DL,100
  1617. DIV DL
  1618. ADD AL,'0'
  1619. STOSB
  1620. MOV AL,AH
  1621. MOV AH,0
  1622. JMP @Dump10
  1623. @1000:
  1624. MOV AL,4
  1625. STOSB
  1626. XCHG AX,BX
  1627. @Dump1000:
  1628. XOR DX,DX
  1629. MOV CX,1000
  1630. DIV CX
  1631. ADD AL,'0'
  1632. STOSB
  1633. XCHG AX,DX
  1634. JMP @Dump100
  1635. @10000:
  1636. MOV AL,5
  1637. STOSB
  1638. XCHG AX,BX
  1639. XOR DX,DX
  1640. MOV CX,10000
  1641. DIV CX
  1642. ADD AL,'0'
  1643. STOSB
  1644. XCHG AX,DX
  1645. JMP @Dump1000
  1646. @FinChiffre:
  1647. EndProc
  1649. ;+----------------------------------------------------------------
  1650. ;| Procédure Information |
  1651. ;+---------------------------------------------------------------|
  1652. ;
  1653. ;
  1654. ; Description
  1655. ; ===========
  1656. ;
  1657. ; Cette procédure informe l'utilisateur sur l'état global du parc
  1658. ; ainsi que les nombres de place prise dans le parc et la rue.
  1659. ;
  1660. ;
  1661. ; Entrée
  1662. ; ======
  1663. ;
  1664. ; Aucun
  1665. ;
  1666. ;
  1667. ; Sortie
  1668. ; ======
  1669. ;
  1670. ; Registre détruit AX, BX, CX, DX, SI, DI et les drapeaux
  1672. Information Proc Near
  1673. MOV SI,Offset TitreInformation
  1674. MOV BL,0
  1675. CALL InitTitre
  1676. MOV SI,Offset InfoParcUsed
  1677. MOV BX,(4 shl 8)+3
  1678. MOV AH,01Fh
  1679. CALL PutTxtXY
  1680. MOV SI,Offset InfoParcFree
  1681. INC BX
  1682. CALL PutTxtXY
  1683. MOV SI,Offset InfoRueUsed
  1684. INC BX
  1685. CALL PutTxtXY
  1686. MOV SI,Offset InfoRueFree
  1687. INC BX
  1688. CALL PutTxtXY
  1689. MOV BX,InfoParc.NB
  1690. CALL AChiffre
  1691. MOV SI,Offset String
  1692. MOV BX,(45 shl 8)+3
  1693. MOV AH,1Bh
  1694. CALL _PutTxtXY
  1695. MOV BX,MaximumVoitureParc
  1696. SUB BX,InfoParc.NB
  1697. CALL AChiffre
  1698. MOV SI,Offset String
  1699. MOV BX,(45 shl 8)+4
  1700. MOV AH,1Bh
  1701. CALL _PutTxtXY
  1702. MOV BX,InfoRue.NB
  1703. CALL AChiffre
  1704. MOV SI,Offset String
  1705. MOV BX,(45 shl 8)+5
  1706. MOV AH,1Bh
  1707. CALL _PutTxtXY
  1708. MOV BX,MaximumVoitureRue
  1709. SUB BX,InfoRue.NB
  1710. CALL AChiffre
  1711. MOV SI,Offset String
  1712. MOV BX,(45 shl 8)+6
  1713. MOV AH,1Bh
  1714. CALL _PutTxtXY
  1715. MOV SI,Offset PresseUneTouche
  1716. CALL Msg
  1717. CMP InfoParc.NB,0
  1718. JE @PersonneDansParc
  1719. MOV SI,Offset InfoVoitureParc
  1720. MOV BX,(0 shl 8)+8
  1721. MOV AH,01Fh
  1722. CALL PutTxtXY
  1723. MOV SI,Offset EnteteParc1
  1724. MOV BX,(0 shl 8)+10
  1725. MOV AH,01Fh
  1726. CALL PutTxtXY
  1727. MOV SI,Offset EnteteParc2
  1728. MOV BX,(0 shl 8)+11
  1729. MOV AH,01Fh
  1730. CALL PutTxtXY
  1731. _MOV_ES_DS
  1732. MOV DI,Offset InfoParc
  1733. CALL RBSetPtrHome
  1734. MOV CX,InfoParc.NB
  1735. MOV BL,12
  1736. @AfficheLigne:
  1737. PUSH CX
  1738. CALL RBGetCurrAuto
  1739. MOV SI,Offset TempAuto.Marque
  1740. MOV BH,0
  1741. MOV AH,01Bh
  1742. CALL _PutTxtXY
  1743. MOV SI,Offset TempAuto.Couleur
  1744. MOV BH,26
  1745. MOV AH,01Bh
  1746. CALL _PutTxtXY
  1747. PUSH BX
  1748. MOV BX,TempAuto.Annee
  1749. CALL AChiffre
  1750. POP BX
  1751. MOV SI,Offset String
  1752. MOV BH,42
  1753. MOV AH,01Bh
  1754. CALL _PutTxtXY
  1755. MOV SI,Offset TempAuto.Immat
  1756. MOV BH,48
  1757. MOV AH,01Bh
  1758. CALL _PutTxtXY
  1759. _MOV_ES_DS
  1760. MOV DI,Offset InfoParc
  1761. CALL RBNext
  1762. INC BX
  1763. POP CX
  1764. LOOP @AfficheLigne
  1765. @PersonneDansParc:
  1766. CALL ReadKey
  1767. EndProc
  1769. ;+--------------------------------------------------------------------
  1770. ;| Procédure DepartVoiture |
  1771. ;+-------------------------------------------------------------------|
  1772. ;
  1773. ;
  1774. ; Description
  1775. ; ===========
  1776. ;
  1777. ; Cette procédure permet à l'utilisateur de faire quitter une
  1778. ; voiture du parc de voiture. Pour se faire il demande à l'utilisateur
  1779. ; d'entrée le numéro d'immatriculation et si la voiture est trouvée
  1780. ; alors il l'efface de la liste symétrique.
  1781. ;
  1782. ;
  1783. ; Entrée
  1784. ; ======
  1785. ;
  1786. ; Aucun
  1787. ;
  1788. ;
  1789. ; Sortie
  1790. ; ======
  1791. ;
  1792. ; Registre détruit AX, BX, CX, DX, SI, DI et les drapeaux
  1794. DepartVoiture Proc Near
  1795. @Depart:
  1796. MOV SI,Offset TitreDepartAuto
  1797. MOV BL,0
  1798. CALL InitTitre
  1799. CMP InfoParc.NB,0
  1800. JE @DVoitureExistePas
  1801. MOV SI,Offset QuestionMat
  1802. MOV BX,5
  1803. MOV AH,01Bh
  1804. CALL PutTxtXY
  1805. MOV DX,37+(5 shl 8)
  1806. MOV CL,15
  1807. MOV SI,Offset TempAuto.Immat
  1808. CALL LireChaine
  1809. MOV DI,Offset InfoParc
  1810. MOV SI,Offset TempAuto.Immat
  1811. _MOV_ES_DS
  1812. CALL RBSearchAuto
  1813. OR AX,AX
  1814. JNZ @DVoiturePresent
  1815. MOV SI,Offset VoitureIntrouvable
  1816. CALL ErrMsg
  1817. JMP @DepartAutre
  1818. @DVoitureExistePas:
  1819. MOV SI,Offset VoitureExistePas
  1820. CALL ErrMsg
  1821. MOV SI,Offset PresseUneTouche
  1822. CALL Msg
  1823. CALL ReadKey
  1824. RET
  1825. @DVoiturePresent:
  1826. CALL RBGetCurrAuto
  1827. MOV SI,Offset StrMarque
  1828. MOV BX,7
  1829. MOV AH,01Bh
  1830. CALL PutTxtXY
  1831. MOV BH,37
  1832. MOV SI,Offset TempAuto.Marque
  1833. CALL _PutTxtXY
  1834. MOV SI,Offset StrCouleur
  1835. MOV BX,8
  1836. MOV AH,01Bh
  1837. CALL PutTxtXY
  1838. MOV BH,37
  1839. MOV SI,Offset TempAuto.Couleur
  1840. CALL _PutTxtXY
  1841. MOV SI,Offset StrAnnee
  1842. MOV BX,9
  1843. MOV AH,01Bh
  1844. CALL PutTxtXY
  1845. MOV BX,TempAuto.Annee
  1846. CALL AChiffre
  1847. MOV SI,Offset String
  1848. MOV AH,01Bh
  1849. MOV BX,(37 shl 8)+9
  1850. CALL _PutTxtXY
  1851. MOV DI,Offset InfoParc
  1852. _MOV_ES_DS
  1853. CALL RBDelCurrBuf
  1854. CMP InfoRue.NB,0
  1855. JE @DepartAutre
  1856. CMP InfoParc.NB,MaximumVoitureParc
  1857. JNB @DepartAutre
  1858. _MOV_ES_DS
  1859. MOV DI,Offset InfoRue
  1860. CALL RBSetPtrHome
  1861. CALL RBGetCurrAuto
  1862. CALL RBDelCurrBuf
  1863. MOV DI,Offset InfoParc
  1864. MOV SI,Offset TempAuto
  1865. MOV CX,TYPE InfoAuto
  1866. CALL RBAdd
  1867. @DepartAutre:
  1868. MOV SI,Offset QuesDepartNewVoiture
  1869. CALL Msg
  1870. CALL LireOuiNon
  1871. CMP AL,'N'
  1872. JE @FinDepart
  1873. JMP @Depart
  1874. @FinDepart:
  1875. EndProc
  1877. ;+-------------------------------------------------------------------
  1878. ;| Procédure Consultation |
  1879. ;+------------------------------------------------------------------|
  1880. ;
  1881. ;
  1882. ; Description
  1883. ; ===========
  1884. ;
  1885. ; Cette procédure permet à l'utilisateur de consulter une voiture du
  1886. ; parc de voiture. Pour se faire il demande à l'utilisateur d'entrée
  1887. ; le numéro d'immatriculation et si la voiture est trouvée alors il
  1888. ; l'efface de la liste symétrique.
  1889. ;
  1890. ;
  1891. ; Entrée
  1892. ; ======
  1893. ;
  1894. ; Aucun
  1895. ;
  1896. ;
  1897. ; Sortie
  1898. ; ======
  1899. ;
  1900. ; Registre détruit AX, BX, CX, DX, SI, DI et les drapeaux
  1902. Consultation Proc Near
  1903. @Consultation:
  1904. MOV SI,Offset TitreConsultationAuto
  1905. MOV BL,0
  1906. CALL InitTitre
  1907. CMP InfoParc.NB,0
  1908. JE @VoitureExistePas
  1909. MOV SI,Offset QuestionMat
  1910. MOV BX,5
  1911. MOV AH,01Bh
  1912. CALL PutTxtXY
  1913. MOV DX,37+(5 shl 8)
  1914. MOV CL,15
  1915. MOV SI,Offset TempAuto.Immat
  1916. CALL LireChaine
  1917. MOV DI,Offset InfoParc
  1918. MOV SI,Offset TempAuto.Immat
  1919. _MOV_ES_DS
  1920. CALL RBSearchAuto
  1921. OR AX,AX
  1922. JNZ @VoiturePresent
  1923. @VoitureExistePas:
  1924. MOV SI,Offset VoitureExistePas
  1925. CALL ErrMsg
  1926. MOV SI,Offset PresseUneTouche
  1927. CALL Msg
  1928. CALL ReadKey
  1929. RET
  1930. @VoiturePresent:
  1931. CALL RBGetCurrAuto
  1932. MOV SI,Offset StrMarque
  1933. MOV BX,7
  1934. MOV AH,01Bh
  1935. CALL PutTxtXY
  1936. MOV BH,37
  1937. MOV SI,Offset TempAuto.Marque
  1938. CALL _PutTxtXY
  1939. MOV SI,Offset StrCouleur
  1940. MOV BX,8
  1941. MOV AH,01Bh
  1942. CALL PutTxtXY
  1943. MOV BH,37
  1944. MOV SI,Offset TempAuto.Couleur
  1945. CALL _PutTxtXY
  1946. MOV SI,Offset StrAnnee
  1947. MOV BX,9
  1948. MOV AH,01Bh
  1949. CALL PutTxtXY
  1950. MOV BX,TempAuto.Annee
  1951. CALL AChiffre
  1952. MOV SI,Offset String
  1953. MOV AH,01Bh
  1954. MOV BX,(37 shl 8)+9
  1955. CALL _PutTxtXY
  1956. @ConsultationAutre:
  1957. MOV SI,Offset QuesConsultNewVoiture
  1958. CALL Msg
  1959. CALL LireOuiNon
  1960. CMP AL,'N'
  1961. JE @FinConsultation
  1962. JMP @Consultation
  1963. @FinConsultation:
  1964. EndProc
  1966. ;+-------------------------------------------------------------------
  1967. ;| Procédure FinJournee |
  1968. ;+------------------------------------------------------------------|
  1969. ;
  1970. ;
  1971. ; Description
  1972. ; ===========
  1973. ;
  1974. ; Cette procédure permet de sauvegarder les voitures contenu dans le
  1975. ; parc de voiture et d'en faire par à l'utilisateur.
  1976. ;
  1977. ;
  1978. ; Entrée
  1979. ; ======
  1980. ;
  1981. ; Aucun
  1982. ;
  1983. ;
  1984. ; Sortie
  1985. ; ======
  1986. ;
  1987. ; Registre détruit AX, BX, CX, DX, SI, DI et les drapeaux
  1989. FinJournee Proc Near
  1990. Local Handle:Byte
  1991. MOV SI,Offset FinJourneeStr
  1992. MOV BL,0
  1993. CALL InitTitre
  1994. MOV SI,Offset SauveMsg
  1995. MOV BX,5
  1996. MOV AH,01Bh
  1997. CALL PutTxtXY
  1998. MOV DI,Offset NomFichier
  1999. CALL DelFile
  2000. CALL NewFile
  2001. CMP AL,errHdl
  2002. JNE @FichierOuvert
  2003. MOV SI,Offset ImpossibleCree
  2004. CALL ErrMsg
  2005. JMP @FinJournee
  2006. @FichierOuvert:
  2007. MOV Handle,AL
  2008. _MOV_ES_DS
  2009. MOV DI,Offset InfoParc
  2010. CALL RBSetPtrHome
  2011. MOV CX,InfoParc.NB
  2012. @SauveEnreg:
  2013. PUSH CX
  2014. CALL RBGetCurrAuto
  2015. MOV CX,TYPE InfoAuto
  2016. MOV BL,Handle
  2017. MOV SI,Offset TempAuto
  2018. CALL _SetRec
  2019. CALL RBNext
  2020. POP CX
  2021. LOOP @SauveEnreg
  2022. MOV BL,Handle
  2023. CALL CloseFile
  2024. @FinJournee:
  2025. MOV SI,Offset PresseUneTouche
  2026. CALL Msg
  2027. CALL ReadKey
  2028. EndProc
  2030. ;+-------------------------------------------------------------------
  2031. ;| Fonction Presentation |
  2032. ;+------------------------------------------------------------------|
  2033. ;
  2034. ;
  2035. ; Description
  2036. ; ===========
  2037. ;
  2038. ; Cette affiche un message de présentation à l'utilisateur et lui
  2039. ; demande s'il veut continuer. Lorsque l'usager a pris sa décision
  2040. ; alors la fonction retourne une lettre O ou N.
  2041. ;
  2042. ;
  2043. ; Entrée
  2044. ; ======
  2045. ;
  2046. ; Aucun
  2047. ;
  2048. ;
  2049. ; Sortie
  2050. ; ======
  2051. ;
  2052. ; Registre détruit AX, BX, CX, DX, SI, DI et les drapeaux
  2053. ;
  2054. ;
  2055. ; Retour
  2056. ; ======
  2057. ;
  2058. ; AL = O s'il veut continuer le processus
  2059. ; N s'il ne veut pas continuer le processus
  2061. Presentation Proc Far
  2062. MOV AH,17h
  2063. CALL ClrScr
  2064. MOV AX,0720h
  2065. MOV DX,0+(79 shl 8)
  2066. MOV BL,24
  2067. CALL BarTxtHor
  2068. MOV BL,3
  2069. MOV AH,01Eh
  2070. MOV SI,Offset Pres1
  2071. CALL PutTxtY
  2072. MOV BL,5
  2073. MOV AH,01Fh
  2074. MOV SI,Offset Pres2
  2075. CALL PutTxtY
  2076. MOV BL,7
  2077. MOV SI,Offset Pres3
  2078. CALL PutTxtY
  2079. MOV BL,10
  2080. MOV AH,01Ch
  2081. MOV SI,Offset Pres4
  2082. CALL PutTxtY
  2083. MOV BL,12
  2084. MOV AH,01Fh
  2085. MOV SI,Offset Pres5
  2086. CALL PutTxtY
  2087. MOV BX,15+(2 shl 8)
  2088. MOV SI,Offset Pres6
  2089. CALL PutTxtXY
  2090. INC BX
  2091. MOV SI,Offset Pres7
  2092. CALL PutTxtXY
  2093. INC BX
  2094. INC BX
  2095. MOV SI,Offset Pres8
  2096. CALL PutTxtXY
  2097. INC BX
  2098. MOV SI,Offset Pres9
  2099. CALL PutTxtXY
  2100. MOV SI,Offset Pres10
  2101. CALL Msg
  2102. CALL LireOuiNon
  2103. EndProc
  2105. ;+------------------------------------------------------------------
  2106. ;| Procédure LectureFichier |
  2107. ;+-----------------------------------------------------------------|
  2108. ;
  2109. ;
  2110. ; Description
  2111. ; ===========
  2112. ;
  2113. ; Cette procédure permet de lire à partir d'un fichier et de mettre
  2114. ; le contenu lu dans une liste symétrique.
  2115. ;
  2116. ;
  2117. ; Entrée
  2118. ; ======
  2119. ;
  2120. ; Aucun
  2121. ;
  2122. ;
  2123. ; Sortie
  2124. ; ======
  2125. ;
  2126. ; Registre détruit AX, BX, CX, DX, SI, DI et les drapeaux
  2128. LectureFichier Proc Near
  2129. Local Handle:Byte
  2130. MOV SI,Offset SaisieDonnee
  2131. MOV BL,0
  2132. CALL InitTitre
  2133. MOV SI,Offset EntrezNom
  2134. MOV BX,4
  2135. CALL PutTxtXY
  2136. @RedemandeFichier:
  2137. MOV DX,(5 shl 8)+1
  2138. MOV CL,80
  2139. MOV SI,Offset NomFichier
  2140. CALL LireChaine
  2141. CMP Byte Ptr NomFichier,0
  2142. JE @Continue
  2143. MOV BL,fmRead
  2144. MOV DI,Offset NomFichier
  2145. CALL OpenFile
  2146. CMP AL,errHdl
  2147. JNE @FichierPret
  2148. CALL DelFile
  2149. CALL NewFile
  2150. CMP AL,errHdl
  2151. JNE @FichierPret
  2152. MOV SI,Offset ImpossibleCree
  2153. CALL ErrMsg
  2154. JMP @RedemandeFichier
  2155. @FichierPret:
  2156. MOV Handle,AL
  2157. MOV BL,AL
  2158. CALL FileSize
  2159. OR AX,AX
  2160. JE @EndFile
  2161. MOV BX,TYPE InfoAuto
  2162. DIV BX
  2163. XCHG AX,CX
  2164. MOV BL,Handle
  2165. CALL Rewind
  2166. @ReadAuto:
  2167. PUSH CX
  2168. _MOV_ES_DS
  2169. MOV BL,Handle
  2170. MOV DI,Offset TempAuto
  2171. MOV CX,TYPE InfoAuto
  2172. CALL _GetRec
  2173. _MOV_ES_DS
  2174. MOV DI,Offset InfoParc
  2175. MOV SI,Offset TempAuto
  2176. CALL RBAdd
  2177. POP CX
  2178. LOOP @ReadAuto
  2179. @EndFile:
  2180. MOV BL,Handle
  2181. CALL CloseFile
  2182. @Continue:
  2183. EndProc
  2185. ;+----------------------------------------------------------------------
  2186. ;| Procédure AvosRisque |
  2187. ;+---------------------------------------------------------------------|
  2188. ;
  2189. ;
  2190. ; Description
  2191. ; ===========
  2192. ;
  2193. ; Cette procédure lance le programme lui-même. Il s'agit d'un programme
  2194. ; de gestion de parc de voiture dans le font du rue *perdue.
  2195. ;
  2196. ;
  2197. ; Entrée
  2198. ; ======
  2199. ;
  2200. ; Aucun
  2201. ;
  2202. ;
  2203. ; Sortie
  2204. ; ======
  2205. ;
  2206. ; Registre détruit AX, BX, CX, DX, SI, DI et les drapeaux
  2208. @Choix:
  2209. DW Offset ArriveeAuto, Offset DepartVoiture, Offset Consultation
  2210. DW Offset Information, Offset FinJournee
  2212. AvosRisque Proc Far
  2213. MOV AX,3
  2214. INT 10h
  2215. _MOV_ES_DS
  2216. MOV DI,Offset InfoParc
  2217. CALL RBInit
  2218. MOV DI,Offset InfoRue
  2219. CALL RBInit
  2220. CALL Presentation
  2221. CMP AL,'N'
  2222. JE @FinAR
  2223. @AutreFichier:
  2224. CALL LectureFichier
  2225. @AR:
  2226. CALL Menu
  2227. PUSH AX
  2228. XCHG AX,BX
  2229. XOR BH,BH
  2230. SUB BL,'1'
  2231. SHL BX,1
  2232. CALL Word Ptr @Choix[BX]
  2233. POP AX
  2234. CMP AL,'5'
  2235. JNE @AR
  2236. _MOV_ES_DS
  2237. MOV DI,Offset InfoParc
  2238. CALL RBDone
  2239. MOV DI,Offset InfoRue
  2240. CALL RBDone
  2241. MOV SI,Offset AutreFichier
  2242. CALL Msg
  2243. CALL LireOuiNon
  2244. CMP AL,'O'
  2245. JE @AutreFichier
  2246. @FinAR:
  2247. MOV AX,3
  2248. INT 10h
  2249. EndProc
  2251. code ends
  2252. end

Dernière mise à jour : Samedi, le 21 décembre 2013


Il est parfois pratique de savoir quel année possède 366 jours dans le calendrier grégorien. On appel s'est année, les années bissextile. A l'aide du code source Assembleur 80x86 suivant, vous trouverez la réponse que vous souhaitez :

  1. .MODEL small
  2.    .STACK 100h
  3.    .DATA
  4. Message1       DB ' est une année bissextile','$'
  5. CRLF           DB 13,10,'$'
  6.    .CODE
  7. PrintDigit PROC NEAR
  8.     OR  AX,AX
  9.     JNS Positif
  10.     PUSH AX
  11.      MOV AH,02h
  12.      MOV DL,'-'
  13.      INT 21h
  14.     POP AX
  15.     NEG AX
  16. Positif:
  17.     MOV BX,10
  18.     XOR CX,CX
  19. NextDigit:
  20.     XOR DX,DX
  21.     DIV BX
  22.     PUSH DX
  23.      INC CX
  24.      OR  AX,AX
  25.      JNZ NextDigit
  26. PrintOneDigit:
  27.     POP AX
  28.     ADD AL,48
  29.     MOV DL,AL
  30.     MOV AH,02h
  31.     INT 21h
  32.     LOOP PrintOneDigit
  33.     RET
  34. ENDP
  35.
  36. IsLeapYear PROC NEAR
  37.     MOV DX,AX
  38.     MOV CX,AX
  39.     AND AX,3
  40.     JNZ @isleapyearFalse
  41.     MOV DI,100
  42.     XCHG AX,DX
  43.     XOR DX,DX
  44.     DIV DI
  45.     OR  DX,DX
  46.     JNZ @isleapyearTrue
  47.     MOV DI,400
  48.     XCHG AX,CX
  49.     XOR DX,DX
  50.     DIV DI
  51.     OR  DX,DX
  52.     JZ  @isleapyearTrue
  53. @isleapyearFalse:
  54.     MOV AX,0
  55.     RET
  56. @isleapyearTrue:
  57.     MOV AX,1
  58.     RET
  59. ENDP
  60.
  61.     .startup
  62.     MOV  AX,1900
  63. @Restart:
  64.     PUSH AX
  65.      CALL IsLeapYear
  66.      OR   AX,AX
  67.      JZ   @Next
  68.      POP  AX
  69.      PUSH AX
  70.      CALL PrintDigit
  71.      MOV  AX,@data
  72.      MOV  DS,AX
  73.      MOV  AH,9
  74.      MOV  DX,OFFSET Message1
  75.      INT  21h
  76.      MOV  AH,9
  77.      MOV  DX,OFFSET CRLF
  78.      INT  21h
  79.
  80. @Next:
  81.     POP AX
  82.     INC AX
  83.     CMP AX,2009
  84.     JNGE @Restart
  85.
  86.     MOV  AX,4C00h
  87.     INT  21h
  88.     END

on obtiendra le résultat suivant :

1904 est une année bissextile
1908 est une année bissextile
1912 est une année bissextile
1916 est une année bissextile
1920 est une année bissextile
1924 est une année bissextile
1928 est une année bissextile
1932 est une année bissextile
1936 est une année bissextile
1940 est une année bissextile
1944 est une année bissextile
1948 est une année bissextile
1952 est une année bissextile
1956 est une année bissextile
1960 est une année bissextile
1964 est une année bissextile
1968 est une année bissextile
1972 est une année bissextile
1976 est une année bissextile
1980 est une année bissextile
1984 est une année bissextile
1988 est une année bissextile
1992 est une année bissextile
1996 est une année bissextile
2000 est une année bissextile
2004 est une année bissextile
2008 est une année bissextile

Si par exemple vous utilisez le Turbo Assembleur version 5.0, vous n'aurez que les trois commandes suivantes a effectuer pour voir le résultat en supposant que le programme s'appel «leapyear.asm» :

TASM leapyear.asm
TLINK leapyear.obj
leapyear.exe

Dernière mise à jour : Vendredi, le 4 mars 2016


Voici un exemple d'un programme permettant d'afficher un triangle Pascal :

  1. .MODEL small
  2.    .STACK 100h
  3.    .DATA
  4. Space     DB ' ','$'
  5. CRLF      DB 13,10,'$'
  6. BeginLine DB '< ','$'
  7.    .CODE
  8. PrintDigit PROC NEAR
  9.     OR  AX,AX
  10.     JNS Positif
  11.     PUSH AX
  12.      MOV AH,02h
  13.      MOV DL,'-'
  14.      INT 21h
  15.     POP AX
  16.     NEG AX
  17. Positif:
  18.     MOV BX,10
  19.     XOR CX,CX
  20. NextDigit:
  21.     XOR DX,DX
  22.     DIV BX
  23.     PUSH DX
  24.      INC CX
  25.      OR  AX,AX
  26.      JNZ NextDigit
  27. PrintOneDigit:
  28.     POP AX
  29.     ADD AL,48
  30.     MOV DL,AL
  31.     MOV AH,02h
  32.     INT 21h
  33.     LOOP PrintOneDigit
  34.     RET
  35. ENDP
  36.
  37.     .startup
  38.     XOR  DX,DX
  39. @Loop1:
  40.     XOR  CX,CX
  41. @Loop2:
  42.     PUSH CX
  43.      PUSH CX
  44.       PUSH DX
  45.        MOV  AX,@data
  46.        MOV  DS,AX
  47.        MOV  AH,9
  48.        MOV  DX,OFFSET Space
  49.        INT  21h
  50.       POP DX
  51.      POP CX
  52.      PUSH DX
  53.       XCHG AX,DX
  54.       MUL CL
  55.       CALL PrintDigit
  56.      POP DX
  57.     POP CX
  58.     INC CX
  59.     CMP CX,DX
  60.     JNG @Loop2
  61.     PUSH DX
  62.      MOV  AX,@data
  63.      MOV  DS,AX
  64.      MOV  AH,9
  65.      MOV  DX,OFFSET CRLF
  66.      INT  21h
  67.     POP DX
  68.     INC  DX
  69.     CMP  DX,10
  70.     JNGE @Loop1
  71.
  72.     MOV  AX,4C00h
  73.     INT  21h
  74.     END

on obtiendra le résultat suivant :

0
0 1
0 2 4
0 3 6 9
0 4 8 12 16
0 5 10 15 20 25
0 6 12 18 24 30 36
0 7 14 21 28 35 42 49
0 8 16 24 32 40 48 56 64
0 9 18 27 36 45 54 63 72 81

Si par exemple vous utilisez le Turbo Assembleur version 5.0, vous n'aurez que les trois commandes suivantes a effectuer pour voir le résultat en supposant que le programme s'appel «triapasc.asm» :

TASM triapasc.asm
TLINK triapasc.obj
triapasc.exe

Voir également

Science - Mathématique

Dernière mise à jour : Vendredi, le 4 mars 2016


Système d'exploitation DOS

Voici un petit programme permettant d'afficher la valeur absolue du nombre -1234 à l'écran sous un système d'exploitation DOS ou compatible :

  1. .MODEL small
  2.    .STACK 100h
  3.    .DATA
  4. Message1       DB 'Valeur absolue (-1234) = ','$'
  5. CRLF           DB 13,10,'$'
  6.    .CODE
  7. PrintDigit PROC NEAR
  8.     OR  AX,AX
  9.     JNS Positif
  10.     PUSH AX
  11.      MOV AH,02h
  12.      MOV DL,'-'
  13.      INT 21h
  14.     POP AX
  15.     NEG AX
  16. Positif:
  17.     MOV BX,10
  18.     XOR CX,CX
  19. NextDigit:
  20.     XOR DX,DX
  21.     DIV BX
  22.     PUSH DX
  23.      INC CX
  24.      OR  AX,AX
  25.      JNZ NextDigit
  26. PrintOneDigit:
  27.     POP AX
  28.     ADD AL,48
  29.     MOV DL,AL
  30.     MOV AH,02h
  31.     INT 21h
  32.     LOOP PrintOneDigit
  33.     RET
  34. ENDP
  35.
  36. AbsInt PROC NEAR
  37.     OR  AX,AX
  38.     JGE exitAbsInt
  39.     NEG AX
  40. exitAbsInt:
  41.     RET
  42. ENDP
  43.
  44.     .startup
  45.     MOV  AX,@data
  46.     MOV  DS,AX
  47.     MOV  AH,9
  48.     MOV  DX,OFFSET Message1
  49.     INT  21h
  50.     MOV  AX,-1234
  51.     CALL AbsInt
  52.     CALL PrintDigit
  53.     MOV  AH,9
  54.     MOV  DX,OFFSET CRLF
  55.     INT  21h
  56.     MOV  AX,4C00h
  57.     INT  21h
  58.     END

Il affichera donc le message suivant :

Valeur absolue (-1234) = 1234

Si par exemple vous utilisez le Turbo Assembleur version 5.0, vous n'aurez que les trois commandes suivantes a effectuer pour voir le résultat en supposant que le programme s'appel «abs.asm» :

TASM abs.asm
TLINK abs.obj
abs.exe

Voir également

Langage de programmation - AWK - Mathématique - Valeur absolue (ABS)

Références

Assembleur Facile, Edition Marabout, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 262 à 265.

Dernière mise à jour : Vendredi, le 4 mars 2016


Introduction

Le langage Assembleur de la famille des 80x86 est de loin le plus populaire des langages assembleurs à avoir été développé. De plus, ses différents modes de fonctionnement (Mode réel, Mode protégé, Mode virtuel) sont le résultat d'un manque de vision d'extension vers le futur. Hélas, on ne peut pas tout prévoir, mais le prix a payer fut des programmes a réécrire, un microprocesseur de plus en plus complexe de style CISC. En faite, tout le contraire des microprocesseurs RISC.

Le bon côté de la complexité de son fonctionnement, tiens du fait qu'il est possible d'écrire des programmes en langages machines avec très peu de code si on est habile pour utiliser spécifiquement ce qu'on a vraiment besoin. Ainsi, si on veut effectué des calculs ne nécessitant que 8 bits et non 16 bits, cette opération est toujours possible. De plus, les experts de ce langage assembleur arrive a effectuer deux opérations 8 bits avec une seule instruction, a mettre la valeur d'un registre avec un opérateur de «ou exclusif binaire» (exemple: XOR AX,AX ou XOR EAX,EAX), lequel est beaucoup compacte en terme de code. Et bien que la folie des grandeurs poussent les programmeurs a consommer toujours le maximum d'un registre, il est souvent préférable d'écrire un code très petit, qu'avec des instructions plus rapide, car, bien que ses processeurs soit très rapide, les programmes, eux sont toujours aussi lent a charger en mémoire!

Avantages

Bien que très peu utilisé, quels sont les avantages d'utiliser le langage de programmation Assembleur ?

  • Les langages assembleurs sont beaucoup plus rapide d'exécution que les langages évolué.
  • Les langages assembleurs sont beaucoup plus petit en terme de taille total d'un programme. Généralement, ils sont 10 fois plus petits qu'une application écrit en langage évolue (3GL ou 4GL).
  • Il est possible d'avoir un contrôle total sur le contexte d'utilisation de la mémoire.
  • Il est possible de tout faire en assembleur, ainsi, si on souhaite écrire un secteur de démarrage entrant spécifiquement dans un espace réduit, c'est possible! Dans un langage évolué, comme le langage C ou Pascal, cette idée peut paraitre à la fois farfelue et dangereuse, car totalement imprévisible en fonction des versions et du fabricant du compilateur.

Inconvénient

Qu'est-ce qu'y bloc l'utilisation du langage de programmation Assembleur ?

  • Les programmes écrits en assembleurs sont destinés au microprocesseur et le matériel pour lequel ils ont étés écrits. Ils ne sont pas portable.
  • Le temps de développements est souvent beaucoup plus long qu'un autre langage, car des erreurs souvent banales, peuvent faire planter le système.
  • Le temps de formation d'un professionnel est beaucoup plus long.

Microprocesseur | Fabricant | Génération | Mode de fonctionnement | Registre | Coprocesseur | Coeur
8088 | Intel | 1re | Mode réel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, ES, IP, SI, SP, SS | 8087 | 1
V20 | NEC | 1re | Mode réel, mode émulation 8080 | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, ES, IP, SI, SP, SS |  | 1
8086 | Intel | 1re | Mode réel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, ES, IP, SI, SP, SS | 8087 | 1
V30 | NEC | 1re | Mode réel, mode émulation 8080 | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, ES, IP, SI, SP, SS |  | 1
80188 | Intel | 1re | Mode réel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, ES, IP, SI, SP, SS | 8087 | 1
80186 | Intel | 1re | Mode réel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, ES, IP, SI, SP, SS | 8087 | 1
80286 | Intel | 2e | Mode réel, mode protégé | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, ES, IP, SI, SP, SS | 80287 | 1
80386DX | Intel | 3e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS | 80387DX | 1
80386DXL | AMD | 3e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS |  | 1
80386DXLV | AMD | 3e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS |  | 1
80386SX | Intel | 3e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS | 80387SX | 1
80386SXL | AMD | 3e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS |  | 1
80386SXLV | AMD | 3e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS |  | 1
80386SL | Intel | 3e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS | 80387SL | 1
80386SLC | IBM | 3e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS |  | 1
80486 | Intel | 4e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
80486DX | Intel | 4e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
80486SL | Intel | 4e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
80486SLC2 | IBM | 4e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS |  | 1
80486SX | Intel | 4e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, SI, SP, SS | 80487SX | 1
Pentium | Intel | 5e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
Pentium MMX | Intel | 5e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
Pentium Pro | Intel | 6e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
Pentium II | Intel | 6e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
Pentium III | Intel | 6e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
Pentium M | Intel | 6e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
Pentium 4 | Intel | 7e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 1
Pentium D | Intel | 7e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 2
Core 2 | Intel | 7e | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | 2
... | ... | ... | Mode réel, mode protégé, mode virtuel | AH, AL, AX, BH, BL, BP, BX, CH, CL, CS, CX, DH, DI, DL, DS, DX, EAX, EBX, ECX, EDI, EDX, ESI, ES, FS, GS, IP, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R0, R1, R2, R3, R4, R5, R6, R7, SI, SP, SS | Intégré | ...

Voir également

Articles - Les géants de l'informatique - Intel

Références

Assembleur - Référence, Edition Micro Application, Pierre Maurette, 2003, ISBN: 2-7429-3061-2, page 84 à 100.
The Undocumented PC: A programmer's Guide to I/O, CPUs, and Fixed Memory Areas - Second Edition, Edition Addison-Wesley, Frank van Gilluwe, 1997, ISBN: 0-201-47950-8, page 51 à 62.

Dernière mise à jour : Samedi, le 2 août 2014


Introduction

Pour effectuer la détection des différents modèles de contrôleur par la BIOS du SCSI dans anciennes cartes SCSI pour bus ISA, sans créer de conflit avec certains pilote DOS comme LBACACHE, il faut effectuer l'appel de la façon suivante :

  1. ChkSCSI Macro
  2.  MOV AX,1800h   ; Fonction 18h: Sélectionne le type de média pour le formatage
  3.  MOV DX,8000h   ; Fixe une unité disque invalide
  4.  MOV CX,0FFFFh  ; Nombre de cylindre et de secteurs par piste impossible...
  5.  XOR BX,BX      ; Afin de ne pas entré en conflit avec le LBACACHE
  6.  INT 13h        ; Interruption 13h: Teste le SCSI
  7. EndM

Cette macro retourne 4321h dans AX si un système de gestion d'unité a été détecté sinon il peut renvoyer n'importe quel autre valeur. Le code de famille de contrôleur est retourné dans le registre CX:

Code | Nom de la famille
0200h | TMC-1680/? (ROM 3.0)
0203h | TMC-1650/1660/1670/1680 (ROM 2.0)
040Ah | TMC-820/830/840/850/860/870/875/880/885 (ROM <= 6.0A)
050Dh | TMC-840/841/880/881 (ROM 5.2D)
0700h | TMC-830/850/860/875/885 (ROM 7.0)

Voir également

Interruption 13h, Fonction 18h : Demande des informations SCSI

Dernière mise à jour : Vendredi, le 4 mars 2016


Introduction

Une des connaissances oublier de tous, c'est que certains modèles de clone de XT ont déjà supporté différents CMOS de fabricant tiers. Afin de facilité la compréhension du problème j'ai retiré certaines partie du code source de démarrage de la bibliothèque du Malte Genesis V: Alias Adèle du progiciel du MonsterBook dont voici pour le plus grand bénéfice de tous l'extrait du source :

  1. ; ---------------------------------------------------------------------------------------------------------------------------------------------------------------------
  2. ; Extrait du système de démarrage du progiciel MonsterBook
  3. ; Tous droits réservés par les Gladir.com
  4. ; Developpeur: Sylvain Maltais (smaltais@gladir.com)
  5. ;
  6. ; Utilisation à titre éducatif ou communautaire seulement
  7. ; ---------------------------------------------------------------------------------------------------------------------------------------------------------------------
  8.
  9. ;Drapeau d'existance des Interruptions de la variable IntExistFlag
  10.  flgInt10h equ 1     ; Drapeau indiquant l'existance de l'interruption 10h
  11.  flgInt11h equ 2     ; Drapeau indiquant l'existance de l'interruption 11h
  12.  flgInt12h equ 4     ; Drapeau indiquant l'existance de l'interruption 12h
  13.  flgInt13h equ 8     ; Drapeau indiquant l'existance de l'interruption 13h
  14.  flgInt14h equ 0010h ; Drapeau indiquant l'existance de l'interruption 14h
  15.  flgInt15h equ 0020h ; Drapeau indiquant l'existance de l'interruption 15h
  16.  flgInt16h equ 0040h ; Drapeau indiquant l'existance de l'interruption 16h
  17.  flgInt1Ah equ 0080h ; Drapeau indiquant l'existance de l'interruption 1Ah
  18.  flgInt21h equ 0100h ; Drapeau indiquant l'existance de l'interruption 21h
  19.  flgInt2Ah equ 0200h ; Drapeau indiquant l'existance de l'interruption 2Ah
  20.  flgInt2Fh equ 0400h ; Drapeau indiquant l'existance de l'interruption 2Fh
  21.  flgInt33h equ 0800h ; Drapeau indiquant l'existance de l'interruption 33h
  22.  flgInt67h equ 1000h ; Drapeau indiquant l'existance de l'interruption 67h
  23.
  24. ; ---------------------------------------------------------------------------------------------------------------------------------------------------------------------
  25. ;                       Structure des cavaliers du démarrage
  26. ; ---------------------------------------------------------------------------------------------------------------------------------------------------------------------
  27.
  28. Jumper STRUC
  29.  FlgMethod DW ?
  30. ENDS
  31.
  32. ; ---------------------------------------------------------------------------------------------------------------------------------------------------------------------
  33. ;                              Structure de démarrage
  34. ; ---------------------------------------------------------------------------------------------------------------------------------------------------------------------
  35.
  36. StartUpRec STRUC
  37.  ; Info sur le Micro-Processeur et son bus système
  38.  CPU           DB ? ; Modèle de CPU
  39.  Up32Bits      DB ? ; Boolean: Support les instructions 32 bits?
  40.  CPUIDSupport  DB ? ; Boolean: Support l'instruction CPUID?
  41.  CPUVendor     DB ? ; Byte: Fabricant du CPU?
  42.  Bus           DB ? ; Taille du Bus de données
  43.  ; Info sur le modèle d'Ordinateur
  44.  ComputerName  DW ?
  45.  PS2           DB ? ; Est-ce un PS/2 d'IBM?
  46.  ; Info sur les Interruptions
  47.  IntExistFlags DW ?
  48.  ;Information sur le DOS
  49.  GetDosVer     DW ?
  50.  GetDosBlock   DD ? ; DosBlockPtr
  51.  HandleExist   DB ? ; Boolean: Est-ce que les Handles existent?
  52.  ;Information sur OS/2 et Windows
  53.  OS2           DB ? ; Boolean
  54.  OS2HiVer      DB ? ; Version OS/2
  55.  OS2LoVer      DB ? ; Sous-version OS/2
  56.  Win           DB ? ; Mode de fonctionnement de Windows
  57.  WinLoVer      DB ? ; Sous-version Windows
  58.  WinHiVer      DB ? ; Version Windows
  59.  ;Information de pays
  60.  CountryCode   DW ?
  61.  CodePage      DW ?
  62.  Date          DW ?        ; Format de la date
  63.  Curr          DB 5 DUP(?) ; Array[0..4]of Chr
  64.  ThSep         DW ?        ; Array[0..1]of Chr
  65.  DeSep         DW ?        ; Array[0..1]of Chr
  66.  DtSep         DW ?        ; Array[0..1]of Chr
  67.  TmSep         DW ?        ; Array[0..1]of Chr
  68.  CurrStyle     DB ?
  69.  Digits        DB ?
  70.  Time          DB ?        ; TimeType
  71.  CaseUp        DD ?        ; Pointer
  72.  DaSep         DW ?        ; Array[0..1]of Chr
  73.  ;Information sur le(s) lecteur(s) de disquette
  74.  FloppyDskExist DB ? ; Boolean
  75.  NmFloppyDsk    DB ?
  76.  ;Info sur le(s) disque(s) dur
  77.  HardDskExist   DB ? ; Boolean
  78.  NmHardDsk      DB ?
  79.  HardDskCtrl    DW ? ; Modèle de contrôleur de disque dur
  80.   ; Information réseau
  81.  IsNovell       DB ? ; Boolean: Réseau Novell présent
  82.  ; Spooler d'imprimante
  83.  Spooler        DB ?
  84.  ;Information sur la manette de jeu
  85.  JoyExist         DB ?
  86.  BiosJoy          DB ?
  87.  JoyPort          DW ?
  88.  JoyPotentioMeter DW ?
  89.  ;Information sur le clavier
  90.  KbdModel         DB ?
  91.  KbdCtrl          DB ?
  92.  KbdReadPort      DW ?
  93.  BiosKbdEnh       DB ?
  94.  ;Information sur le port parallèle
  95.  LPTExist         DB ? ; Boolean
  96.  NmLPT            DB ?
  97.  Get1LPT          DB ?
  98.  ;Information sur le port série
  99.  ComExist         DB ? ; Boolean
  100.  NmCom            DB ?
  101.  ;Information sur la mémoire conventionnel
  102.  MemTotalSize     DW ?
  103.  ;Information sur l'Expanded Memory Manager (EMS)
  104.  EmmExist         DB ? ; Boolean
  105.  EmmSeg           DW ?
  106.  EmmTotalSize     DW ?
  107.  ;Information sur l'eXtended Memory Manager (XMS)
  108.  XmmExist         DB ? ; Boolean
  109.  XmmCtrl          DD ? ; Pointer
  110.  XmsTotalSize     DW ?
  111.  ;Information sur la mémoire étendu géré par le Bios Int 15h
  112.  ExtBiosExist     DB ? ; Boolean
  113.  ExtBiosSizeK     DW ?
  114.  ;Information sur le CMOS
  115.  CtrlCmos         DB ?
  116.  CmosPort         DW ?
  117.  ;Information sur la souris
  118.  Mouse            DB ?
  119.  MouseVer         DW ?
  120.  MsButton         DW ?
  121.  ; Index de procédures ou fonctions à référence ressource RLL
  122.  indAltPress      DB ? ; AltPressed
  123.  indCtrlPress     DB ? ; CtrlPressed
  124.  indFillChr       DB ? ; FillByte/FillCharacter
  125.  indGetIntVec     DB ? ; GetInterruptVector
  126.  indGetRawTimer   DB ? ; GetRawTimer
  127.  indGetRawTimerB  DB ? ; GetRawTimerInByte
  128.  indJoyPos        DB ? ; JoystickPosition
  129.  indKeyPress      DB ? ; KeyPressed
  130.  indLShiftPress   DB ? ; LeftShiftPressed
  131.  indMove          DB ? ; Move/MoveLeft
  132.  indPushKey       DB ? ; PushKey
  133.  indReadKey       DB ? ; ReadKey
  134.  indRShiftPress   DB ? ; RightShiftPressed
  135.  indSetIntVec     DB ? ; SetInterruptVector
  136.  indShiftPress    DB ? ; ShiftPressed
  137. ENDS
  138.
  139. ; ***********************************************************************************************
  140. ; Détection de la présence des interruptions et de certains services de base ici ...
  141. ; ***********************************************************************************************
  142.
  143.    ;-----------------------------------------------------------------------------------------------------------------------------
  144.    ;--                         Détection du CMOS
  145.    ;--                (GetCmosPort/CtrlCmos/ExtBiosExist)
  146.    ;-----------------------------------------------------------------------------------------------------------------------------
  147.   MOV StartUp.StartUpRec.ExtBiosExist,No
  148.   MOV StartUp.StartUpRec.ExtBiosSizeK,0
  149.   TEST Jump.Jumper.FlgMethod,flgProtectedMode
  150.   JNZ nXTCmosTst
  151.   TEST StartUp.StartUpRec.IntExistFlags,flgInt15h
  152.   MOV AX,0FFFFh
  153.   MOV ES,AX
  154.   JZ  @@SetCmosPort ;
  155.   CMP Byte Ptr ES:[0Eh],253
  156.   JA  @@SetCmosPort
  157. nXTCmosTst:
  158.   XOR AX,AX
  159.   TEST Jump.Jumper.FlgMethod,flgNoExtBiosMemDetect
  160.   JNZ nExtInt15
  161.   MOV AH,88h
  162.   INT 15h
  163. nExtInt15:
  164.   OR  AX,AX
  165.   MOV CX,70h
  166.   MOV BL,ctrlCmosMC146818
  167.   JE  @@SetCmosPort ; Pas de Ext Bios Int 15h
  168.   MOV StartUp.StartUpRec.ExtBiosExist,Ya
  169.   MOV StartUp.StartUpRec.ExtBiosSizeK,AX
  170.   JMP @@DetectCmos
  171. @@SetCmosPort:
  172.   MOV AX,0FFFFh
  173.   MOV ES,AX
  174.   CMP Byte Ptr ES:[0Eh],252
  175.   JE  @@DetectCmos
  176.   TEST Jump.Jumper.FlgMethod,flgNoCmosDetect
  177.   JZ @@NoCmos
  178.   CMP Byte Ptr ES:[0Eh],255 ; PC ?
  179.   JE  @@NoCmos
  180.   CMP Byte Ptr ES:[0Eh],253 ; PC Junior ?
  181.   JE  @@NoCmos
  182.   MOV DX,02C0h
  183.   IN  AL,DX
  184.   TEST AL,0Fh
  185.   JNZ @TooBad
  186.   MOV DX,2CBh
  187.   IN  AL,DX
  188.   CMP AL,0DEh
  189.   JE  @CmosB
  190.   MOV AL,0DEh
  191.   OUT DX,AL
  192.   IN  AL,DX
  193.   CMP AL,0DEh
  194.   JE  @CmosB
  195. @TooBad:
  196.   XOR AL,AL
  197.   OUT DX,AL
  198.   INC DX
  199.   IN  AL,DX
  200.   DEC DX
  201.   TEST AL,0Fh
  202.   JNZ @TriBad
  203.   MOV AL,0Bh
  204.   OUT DX,AL
  205.   INC DX
  206.   IN  AL,DX
  207.   CMP AL,0DEh
  208.   JE  @CmosC
  209.   MOV AL,0DEh
  210.   OUT DX,AL
  211.   IN  AL,DX
  212.   CMP AL,0DEh
  213.   JE  @CmosC
  214. @TriBad:
  215.   XOR AL,AL
  216.   OUT DX,AL
  217.   MOV AL,80h
  218.   OUT DX,AL
  219.   MOV BL,0Eh
  220.   INC DX
  221.   MOV AL,BL
  222.   OUT DX,AL
  223.   DEC DX
  224.   MOV AL,88h
  225.   OUT DX,AL
  226.   MOV AL,98h
  227.   OUT DX,AL
  228.   MOV AL,88h
  229.   OUT DX,AL
  230.   MOV AL,80h
  231.   OUT DX,AL
  232.   MOV AL,0A0h
  233.   OUT DX,AL
  234.   INC DX
  235.   MOV CX,100h
  236. @LoopA:
  237.   IN  AL,DX
  238.   TEST AL,1
  239.   LOOPZ @LoopA
  240.   JZ  @NoCmosXT
  241.   MOV CX,100h
  242. @LoopB:
  243.   IN  AL,DX
  244.   TEST AL,1
  245.   LOOPNZ @LoopB
  246.   JZ @CmosA
  247. @NoCmosXT:
  248.   MOV DX,2C0h
  249.   XOR AL,AL
  250.   OUT DX,AL
  251.   ; XT, difficile à dire si un CMOS existe... Wyse, Commodore,...
  252.   ; mais si oui: le Port est E0h pour les ordinateurs Wyses XT
  253.   MOV CX,0E0h
  254.   MOV BL,ctrlCmosUnknown
  255.   JMP nCmosXT
  256. @CmosA:
  257.   MOV BL,ctrlCmosRTC58321 ; RTC-58321, 2C0h-2C1h
  258.   JMP @SetCmosXTPort
  259. @CmosB:
  260.   MOV BL,ctrlCmosMM58167a ; MM58167, 2C0h-2DFh
  261.   JMP @SetCmosXTPort
  262. @CmosC:
  263.   MOV BL,ctrlCmosMM58167b ; MM58167, 2C0h-2C7h
  264. @SetCmosXTPort:
  265.   MOV CX,02C0h
  266. nCmosXT:
  267.   JMP @@DetectCmos
  268. @@NoCmos:
  269.   XOR CX,CX ; Je fixe le port à 0, mais il faudrait
  270.             ; surtout pas essayez pour voir...
  271.   MOV BL,ctrlCmosNo
  272. @@DetectCmos:
  273. ;  LES DI,StartUp
  274.   MOV StartUp.StartUpRec.CmosPort,CX
  275.   MOV StartUp.StartUpRec.CtrlCmos,BL
  276.
  277.
  278. ; ***********************************************************************************************
  279. ; Suite des routines détections du démarrage ici...
  280. ; ***********************************************************************************************

Voir également

Basic Pro: Fonction CMOS
Basic Pro: Fonction CMOSEXIST
Basic Pro: Fonction CMOSPORT

Dernière mise à jour : Vendredi, le 4 mars 2016


Introduction

Un des meilleurs environnement graphique multitâche a avoir été inventé pour PC, fut sans nulle doute DESQview. Ce logiciel relativement petit permettait de faire fonctionner des programmes avec des capacités redoubler de possibilité, dont celle d'effectuer la détection de son installation comme le montre le code suivant :

  1. ChkDESQview Macro
  2.  MOV AX,0DE00h
  3.  INT 2Fh
  4. EndM

Cette macro retourne si l'installation est confirmé AL=FFh ou toutes autres valeurs dans le cas où le résultat serait faut.

Voir également

Logiciel - DESQview - Présentation du logiciel

Dernière mise à jour : Vendredi, le 4 mars 2016


Introduction

Contrairement aux cartes vidéos, les cartes de son ne sont pas le fruit d'un standard proposé par IBM pour sa gamme des PC. Ainsi, se sont des fabricants indépendant ayant proposer des cartes de son et que seul des logiciels spécialisé était capable d'en exploiter les possibilités.

Organigramme de détection de la carte vidéo AdLib

Bien qu'il existait cette possibilité sous les ordinateurs Amiga et Atari de l'époque, la carte de son AdLib est la première carte de son proposé pour un ordinateur de la gamme PC d'IBM. Laquelle, remplaçait l'utilisation d'un PC Speaker Mono par une sortie stéréo de bien meilleure qualité. Cette carte de son est né de l'idée d'un professeur de musique, Martin Prevel, de l'université Laval, dans la ville de Québec et le nom de la carte de son était «AdLib Music Synthesizer Card». Puisqu'il n'y avait pas de BIOS de fournit avec la carte ISA 8 bits, il fallait détecté directement à partir des ports d'entrée/sorties 388h/389h la présence de la carte de son, sinon on pouvait utiliser un pilote chargé lors du démarrage du système d'exploitation.

Dernière mise à jour : Vendredi, le 4 mars 2016


Introduction

La détection des cartes vidéos est un processus complexe provoquer, d'une part, par l'évolution du matériel proposé par la gamme PC d'IBM et d'autres part les choix des manufacturiers parfois difficile à cerner. Dans les faits, on tente d'abord de détecter le matériel le plus récent jusqu'au matériel le plus ancien. Ce phénomène n'est pas sans difficulté, car dans certaines situations, on peut être obligé d'effectuer un redémarrage à froid pour compléter la détection. Ainsi, la plupart des systèmes d'exploitation choisis d'effectuer une détection en plusieurs redémarrage pour éviter les ennuis, tandis que les applications démarrant sans système d'exploitation se centreront uniquement sur le standard VESA.

Organigramme de détection de la carte vidéo Tseng Labs

Les cartes vidéos de la famille des Tseng Labs sont arrivés avant que le standard VESA soit développés, il fallait donc, une fois que la détection classique de VGA est été effectué, faire des appels directement au port d'entrée/sortie de la carte vidéo afin de vérifier que le comportement lui étant propre est été détecté. Ainsi, il fallait utiliser 3B4h/3B5h et 3CCh/3CDh pour connaitre la réponse.

Organigramme de détection de la carte vidéo Video 7

Les cartes vidéos de la famille des Video 7 sont arrivés permettent d'être uniquement avec des valeurs de retour du port 3C4h/3C5h. Cependant, certains sous-modèle doivent être détecter à l'aide de l'interruption 10h, Fonction 6Fh, Sous-Fonction 07h.

Organigramme de détection de la carte vidéo XGA

La détection de la carte vidéo XGA est une combinaison de test au niveau du BIOS (Interruption 10h, Fonction CFh, Sous-fonction 00h) et de l'électronique, car de nombreuses cartes Super VGA tentent de se faire passer pour des cartes vidéo XGA au niveau BIOS, mais pas au niveau de l'électronique.

Organigramme de détection de la carte vidéo compatible avec le standard VESA

Le standard VESA est un standard destiné au fournit une solution universel de gestion de la RAM des cartes vidéo Super VGA. La première carte vidéo Super VGA ne supportait par le standard VESA à partir du BIOS, il fallait donc charger un programme résident (TSR) afin de fournir le même service que le BIOS fournissait. Par la suite, au environ de 1994, toutes les cartes vidéo, fournissait inclut dans la ROM du BIOS de la carte vidéo situé à l'adresse C000h:0000h les services nécessaire au standard VESA. Dans tous les cas, il faut utiliser l'interruption 10h, fonction 4F00h pour détecter la présence du standard VESA.

Dernière mise à jour : Vendredi, le 4 mars 2016


Les directives conditionnelles

Voir les directives conditionnels utilisés par les compilateurs tel Macro Assembler de Microsoft (MASM) ou Turbo Assembler de Borland (TASM):

Directive | Syntaxe | Description | Mode
.186 | .186 | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 80186. | MASM
.286 | .286 | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 80286 en mode réel sans privilège et les instructions du coprocesseur mathématique 80287. | MASM
.286C | .286C | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 80286 en mode réel sans privilège et les instructions du coprocesseur mathématique 80287. | MASM
.286P | .286P | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 80286 incluant le mode protégé et les instructions du coprocesseur mathématique 80287. | MASM
.287 | .287 | Cette directive permet d'activer l'assemblage des instructions du coprocesseur mathématique 80287. | MASM
.386 | .386 | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 80386 en mode réel sans privilège et les instructions du coprocesseur mathématique 80387. | MASM
.386C | .386C | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 80386 en mode réel sans privilège et les instructions du coprocesseur mathématique 80387. | MASM
.386P | .386P | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 80386 incluant le mode protégé et les instructions du coprocesseur mathématique 80387. | MASM
.387 | .387 | Cette directive permet d'activer l'assemblage des instructions du coprocesseur mathématique 80387. | MASM
.486 | .486 | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 80486 en mode réel sans privilège. | MASM
.486C | .486C | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 80486 en mode réel sans privilège. | MASM
.486P | .486P | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 80486 incluant le mode protégé. | MASM
.487 | .487 | Cette directive permet d'activer l'assemblage des instructions du coprocesseur mathématique 80487. | MASM
.8086 | .8086 | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 8086 seulement. C'est le mode par défaut des modes d'instructions de Turbo Assembler. | MASM
.8087 | .8087 | Cette directive permet d'activer l'assemblage des instructions du coprocesseur mathématique 8087 seulement. C'est le mode par défaut des modes d'instructions de Turbo Assembler. | MASM
: :nom Cette directive permet d'appeler un étiquette du nom spécifié. MASM et IDEAL
= nom=expression Cette directive permet de définir ou redéfinir une équation numérique. MASM et IDEAL
ALIGN | ALIGN limite | Cette directive permet d'arrondir un compteur d'emplacement à la limite d'une puissance 2 d'adressage (2, 4, 8,...). | MASM et IDEAL
.ALPHA | .ALPHA | Cette directive permet de fixer l'ordre de segment alphanumérique. La ligne de commande avec le paramètre «/a» effectue la même fonctionnalité. | MASM
ARG ARG argument[,argument]...[symbol]
[RETURNS argument[,argument]] 		Cette directive permet de fixer les arguments de la pile d'une procédure. Chaque argument est fixé à un déplacement positif dans le registre BP en supposant que l'adresse de retour d'une procédure d'appel et de l'appeleur avec BP est empilé la pile correctement. MASM et IDEAL
ASSUME ASSUME argument:nom[,segmentreg:nom]...
ASSUME segmentreg:NOTHING
ASSUME NOTHING 		Cette directive permet de fixer les arguments de la pile d'une procédure. Chaque argument est fixé à un déplacement positif dans le registre BP en supposant que l'adresse de retour d'une procédure d'appel et de l'appeleur avec BP est empilé la pile correctement. MASM et IDEAL
%BIN | %BIN taille | Cette directive permet de fixer la taille de la colonne spécifié d'un champ d'objet de code dans la liste de fichier. | MASM et IDEAL
CALL CALL instanceptrMETHOD{nomobjet:}
nommethode{USES{segreg}:offreg}
{appelparametreetendu}} 		Cette directive permet d'appeler une procédure avec la méthode de procédure spécifié. MASM et IDEAL
CATSTR | nom CATSTR chaine[,chaine] | Cette directive permet d'effectuer une concaténation de chaine de caractères sous la forme d'une simple chaine de caractères du nom spécifié. | MASM et IDEAL
.CODE | .CODE | Cette directive permet d'indiquer un segment de code | MASM
.CODE | .CODE nom | Cette directive permet d'indiquer le début d'un segment de code quand il est utilisé avec la directive .MODEL. | MASM et IDEAL
.CODESEG | .CODESEG nom | Cette directive permet d'indiquer le début d'un segment de code quand il est utilisé avec la directive .MODEL. | MASM et IDEAL
COMM COMM definition[,definition] Cette directive permet de définir des variables communes. Chaque définition permet de décrire un symbole selon le format suivant:
[distance][langage]nomsymbole[[compteur]]:type[:compteur2]
La distance est NEAR ou FAR et la taille par défaut est celle du modèle mémoire de données. Le langage peut être C, PASCAL, BASIC, FORTRAN, PROLOG ou NOLANGUAGE. Le nomsymbole permet d'indiquer le symbole communs. Le type peut-être BYTE, WORD, DATAPTR, CODEPTR, DWORD, FWORD, PWORD, PWORD, QWORD ou TBYTE ou une structure de nom. 		MASM et IDEAL
COMMENT COMMENT delimiteur [texte]
[texte]
delimiteur [texte] 		Cette directive permet d'indiquer un commentaire ou une remarque utilisant plusieurs lignes. Le délimiteur est le premier caractère n'étant pas un espace suivant COMMENT. MASM
%COND | %COND | Cette directive permet d'indiquer toutes les instructions d'un bloc conditionnel contenu dans une liste. C'est le mode par défaut du Turbo Assembler. | MASM et IDEAL
.CONST | .CONST | Cette directive permet d'indiquer des constantes. | MASM
CONST | CONST | Cette directive permet d'indiquer le début d'un segment de données de constantes. | MASM et IDEAL
.CREF | .CREF | Cette directive permet d'indiquer des références croisés d'informations. | MASM
%CREF | %CREF | Cette directive permet d'indiquer des références croisés d'informations à accumulé dans tous les symboles d'un point suivant de fichier source .CREF. L'effet s'inverse avec n'importe quel directive %XCREF ou .XCREF des informations de collection. | MASM et IDEAL
%CREFALL | %CREFALL | Cette directive permet d'indiquer la cause des sous-séquences des symboles dans un fichier source d'une liste de référence-croisé. C'est le mode par défaut du Turbo Assembler. | MASM et IDEAL
%CREFREF | %CREFREF | Cette directive permet de désactiver la liste des symboles sans référence dans une référence croisé. | MASM et IDEAL
%CREFUREF | %CREFUREF | Cette directive permet de lister seulement les symboles sans référence dans une référence croisé. | MASM et IDEAL
%CTLS | %CTLS | Cette directive permet de provoqué un contrôle de liste (comme avec %LIST, %INCL,...) pour placé dans la liste de fichier. | MASM et IDEAL
.DATA | .DATA | Cette directive permet d'indiquer des données. | MASM
DATASEG | DATASEG | Cette directive permet d'indiquer le début de l'initialisation du segment de données dans le module. La première fois que vous utilisez la directive .MODEL indique le modèle de mémoire. Le segment de données peut appeler dans le groupe DGROUP, lequel contraint également le segment définit avec les directives .STACK, .CONST et .DATA. | IDEAL
.DATA? | .DATA? | Cette directive permet d'indiquer le début de l'initialisation du segment de données dans le module. La première fois que vous utilisez la directive .MODEL indique le modèle de mémoire. Le segment de données peut appeler dans le groupe DGROUP, lequel contraint également le segment définit avec les directives .STACK, .CONST et .DATA. | IDEAL
DB | [nom] DB expression[,expression]... | Cette directive permet d'indiquer une allocation et entreposage de données sous forme d'octets à cette emplacement. L'opérateur DUP peut être utilisé dans expression pour indiquer des données répétitives. | MASM et IDEAL
DD | [nom] DD expression[,expression]... | Cette directive permet d'indiquer une allocation et entreposage de données sous forme de double mot à cette emplacement. L'opérateur DUP peut être utilisé dans expression pour indiquer des données répétitives. | MASM et IDEAL
%DEPTH | %DEPTH largeur | Cette directive permet de fixer la taille de la profondeur d'un champ dans une liste de fichier avec une colonne de largeur spécifié. | MASM et IDEAL
DF | [nom] DF [type PTR] expression[,expression]... | Cette directive permet d'indiquer une allocation et entreposage de données sous forme de 6 octets (un pointeur long de 48 bits) à cette emplacement. Le type peut être BYTE, WORD, DATAPTR, CODEPTR, DWORD, FWORD, FWORD, PWORD, QWORD, TBYTE, SHORT, NEAR, NEAR, FAR ou un nom de structure. L'opérateur DUP peut être utilisé dans expression pour indiquer des données répétitives. | MASM et IDEAL
DISPLAY | DISPLAY "texte" | Cette directive permet de faire sortir le texte spécifié immédiatement à l'écran. | MASM et IDEAL
DOSSEG | DOSSEG | Cette directive permet d'activer l'ordre de segment DOS au temps de liaison. | MASM et IDEAL
DP | [nom] DP [type PTR] expression[,expression]... | Cette directive permet d'indiquer une allocation et entreposage de données sous forme de 6 octets (un pointeur long de 48 bits) à cette emplacement. Le type peut être BYTE, WORD, DATAPTR, CODEPTR, DWORD, FWORD, FWORD, PWORD, QWORD, TBYTE, SHORT, NEAR, NEAR, FAR ou un nom de structure. L'opérateur DUP peut être utilisé dans expression pour indiquer des données répétitives. | MASM et IDEAL
DQ | [nom] DQ expression[,expression]... | Cette directive permet d'indiquer une allocation et entreposage de données sous forme de quadruple mot à cette emplacement. L'opérateur DUP peut être utilisé dans expression pour indiquer des données répétitives. | MASM et IDEAL
DT | [nom] DT expression[,expression]... | Cette directive permet d'indiquer une allocation et entreposage de données sous forme de 10 octets (80 bits) à cette emplacement. L'opérateur DUP peut être utilisé dans expression pour indiquer des données répétitives. | MASM et IDEAL
DW | [nom] DW expression[,expression]... | Cette directive permet d'indiquer une allocation et entreposage de données sous forme d'un mot à cette emplacement. L'opérateur DUP peut être utilisé dans expression pour indiquer des données répétitives. | MASM et IDEAL
ELSE IF condition
instruction1
[ELSE
instruction2]
ENDIF 		Cette directive permet d'indiquer que si la condition est fausse les instructions instructions2 sont assemblés et seront inclus dans l'exécutable potentiel. MASM et IDEAL
ELSEIF IF condition1
instruction1
[ELSEIF condition2
instruction2]
ENDIF 		Cette directive permet d'indiquer que si la condition condition1 est fausse et que la condition condition2 est vrai, les instructions instructions2 sont assemblés et seront inclus dans l'exécutable potentiel. D'autres formes sont également supportées: ELSEIF1, ELSEIF2, ELSEIFB, ELSEIFDEF, ELSEIFDIF, ELSEIFDEFI, ELSEIFDEFE, ELSEIFDN, ELSEIFIDNI, ELSEIFNB et ELSEIFNDEF. MASM et IDEAL
EMUL | EMUL | Cette directive permet d'indiquer que toutes les sous-séquences des instructions du coprocesseur mathématique génère une instructions d'émulations, comme si elles sont réellement existantes. | MASM et IDEAL
END | END [adressedebut] | Cette directive permet d'indiquer la marque de la fin du fichier source. L'adressedebut permet d'indiquer l'expression ou le symbole spécifié l'adresse où commence l'exécution du programme. Le Turbo Assembler ignore n'importe quel texte suivant cette directive. | MASM et IDEAL
ENDIF IF condition
instruction1

ENDIF 		Cette directive permet d'indiquer la fin d'une condition SI ... ALORS d'une des directives conditions IFxxx. MASM et IDEAL
ENDM | ENDM | Cette directive permet d'indiquer la fin d'un bloc de répétition ou d'une définition de macro. | MASM et IDEAL
ENDP ENDP [nomproc]
[nomproc] ENDP 		Cette directive permet d'indiquer la fin d'une procédure. Si le nom de procédure nomproc est fournit, il correspond au nom de la procédure avec la directive PROC au début de la procédure. MASM et IDEAL
ENDS ENDS [nomsegment | nomstructure]
[nomsegment | nomstructure] ENDS 		Cette directive permet d'indiquer la fin d'un segment, d'une structure ou d'une union. Si un nom optionnel est fournit, il doit correspondre une directive SEGMENT, STRUC ou UNION. MASM et IDEAL
ENUM ENUM nom[var_enum[,var_enum..]]
nom ENUM [var_enum[,var_enum..]] 		Cette directive permet d'effectuer la déclaration d'une énumération de type de données. MASM et IDEAL
EQU | nom EQU expression | Cette directive permet d'effectuer la déclaration d'une chaine de caractères, d'un alias ou d'une équation numérique contenant le résultat de l'évaluation de l'expression. | MASM et IDEAL
.ERR | .ERR chaine | Cette directive permet d'arrêter la compilation à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM
ERR | ERR chaine | Cette directive permet d'arrêter la compilation à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM et IDEAL
.ERR1 | .ERR1 chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur de premier passage à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM
.ERR2 | .ERR2 chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur de deuxième passage à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM
.ERRB | .ERRB argument chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur avec un argument vide à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM
.ERRDEF | .ERRDEF symbole chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si le symbole symbole est définit à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM
.ERRDIF | .ERRDIF argument1,argument2 chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si les arguments sont différents à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM
.ERRDIFI | .ERRDIFI argument1,argument2 chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si les arguments sont différents à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. La comparaison ne fait aucune distinction entre les majuscules et minuscules. | MASM
.ERRE | .ERRE expression chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si l'expression expression est fausse à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM
.ERRIDN | .ERRIDN argument1,argument2 chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si les arguments argument1 et argument2 sont identiques à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM
.ERRIDNI | .ERRIDNI argument1,argument2 chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si les arguments argument1 et argument2 sont identiques à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. La comparaison ne fait aucune distinction entre les majuscules et minuscules. | MASM
.ERRIF | .ERRIF expression chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si l'expression expression est vrai à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM et IDEAL
.ERRIF1 | .ERRIF1 chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si s'est le premier passage de compilation à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM et IDEAL
.ERRIF2 | .ERRIF2 chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si s'est le deuxième passage de compilation à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM et IDEAL
.ERRIFB | .ERRIFB argument chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur avec un argument vide à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM et IDEAL
.ERRIFDEF | .ERRIFDEF symbole chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si le symbole symbole est définit à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM et IDEAL
.ERRIFDIF | .ERRIFDIF argument1,argument2 chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si les arguments sont différents à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM et IDEAL
.ERRIFDIFI | .ERRIFDIFI argument1,argument2 chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si les arguments sont différents à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. La comparaison ne fait aucune distinction entre les majuscules et minuscules. | MASM et IDEAL
.ERRIFE | .ERRIFE expression chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si l'expression expression est fausse à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM et IDEAL
.ERRIFIDN | .ERRIFIDN argument1,argument2 chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si les arguments argument1 et argument2 sont identiques à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM et IDEAL
.ERRIFIDNI | .ERRIFIDNI argument1,argument2 chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si les arguments argument1 et argument2 sont identiques à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. La comparaison ne fait aucune distinction entre les majuscules et minuscules. | MASM et IDEAL
.ERRIFNB | .ERRIFNB argument chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si l'argument n'est pas vide à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM et IDEAL
.ERRIFNDEF | .ERRIFNDEF symbole chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si le symbole symbole n'est pas définit à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM et IDEAL
.ERRNB | .ERRNB argument chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si l'argument n'est pas vide à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM
.ERRNDEF | .ERRNDEF symbole chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si le symbole symbole n'est pas définit à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM
.ERRNZ | .ERRNZ expression chaine | Cette directive permet d'arrêter la compilation avec un message d'erreur si l'expression expression ne vaut pas 0 à la ligne où est situé cette directive et d'afficher le message d'erreur optionnel spécifié par chaine. | MASM
EVEN | EVEN | Cette directive permet d'arrondir au compteur d'emplacement de la prochaine même adresse. | MASM et IDEAL
EVENDATA | EVENDATA | Cette directive permet d'arrondir au compteur d'emplacement de la prochaine même adresse dans le segment de données. | MASM et IDEAL
.EXIT | .EXIT [expressionvaleurretour] | Cette directive permet de terminer la compilation immédiatement en envoyer un code de retour optionnel au système d'exploitation. Alias de la directive EXITCODE. | MASM
EXITCODE | EXITCODE [expressionvaleurretour] | Cette directive permet de terminer la compilation immédiatement en envoyer un code de retour optionnel au système d'exploitation. Alias de la directive .EXIT. | MASM et IDEAL
EXITM | EXITM | Cette directive permet de terminer la définition d'une macro ou d'un extension de bloc de répétition et retourne le contrôle à la prochaine instruction suivante la macro ou l'appel bloc de répétition. | MASM et IDEAL
EXTRN EXTRN defintion[,definition]... Cette directive permet d'indiquer un symbole étant définit dans un autre module. La description de la définition definition d'un symbole doit avoir le format suivant:
[langage] nom[compteur1]:type[:compteur2]
Le langage langage peut avoir la convention de nommage suivantes: C, PASCAL, BASIC, FORTRAN, ASSEMBLER ou PROLOG. Le type type peut être les suivants: NEAR, FAR, PROC, BYTE, WORD, DWORD, DATAPTR, CODEPTR, FWORD, PWORD, PWORD, QWORD, TBYTE, ABS ou une structure de nom de fichiers. 		MASM et IDEAL
.FARDATA | .FARDATA [nomsegment] | Cette directive permet de définir le début d'un long segment de données a initialiser. | MASM
FARDATA | FARDATA [nomsegment] | Cette directive permet de définir le début d'un long segment de données a initialiser. | MASM et IDEAL
.FARDATA? | .FARDATA? [nomsegment] | Cette directive permet de définir le début d'un long segment de données non initialisé. | MASM
FASTIMUL | FASTIMUL reg_dest,source_r/m,valeur | Cette directive permet de générer du code multipliant le registre sources ou l'adresse mémoire par une valeur, et met le résultat dans le registre de destination. | MASM et IDEAL
FLIPFLAG | flagreg FLIPFLAG flagreg | Cette directive est une forme d'optimisation du complément des bits XOR avec une instruction courte. | MASM et IDEAL
GETFIELD | GETFIELD nomchamp reg_destination, source_rm | Cette directive est un générateur de code demander la valeur d'un champ trouvé dans la même source de registre ou mémoire, et fixe la destination avec cette valeur. | MASM et IDEAL
GLOBAL GLOBAL defintion[,definition]... Cette directive permet d'indiquer des définitions de portée global, soit une combinaison de «EXTRN» et «PUBLIC». La description de la définition definition d'un symbole doit avoir le format suivant:
[langage] nom[compteur1]:type[:compteur2]
Le langage langage peut avoir la convention de nommage suivantes: C, PASCAL, BASIC, FORTRAN, ASSEMBLER ou PROLOG. Le type type peut être les suivants: NEAR, FAR, PROC, BYTE, WORD, DWORD, DATAPTR, CODEPTR, FWORD, PWORD, PWORD, QWORD, TBYTE, ABS ou une structure de nom de fichiers. 		MASM et IDEAL
GOTO | GOTO symbole_balise | Cette directive permet de compléter n'importe quel bloc conditionnel pour indiquer un branchement. | MASM et IDEAL
GROUP GROUP nomgroupe nomsegment[,nomsegment]...
nomgroupe GROUP nomsegment[,nomsegment]... 		Cette directive permet d'associer un nom de groupe avec un plusieurs segment de code. MASM et IDEAL
IDEAL | IDEAL | Cette directive permet d'entrer l'assembleur en mode «IDEAL». | MASM et IDEAL
IF IF expression
instructionsivrai
[ELSE
instructionsifaux]
ENDIF
 Cette directive permet de définir un bloc conditionnel assemblant le code instructionsivrai si l'expression est vrai sinon il assemblera instructionsifaux si cette partie est définit. MASM et IDEAL
IF1 IF1
instructionsivrai
[ELSE
instructionsifaux]
ENDIF
 Cette directive permet de définir un bloc conditionnel assemblant le code instructionsivrai s'il s'agit du premier passage de compilation sinon il assemblera instructionsifaux si cette partie est définit. MASM et IDEAL
IF2 IF2
instructionsivrai
[ELSE
instructionsifaux]
ENDIF
 Cette directive permet de définir un bloc conditionnel assemblant le code instructionsivrai s'il s'agit du deuxième passage de compilation sinon il assemblera instructionsifaux si cette partie est définit. MASM et IDEAL
IFB IFB argument
instructionsivrai
[ELSE
instructionsifaux]
ENDIF
 Cette directive permet de définir un bloc conditionnel assemblant le code instructionsivrai si l'argument est vide sinon il assemblera instructionsifaux si cette partie est définit. MASM et IDEAL
IFDEF IFDEF symbole
instructionsivrai
[ELSE
instructionsifaux]
ENDIF
 Cette directive permet de définir un bloc conditionnel assemblant le code instructionsivrai si le symbole est définit sinon il assemblera instructionsifaux si cette partie est définit. MASM et IDEAL
IFDIF IFDIF argument1,argument2
instructionsivrai
[ELSE
instructionsifaux]
ENDIF
 Cette directive permet de définir un bloc conditionnel assemblant le code instructionsivrai si les arguments argument1 et argument2 sont différents sinon il assemblera instructionsifaux si cette partie est définit. MASM et IDEAL
IFDIFI IFDIFI argument1,argument2
instructionsivrai
[ELSE
instructionsifaux]
ENDIF
 Cette directive permet de définir un bloc conditionnel assemblant le code instructionsivrai si les arguments argument1 et argument2 sont différents sinon il assemblera instructionsifaux si cette partie est définit. La comparaison ne fait aucune distinction entre les majuscules et minuscules. MASM et IDEAL
IFE IFE expression
instructionsivrai
[ELSE
instructionsifaux]
ENDIF
 Cette directive permet de définir un bloc conditionnel assemblant le code instructionsivrai si l'expression est fausse sinon il assemblera instructionsifaux si cette partie est définit. MASM et IDEAL
IFIDN IFIDN argument1,argument2
instructionsivrai
[ELSE
instructionsifaux]
ENDIF
 Cette directive permet de définir un bloc conditionnel assemblant le code instructionsivrai si les arguments argument1 et argument2 sont identiques sinon il assemblera instructionsifaux si cette partie est définit. MASM et IDEAL
IFIDNI IFIDNI argument1,argument2
instructionsivrai
[ELSE
instructionsifaux]
ENDIF
 Cette directive permet de définir un bloc conditionnel assemblant le code instructionsivrai si les arguments argument1 et argument2 sont identiques sinon il assemblera instructionsifaux si cette partie est définit. La comparaison ne fait aucune distinction entre les majuscules et minuscules. MASM et IDEAL
IFNB IFNB argument
instructionsivrai
[ELSE
instructionsifaux]
ENDIF
 Cette directive permet de définir un bloc conditionnel assemblant le code instructionsivrai si l'argument n'est pas vide sinon il assemblera instructionsifaux si cette partie est définit. MASM et IDEAL
IFNDEF IFNDEF symbole
instructionsivrai
[ELSE
instructionsifaux]
ENDIF
 Cette directive permet de définir un bloc conditionnel assemblant le code instructionsivrai si le symbole n'est pas définit sinon il assemblera instructionsifaux si cette partie est définit. MASM et IDEAL
%INCL | %INCL | Cette directive permet d'activer l'inclusion des fichiers. C'est le mode par défaut du mode de liste de la directive «INCLUDE» | MASM et IDEAL
INCLUDE | INCLUDE nomfichier | Cette directive permet d'indiquer un fichier de code source à inclure à la position courante du module à assembler. S'il n'a pas d'extension, par défaut il utilise «.ASM». | MASM et IDEAL
INCLUDELIB | INCLUDELIB nomfichier | Cette directive permet d'indiquer un fichier de bibliothèque à inclure dans le module à assembler. S'il n'a pas d'extension, par défaut il utilise «.LIB». | MASM et IDEAL
INSTR | position INSTR [debut,]chaine1,chaine2 | Cette directive permet de demander la position de la seconde chaine dans la première et tenant compte que la recherche comme à la position spécifié par debut s'il est définit. | MASM et IDEAL
IRP IRP parametre,arg1[,arg2]...
instructions
ENDM 		Cette directive permet de définir une macro avec un bloc d'instruction répété par un chaine de caractères de substitution. MASM et IDEAL
IRPC IRPC parametre,chaine
instructions
ENDM 		Cette directive permet de définir une macro avec un bloc d'instruction répété par un caractère de substitution. MASM et IDEAL
JMP JMP ptr_instance METHOD {nom_objet:}
nom_methode {USES{segreg:}offsreg} 		Cette directive permet d'effectuer un saut à une procédure mais en empilant les paramètres dans la pile comme une instruction «CALL». Cette macro est destiné au développement de routine récursive. MASM et IDEAL
JUMPS | JUMPS | Cette directive permet d'ajuster les instructions de saut (JMP, JB, JE, JG,... ) automatiquement pour un saut court, proche ou long en fonction du contexte du code source. | MASM et IDEAL
LABEL nom LABEL type
LABEL nom type 		Cette directive permet de définir un symbole de type spécifié. Le paramètre nom permet d'indiquer le nom du symbole. Le paramètre type permet d'indiquer l'un des types suivantes : NEAR, FAR, PROC, BYTE, WORD, DATAPTR, WORD, DATAPTR, CODEPTR, DWORD, FWORD, PWORD, QWORD, TBYTE ou un nom de structure. MASM et IDEAL
.LALL | .LALL | Cette directive permet d'activer une liste dans une macro étendue. | MASM
LARGESTACK | LARGESTACK | Cette directive permet d'indiquer que la taille de la pile est en 32 bits. | MASM et IDEAL
.LFCOND | .LFCOND | Cette directive permet d'afficher toutes les instructions dans un bloc condtionnel d'une liste. | MASM
%LINUM | %LINUM taille | Cette directive permet de fixer la largueur d'un champ de numérotation de ligne dans une liste d'un fichier avec des colonnes de taille indiquer par le paramètre taille. La valeur par défaut est de 4 colonnes. | MASM et IDEAL
%LIST | %LIST | Cette directive permet d'afficher les lignes de sources d'une liste. C'est la valeur par défaut du mode de liste. | MASM et IDEAL
.LIST | .LIST | Cette directive permet d'afficher les lignes de sources d'une liste. C'est la valeur par défaut du mode de liste. | MASM
LOCAL LOCAL symbole[,symbole]...
LOCAL element[,element]=[=symbole] 		Cette directive permet de définir les variables locales pour des macros ou procédures. Quand une macro à une définition, LOCAL définit temporairement les noms de symboles étant remplacer par un nouveau nom de symbole unique à chaque fois que la macro est étendue. LOCAL peut apparaitre avant n'importe quel autres instructions dans la définition d'une macro. Quand c'est une procédure, LOCAL définit le nom d'accès dans l'emplacement de la pile, lequel en un positionnement relatif négatif calculer à l'aide du registre BP. Si la fin de la liste de paramètres contient un signe d'égalité (=) et un symbole, le symbole doit être égale à la taille total d'un bloc de symboles local en octets. Chaque element a la syntaxe suivante : «nomsymbole [[compteur1]] [:taille_deboguage] [:type] [:compteur2]». Le paramètre type permet d'indiquer le type de données d'un paramètre, lequel peut-être BYTE, WORD, DATAPTR, CODEPTR, DWORD, FWORD, PWORD, QWORD, TBYTE, NEAR, FAR, PROC ou un nom de structure. Si le type n'est pas définit, la taille WORD est utilisé par défaut. Le paramètre compteur2 permet d'indiquer combien d'items de type de symboles sont définit. La valeur par défaut pour compteur2 est 1. Le paramètre compteur1 permet d'indiquer le nombre d'élément d'un tableau. L'espace total alloué par le symbole est est le nombre de fois compteur2 que la longueur spécifié est de type champ fois compteur1. Si le paramètre compteur1 n'est pas spécifié, sa valeur par défaut est 1. Le paramètre optionnel taille_deboguage à la syntaxe suivante : «[type] PTR». MASM et IDEAL
LOCALS | LOCALS prefixe | Cette directive permet d'activer un symbole local, les noms noms doivent débuter par deux arobas (@@) ou deux caractères de préfix spécifié par le paramètre prefixe si spécifié. Les symboles locales sont automatiquement activé en mode Ideal. | MASM et IDEAL
MACRO MACRO nom parametre[,parametre]...
nom MACRO parametre[,parametre]... 		Cette directive permet de définir une macro pouvant être étendue après que le paramètre nom est rencontré. Le paramètre parametre est placé dans le corps de la macro afin d'indiquer une substitution d'un des arguments actuels de la macro appelé. MASM et IDEAL
%MACS | %MACS | Cette directive permet d'activer une liste d'une macro étendue. | MASM et IDEAL
MASKFLAG | MASKFLAG destination,source | Cette directive permet d'optimiser la forme d'un instruction AND («ET BINAIRE») en affectant les bits avec l'instruction la plus courte possible. Utilisé seulement si le résultat contenu dans les registres de drapeaux n'est pas important. | MASM et IDEAL
MASM | MASM | Cette directive permet d'entrer en mode d'assemblage MASM. C'est le mode d'assemblage par défaut du Turbo Assembler. | MASM et IDEAL
MASM51 | MASM51 | Cette directive permet d'activer le mode étendue de l'assemblage du MASM version 5.1. | MASM et IDEAL
MODEL MODEL [modifieurmodele] modelememoire
[nommodule][,[modifieurlangage]
langage][,modifieurmodele] 		Cette directive permet de fixer le modèle de mémoire avec une segmentation simplifié. Le paramètre modifieurmodele permet d'indiquer le modèle de la pile : NEARSTACK ou FARSTACK. Le paramètre modelememoire permet d'indiquer un modèle de mémoire : TINY, SMALL, MEDIUM, COMPACT, LARGE, HUGE ou TCHUGE. Le paramètre nommodule est utilisé dans les modèles larges afin de déclarer le nom des segments de code. Le paramètre modifieurlangage permet d'indiquer la génération spécifique d'une entrée de procédure MSWindows et de code de sortie ou l'un des modificateurs de langage suivant : WINDOWS, ODDNEAR, ODDFAR ou NORMAL. Le paramètre langage permet d'indiquer comment le langage de programmation fait ses appels d'accès dans un module : C, PASCAL, BASIC, FORTRAN, PROLOG ou NOLANGUAGE. Le Turbo Assembler génère automatiquement l'entrée de procédure approprié et le code de sortie quand vous utilisez les directives PROC et ENDP. Les conventions de nommage qu'utilise le Turbo Assembler sont indiqués par le paramètre langage pour les symboles publiques ou externes et l'ordre des arguments de procédure empilé dans la pile lors de l'appel d'un module. Aussi, la forme approprié d'instruction RET est généré pour enlever les arguments de la pile avant de retourner au code l'appelant si nécessaire. MASM et IDEAL
.MODEL .MODEL [modifieurmodele] modelememoire
[nommodule][,[modifieurlangage]
langage][,modifieurmodele] 		Cette directive permet de fixer le modèle de mémoire avec une segmentation simplifié. Le paramètre modifieurmodele permet d'indiquer le modèle de la pile : NEARSTACK ou FARSTACK. Le paramètre modelememoire permet d'indiquer un modèle de mémoire : TINY, SMALL, MEDIUM, COMPACT, LARGE, HUGE ou TCHUGE. Le paramètre nommodule est utilisé dans les modèles larges afin de déclarer le nom des segments de code. Le paramètre modifieurlangage permet d'indiquer la génération spécifique d'une entrée de procédure MSWindows et de code de sortie ou l'un des modificateurs de langage suivant : WINDOWS, ODDNEAR, ODDFAR ou NORMAL. Le paramètre langage permet d'indiquer comment le langage de programmation fait ses appels d'accès dans un module : C, PASCAL, BASIC, FORTRAN, PROLOG ou NOLANGUAGE. Le Turbo Assembler génère automatiquement l'entrée de procédure approprié et le code de sortie quand vous utilisez les directives PROC et ENDP. Les conventions de nommage qu'utilise le Turbo Assembler sont indiqués par le paramètre langage pour les symboles publiques ou externes et l'ordre des arguments de procédure empilé dans la pile lors de l'appel d'un module. Aussi, la forme approprié d'instruction RET est généré pour enlever les arguments de la pile avant de retourner au code l'appelant si nécessaire. MASM
.MODEL TPASCAL | .MODEL TPASCAL | Ce paramètre de directive permet la configurant du modèle de mémoire simplifié pour écrire des procédures appelable du TURBO PASCAL. | IDEAL
MULTERRS | MULTERRS | Cette directive permet d'allouer de multiples erreurs a être rapporté dans une simple ligne de source. | MASM et IDEAL
NAME | NAME nommodule | Cette directive permet de fixer le nom d'un module de fichier d'objet. Cette directive n'a aucun effet en mode MASM; il fonctionne seulement en mode Ideal. | MASM et IDEAL
%NEWPAGE | %NEWPAGE | Cette directive permet d'indiquer une nouvelle page dans une liste de fichier. | MASM et IDEAL
%NOCONDS | %NOCONDS | Cette directive permet de désactiver le positionnement des instructions dans un bloc conditionnel d'une liste de fichiers. | MASM et IDEAL
%NOCREF | %NOCREF [symbole,...] | Cette directive permet de désactiver l'accumulation d'information de référence croisé d'une liste (CREF). Si vous fournissez un ou plusieurs symboles de noms, la référence croisé est seulement désactivé pour ces symboles. | MASM et IDEAL
%NOCTLS | %NOCTLS | Cette directive permet de désactiver le positionnement d'une directive de contrôle de liste dans une liste de fichier. C'est le mode par défaut du contrôle de liste du Turbo Assembler. | MASM et IDEAL
NOEMUL | NOEMUL | Cette directive permet de provoquer la génération des instructions réels de tous les sous-séquences d'instructions du coprocesseur mathématique plutôt que d'émuler les instructions. Quand votre programme est exécuté, vous devez disposer d'un coprocesseur mathématique 80x87 d'installé ou ces instructions ne s'exécuteront pas proprement. C'est la valeur par défaut mode d'assemblage des nombres réels (virgules flottante) du Turbo Assembler. | MASM et IDEAL
%NOINCL | %NOINCL | Cette directive permet de désactiver la liste des lignes sources des fichiers INCLUDE. | MASM et IDEAL
NOJUMPS | NOJUMPS | Cette directive permet de désactiver les arrangements de sauts conditionnels trop long activés par la directive JUMPS. C'est le mode par défaut du Turbo Assembler. | MASM et IDEAL
%NOLIST | %NOLIST | Cette directive permet de désactiver la sortie de la liste de fichier. | MASM et IDEAL
NOLOCALS | NOLOCALS | Cette directive permet de désactiver les symboles locales activé par la directive LOCALS. C'est la valeur par défaut du Turbo Assembler en mode MASM. | MASM et IDEAL
%NOMACS | %NOMACS | Cette directive permet de afficher seulement la liste des macros étendu que le code génère. C'est le mode de macro de liste par défaut du Turbo Assembler. | MASM et IDEAL
NOMASM51 | NOMASM51 | Cette directive permet de désactiver le mode étendue de l'assemblage du MASM version 5.1 de la directive MASM51. C'est le mode par défaut du Turbo Assemhler. | MASM et IDEAL
NOMULTERRS | NOMULTERRS | Cette directive permet d'allouer seulement les simples erreurs a être rapporté dans une ligne de source. C'est le mode par défaut du reportage d'erreur du Turbo Assembler. | MASM et IDEAL
NOSMART | NOSMART | Cette directive permet de désactiver l'optimisation du code que génère les différents code du MASM. | MASM et IDEAL
%NOSYMS | %NOSYMS | Cette directive permet de désactiver le positionnement d'une table symbole dans une liste de fichier. | MASM et IDEAL
%NOTRUNC | %NOTRUNC | Cette directive permet d'avertir lorsque des tronquages de champs dont le contenu est trop long pour la longueur du champ correspondant d'une liste de fichiers se produit. | MASM et IDEAL
NOWARN | NOWARN [classeattention] | Cette directive permet de désactiver les messages d'avertissements avec les identificateurs d'avertissement classeattention ou toutes les messages d'avertissement si le paramètre classeattention n'est pas spécifié. | MASM et IDEAL
ORG | ORG expression | Cette directive permet de fixer l'emplacement de départ ou le segment courant commence son adressage de code. | MASM et IDEAL
%OUT | %OUT texte | Cette directive permet d'afficher le texte spécifier à l'écran. | MASM
P186 | P186 | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 80186. | MASM et IDEAL
P286 | P286 | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 80286 en mode protégé et les instructions du coprocesseur mathématique 80287. | MASM et IDEAL
P286N | P286N | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 80286 en mode réel sans prévilège et les instructions du coprocesseur mathématique 80287. | MASM et IDEAL
P286P | P286P | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 80286 en mode protégé et les instructions du coprocesseur mathématique 80287. | MASM et IDEAL
P287 | P287 | Cette directive permet d'activer l'assemblage des instructions du coprocesseur mathématique 80287. | MASM et IDEAL
P386 | P386 | Cette directive permet d'activer l'assemblage des instructions de tous le microprocesseur 80386 (incluant le mode protégé) et les instructions du coprocesseur mathématique 80387. | MASM et IDEAL
P386N | P386N | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 80386 en mode réel sans privilège et les instructions du coprocesseur mathématique 80387. | MASM et IDEAL
P386P | P386P | Cette directive permet d'activer l'assemblage des instructions de tous le microprocesseur 80386 (incluant le mode protégé) et les instructions du coprocesseur mathématique 80387. | MASM et IDEAL
P387 | P387 | Cette directive permet d'activer l'assemblage des instructions du coprocesseur mathématique 80387. | MASM et IDEAL
P486 | P486 | Cette directive permet d'activer l'assemblage des instructions de tous le microprocesseur 80486 (incluant le mode protégé). | MASM et IDEAL
P486N | P486N | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 80486 en mode réel sans privilège. | MASM et IDEAL
P487 | P487 | Cette directive permet d'activer l'assemblage des instructions du coprocesseur mathématique 80487. | MASM et IDEAL
P8086 | P8086 | Cette directive permet d'activer l'assemblage des instructions du microprocesseur 8086 seulement. Cette directive est activé par défaut sur le Turbo Assembler. | MASM et IDEAL
P8087 | P8087 | Cette directive permet d'activer l'assemblage des instructions du coprocesseur mathématique 8087 seulement. Cette directive est le mode de coprocesseur par défaut sur le Turbo Assembler. | MASM et IDEAL
%PAGESIZE | PAGE [lignes] [,cols] %PAGESIZE [lignes] [,cols] | Cette directive permet de fixer la largeur et la hauteur de page de la liste et du début des nouvelles pages. Le paramètre lignes permet d'indiquer le nombre de lignes apparaissant dans chacune des pages de liste (10 à 255). Le paramètre cols permet d'indiquer le nombre de colonnes qu'une page doit avoir (59 à 255). Quand le paramètre lignes ou cols est omis, la taille des ajustements courant reste inchangé. Si le paramètre PAGE est suivi d'un symbole plus (+), une nouvelle page commence, le numéro de la section est incrémenté, et le numéro de la page redémarre à 1. Lorsque le PAGE n'a pas de paramètre, la liste est forcé de résumé une nouvelle page, sans changé le numéro de section. | MASM et IDEAL
%PCNT | %PCNT largeur | Cette directive permet de fixer la largeur du champ segment:offset d'une colonne largeur d'une liste d'un fichier. La valeur par défaut est 4 pour un segment de 16 bits et 8 pour un segment de 32 bits. | MASM et IDEAL
PNO87 | PNO87 | Cette directive permet de prévenir de l'assemblage d'instruction du coprocesseur mathématique (réel ou en émulation). | MASM et IDEAL
%POPLCTL | %POPLCTL | Cette directive permet de réinitialiser le contrôle de liste dans le chemin précédent la directive %PUSHLCTL. | MASM et IDEAL
POPSTATE | POPSTATE | Cette directive permet de retourner le dernier état de la pile interne du Turbo Assembler. | MASM et IDEAL
PROC PROC [modificateurdelangage] [langage] nom [distance]
[USES items,] [arguments [,arguments]...]
[RETURNS argument [,argument]]
...
ENDP nom
 Cette directive permet de définir une procédure (sous-programme). MASM et IDEAL
PROCDESC PROCDESC nom [langage] [modificateurdelangage] [distance] [arguments]
nom PROCDESC [langage] [modificateurdelangage] [distance] [arguments] 		Cette directive permet de déclarer une prototype de procédure, lequel Turbo Assembler vérifie les types et le nombre de paramètres de la procédure appelante, les déclarations, le langage spécifié et la distance. Peut également utilisé PUBLIC et EXTRN avec les noms de procédures. MASM et IDEAL
PROCTYPE PROCTYPE nom [descriptionprocedure]
nom PROCTYPE [descriptionprocedure]
 Cette directive permet d'effectuer la déclaration d'un type de procédure. Le paramètre descriptionprocedure à la définition suivante «[modifierlangage] [langage] [distance] [argument[,argument]...]». Le paramètre argument a la définition suivante «[nomarg][[compteurexpression1]]:typecomplexe[:compteurexpression2]». La description d'une procédure ne crée pas le prototype de celui-ci. Peut-être utilisé à la place du spécifieur de langage de l'appelant, le type d'argument a vérifier durant la compilation. MASM et IDEAL
PUBLIC | PUBLIC [langage] symbole[,langage] symbole].... | Cette directive permet de rendre publique un/des symbole(s) pour des liaisons externe. | MASM et IDEAL
PUBLICDLL | PUBLICDLL [langage]symbole[,langage]symbole]... | Cette directive permet d'effectuer la déclaration de symbole accessible dans un point d'entrée de lien dynamique des autres modules. Le paramètre symbole (d'une directive PROC, d'une étiquette de programme, d'une données de nom de variable ou d'une constante numérique définit avec la directive EQU) rendre les autres programmes accessibles en dehors d'OS/2. Si le paramètre langage (C, PASCAL, BASIC, FORTRAN, PROLOG ou NOLANGUAGE) est spécifié, le paramètre symbole est de porté publique après que la convention de nommage est appliqué au langage spécifié. | MASM et IDEAL
PURGE | PURGE nommacro[,nommacro] | Cette directive permet de supprimer la définition de macro spécifié. | MASM et IDEAL
%PUSHLCTL | %PUSHLCTL | Cette directive permet de sauvegarder l'état courant de la liste contrôle dans une pile à 16 niveaux. | MASM et IDEAL
PUSHSTATE | PUSHSTATE | Cette directive permet de sauvegarder l'état d'opération dans une pile interne à 16 niveaux. | MASM et IDEAL
QUIRKS | QUIRKS | Cette directive permet d'effectuer l'assemblage de fichier source faisant usage de l'un des vrai bogues du MASM. | MASM et IDEAL
.RADIX | .RADIX basenumerique | Cette directive permet de fixer la base numérique d'une constante entière d'une expression à 2 (binaire), 8 (octal), 10 (décimal) ou 16 (hexadécimal). | MASM
RADIX | RADIX basenumerique | Cette directive permet de fixer la base numérique d'une constante entière d'une expression à 2 (binaire), 8 (octal), 10 (décimal) ou 16 (hexadécimal). | MASM et IDEAL
RECORD nom RECORD champ[,champ]...
RECORD nom champ[,champ]... 		Cette directive permet de définir une structure de données du nom du paramètre nom avec des champs de bit. Chaque champ contient une description d'un groupe de bits dans enregistrement et on le format suivant : «nomchamp:largeur[=expression]». Le paramètre nomchamp permet d'indiquer le nom du champ dans un enregistrement. Le paramètre largeur (valeur de 1 à 16) permet d'indiquer le nombre de bits d'un champ. Si le nombre total de bits dans tous les champs est 8 ou moins, l'enregistrement n'occupera qu'un octet; si le nombre de bits est entre 9 et 16 bits, il occupera 2 octets; autrement il occupera 4 octets. Le paramètre expression permet de fournir une valeur par défaut pour le champ. MASM et IDEAL
REPT REPT expression
instructions
ENDM 		Cette directive permet d'effectuer une répétition d'un bloc d'instructions le nombre de fois spécifié par le paramètre expression. MASM et IDEAL
RETCODE | RETCODE | Cette directive permet d'effectuer la génération d'un retour court (2 octets de déplacement) ou d'un retour long (4 octets de déplacement) dépendamment de la taille du modèle de mémoire déclaré dans la directive .MODEL. Si le modèle de mémoire est TINY, SMALL ou COMPACT, le résultat est un retour court (NEAR), si le modèle est MEDIUM, LARGE ou HUGE, le résultat est long (FAR). | MASM et IDEAL
RETF | RETF | Cette directive permet d'effectuer la génération d'un retour long (4 octets de déplacement) (FAR). | MASM et IDEAL
RETN | RETN | Cette directive permet d'effectuer la génération d'un retour court (2 octets de déplacement) (NEAR). | MASM et IDEAL
.SALL | .SALL | Cette directive permet de supprimer la liste de tous les instructions dans une macro étendue. | MASM
SEGMENT SEGMENT nom alignement [combine] [utilise] ['classe']
nom SEGMENT alignement [combine] [utilise] ['classe']
 Cette directive permet de définir un segment de nom du paramètre nom avec plein d'attribut secondaire. Si vous avez déjà un segment avec le même nom, ce segment est traité en continuité avec le précédent. Le paramètre alignement permet de spécifié le type de limite de mémoire où le segment doit commencé : BYTE, WORD, DWORD, PARA (par défaut) ou PAGE. Le paramètre combine permet de spécifié comment les segments de différents modules, mais avec les mêmes noms, sont combiné à chaque liaison : AT expression (emplacement de segment dans un paragraphe absolue d'une adresse d'expression), COMMON (emplacement de ce segment et des autres segments avec le même nom à la même adresse), MEMORY (concaténation de tous les segments avec le même nom de forme de continuité de segment simple) PRIVATE (ne combine pas ce segment avec n'importe quel autres segments; c'est la valeur par défaut si pas spécifié), PUBLIC (même que MEMORY), STACK (concaténation de tous les segments avec le même nom qu'un continuité de segment simple, alors initialisé avec le registre SS au début du segment et le registre SP pour la longueur du segment) ou VIRTUAL (définie un genre spécial de segment pouvant être traité dans une région commune et attaché à un autre segment à chaque liaison). Le paramètre utilise permet de spécifié le taille du mode par défaut pour un segment, si l'activation du code généré est pour un microprocesseur 80386, et peut être USE16 ou USE32. Le paramètre classe permet d'indiquer l'ordre de contrôle d'un segment de liaison, segments avec la même classe chargé dans le même ensemble de mémoire, quel que soit l'ordre dans lequel apparait le fichier source. MASM et IDEAL
.SEQ | .SEQ | Cette directive permet de fixer l'ordre de séquence d'un segment. C'est le mode d'ordre par défaut pour Turbo Assembler. Cette directive produit le même résultat que le paramètre en ligne de commande «/s». | MASM
SETFIELD | SETFIELD nomchamp destinationrm sourcereg | Cette directive permet d'effectuer la génération d'un ensemble de valeur dans un champ d'enregistrement. L'ensemble de champ dans l'adresse de registre ou de mémoire à le même contenu qu'une source de registre. | MASM et IDEAL
SETFLAG | SETFLAG destination,source | Cette directive permet d'optimiser la forme d'une instruction OR («OU BINAIRE») en affectant les bits avec l'instruction la plus courte possible. Utilisé seulement si le résultat contenu dans les registres de drapeaux n'est pas important. | MASM et IDEAL
.SFCONF | .SFCONF | Cette directive permet d'envoyer un avertissement lorsque des instructions avec des conditions de bloc de valeur fausse apparaisse dans la liste du fichier. | MASM
SIZESTR | nom SIZESTR nombrecaracteres | Cette directive permet de fixer le nombre de caractères indiquer par le paramètre nombrecaracteres que doit avoir une chaine de caractères du nom indiquer par le paramètre nom. | MASM et IDEAL
SMALLSTACK | SMALLSTACK | Cette directive permet d'indiquer que la taille de la pile est en 16 bits. | MASM et IDEAL
NOSMART | NOSMART | Cette directive permet d'activer l'optimisation du code que génère les différents code du MASM. | MASM et IDEAL
.STACK | .STACK [taille] | Cette directive permet de définir le début du segment de pile et d'allouer le nombre d'octets indiquer par le paramètre taille. Les 1024 octets sont alloué si le paramètre taille n'est pas spécifié. | MASM
STACK | STACK [taille] | Cette directive permet de définir le début du segment de pile et d'allouer le nombre d'octets indiquer par le paramètre taille. Les 1024 octets sont alloué si le paramètre taille n'est pas spécifié. | MASM et IDEAL
.STARTUP | .STARTUP | Cette directive permet de provoquer l'initialisation du code et marque le début du programme. Équivalent de la directive «STARTUPCODE». | MASM
STARTUPCODE | STARTUPCODE | Cette directive permet de provoquer l'initialisation du code et marque le début du programme. Équivalent de la directive «.STARTUP». | MASM et IDEAL
STRUC [nom] STRUC [modifieurs] [nomparent] [METHOD listemethode]
structuredonnees
ENDS nom
STRUC [nom] [modifieurs] [nomparent] [METHOD listemethode]
structuredonnees
ENDS nom
 Cette directive permet de définir une structure de données. Le paramètre nomparent permet d'indiquer le nom du bloc parent d'un objet de structure de données. Le paramètre listemethode est comme la directive TABLE. Le paramètre structuredonnees correspond à n'importe quel données contenu dans l'objet. Le modifieurs peut être GLOBAL, NEAR ou FAR. MASM et IDEAL
SUBSTR | nom SUBSTR chaine,position[,taille] | Cette directive permet de définir une nouvelle chaine de caractères constitué des caractères du paramètre chaine et débutant à la position du paramètre position et avec la longueur du paramètre taille. Tous les caractères du paramètre chaine, débutant à la position spécifié par le paramètre position, sont associés au paramètre nom si le paramètre taille n'est pas spécifié. | MASM51 et IDEAL
SUBTTL | SUBTTL texte | Cette directive permet de fixer les sous-titres d'une liste de fichier indiquer par le paramètre texte. | MASM
%SUBTTL | %SUBTTL texte | Cette directive permet de fixer les sous-titres d'une liste de fichier indiquer par le paramètre texte. | MASM et IDEAL
%SYMS | %SYMS | Cette directive permet d'activer le table de symbole situé dans la liste de fichier. C'est le symbole par défaut du mode de liste du Turbo Assembler. | MASM et IDEAL
TABLE | TABLE nom [table_membre[,table_membre...]] | Cette directive permet de construire une table de structure utilisable pour contenir les pointeurs de méthodes pour des objets. | MASM et IDEAL
%TABSIZE | %TABSIZE largeur | Cette directive permet de fixer le nombre de colonnes entres les tabulations dans liste de fichier de largeur indiqué par le paramètre largeur. La valeur de la colonne par défaut est 8. | MASM et IDEAL
TBLINIT | TBLINIT | Cette directive permet d'initialiser un pointeur d'objet dans une table de méthode virtuel. | MASM et IDEAL
TBLPTR | TBLPTR | Cette directive permet de placer un pointeur de table virtuel dans l'objet de données. La définition d'un membre de structure d'un nom est indiqué par «@Mptr_objet». Cette directive peut seulement être utilisé à l'intérieur de la définition d'objet. | MASM et IDEAL
TESTFLAG | TESTFLAG destination,source | Cette directive permet d'optimiser la forme d'une instruction TEST («ET BINAIRE» sans affectation des opérandes) en affectant les drapeaux avec l'instruction la plus courte possible. | MASM et IDEAL
%TEXT | %TEXT largeur | Cette directive permet de fixer le champ source d'une liste de fichier avec la largeur de colonne indiqué par le paramètre largeur. | MASM et IDEAL
.TFCOND | .TFCOND | Cette directive permet de faire bascule le mode de conditionnel de liste de bloc. | MASM
TITLE | TITLE texte | Cette directive permet de fixer le titre d'une liste de fichier avec le paramètre texte. | MASM
%TITLE | %TITLE texte | Cette directive permet de fixer le titre d'une liste de fichier avec le paramètre texte. | MASM et IDEAL
%TRUNC | %TRUNC | Cette directive permet d'effectuer le tronquage des champs d'une liste étant trop long. | MASM et IDEAL
TYPEDEF TYPEDEF nom_type type_complexe
nom_type TYPEDEF type_complexe
 Cette directive permet d'effectuer la définition de types nommés. MASM et IDEAL
UDATASEG | UDATASEG | Cette directive permet de définir le début d'un segment de données non-initialisé. | MASM et IDEAL
UFARDATA | UFARDATA | Cette directive permet de définir le début d'un long segment de données non-initialisé. | MASM et IDEAL
UNION UNION nom
champs
ENDS [nom]
nom UNION
champs
ENDS [nom]
 Cette directive permet de définir union avec le nom indiqué par le paramètre nom. Une union est comme la directive STRUC sauf que tous le mêmes déplacement, soit un offset à 0 au début de l'union. Le résultat de cette ensemble de champ est un recouvrement, allouant la référent à la région de mémoire définit par une union avec différent noms et différentes tailles de données. La longueur d'une union est la longueur du plus large de c'est membres et non pas la somme de tous la longueur de tous ses membres comme la directive STRUCT. Le paramètre champs permet de définir les champs compris dans l'union. Chaque champ utilise l'allocation de directive de données normal (DB, DW et les autres) pour définir leur taille. MASM et IDEAL
USES | USES item[,item]... | Cette directive permet d'indiquer quel registre ou simple jeton d'item de données sont empilés en premier dans la procédure quand la procédure les dépiles durant le retour de la procédure. Vous pouvez utilisé cette directive avant le début des instructions qu'il génère en code dans votre procédure. | MASM et IDEAL
VERSION | VERSION version_ID | Cette directive permet de placer le Turbo Assembler dans le mode d'opération d'équivalence de la version spécifié par le paramètre version_ID. | MASM et IDEAL
WARN | WARN classeattention | Cette directive permet d'activer le type de message d'avertissement spécifié avec le paramètre classeattention, ou tous les avertissements si le paramètre n'est pas spécifié. Le paramètre classeattention peut avoir une des valeurs suivantes : ALN, ASS, BRK, ICG, LCO, OPI, OPP, OPS, OVF, PDC, PRO, PQK, RES ou TPI. | MASM et IDEAL
WHILE WHILE tantqueexpression
corpsmacro
ENDM 		Cette directive permet d'effectuer une répétition du corps de la macro, indiqué par le paramètre corpsmacro, jusqu'à ce que la valeur du paramètre tantqueexpression égale 0 (ou faux). MASM et IDEAL
.XALL | .XALL | Cette directive permet d'indiquer que seul les macros étendue génère du code ou des données dans la liste. | MASM
.XCREF | .XCREF | Cette directive permet de désactiver l'accumulation d'information des références croisés (CREF) de liste. | MASM
.XLIST | .XLIST | Cette directive permet de désactiver les sous-séquences de sortie d'une liste de fichier. | MASM

Références

Turbo Assembler - Version 3.2: Quick Reference Guide, Edition Borland International, 1992, Part #11MN-BPL-10-70, BOR 4703, page 17 à 50.

Dernière mise à jour : Samedi, le 2 août 2014


Les opérateurs

Les opérateurs sont le fondement même du traitement des opérations mathématique et comparatif de n'importe quel langage, toutefois, le langage de programmation assembleur du 80x86 ne l'utilise pas de la même manière. Puisqu'il s'agit d'un langage de programmation de bas de niveau, les expressions mathématiques doivent retourner un résultat immédiat, donc il ne peut pas avoir aucune forme de variable incluse dans celle-ci, mais les constantes sont autorisées. De plus, certains compilateurs de bas gamme (autre que Macro Assembler de Microsoft (MASM) ou Turbo Assembler de Borland (TASM)) ne support carrément pas les opérateurs mathématiques.

Liste des opérateurs

Opérateur | Syntaxe | Description | Mode
( ) | (expression) | Cet opérateur marque une priorité d'opération dans l'évaluation | IDEAL et MASM
* | expression1 * expression2 | Cet opérateur permet d'effectuer la multiplication des expressions entières. Peut également être utilisé avec un mode d'adressage 80386 dans une expression avec un registre. | IDEAL et MASM
+ (binaire) | expression1 + expression2 | Cet opérateur permet d'effectuer une addition de deux expressions | IDEAL et MASM
+ (unaire) | + expression | Cet opérateur permet d'indiquer que l'expression est positive | IDEAL et MASM
- (binaire) | expression1 - expression2 | Cet opérateur permet d'effectuer une soustraction de deux expressions | IDEAL et MASM
- (unaire) | - expression | Cet opérateur permet d'indiquer que l'expression est négative | IDEAL et MASM
. | memptr.fieldname | Cet opérateur permet de sélectionner un membre (champ) de la structure (enregistrement) | IDEAL et MASM
/ | expression1 / expression2 | Cet opérateur permet d'effectuer une division entière de deux expressions. | IDEAL et MASM
: | segorgroup:expression | Cet opérateur permet d'effectuer une génération de segment ou d'un groupe «override». | IDEAL et MASM
? | Dx ? | Cet opérateur permet d'effectuer une initialisation avec une données indéterminé (où Dx peut être DB, DD, DF, DP ou DQ) | IDEAL et MASM
[ ] | expression1[expression2] | Cet opérateur peut être utilisé pour spécifier une opérande d'ajout ou de registre indirecte en mémoire | MASM
[ ] | [expression1][expression2] | Cet opérateur peut être utilisé pour spécifier une référence mémoire. | IDEAL
AND | expression1 AND expression2 | Cet opérateur permet d'effectuer un «Et binaire». | IDEAL et MASM
BYTE | BYTE expression | Cet opérateur permet de forcer l'adressage d'une expression avec un castre d'une taille d'un octet. | IDEAL
BYTE PTR | BYTE PTR expression | Cet opérateur permet de forcer l'adressage d'une expression avec un castre d'une taille d'un octet. | IDEAL et MASM
CODEPTR | CODEPTR expression | Cet opérateur permet de retourner la taille par défaut de l'adresse d'une procédure. | IDEAL et MASM
DATAPTR | DATAPTR expression | Cet opérateur permet de forcer l'expression avec la taille d'un modèle dépendant. | IDEAL et MASM
DUP | compteur DUP (expression[,expression]...) | Cet opérateur permet d'effectuer la répétition de données un nombre de fois spécifié par «compteur». | IDEAL et MASM
DWORD | DWORD expression | Cet opérateur permet de forcer l'adressage d'une expression avec un castre d'une taille d'un double mot (4 octets). | IDEAL
DWORD PTR | DWORD PTR expression | Cet opérateur permet de forcer l'adressage d'une expression avec un castre d'une taille d'un double mot (4 octets). | IDEAL et MASM
EQ | expression1 EQ expression2 | Cet opérateur permet de retourner vrai si les deux expressions sont égales. | IDEAL et MASM
FAR | FAR expression | Cet opérateur permet de forcer l'adressage d'une expression avec un code pointeur long. | IDEAL
FAR PTR | FAR PTR expression | Cet opérateur permet de forcer l'adressage d'une expression avec un code pointeur long. | IDEAL et MASM
FWORD | FWORD expression | Cet opérateur permet de forcer l'adressage d'une expression avec un code pointeur long de taille 32 bits. | IDEAL
FWORD PTR | FWORD PTR expression | Cet opérateur permet de forcer l'adressage d'une expression avec un code pointeur long de taille 32 bits. | IDEAL et MASM
GE | expression1 GE expression2 | Cet opérateur permet de retourner vrai si la première expression est supérieur ou égale à la deuxième expression. | IDEAL et MASM
GT | expression1 GT expression2 | Cet opérateur permet de retourner vrai si la première expression est supérieur à la deuxième expression. | IDEAL et MASM
HIGH | HIGH expression | Cet opérateur permet de retourner la partie haute d'une expression. Par exemple dans une expression 16 bits, il retournera les 8 bits de la partie haute de l'expression 16 bits. | IDEAL et MASM
HIGH | type HIGH expression | Cet opérateur permet de retourner la partie haute (8 bits ou de la taille type) d'une expression. | IDEAL
LARGE | LARGE expression | Cet opérateur permet de fixer la taille du déplacement 32 bits. Dans le mode «IDEAL», cette opération est autorisé seulement si la génération du code 386 est activé. | IDEAL
LE | expression1 LE expression2 | Cet opérateur permet de retourner vrai si la première expression est inférieur ou égale à la deuxième expression. | IDEAL et MASM
LOW | LOW expression | Cet opérateur permet de retourner la partie basse d'une expression. Par exemple dans une expression 16 bits, il retournera les 8 bits de la partie basse de l'expression 16 bits. | IDEAL et MASM
LOW | type LOW expression | Cet opérateur permet de retourner la partie basse (8 bits ou de la taille type) d'une expression. | IDEAL
LT | expression1 LT expression2 | Cet opérateur permet de retourner vrai si la première expression est inférieur à la deuxième expression. | IDEAL et MASM
MASK | MASK recordorfieldname | Cet opérateur permet de retourner le bit de masque d'un champ d'enregistrement ou d'une entrée d'enregistrement. | IDEAL et MASM
MOD | expression1 MOD expression2 | Cet opérateur permet de retourner le restant d'une division de deux expressions. | IDEAL et MASM
NE | expression1 NE expression2 | Cet opérateur permet de retourner vrai si les deux expressions ne sont pas égales. | IDEAL et MASM
NEAR | NEAR expression | Cet opérateur permet de forcer l'adressage d'une expression avec un code pointeur court. | IDEAL
NEAR PTR | NEAR PTR expression | Cet opérateur permet de forcer l'adressage d'une expression avec un code pointeur court. | IDEAL et MASM
NOT | NOT expression | Cet opérateur permet d'effectuer l'inversion de la valeur de chacun des bits d'un expression. | IDEAL et MASM
OFFSET | OFFSET expression | Cet opérateur permet de retourner l'adressage de déplacement d'une expression avec le segment courant (ou le groupe de segment). | IDEAL et MASM
OR | expression1 OR expression2 | Cet opérateur permet d'effectuer un «Ou binaire». | IDEAL et MASM
PROC | PROC expression | Cet opérateur permet de forcer l'adressage d'une expression avec un code pointeur court ou long. | IDEAL
PROC PTR | PROC PTR expression | Cet opérateur permet de forcer l'adressage d'une expression avec un code pointeur court ou long. | IDEAL et MASM
PTR | type PTR expression | Cet opérateur permet de forcer l'adressage d'une expression de la taille du type spécifié. | IDEAL et MASM
PWORD | PWORD expression | Cet opérateur permet de forcer l'adressage d'une expression avec un code pointeur long de taille 32 bits. | IDEAL
PWORD PTR | PWORD PTR expression | Cet opérateur permet de forcer l'adressage d'une expression avec un code pointeur long de taille 32 bits. | IDEAL et MASM
QWORD | QWORD expression | Cet opérateur permet de forcer l'adressage d'une expression avec un castre d'une taille d'un quadruple mot (8 octets). | IDEAL
QWORD PTR | QWORD PTR expression | Cet opérateur permet de forcer l'adressage d'une expression avec un castre d'une taille d'un quadruple mot (8 octets). | IDEAL et MASM
SEG | SEG expression | Cet opérateur permet de retourner le segment d'adressage d'une référence mémoire d'une expression. | IDEAL et MASM
SHL | expression SHL compteur | Cet opérateur permet d'effectuer un décalage de bit vers la gauche. | IDEAL et MASM
SHORT | SHORT expression | Cet opérateur permet de forcer l'adressage d'une expression d'un code pointeur très court (-128 à 127 de déplacement de l'emplacement courant). | IDEAL et MASM
SHR | expression SHR compteur | Cet opérateur permet d'effectuer un décalage de bit vers la droite. | IDEAL et MASM
SIZE | SIZE nom | Cet opérateur permet de retourner la taille d'un item de données alloué avec le nom spécifié. En mode MASM, SIZE retourne la valeur de LENGTH multiplier par TYPE. En mode IDEAL, SIZE retourne le compteur d'octets dans le «nom DUP». | IDEAL et MASM
SMALL | SMALL expression | Cet opérateur permet de retourner la taille du déplacement en 16 bits. Dans le mode IDEAL, l'opération est légale seulement si la génération du code 386 est activé. | IDEAL et MASM
SYMTYPE | SYMTYPE expression | Cet opérateur permet de retourner l'octet de décrivant l'expression. | IDEAL
TBYTE | TBYTE expression | Cet opérateur permet de forcer l'adressage d'une expression de taille de 10 octets. | IDEAL
TBYTE PTR | TBYTE PTR expression | Cet opérateur permet de forcer l'adressage d'une expression de taille de 10 octets. | IDEAL et MASM
THIS | THIS type | Cet opérateur permet de créer une opérande avec l'adresse du segment courant et le compteur d'emplacement. | IDEAL et MASM
.TYPE | .TYPE expression | Cet opérateur permet de retourner l'octet de mode descriptif et la porté de l'expression. | MASM
TYPE | TYPE nom1 nom2 | Cet opérateur permet d'appliquer le type d'une variable existante ou d'un membre d'une structure dans l'autre variable ou membre d'une structure. | IDEAL
TYPE | TYPE nom1 nom2 | Cet opérateur permet de retourner le nombre indiquant la taille ou le type d'une expression. | MASM
UNKNOWN | UNKNOWN expression | Cet opérateur permet d'enlever le type d'information de l'expression d'adressage. | IDEAL
WIDTH | WIDTH recordorfieldname | Cet opérateur permet de retourner le nombre de bits que contient un champ dans un enregistrement ou d'un enregistrement. | IDEAL et MASM
WORD | WORD expression | Cet opérateur permet de forcer l'adressage d'une expression avec un castre d'une taille d'un mot. | IDEAL
WORD PTR | WORD PTR expression | Cet opérateur permet de forcer l'adressage d'une expression avec un castre d'une taille d'un mot. | IDEAL et MASM
XOR | expression1 XOR expression2 | Cet opérateur permet d'effectuer un «Ou exclusif binaire». | IDEAL et MASM

Références

Turbo Assembler - Version 3.2: Quick Reference Guide, Edition Borland International, 1992, Part #11MN-BPL-10-70, BOR 4703, page 5 à 15.

Dernière mise à jour : Samedi, le 2 août 2014


Les symboles prédéfinies

Voir les symboles prédéfinies utilisé par les compilateurs tel Macro Assembler de Microsoft (MASM) ou Turbo Assembler de Borland (TASM) :

Symboles | Description | Mode
$ | Ce symbole prédéfinies permet de représenter le compteur d'emplacement courant dans le segment courant | IDEAL et MASM
@32Bit | Ce symbole prédéfinies permet d'indiquer que l'équation numérique du segment est dans le modèle courant de 16 ou 32 bits. | IDEAL et MASM
@code | Ce symbole prédéfinies permet d'indiquer un segment de code, alias de «.CODE». | IDEAL et MASM
@CodeSize | Ce symbole prédéfinies permet d'indiquer le code de modèle de mémoire: 0=NEAR, 1=FAR. | IDEAL et MASM
@CPU | Ce symbole prédéfinies permet d'indiquer les informations a propos des directive de microprocesseur. | IDEAL et MASM
@curseg | Ce symbole prédéfinies permet d'indiquer le segment courant. | IDEAL et MASM
@data | Ce symbole prédéfinies permet d'indiquer le nom du groupe de données court. | IDEAL et MASM
@DataSize | Ce symbole prédéfinies permet d'indiquer le modèle mémoire de données: 0=Near, 1=Far, 2=Huge. | IDEAL et MASM
??date | Ce symbole prédéfinies permet de retourner la chaine de caractères de la date courante. | IDEAL et MASM
@fardata | Ce symbole prédéfinies permet d'initialiser le nom de segment de données. | IDEAL et MASM
@fardata? | Ce symbole prédéfinies permet de désinitialiser le nom de segment de données. | IDEAL et MASM
@FileName | Ce symbole prédéfinies permet d'indiquer le nom du fichier actuellement assemblés. | IDEAL et MASM
??filename | Ce symbole prédéfinies permet d'indiquer une chaine de caractères du nom du fichier actuellement assemblés. | IDEAL et MASM
@Interface | Ce symbole prédéfinies permet d'indiquer le langage de programmation et le système d'exploitation sélectionné par MODEL. | IDEAL et MASM
@Model | Ce symbole prédéfinies permet d'indiquer le modèle actuellement utilisé. | IDEAL et MASM
@Object | Ce symbole prédéfinies permet d'indiquer la macro texte contenant le nom de l'objet courant. Alias du segment de pile. | IDEAL et MASM
@Stack | Ce symbole prédéfinies permet d'indiquer la macro texte contenant le nom de l'objet courant. Alias du segment de pile. | IDEAL et MASM
@Startup | Ce symbole prédéfinies permet d'indiquer l'étiquette marquant le début du code de démarrage. | IDEAL et MASM
@Table_objectname | Ce symbole prédéfinies permet d'indiquer le type de données contenant la table de méthode d'objet. | IDEAL et MASM
@TableAddr_objectname | Ce symbole prédéfinies permet d'indiquer l'étiquette décrivant l'adresse de l'instance de la méthode de la table d'objet virtuel. | IDEAL et MASM
??date | Ce symbole prédéfinies permet de retourner la chaine de caractères de l'heure courante. | IDEAL et MASM
??version | Ce symbole prédéfinies permet d'indiquer la version du compilateur. | IDEAL et MASM
@WordSize | Ce symbole prédéfinies permet si le segments est 16 ou 32 bits: 2=16 bits, 4=32 bits. | IDEAL et MASM

Références

Turbo Assembler - Version 3.2: Quick Reference Guide, Edition Borland International, 1992, Part #11MN-BPL-10-70, BOR 4703, page 2 à 3.

Dernière mise à jour : Samedi, le 2 août 2014


Les registres des microprocesseurs

Voici un tableau de référence des différents registres des microprocesseur 80x86 :

Nom | Description | Taille | Prérequis
AH | Ce nom permet d'indiquer la partie haute du registre accumulateur. | 8 bits | 8086+
AL | Ce nom permet d'indiquer la partie basse du registre accumulateur. | 8 bits | 8086+
AX | Ce nom permet d'indiquer le registre accumulateur. | 16 bits | 8086+
BH | Ce nom permet d'indiquer la partie haute du registre de base. | 8 bits | 8086+
BL | Ce nom permet d'indiquer la partie basse du registre de base. | 8 bits | 8086+
BP | Ce nom permet d'indiquer le registre d'offset de base. | 16 bits | 8086+
BX | Ce nom permet d'indiquer le registre de base. | 16 bits | 8086+
CH | Ce nom permet d'indiquer la partie haute du registre de compteur. | 8 bits | 8086+
CL | Ce nom permet d'indiquer la partie basse du registre de compteur. | 8 bits | 8086+
CR0 | Ce nom permet d'indiquer le registre de contrôle 0. | 32 bits | 80386+
CR1 | Ce nom permet d'indiquer le registre de contrôle 1. | 32 bits | 80386+
CR2 | Ce nom permet d'indiquer le registre de contrôle 2. | 32 bits | 80386+
CR3 | Ce nom permet d'indiquer le registre de contrôle 3. | 32 bits | 80386+
CR4 | Ce nom permet d'indiquer le registre de contrôle 4. | 32 bits | 80386+
CS | Ce nom permet d'indiquer le registre de segment de code d'instruction machine. | 16 bits | 8086+
CX | Ce nom permet d'indiquer le registre de compteur. | 16 bits | 8086+
DH | Ce nom permet d'indiquer la partie haute du registre de données. | 8 bits | 8086+
DI | Ce nom permet d'indiquer le registre d'offset de destination de données. | 16 bits | 8086+
DL | Ce nom permet d'indiquer la partie basse du registre de données. | 8 bits | 8086+
DS | Ce nom permet d'indiquer le registre de segment de données. | 16 bits | 8086+
DX | Ce nom permet d'indiquer le registre de données. | 16 bits | 8086+
EAX | Ce nom permet d'indiquer le registre accumulateur étendue. | 32 bits | 80386+
EBX | Ce nom permet d'indiquer le registre de base étendue. | 32 bits | 80386+
ECX | Ce nom permet d'indiquer le registre de compteur étendue. | 32 bits | 80386+
EDI | Ce nom permet d'indiquer le registre d'offset de destination de données étendue. | 32 bits | 80386+
EDX | Ce nom permet d'indiquer le registre de données étendue. | 32 bits | 80386+
ESI | Ce nom permet d'indiquer le registre d'offset de source de données étendue. | 32 bits | 80386+
ES | Ce nom permet d'indiquer le registre de segment supplémentaire. | 16 bits | 8086+
FS | Ce nom permet d'indiquer le registre de segment supplémentaire FS. | 16 bits | 80386+
GS | Ce nom permet d'indiquer le registre de segment supplémentaire GS. | 16 bits | 80386+
IP | Ce nom permet d'indiquer le registre d'offset du code d'instruction machine. | 16 bits | 8086+
MM0 | Ce nom permet d'indiquer le registre MMX 0. | 64 bits | Pentium MMX+
MM1 | Ce nom permet d'indiquer le registre MMX 1. | 64 bits | Pentium MMX+
MM2 | Ce nom permet d'indiquer le registre MMX 2. | 64 bits | Pentium MMX+
MM3 | Ce nom permet d'indiquer le registre MMX 3. | 64 bits | Pentium MMX+
MM4 | Ce nom permet d'indiquer le registre MMX 4. | 64 bits | Pentium MMX+
MM5 | Ce nom permet d'indiquer le registre MMX 5. | 64 bits | Pentium MMX+
MM6 | Ce nom permet d'indiquer le registre MMX 6. | 64 bits | Pentium MMX+
MM7 | Ce nom permet d'indiquer le registre MMX 7. | 64 bits | Pentium MMX+
MXCSR | Ce nom permet d'indiquer le registre de contrôle et d'état des instructions SSE. | 32 bits | SSE+
R0 | Ce nom permet d'indiquer le registre 0 du coprocesseur mathématique. | 80 bits | 8087+
R1 | Ce nom permet d'indiquer le registre 1 du coprocesseur mathématique. | 80 bits | 8087+
R2 | Ce nom permet d'indiquer le registre 2 du coprocesseur mathématique. | 80 bits | 8087+
R3 | Ce nom permet d'indiquer le registre 3 du coprocesseur mathématique. | 80 bits | 8087+
R4 | Ce nom permet d'indiquer le registre 4 du coprocesseur mathématique. | 80 bits | 8087+
R5 | Ce nom permet d'indiquer le registre 5 du coprocesseur mathématique. | 80 bits | 8087+
R6 | Ce nom permet d'indiquer le registre 6 du coprocesseur mathématique. | 80 bits | 8087+
R7 | Ce nom permet d'indiquer le registre 7 du coprocesseur mathématique. | 80 bits | 8087+
R8 | Ce nom permet d'indiquer le registre général étendue 64 bits. | 64 bits | Intel 64+
R9 | Ce nom permet d'indiquer le registre général étendue 64 bits. | 64 bits | Intel 64+
R9 | Ce nom permet d'indiquer le registre général étendue 64 bits. | 64 bits | Intel 64+
R10 | Ce nom permet d'indiquer le registre général étendue 64 bits. | 64 bits | Intel 64+
R11 | Ce nom permet d'indiquer le registre général étendue 64 bits. | 64 bits | Intel 64+
R12 | Ce nom permet d'indiquer le registre général étendue 64 bits. | 64 bits | Intel 64+
R13 | Ce nom permet d'indiquer le registre général étendue 64 bits. | 64 bits | Intel 64+
R14 | Ce nom permet d'indiquer le registre général étendue 64 bits. | 64 bits | Intel 64+
R15 | Ce nom permet d'indiquer le registre général étendue 64 bits. | 64 bits | Intel 64+
RAX | Ce nom permet d'indiquer le registre accumulateur étendue 64 bits. | 64 bits | AMD64+, Intel 64+
RBP | Ce nom permet d'indiquer le registre de pointeur de base étendue 64 bits. | 64 bits | AMD64+, Intel 64+
RBX | Ce nom permet d'indiquer le registre de base étendue 64 bits. | 64 bits | AMD64+, Intel 64+
RCX | Ce nom permet d'indiquer le registre de compteur étendue 64 bits. | 64 bits | AMD64+, Intel 64+
RDI | Ce nom permet d'indiquer le registre d'offset de destination étendue 64 bits. | 64 bits | AMD64+, Intel 64+
RDX | Ce nom permet d'indiquer le registre de données étendue 64 bits. | 64 bits | AMD64+, Intel 64+
RIP | Ce nom permet d'indiquer le registre d'accès relatifs au pointeur d'instruction. | 64 bits | AMD64+, Intel 64+
RSI | Ce nom permet d'indiquer le registre accumulateur étendue 64 bits. | 64 bits | AMD64+, Intel 64+
RSP | Ce nom permet d'indiquer le registre accumulateur étendue 64 bits. | 64 bits | AMD64+, Intel 64+
SI | Ce nom permet d'indiquer le registre d'offset de source de données. | 16 bits | 8086+
SP | Ce nom permet d'indiquer le registre d'offset de la pile. | 16 bits | 8086+
SS | Ce nom permet d'indiquer le registre de segment de la pile. | 16 bits | 8086+

Les registres par langages de programmation

Voici un tableau de référence celons des langages évoluées comme le C, C++ et Turbo Pascal :

Nom | Variable en C | Type de données C | Type de données Pascal | Structure de données C | Structure de données Pascal
AH | _AH | unsigned char | BYTE | regs.h.ah | Registers.AH
AL | _AL | unsigned char | BYTE | regs.h.al | Registers.AL
AX | _AX | unsigned int | WORD | regs.x.ax | Registers.AX
BH | _BH | unsigned char | BYTE | regs.h.bh | Registers.BH
BL | _BL | unsigned char | BYTE | regs.h.bl | Registers.BL
BP | _BP | unsigned int | WORD | regs.x.bp | Registers.BP
BX | _BX | unsigned int | WORD | regs.x.bx | Registers.BX
CH | _CH | unsigned char | BYTE | regs.h.ch | Registers.CH
CL | _CL | unsigned char | BYTE | regs.h.cl | Registers.CL
CS | _CS | unsigned int | WORD | regs.x.cs |
CX | _CX | unsigned int | WORD | regs.x.cx | Registers.CX
DH | _DH | unsigned char | BYTE | regs.h.dh | Registers.DH
DI | _DI | unsigned int | WORD | regs.x.di | Registers.DI
DL | _DL | unsigned char | BYTE | regs.h.dl | Registers.DL
Drapeaux | _FLAGS | unsigned int | WORD | regs.x.flags | Registers.Flags
DS | _DS | unsigned int | WORD | regs.x.ds | Registers.DS
DX | _DX | unsigned int | WORD | regs.x.dx | Registers.DX
ES | _ES | unsigned int | WORD | regs.x.es | Registers.ES
SI | _SI | unsigned int | WORD | regs.x.si | Registers.SI
SP | _SP | unsigned int | WORD | regs.x.sp |
SS | _SS | unsigned int | WORD | regs.x.ss |

Références

Assembleur - Référence, Edition Micro Application, Pierre Maurette, 2003, ISBN: 2-7429-3061-2, page 95, 99.
The Undocumented PC: A programmer's Guide to I/O, CPUs, and Fixed Memory Areas - Second Edition, Edition Addison-Wesley, Frank van Gilluwe, 1997, ISBN: 0-201-47950-8, page 46.
Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 1: Basic Architecture, Order Number: 253665-032US, Septembre 2009, volume I, 3-17.

Dernière mise à jour : Samedi, le 2 août 2014


Le langage Assembleur de la famille des 80x86 ne support qu'un format de remarque.

Sa syntaxe est la suivante :

; ma remarque

Remarque

  • Format des remarques : Il a bien une personne, surnommée Verbosity, ayant tenté de réaliser un projet appelé «AsmDoc» au début des années 2000, similaire à JavaDoc, mais le projet fut abandonné et les sources sont actuellement introuvables. Ainsi, l'assembleur est toujours en attente d'un standard au niveau de ses commentaires. Il proposait d'utiliser «@name», «@desc», «@ret» et «@arg» afin que l'analyseur de l'éditeur retrouve l'information.

Dernière mise à jour : Vendredi, le 4 mars 2016


Les types de données élémentaires

Voici les types de données élémentaires (soit les types de données sur lesquels reposent tous les autres types de données) :

Type | Directive de données | Taille en octet | Taille en bits | Valeur autorisé
BYTE | DB | 1 | 8 | Nombre naturel de 0 à 255
SBYTE | DB | 1 | 8 | Nombre entier de -128 à 127
WORD | DW | 2 | 16 | Nombre naturel de 0 à 65 535
SWORD | DW | 2 | 16 | Nombre entier de -32 768 à 32 767
DWORD | DD | 4 | 32 | Nombre naturel de 0 à 4 294 967 295
SDWORD | DD | 4 | 32 | Nombre entier de -2 147 483 648 à 2 147 483 647
FWORD | DF | 6 | 48 | Type pointeur Segment de 16 bits:Offset de 32 bits
QWORD | DQ | 8 | 64 | Format utilisateur
TBYTE | DT | 10 | 80 | Format utilisateur
REAL4 | DD | 4 | 32 | Nombre réel court
REAL8 | DQ | 8 | 64 | Nombre réel long
REAL10 | DT | 10 | 80 | Nombre réel étendu

Dernière mise à jour : Samedi, le 2 août 2014


Cliquez sur l'instruction recherchée pour atteindre plus rapidement votre commande du langage de programmation assembleur de la famille 80x86 recherché.

Instruction | Description | CPU/MPU
AAA | Cette instruction permet d'adapter le résultat obtenu par l'addition de 2 valeurs en format DCB. | INTEL 8088+
AAD | Cette instruction permet de convertir une valeur de format DCB non compactée. | INTEL 8088+
AAM | Cette instruction offre la possibilité de convertir le produit de la multiplication de 2 valeurs de format DCB en un format DCB. | INTEL 8088+
AAS | Cette instruction permet d'adapter le résultat de la soustraction de nombre de format DCB. | INTEL 8088+
ADC | Cette instruction additionne 2 quantités numériques sur 8, 16, 32 ou 64 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu. | INTEL 8088+
ADD | Cette instruction additionne 2 quantités numériques sur 8, 16, 32 ou 64 bits. | INTEL 8088+
ADDPD | Cette instruction permet d'effectuer une addition de 2 paquets de valeurs réels de double précision d'un opérande source et d'un opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de double précision. | INTEL Pentium 4+
ADDPS | Cette instruction permet d'effectuer une addition SIMD de 4 paquets de valeurs réels de simple précision d'un opérande source et d'un opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de simple précision. | INTEL Pentium III (SSE)+
ADDSD | Cette instruction permet d'effectuer une addition de la partie basse d'une valeur réel de double précision d'un opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de double précision. | INTEL Pentium 4+
ADDSS | Cette instruction permet d'effectuer une addition de la partie basse d'une valeur réel de simple précision d'un opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de simple précision. | INTEL Pentium III (SSE)+
ADDSUBPD | Cette instruction permet d'effectuer une soustraction de la partie basse d'une valeur réel de double précision d'un opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de double précision et d'effectuer une addition de la partie haute d'une valeur réel de double précision d'un opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de double précision. | INTEL Pentium 4 (SSE3)+
ADDSUBPS | Cette instruction permet d'effectuer une soustraction de la partie basse d'un paquet de valeur réel de simple précision d'un opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de simple précision et d'effectuer une addition de la partie haute d'un paquet de valeur réel de simple précision d'une opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de simple précision. | INTEL Pentium 4 (SSE3)+
AESDEC | Cette instruction permet d'effectuer un arrondissement du décryptage AES en utilisant l'équivalence de Cipher inversé, avec un clef arrondie pour le deuxième opérande source, opération dans une données de 128 bits du premier opérande source, et enregistre le résultat dans l'opérande de destination. | Intel AES
AESDECLAST | Cette instruction permet d'effectuer le dernier arrondissement du décryptage AES en utilisant l'équivalence de Cipher inversé, avec un clef arrondie pour le deuxième opérande source, opération dans une données de 128 bits du premier opérande source, et enregistre le résultat dans l'opérande de destination. | Intel AES
AESENC | Cette instruction permet d'effectuer un arrondissement d'encryptage AES en utilisant la clef arrondie pour le deuxième opérande source, opération dans une données de 128 bits du premier opérande source, et enregistre le résultat dans l'opérande de destination. | Intel AES
AESENCLAST | Cette instruction permet d'effectuer le dernier arrondissement d'encryptage AES en utilisant la clef arrondie pour le deuxième opérande source, opération dans une données de 128 bits du premier opérande source, et enregistre le résultat dans l'opérande de destination. | Intel AES
AESIMC | Cette instruction permet d'effectuer une transformation InvMixColumns de l'opérande source et enregistre le résultat dans l'opérande de destination. | Intel AES
AESKEYGENASSIST | Cette instruction permet d'effectuer l'expansion de clef AES Cipher, en calculant la génération des clefs arrondies pour l'encryption, en utilisant les données 128 bits spécifiés de l'opérande source et de la constante arrondie arrondie 8 bits spécifié immédiate et enregistre le résultat dans l'opérande de destination. | Intel AES
AND | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés. | INTEL 8088+
ANDNPD | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 paquets d'opérandes de valeur de format réel de double précision et inverse chacun des bits du résultat. | INTEL Pentium 4+
ANDNPS | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes 128 bits spécifiés et inverse chacun des bits du résultat. | INTEL Pentium III (SSE)+
ANDPD | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 paquets d'opérandes de valeur de format réel de double précision. | INTEL Pentium 4+
ANDPS | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes 128 bits spécifiés. | INTEL Pentium III (SSE)+
ARPL | Cette instruction permet de contrôler et corriger le niveau de privilège du segment de code en mode protégée. | INTEL 80286+
BLENDPD | Cette instruction permet de copier le paquet de valeurs réel de double précisions de l'opérande source dans l'opérande de destination si la condition de masque de l'opérande immédiate est rempli. | SSE4.1
BLENDPS | Cette instruction permet de copier le paquet de valeurs réel de simple précisions de l'opérande source dans l'opérande de destination si la condition de masque de l'opérande immédiate est rempli. | SSE4.1
BLENDVPD | Cette instruction permet de copier le paquet de valeurs réel de double précisions de l'opérande source dans l'opérande de destination si la condition de masque de l'opérande du troisième opérande en registre est rempli. | SSE4.1
BLENDVPS | Cette instruction permet de copier le paquet de valeurs réel de simple précisions de l'opérande source dans l'opérande de destination si la condition de masque de l'opérande du troisième opérande en registre est rempli. | SSE4.1
BOUND | Cette instruction permet de vérifier la validité pouvant exister entre avec un tableau et son indexation. | INTEL 80186+
BSF | Cette instruction permet d'effectuer une comparaison binaire de la droite vers la gauche. | INTEL 80386+
BSR | Cette instruction permet d'effectuer une comparaison binaire de la gauche vers la droite. | INTEL 80386+
BSWAP | Cette instruction permet d'inverse l'ordre des 4 octets d'un registre de taille de 32 bits. | INTEL 80486+
BT | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue. | INTEL 80386+
BTC | Cette instruction transfère une Opérande vers l'indicateur de retenue le bit spécifié et inverser la valeur du bit correspondant. | INTEL 80386+
BTR | Cette instruction permet de transférer l'Opérande vers l'indicateur de retenue le bit spécifié puis met le bit correspondant de l'Opérande à 0. | INTEL 80386+
BTS | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue le bit spécifié puis ensuite met le bit correspondant dans Opérande à 1. | INTEL 80386+
CALL | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse d'appel avant de continuer. | INTEL 8088+
CBW | Cette instruction permet de convertir un nombre contenu dans le registre AL en un format sur 16 bits pour se retrouver dans le registre AX en appliquant une extension du signe. | INTEL 8088+
CDQ | Cette instruction permet de convertir le double mot en un quadruple mot, le résultat tient sur une taille de 64 bits. | INTEL 80386+
CDQE | Cette instruction permet de convertir le double mot du registre EAX en un quadruple mot RAX, le résultat tient sur une taille de 64 bits. | x86-64+
CLC | Cette instruction permet de mettre l'indicateur d'état de retenu CF à 0. | INTEL 8088+
CLD | Cette instruction met l'indicateur d'état DF à 0. | INTEL 8088+
CLFLUSH | Cette instruction permet de vider la ligne de cache d'une adresse linéaire. | INTEL Pentium 4 (SSE2)+
CLGI | Cette instruction permet d'effacer le drapeau global d'interruption (GIF). Quand le GIF est à 0, toutes les interruptions externes sont désactivées. | AMD-V
CLI | Cette instruction met l'indicateur d'état IF à 0. | INTEL 8088+
CLTS | Cette instruction permet de mettre à 0 le drapeau de l'indicateur de tâche (Task-Switch) du registre CR0. | INTEL 80286+
CMC | Cette instruction offre la possibilité d'inverser la valeur de l'indicateur de retenue. Si ce dernier vaut 1, elle le met à 0 et inversement. | INTEL 8088+
CMOV | Cette instruction copie des données d'une source (valeur) à une destination (registre) à la condition que la condition demandée soit remplie. | INTEL Pentium Pro+
CMP | Cette instruction offre la possibilité essentielle de comparer 2 registres ou emplacements de mémoire. | INTEL 8088+
CMPPD | Cette instruction permet d'effectuer une comparaison SIMD de 2 paquets de valeurs réels de double précision d'un opérande source et d'un opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination. | INTEL Pentium 4 (SSE2)+
CMPPS | Cette instruction permet d'effectuer une comparaison SIMD de 4 paquets de valeurs réels de simple précision d'un opérande source et d'un opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination. | INTEL Pentium III (SSE)+
CMPS | Cette instruction permet d'effectuer la comparaison d'un octet, d'un mot ou double mot spécifié avec l'opérande source et destination spécifié et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison. | INTEL 8088+
CMPSB | Cette instruction permet d'effectuer la comparaison d'un octet avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison. | INTEL 8086+
CMPSD | Cette instruction permet d'effectuer la comparaison d'un double mot avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison. | INTEL 80386+
CMPSD | Cette instruction permet d'effectuer une comparaison de la partie basse de valeurs réelles de double précision d'un opérande source et d'un opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination. | INTEL Pentium 4 (SSE2)+
CMPSQ | Cette instruction permet d'effectuer la comparaison d'un quadruple mot avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison. | x86-64+
CMPSS | Cette instruction permet d'effectuer une comparaison de la partie basse de valeurs réelles de simple précision d'un opérande source et d'un opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination. | INTEL Pentium III (SSE)+
CMPSW | Cette instruction permet d'effectuer la comparaison d'un mot avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison. | INTEL 8086+
CMPXCHG | Cette instruction compare la destination avec l'accumulateur (AL, AX ou EAX) et les échanges si la condition est vraie. | INTEL Pentium+
CMPXCHG8B | Cette instruction compare un nombre de 64 bits et les échanges si la condition est vraie. | INTEL Pentium+
CMPXCHG16B | Cette instruction permet de comparer un nombre de 128 bits et les échanges si la condition est vraie. | INTEL x86-64+
COMISD | Cette instruction permet de comparer deux valeurs réel de double-précision dans la partie faible du quadruple mot de deux opérande et fixe les drapeaux de ZF, PF et FC du registre EFLAGS en fonction du résultat (non-ordonnée, supérieur à, inférieur ou égal). | INTEL Pentium III+
COMISS | Cette instruction permet de comparer deux valeurs réel de simple-précision dans la partie faible du quadruple mot de deux opérande et fixe les drapeaux de ZF, PF et FC du registre EFLAGS en fonction du résultat (non-ordonnée, supérieur à, inférieur ou égal). | INTEL Pentium III+
CPUID | Cette instruction retourne le code d'identification du microprocesseur. | INTEL Pentium+
CQO | Cette instruction permet de convertir le quadruple mot du registre EAX en deux quadruples mots RDX:RAX, le résultat tient sur une taille de 128 bits. | x86-64+
CRC32 | Cette instruction débute avec une valeur initiale dans l'opérande de destination, accumule une valeur de code CRC-32 (polynomial de 11EDC6F41h) dans l'opérande source et enregistre le résultat dans l'opérande de destination. | Nehalem (SSE4.2)+
CVTDQ2PD | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de double précision. | INTEL Pentium 4+
CVTDQ2PS | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de simple précision. | INTEL Pentium 4+
CVTPD2DQ | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en double mot entier et fixe à 0 le reste du paquet. | INTEL Pentium 4+
CVTPD2PI | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en double mot entier. | INTEL Pentium 4+
CVTPD2PS | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en valeurs réel de simple précision et fixe à 0 le reste du paquet. | INTEL Pentium 4+
CVTPI2PD | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de double précision compacté. | INTEL Pentium 4+
CVTPI2PS | Cette instruction permet de convertir un entier de format double mot en une valeur réel de simple précision compacté. | Pentium III (KNI/MMX2)+
CVTPS2DQ | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de simple précision en paquet de doubles mots entiers. | INTEL Pentium 4+
CVTPS2PD | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de simple précision en paquet de valeurs réel de double précision. | INTEL Pentium 4+
CVTPS2PI | Cette instruction permet de convertir une valeur réel de simple précision compacté en un entier de format double mot. | Pentium III (KNI/MMX2)+
CVTSD2SI | Cette instruction permet d'effectuer la conversion d'une valeur réel de simple précision en valeur entier de double mots. | INTEL Pentium 4+
CVTSD2SS | Cette instruction permet d'effectuer la conversion d'une valeur réel de double précision en valeur réel de simple précision. | INTEL Pentium 4+
CVTSI2SD | Cette instruction permet de convertir un entier de format double mot en une valeur réel de double précision. | INTEL Pentium 4+
CVTSI2SS | Cette instruction permet de convertir un entier de format double mot en une valeur réel de simple précision. | Pentium III (KNI/MMX2)+
CVTSS2SD | Cette instruction permet de convertir une valeur réel de simple précision en une valeur réel de double précision. | INTEL Pentium 4+
CVTSS2SI | Cette instruction permet de convertir une valeur réel de simple précision en un entier de format double mot. | Pentium III (KNI/MMX2)+
CVTTPD2DQ | Cette instruction permet de convertir un paquet de valeur réel de double précision avec en un paquet d'entier de format double mot tronquer et fixe à 0 le reste du paquet. | INTEL Pentium 4+
CVTTPD2PI | Cette instruction permet de convertir une valeur réel de double précision compacté avec tronquage en un entier de format double mot compacté. | INTEL Pentium 4+
CVTTPS2DQ | Cette instruction permet de convertir un paquet de valeur réel de simple précision avec en un paquet d'entier de format double mot tronquer. | INTEL Pentium 4+
CVTTPS2PI | Cette instruction permet de convertir une valeur réel de simple précision compacté avec tronquage en un entier de format double mot compacté. | Pentium III (KNI/MMX2)+
CVTTSD2SI | Cette instruction permet de convertir une valeur réel de double précision avec en un entier de format double mot tronquer. | INTEL Pentium 4+
CVTTSS2SI | Cette instruction permet de convertir un entier de format double mot avec tronquage en une valeur réel de simple précision. | Pentium III (KNI/MMX2)+
CWD | Cette instruction est l'alternative pour convertir le mot du registre AX en un double mot contenu dans le couple de registre DX et AX par extension du signe. | INTEL 8088+
CWDE | Cette instruction est l'alternative pour convertir le mot du registre AX en un double mot contenu dans le registre EAX par extension du signe. | INTEL 80386+
DAA | Cette instruction corrige après coup les retenues lors de la manipulation de valeur DCB. | INTEL 8088+
DAS | Cette instruction offre l'intéressante possibilité de corrige le résultat d'une soustraction de 2 nombres de format DCB compactées. | INTEL 8088+
DEC | Cette instruction décrément de 1 le registre ou l'adresse mémoire spécifié. | INTEL 8088+
DIV | Cette instruction permet d'effectuer une division non-signée (nombre naturel). | INTEL 8088+
DIVPD | Cette instruction permet d'effectuer une division de valeur réel de double précision de registre XMM ou d'emplacement mémoire de 128 bits. | INTEL Pentium 4+
DIVPS | Cette instruction permet d'effectuer une division de valeur réel de simple précision de registre XMM ou d'emplacement mémoire de 128 bits. | INTEL Pentium III (KNI/MMX2)+
DIVSD | Cette instruction permet d'effectuer une division scalaire de valeur réel de double précision de registre XMM ou d'emplacement mémoire de 128 bits. | INTEL Pentium 4+
DIVSS | Cette instruction permet d'effectuer une division scalaire de valeur réel de simple précision de registre XMM ou d'emplacement mémoire de 128 bits. | Pentium III (KNI/MMX2)+
DPPD | Cette instruction permet d'effectuer une multiplication conditionnel d'un paquet de valeurs réel de double précision dans l'opérande de destination avec le paquet de valeurs réel de l'opérande source et effectue un masque des bits extrait d'un opérande immédiat. | SSE4.1
DPPS | Cette instruction permet d'effectuer une multiplication conditionnel d'un paquet de valeurs réel de simple précision dans l'opérande de destination avec le paquet de valeurs réel de l'opérande source et effectue un masque des bits extrait d'un opérande immédiat. | SSE4.1
EMMS | Cette instruction fixe les mots marqués du MPU de chacun un. | INTEL Pentium-MMX
ENTER | Cette instruction permet de créer les structures de paramètres nécessaires aux procédures des langages de haut niveau. | INTEL 80186+
ESC | Cette instruction active le coprocesseur, lequel se permettra d'utiliser les méthodes d'adressage du processeur principal (CPU). | INTEL 8088 au 80386
F2XM | Cette instruction s'applique à calculer 2 puissance le registre mathématique ST(0) moins 1 et enregistre son produit dans le registre mathématique ST(0). Alias de F2XM1, mais déconseillé. | INTEL MPU 8087+
F2XM1 | Cette instruction permet d'effectuer le calcul de 2 puissance le registre mathématique ST(0) moins 1 et enregistre son produit dans le registre mathématique ST(0). | INTEL MPU 8087+
FABS | Cette instruction permet de convertir le nombre réel contenu dans le registre mathématique ST(0) en sa valeur absolue. | INTEL MPU 8087+
FADD | Cette instruction offre l'essentiel possibilité d'ajouter le nombre réel de valeur positive «source» à «cible» et enregistre la somme dans «cible». | INTEL MPU 8087+
FADDP | Cette instruction complémentaire ajoute le nombre réel source au nombre réel cible et enregistrer la somme dans cible puis prendre le registre mathématique ST(0) et le dépile. | INTEL MPU 8087+
FBLD | Cette instruction charge la valeur de format DCB compactée après le registre mathématique ST(0). | INTEL MPU 8087+
FBSTP | Cette instruction extrait la valeur de format DCB compactée du registre mathématique ST(0), l'enregistrer dans cible et prendre le registre mathématique ST(0) et sort de la pile. | INTEL MPU 8087+
FCHS | Cette instruction inverse tout simplement le signe du registre mathématique ST(0). | INTEL MPU 8087+
FCLEX | Cette instruction efface toutes les exceptions contenu dans les drapeaux de registres du coprocesseur mathématique. | INTEL MPU 8087+
FCMOV | Cette instruction permet de déplacé des nombres réel (virgule flottante) si la condition en question est satisfaite. | INTEL P6+
FCOM | Cette instruction permet de comparer le nombre réel de valeur positive source avec le registre mathématique ST(0) et mettre les indicateurs d'état C0 à C3 avec la valeur 1. | INTEL MPU 8087+
FCOMI | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats. | INTEL Pentium III+
FCOMIP | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats et désempile de la pile la valeur dans le registre. | INTEL Pentium III+
FCOMP | Cette instruction compare le nombre réel de valeur positive «source» avec le registre mathématique ST(0), mettre les indicateurs d'état C0 à C3 avec la valeur 1 et dépile le registre mathématique ST(0) de la pile de registres. | INTEL MPU 8087+
FCOMPP | Cette instruction permet de comparer les nombres réels du registre mathématique ST(1) avec le registre mathématique ST(0), ensuite de mettre les indicateurs d'état C0 à C3 à la valeur 1 et prendre le couple de registre mathématique ST(1) et ST(0) dans la pile de registres (2 dépilages). | INTEL MPU 8087+
FCOS | Cette instruction calcule le cosinus du registre mathématique ST(0). | INTEL MPU 80387+
FDECSTP | Cette instruction permet de décrémenter le pointeur de pile de registres. | INTEL MPU 8087+
FDISI | Cette instruction permettait de désactiver les interruptions. | INTEL MPU 8087+
FDIV | Cette instruction offre la possibilité d'effectuer des division de nombre réel de valeur positive. | INTEL MPU 8087+
FDIVP | Cette instruction offre la possibilité d'effectuer des division de nombre réel et place ST(0) dans la pile. | INTEL MPU 8087+
FDIVR | Cette instruction offre la possibilité d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source». | INTEL MPU 8087+
FDIVRP | Cette instruction offre la possibilité d'effectuer des division de nombre réel avec les registres inversés «cible» par «source» et place ST(0) dans la pile. | INTEL MPU 8087+
FEMMS | Cette instruction permet d'effacer les états MMX après le passage d'instructions MMX. | AMD 3DNow!
FENI | Cette instruction permet d'autoriser les interruptions. | INTEL MPU 8087
FFREE | Cette instruction permet de libérer un des registres de la pile. | INTEL MPU 8087+
FFREEP | Cette instruction permet de libérer un des registres de la pile et d'ensuite de désempiler le registre de la pile. | INTEL MPU 80287+
FIADD | Cette instruction offre l'essentiel possibilité d'ajouter le nombre réel source à cible et enregistre la somme dans cible. | INTEL MPU 8087+
FICOM | Cette instruction permet de comparer le nombre réel source avec le registre mathématique ST(0) et mettre les indicateurs d'état C0 à C3 avec la valeur 1. | INTEL MPU 8087+
FICOMP | Cette instruction compare le nombre réel «source» avec le registre mathématique ST(0), mettre les indicateurs d'état C0 à C3 avec la valeur 1 et dépile le registre mathématique ST(0) de la pile de registres. | INTEL MPU 8087+
FIDIV | Cette instruction offre la possibilité d'effectuer des division de nombre réel. | INTEL MPU 8087+
FIDIVR | Cette instruction offre la possibilité d'effectuer des division de nombre réel avec les registres inversés «cible» par «source». | INTEL MPU 8087+
FILD | Cette instruction permet de charger le nombre entier auprès du registre ST(0). | INTEL MPU 8087+
FIMUL | Cette instruction permet de multiplier le nombre réel «source» par «cible» et sauvegarde le résultat dans «cible». | INTEL MPU 8087+
FINCSTP | Cette instruction permet d'incrémenter le pointeur de pile de registres. | INTEL MPU 8087+
FINIT | Cette instruction permet d'effectuer l'initialisation du coprocesseur mathématique. | INTEL MPU 8087+
FIST | Cette instruction permet de sauvegarder le nombre du registre ST(0) dans «cible». | INTEL MPU 8087+
FISTP | Cette instruction permet de sauvegarder le nombre du registre ST(0) dans «cible» et prendre le registre ST(0) de la pile du registres. | INTEL MPU 8087+
FISTTP | Cette instruction permet de convertir la valeur contenu dans le registre ST dans un entier en utilisant on tronquage, de type chop, lequel est un mode d'arrondissement, et transfert le résultat dans la destination et ensuite effectuer un désempilage de ST. | SSE3+
FISUB | Cette instruction offre l'essentielle possibilité de soustraire le nombre «source» du registre ST(0). | INTEL MPU 8087+
FISUBR | Cette instruction offre l'essentielle possibilité de soustraire le nombre du registre ST(0) de «source». | INTEL MPU 8087+
FLD | Cette instruction permet de charger le nombre réel du registre ST(0) dans la pile. | INTEL MPU 8087+
FLD1 | Cette instruction permet de charger la constante 1,0 du registre ST(0) dans la pile. | INTEL MPU 8087+
FLDCW | Cette instruction permet de charger le «mot de contrôle» avec «source». | INTEL MPU 8087+
FLDENV | Cette instruction permet de charger l'environnement à partir de «source». | INTEL MPU 8087+
FLDL2E | Cette instruction permet de mettre le résultat du logarithme de «e» de la base 2 dans ST(0). | INTEL MPU 8087+
FLDL2T | Cette instruction permet de mettre le résultat du logarithme de 10 de la base 2 dans ST(0). | INTEL MPU 8087+
FLDLG2 | Cette instruction permet de mettre le résultat du logarithme de 2 de la base 10 dans ST(0). | INTEL MPU 8087+
FLDLN2 | Cette instruction permet de mettre le résultat du logarithme de «e» de la base 10 dans ST(0). | INTEL MPU 8087+
FLDPI | Cette instruction permet de mettre le résultat de la constante PI (Π) dans le registre ST(0). | INTEL MPU 8087+
FLDZ | Cette instruction permet de mettre le résultat de la constante 0,0 dans le registre ST(0). | INTEL MPU 8087+
FMUL | Cette instruction permet de multiplier le nombre réel de valeur positive «source» par «cible» et sauvegarde le résultat dans «cible». | INTEL MPU 8087+
FMULP | Cette instruction permet de multiplier le nombre réel de valeur positive «source» par «cible» et sauvegarde le résultat dans «cible» et prend ensuite ST(0) dans la pile de registres. | INTEL MPU 8087+
FNCLEX | Cette instruction permet d'éliminer et de gérer les exceptions non masquées. | INTEL MPU 8087+
FNDISI | Cette instruction permet de désactiver les interruptions et de gérer les exceptions non masquées. | INTEL MPU 8087
FNENI | Cette instruction permet d'activer les interruptions et de gérer les exceptions non masquées. | INTEL MPU 8087
FNINIT | Cette instruction permet d'initialiser le coprocesseur mathématique et de gérer les exceptions non masquées. | INTEL MPU 8087+
FNOP | Cette instruction permet de ne rien faire et de simplement passer à l'instruction suivante. | INTEL MPU 8087+
FNSAVE | Cette instruction permet de sauvegarder l'état courant du coprocesseur mathématique dans l'emplacement mémoire à partir de «source» et gérer les exceptions numériques non masquées. | INTEL MPU 8087+
FNSTCW | Cette instruction permet de sauvegarder le «mot de contrôle» dans «cible» et gérer les exceptions numériques non masquées. | INTEL MPU 8087+
FNSTENV | Cette instruction permet de copier l'environnement du coprocesseur mathématique vers une cible mais sans toutefois attendre que l'exception de nombre réel (virgule flottante) soit effacé. | INTEL MPU 8087+
FNSTSW | Cette instruction permet de copier le mot d'état du coprocesseur mathématique vers une cible mais sans toutefois attendre que l'exception de nombre réel (virgule flottante) soit effacé. | INTEL MPU 8087+
FPATAN | Cette instruction permet de calculer le résultat de l'arc tangente de ST(1) par ST(0) et de mettre le résultat dans le registre ST(0). | INTEL MPU 8087+
FPREM | Cette instruction permet de diviser le registre ST(0) par le registre ST(1) et enregistre le reste dans registre ST(0). | INTEL MPU 8087+
FPREM1 | Cette instruction permet de diviser le registre ST(0) par le registre ST(1) et enregistre le reste IEEE dans registre ST(0). | INTEL MPU 80387+
FPTAN | Cette instruction permet d'effectuer le calcule de la fonction trigonométrique de la tangente du registre ST(0) et enregistre son résultat dans le registre ST(0). | INTEL MPU 8087+
FRICHOP | Cette instruction permet d'effectuer le calcul de l'arrondissement de ST avec 0 décimal selon la méthode CHOP. | Cyrix 486 avec FPU
FRINEAR | Cette instruction permet d'effectuer le calcul de l'arrondissement de ST avec 0 décimal selon la méthode du plus proche. | Cyrix 486 avec FPU
FRINT2 | Cette instruction permet d'effectuer le calcul de l'arrondissement de ST avec 0 décimal selon la méthode du plus proche et si le nombre est exactement la moitié, alors l'instruction arrondit au signe de l'infini. | Cyrix 486 avec FPU
FRNDINT | Cette instruction permet d'arrondir le registre ST(0) à l'entier le plus proche et enregistre son résultat dans le registre ST(0). | INTEL MPU 8087+
FRSTOR | Cette instruction permet de restituer l'état du coprocesseur précédemment sauvegardé dans l'emplacement mémoire spécifié par source. | INTEL MPU 8087+
FSAVE | Cette instruction permet de sauvegarder l'état courant du coprocesseur dans l'emplacement mémoire spécifié par source. | INTEL MPU 8087+
FSCALE | Cette instruction permet d'effectuer la multiplication du registre ST(0) par 2 puissance le registre ST(1) et sauvegarde le résultat dans le registre ST(0). | INTEL MPU 8087+
FSETPM | Cette instruction permet de faire passer le coprocesseur mathématique en mode protégé. | INTEL MPU 80287
FSIN | Cette instruction permet d'effectuer le calcule de la fonction trigonométrique du sinus du registre ST(0) et le copie dans le registre ST(1), le registre ST(0) prend la valeur 1,0. | INTEL MPU 80387+
FSINCOS | Cette instruction permet d'effectuer le calcule de la fonction trigonométrique du sinus et du cosinus du registre ST(0) puis copie le résultat du sinus dans le registre ST(0) et le cosinus dans le registre ST(1). | INTEL MPU 80387+
FSQRT | Cette instruction permet d'extraire la racine carrée du registre ST(0) et de copier son résultat dans le registre ST(0). | INTEL MPU 8087+
FST | Cette instruction permet de copier la valeur réel contenu le registre ST(0) vers une cible. | INTEL MPU 8087+
FSTCW | Cette instruction permet de copier le mot de contrôle CW vers une cible. | INTEL MPU 8087+
FSTENV | Cette instruction permet de copier l'environnement du coprocesseur mathématique vers une cible. | INTEL MPU 8087+
FSTP | Cette instruction permet de copier un nombre entier et prendre le contenu du registre ST(0) dans la pile de registres (dépilage). | INTEL MPU 8087+
FSTSW | Cette instruction permet de copier le mot d'état du coprocesseur mathématique vers une cible. | INTEL MPU 8087+
FSUB | Cette instruction permet de soustraire un nombre entier du registre ST(0). | INTEL MPU 8087+
FSUBP | Cette instruction permet de soustraire un nombre entier du registre ST(0) et copie le registre ST(0) dans la pile de registres. | INTEL MPU 8087+
FSUBPP | Cette instruction permet de soustraire un nombre entier du registre ST(0) et copie le registre ST(0) dans la pile de registres. Cette instruction est déconseillée. | INTEL MPU 8087+
FSUBR | Cette instruction permet de soustraire le registre ST(0) du nombre entier et place le résultat dans le registre ST(0). | INTEL MPU 8087+
FSUBRP | Cette instruction permet de soustraire le registre ST(0) du nombre entier et place le résultat dans le registre ST(0) et copie le registre ST(0) dans la pile de registres. | INTEL MPU 8087+
FTST | Cette instruction permet de comparer le sommet de la pile avec la valeur 0,0 et définit les indicateurs d'états C0 et C3 de façon approprié. | INTEL MPU 8087+
FUCOM | Cette instruction compare le registre ST0 avec un opérande et fixe les drapeaux de façon approprié. | INTEL MPU 80387+
FUCOMI | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et vérifie l'ordre des valeurs et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats. | INTEL Pentium III+
FUCOMIP | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et vérifie l'ordre des valeurs et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats et désempile de la pile la valeur dans le registre. | INTEL Pentium III+
FUCOMP | Cette instruction compare le registre ST0 avec un opérande et fixe les drapeaux de façon approprié et désempile la pile. | INTEL MPU 80387+
FUCOMPP | Cette instruction compare le registre ST0 avec le registre ST1 et fixe les drapeaux de façon approprié et désempile les registres ST0 et ST1 de la pile. | INTEL MPU 80387+
FWAIT | Cette instruction permet d'attendre la fin de l'exécution d'une commande avant de poursuivre. | INTEL MPU 8087+
FXAM | Cette instruction permet d'examiner le sommet de la pile et définit les indicateurs d'état C0 et C3 de façon approprié. | INTEL MPU 8087+
FXCH | Cette instruction permet d'échanger le contenu d'une expression avec celle du registre ST(0) s'il est omis. | INTEL MPU 8087+
FXRSTOR | Cette instruction permet de restituer rapidement 94 (en mode 16 bits) ou 108 (en mode 32 bits) octets d'un contexte de coprocesseur mathématique vers la mémoire. | INTEL MMX-2+
FXSAVE | Cette instruction permet de sauvegarder rapidement 94 (en mode 16 bits) ou 108 (en mode 32 bits) octets d'un contexte de coprocesseur mathématique de la mémoire. | INTEL MMX-2+
FXTRACT | Cette instruction permet de copier l'exposant du registre ST(0) dans le registre ST(1) comme nombre entier puis copie la mantisse dans la registre ST(0) comme nombre entier. | INTEL MPU 8087+
FYL2X | Cette instruction permet de calculer la multiplication du registre ST(1) par le logarithme du registre ST(0) dans la base 2 et copie le résultat dans le registre ST(0). | INTEL MPU 8087+
FYL2XP1 | Cette instruction permet de calculer la multiplication du registre ST(1) par le logarithme du registre ST(0) plus 1 dans la base 2 et copie le résultat dans le registre ST(0). | INTEL MPU 8087+
HADDPD | Cette instruction permet d'effectuer l'addition horizontal de paquet de nombre réel de double précision des deux opérandes. | INTEL Pentium 4 (SSE3)+
HADDPS | Cette instruction permet d'effectuer l'addition horizontal de paquet de nombre réel de simple précision des deux opérandes. | INTEL Pentium 4 (SSE3)+
HLT | Cette instruction permet de faire passer le microprocesseur en mode d'arrêt. Toutefois, le processeur peut quitter cet état lorsqu'une ligne matérielle RESET ou lorsqu'une interruption non-masquable (NMI) reçoit un signal. | INTEL 8088+
HSUBPD | Cette instruction permet d'effectuer la soustraction horizontal de paquet de nombre réel de double précision des deux opérandes. | INTEL Pentium 4 (SSE3)+
HSUBPS | Cette instruction permet d'effectuer la soustraction horizontal de paquet de nombre réel de simple précision des deux opérandes. | INTEL Pentium 4 (SSE3)+
IBTS | Cette instruction permet de faire un tableau de bits du deuxième opérande et le met dans le premier. | INTEL 80386+
ICEBP | Cette instruction permet de passer en mode d'instruction ICE (In-Circuit Emulator) si le bit 12 du registre DR7 vaut 1 sinon il exécute l'interruption 1. | INTEL 80386 au Pentium Pro
IDIV | Cette instruction permet d'effectuer une division signée (nombre entier). | INTEL 8086+
IMUL | Cette instruction permet d'effectuer une multiplication signée (nombre entier). | INTEL 8086+
IN | Cette instruction permet de demander un octet, un mot ou un double mot provenant du port d'entrée/sortie et le retourne dans le registre accumulateur (AL, AX, EAX). | INTEL 8086+
INC | Cette instruction permet d'incrémenter un registre ou un emplacement mémoire. | INTEL 8086+
INS | Cette instruction permet de demander un octet, un mot ou un double mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | INTEL 8086+
INSB | Cette instruction permet de demander un octet du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction. | INTEL 80286+
INSD | Cette instruction permet de demander un double mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
INSERTPS | Cette instruction permet d'insérer une valeur réel de simple précision d'un opérande source dans l'emplacement d'un registre d'opérande de destination et met des 0 dans les données en dehors du masque de destination. | SSE4.1+
INSW | Cette instruction permet de demander un mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction. | INTEL 80286+
INT | Cette instruction permet d'exécuter l'interruption avec le numéro spécifié. | INTEL 8086+
INTO | Cette instruction permet d'exécuter l'interruption numéro 4 si le drapeau de débordement (OF) est fixé sur 1 | INTEL 8086+
INVD | Cette instruction permet de désactiver et de vider le tampon interne du micro-processeur. | INTEL 80486+
INVEPT | Cette instruction permet d'invalider la cartographie dans translation des tampons (TLB) et des caches de pagination structuré dérivé des tables de pages étendue (EPT). | INTEL VMX (Virtualisation)
INVLPG | Cette instruction permet d'invalider les transferts du TLB (Translation Lookaside Buffer) du micro-processeur | INTEL 80486+
INVLPGA | Cette instruction permet d'invalider la cartographie TLB (Translation Lookaside Buffer) pour une page virtuel et un ASID spécifié. | x86-64+
INVVPID | Cette instruction permet d'invalider la cartographie dans translation des tampons (TLB) et des caches de pagination structuré basé sur l'identificateur de processeur virtuel (VPID). | INTEL VMX (Virtualisation)
IRET | Cette instruction permet d'effectuer un retour précédemment provoquer par une interruption. | INTEL 8086+
IRETD | Cette instruction permet d'effectuer un retour 32-bits précédemment provoquer par une interruption. | INTEL 80386+
IRETQ | Cette instruction permet d'effectuer un retour 64-bits précédemment provoquer par une interruption. | x86-64+
JA | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si supérieur. | INTEL 8086+
JAE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si supérieur ou égal. | INTEL 8086+
JB | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si inférieur. | INTEL 8086+
JBE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si inférieur ou égal. | INTEL 8086+
JC | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si l'indicateur de retenue est égal à 1. | INTEL 8086+
JCXZ | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si CX = 0. | INTEL 8086+
JE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si zéro (égal). | INTEL 8086+
JECXZ | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si ECX = 0. | INTEL 80386+
JG | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si supérieur. | INTEL 8086+
JGE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si supérieur ou égal. | INTEL 8086+
JL | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si inférieur. | INTEL 8086+
JLE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si inférieur ou égal. | INTEL 8086+
JMP | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | INTEL 8086+
JNA | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas supérieur. | INTEL 8086+
JNAE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si ni supérieur ni égal. | INTEL 8086+
JNB | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas inférieur. | INTEL 8086+
JNC | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si indicateur de retenue égal à 0. | INTEL 8086+
JNE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas égal (zéro). | INTEL 8086+
JNG | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas supérieur. | INTEL 8086+
JNGE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si ni supérieur ni égal. | INTEL 8086+
JNL | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas inférieur. | INTEL 8086+
JNLE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si ni inférieur ni égal. | INTEL 8086+
JNO | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas de débordement (indicateur de débordement égal à 0). | INTEL 8086+
JNP | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas de parité. | INTEL 8086+
JNS | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas de signe. | INTEL 8086+
JNZ | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si pas zéro. | INTEL 8086+
JO | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si débordement (indicateur de débordement égal à 1). | INTEL 8086+
JP | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si parité. | INTEL 8086+
JPE | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si parité paire. | INTEL 8086+
JPO | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si parité impaire. | INTEL 8086+
JRCXZ | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si RCX = 0. | x86-64+
JS | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si signe. | INTEL 8086+
JZ | Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié si zéro. | INTEL 8086+
LAHF | Cette instruction permet de transférer les bits d'indicateurs du registre d'état vers le registre AH. | INTEL 8086+
LAR | Cette instruction permet de charger le registre des indicateurs d'un descripteur. | INTEL 80286+
LDDQU | Cette instruction permet de copier un quadruple mot d'une opérande source vers une opérande destination. | INTEL Pentium 4 (SSE3)+
LDMXCSR | Cette instruction permet d'effectuer le chargement du mot de contrôle et d'état du flux d'extension SIMD d'une opérande mémoire 32 bits. | INTEL Pentium III (KNI/MMX2)+
LDS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment DS et dans un registre d'offset spécifié. | INTEL 8086+
LEA | Cette instruction permet de copier l'offset d'une adresse de mémoire contenu dans un registre spécifié. | INTEL 8086+
LEAVE | Cette instruction permet de libérer une zone de mémoire attribué par l'instruction «ENTER» lorsqu'on utilise des procédures dans des langages de programmation de haut niveau. | INTEL 80286+
LES | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment ES et dans un registre d'offset spécifié. | INTEL 8086+
LFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant le LFENCE et les instructions de chargement suivant le LFENCE. | INTEL Pentium 4 (SSE2)+
LFS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment FS et dans un registre d'offset spécifié. | INTEL 80386+
LGDT | Cette instruction permet de charger un descripteur de tables globale. | INTEL 80286+
LGS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment GS et dans un registre d'offset spécifié. | INTEL 80386+
LIDT | Cette instruction permet de charger un descripteur de tables d'interruption. | INTEL 80286+
LLDT | Cette instruction permet de charger un descripteur de tables local. | INTEL 80286+
LMSW | Cette instruction permet de copier 4 des bits d'une opérande vers les 4 bits de registre de contrôle CR0. | INTEL 80286+
LOADALL | Cette instruction permet d'effectuer le chargement de tous les registres de descripteur de cache. | INTEL 80286 ou 80386
LOCK | Cette instruction est utilisé comme préfixe avec d'autres instructions pour amener le microprocesseur à émettre un signal de verrouillage (Lock) sur le bus lors du traitement de l'instruction suivante. | INTEL 8086+
LODS | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction. | INTEL 8086+
LODSB | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 1 en fonction de l'état du drapeau de direction. | INTEL 8086+
LODSD | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
LODSQ | Cette instruction permet de copier un élément de l'adresse DS:(R)SI dans le registre accumulateur et incrémente/décrémente le registre (R)SI de 8 en fonction de l'état du drapeau de direction. | x86-64+
LODSW | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 2 en fonction de l'état du drapeau de direction. | INTEL 8086+
LOOP | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0. | INTEL 8086+
LOOPD | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0. | INTEL 80386+
LOOPE | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1. | INTEL 8086+
LOOPED | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0 et si le drapeau ZF vaut 1. | INTEL 80386+
LOOPNE | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0. | INTEL 8086+
LOOPNED | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0 et si le drapeau ZF vaut 0. | INTEL 80386+
LOOPNZ | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0. | INTEL 8086+
LOOPNZD | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0 et si le drapeau ZF vaut 0. | INTEL 80386+
LOOPZ | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1. | INTEL 8086+
LOOPZD | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0 et si le drapeau ZF vaut 1. | INTEL 80386+
LSL | Cette instruction permet de charger la limite de segment d'un descripteur de segment spécifié avec l'opérande source dans l'opérande de destination et fixe le drapeau ZF du registre EFLAGS. | INTEL 80286+
LSS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment SS (Segment de pile) et dans un registre d'offset spécifié. | INTEL 80386+
LTR | Cette instruction permet de charger l'opérande source dans le champ du sélecteur de segment du registre de tâche. | INTEL 80286+
LZCNT | Cette instruction permet de compter le nombre de bits à 0 dans un registre 16, 32 ou 64 bits contenu dans l'opérande source. | AMD K10 (SSE4a)+
MASKMOVDQU | Cette instruction permet d'entreposer les octets sélectionnés par l'opérande source dans une emplacement mémoire de 128 bits. | INTEL Pentium 4 (SSE2)+
MASKMOVQ | Cette instruction permet d'entreposer les octets sélectionner de l'opérande source dans un emplacement mémoire de 64 bits. | Pentium III (KNI/MMX2)+
MAXPD | Cette instruction permet de retourner la valeur maximal de chacune des paires de valeur entre l'opérande source et l'opérande de destination de nombre réel de double précision. | INTEL Pentium 4 (SSE2)+
MAXPS | Cette instruction permet de retourner la valeur maximal de chacune des paires de valeur entre l'opérande source et l'opérande de destination. | Pentium III (KNI/MMX2)+
MAXSD | Cette instruction permet de retourner la valeur maximal entre l'opérande source et destination de nombre réel de simple précision. | INTEL Pentium 4 (SSE2)+
MAXSS | Cette instruction permet de retourner la valeur maximal entre l'opérande source et destination. | Pentium III (KNI/MMX2)+
MFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant le MFENCE et les instructions de chargement et d'entreposage précédent le MFENCE. | INTEL Pentium 4 (SSE2)+
MINPD | Cette instruction permet de retourner la valeur minimal de chacune des paires de valeur entre l'opérande source et l'opérande de destination de nombre réel de double précision. | INTEL Pentium 4 (SSE2)+
MINPS | Cette instruction permet de retourner la valeur minimal de chacune des paires de valeur entre l'opérande source et l'opérande de destination. | Pentium III (KNI/MMX2)+
MINSD | Cette instruction permet de retourner la valeur minimal entre l'opérande source et destination de nombre réel de simple précision. | INTEL Pentium 4 (SSE2)+
MINSS | Cette instruction permet de retourner la valeur minimal entre l'opérande source et destination. | Pentium III (KNI/MMX2)+
MONITOR | Cette instruction permet d'indiquer au microprocesseur quel rangé d'adresse est à surveiller par l'instruction STORE. | INTEL Pentium 4+
MOV | Cette instruction permet de copier opérande source dans une opérande destinataire. | INTEL 8086+
MOVAPD | Cette instruction permet de copier le contenu de 2 paquets alignés de valeurs réel de double précision. | INTEL Pentium 4 (SSE2)+
MOVAPS | Cette instruction permet de copier le contenu de 4 paquets alignés de valeurs réel de simple précision (4 x 32 bits). | Pentium III (KNI/MMX2)+
MOVBE | Cette instruction permet d'effectuer l'échange des octets lors de l'opération de copiage de l'opérande source dans l'opérande de destination. | SSE4.2+
MOVD | Cette instruction permet de copier l'opérande dans un registre XMM ou vice-versa. | INTEL Pentium MMX+
MOVDDUP | Cette instruction permet de copier les 64 bits d'une opérande dans la partie basse et haute d'une opérande de 128 bits. | INTEL Pentium 4 (SSE3)+
MOVDQ2Q | Cette instruction permet de copier la partie basse d'un quadruple mots d'un opérande source vers un opérande de destination. | INTEL Pentium 4 (SSE2)+
MOVDQA | Cette instruction permet de copier un double quadruple mots d'un opérande source vers un opérande de destination. | INTEL Pentium 4 (SSE2)+
MOVDQU | Cette instruction permet de copier un double quadruple mots désaligné d'un opérande source vers un opérande de destination. | INTEL Pentium 4 (SSE2)+
MOVHLPS | Cette instruction permet de copier le contenu du haut d'un paquet de valeurs réel de simple précision dans sa partie basse. | Pentium III (KNI/MMX2)+
MOVHPD | Cette instruction permet de copier le contenu du haut de deux paquets de valeurs réel de double précision dans une opérande de destination. | INTEL Pentium 4 (SSE2)+
MOVHPS | Cette instruction permet de copier le contenu du haut de deux paquets de valeurs réel de simple précision dans une opérande de destination. | Pentium III (KNI/MMX2)+
MOVLHPS | Cette instruction permet de copier le contenu du bas d'un paquet de valeurs réel de simple précision dans sa partie haute. | Pentium III (KNI/MMX2)+
MOVLPD | Cette instruction permet de copier le contenu du bas de deux paquets de valeurs réel de double précision dans un opérande de destination. | INTEL Pentium 4 (SSE2)+
MOVLPS | Cette instruction permet de copier le contenu du bas de deux paquets de valeurs réel de simple précision dans un opérande de destination. | Pentium III (KNI/MMX2)+
MOVMSKPD | Cette instruction permet de copier les bits de signes de deux paquets de valeurs réels de double précision d'un registre XMM dans les 2 bits les plus bas d'un registre 32 bits. Les autres bits du registres 32 bits sont fixés à 0. | INTEL Pentium 4 (SSE2)+
MOVMSKPS | Cette instruction permet de copier les bits de signes de quatre paquets de valeurs réels de simple précision d'un registre XMM dans les 4 bits les plus bas d'un registre 32 bits. Les autres bits du registres 32 bits sont fixés à 0. | INTEL Pentium 3 (SSE)+
MOVNTI | Cette instruction permet de copier une valeur 32 ou 64 bits dans un emplacement mémoire afin de minimiser la pollution du cache dans un processus léger. | INTEL Pentium 4 (SSE2)+
MOVNTDQ | Cette instruction permet de copier le contenu de double quadruple mots d'un opérande source vers un opérande de destination sans utiliser la méthode temporel pour minimiser la pollution du cache. | SSE4.1+
MOVNTDQA | Cette instruction permet de copier le contenu aligné de double quadruple mots d'un opérande source vers un opérande de destination sans utiliser la méthode temporel pour minimiser la pollution du cache. | SSE4.1+
MOVNTPD | Cette instruction permet de copier le contenu de valeur réel de double précision d'un opérande source vers un opérande de destination sans utiliser la méthode temporel pour minimiser la pollution du cache. | INTEL Pentium 4 (SSE2)+
MOVNTPS | Cette instruction permet de copier le contenu de 4 paquets alignés de valeurs réel de simple précision sans utiliser la méthode temporel pour minimiser la pollution du cache. | Pentium III (KNI/MMX2)+
MOVNTQ | Cette instruction permet de copier une valeur 64 bits sans utiliser la méthode temporel pour minimiser la pollution du cache. | Pentium III (KNI/MMX2)+
MOVQ | Cette instruction permet de copier un quadruple mot d'une opérande source vers une opérande destination dans le cas des registres XMM. | INTEL Pentium MMX+
MOVQ2DQ | Cette instruction permet de copier un quadruple mot d'un opérande source vers la partie basse d'un opérande destination dans le cas des registres XMM. | INTEL Pentium 4 (SSE2)+
MOVS | Cette instruction permet de copier un élément de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction. | INTEL 8086+
MOVSB | Cette instruction permet de copier un octet de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 1 en fonction de l'état du drapeau de direction. | INTEL 8086+
MOVSD | Cette instruction permet de copier un double mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
MOVSD | Cette instruction permet de copier un scalaire de valeur de double précision d'un opérande source vers un opérande destination. | INTEL Pentium 4 (SSE2)+
MOVSHDUP | Cette instruction permet de copier la partie du haut de 32 bits d'une valeur 64 bits dans sa partie basse et haute d'une valeur réel de simple précision de 64 bits contenu dans un paquet de 128 bits. | INTEL Pentium 4 (SSE3)+
MOVSLDUP | Cette instruction permet de copier la partie du basse de 32 bits d'une valeur 64 bits dans sa partie basse et haute d'une valeur réel de simple précision de 64 bits contenu dans un paquet de 128 bits. | INTEL Pentium 4 (SSE3)+
MOVSQ | Cette instruction permet de copier un quadruple mot de l'adresse DS:(R)SI dans l'adresse ES:(R)DI et incrémente/décrémente les registres (R)DI et (R)SI de 8 en fonction de l'état du drapeau de direction. | x86-64+
MOVSS | Cette instruction permet de copier une valeur réel de simple précision d'une opérande source vers une opérande de destination. | Pentium III (KNI/MMX2)+
MOVSW | Cette instruction permet de copier un mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 2 en fonction de l'état du drapeau de direction. | INTEL 8086+
MOVSX | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires avec l'extension des signes. | INTEL 80386+
MOVSXD | Cette instruction permet de copier un registre de taille inférieur dans un registre 64 bits en remplissant les bits supplémentaires avec l'extension des signes. | x86-64+
MOVUPD | Cette instruction permet de copier le contenu de 2 paquets désalignés de valeurs réel de double précision. | Intel Pentium 4 (SSE2)+
MOVUPS | Cette instruction permet de copier le contenu de 4 paquets désalignés de valeurs réel de simple précision (4 x 32 bits). | Pentium III (KNI/MMX2)+
MOVZX | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires par des 0. | INTEL 80386+
MPSADBW | Cette instruction permet d'effectuer le calcul de la somme de la différence absolue (SAD) d'une paire d'octets d'un groupe de 4 octets paires et produit 8 résultats SAD entreposé dans 8 entier contenu dans l'opérande de destination. | SSE4.1+
MUL | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). | INTEL 8086+
MULPD | Cette instruction permet d'effectuer la multiplication de chacune des paires de valeur de double précision de l'opérande source et l'opérande de destination. | Intel Pentium 4 (SSE2)+
MULPS | Cette instruction permet d'effectuer la multiplication de chacune des paires de valeur de l'opérande source et l'opérande de destination. | Pentium III (KNI/MMX2)+
MULSD | Cette instruction permet d'effectuer la multiplication scalaire de valeurs réel de double précision de l'opérande source et l'opérande de destination. | Intel Pentium 4 (SSE2)+
MULSS | Cette instruction permet d'effectuer la multiplication scalaire de l'opérande source et l'opérande de destination. | Pentium III (KNI/MMX2)+
MWAIT | Cette instruction permet d'indiquer au microprocesseur que l'état de l'alimentation de la ligne de cache est en attente d'écriture dans la plage d'adresse, mettant fin à la plupart des activités dans le noyau en le faisant. | INTEL Pentium 4+
NEG | Cette instruction permet d'effectuer le complément à 2 d'une opérande. | INTEL 8086+
NOP | Cette instruction ne fait rien. | INTEL 8086+
NOT | Cette instruction permet d'inverser la valeur de chacun des bits d'une opérande. | INTEL 8086+
OIO | Cette instruction permet de provoquer l'exécution d'un code indéfinie. | Cyrix Cx6x86/AMD Am5k86
OR | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandes spécifiés. | INTEL 8086+
ORPD | Cette instruction permet d'effectuer un OU BINAIRE de 128 bits sur les 2 opérandes réels de double précisions spécifiés. | Intel Pentium 4 (SSE2)+
ORPS | Cette instruction permet d'effectuer un OU BINAIRE de 128 bits sur les 2 opérandes spécifiés. | Pentium III (KNI/MMX2)+
OUT | Cette instruction permet d'envoyer un octet, un mot ou un double mot sur le port d'entrée/sortie. | INTEL 8086+
OUTS | Cette instruction permet d'envoyer un octet, un mot ou un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | INTEL 80286+
OUTSB | Cette instruction permet d'envoyer un octet contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 1 en fonction de l'état du drapeau de direction. | INTEL 80286+
OUTSD | Cette instruction permet d'envoyer un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
OUTSW | Cette instruction permet d'envoyer un mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 2 en fonction de l'état du drapeau de direction. | INTEL 80286+
PABSB | Cette instruction permet d'effectuer le calcul de la valeur absolue de chacun des octets d'un opérande source et entrepose le résultat dans un opérande destination. | SSSE3+
PABSD | Cette instruction permet d'effectuer le calcul de la valeur absolue de chacun des doubles mots d'un opérande source et entrepose le résultat dans un opérande destination. | SSSE3+
PABSW | Cette instruction permet d'effectuer le calcul de la valeur absolue de chacun des mots d'un opérande source et entrepose le résultat dans un opérande destination. | SSSE3+
PACKSSDW | Cette instruction permet de compacté 8 paquets de double mots en mots. | INTEL Pentium MMX+
PACKSSWB | Cette instruction permet de compacté 8 paquets d'entier en octets. | INTEL Pentium MMX+
PACKUSDW | Cette instruction permet de compacté 8 paquets de double mots naturel en mots naturel. | SSE4.1+
PACKUSWB | Cette instruction permet de compacté 8 paquets de mots en octets. | INTEL Pentium Pro+
PADDB | Cette instruction permet d'effectuer une addition scalaire sur un paquet de 8 octets. | INTEL Pentium Pro+
PADDD | Cette instruction permet d'effectuer une addition scalaire sur un paquet de 2 double mots. | INTEL Pentium Pro+
PADDQ | Cette instruction permet d'effectuer une addition scalaire sur un paquet de quadruple mots. | INTEL Pentium 4 (SSE2)+
PADDSB | Cette instruction permet d'effectuer une addition scalaire avec saturation sur un paquet de 8 octets signés. | INTEL Pentium Pro+
PADDSIW | Cette instruction permet d'effectuer l'addition du mot de format entier de l'opérande source au mot de format entier de l'opérande de destination et écrit le résultat dans le registre MMX. | Cyrix 6x86MX (EMMX)+
PADDSW | Cette instruction permet d'effectuer une addition scalaire avec saturation sur un paquet de 4 entiers. | INTEL Pentium Pro+
PADDUSB | Cette instruction permet d'effectuer une addition scalaire avec saturation sur un paquet de 8 octets. | INTEL Pentium Pro+
PADDUSW | Cette instruction permet d'effectuer une addition scalaire avec saturation sur un paquet de 4 mots. | INTEL Pentium Pro+
PADDW | Cette instruction permet d'effectuer une addition scalaire sur un paquet de 4 mots. | INTEL Pentium Pro+
PALIGNR | Cette instruction permet d'effectuer la concaténation de l'opérande de destination et de l'opérande source et effectue un décalage d'une constante immédiate de la composante de granulité d'octets, et enfin extrait le résultat aligné dans l'opérande de destination. | SSSE3+
PAND | Cette instruction permet d'effectuer un «ET BINAIRE» d'un quadruple mot d'une opérande source avec une opérande destination dans le cas des registres XMM. | INTEL Pentium MMX+
PANDN | Cette instruction permet d'effectuer un «ET BINAIRE» et une «NEGATION» de chacun des bits d'un quadruple mot d'une opérande source avec une opérande destination dans le cas des registres XMM. | INTEL Pentium Pro+
PAUSE | Cette instruction permet d'améliorer les performances des boucles de «SPIN», en fournissant une indication pour le microprocesseur que le code courant est dans une boucle en «SPIN». | INTEL Pentium 4 (SSE2)+
PAVEB | Cette instruction permet d'effectuer le calcul de la moyenne des paquets spécifiés. | Cyrix 6x86MX (EMMX)+
PAVGB | Cette instruction permet d'effectuer le calcul de la moyenne des paquets d'octets spécifiés. | Intel Pentium III (SSE)+
PAVGUSB | Cette instruction permet d'effectuer le calcul de la moyenne de paquets de 8 octets spécifiés. | AMD 3DNow!
PAVGW | Cette instruction permet d'effectuer le calcul de la moyenne des paquets des mots spécifiés. | Intel Pentium III (SSE)+
PBLENDVB | Cette instruction permet d'effectuer une copie conditionnel d'un élément d'octets d'un opérande source vers un opérande de destination en fonction des bits de masque définit dans un troisième opérande. | SSE4.1+
PBLENDW | Cette instruction permet d'effectuer une copie conditionnel d'un élément d'octets d'un opérande source vers un opérande de destination en fonction des bits de masque définit dans un troisième opérande. | SSE4.1+
PCLMULQDQ | Cette instruction permet d'effectuer une multiplication de quadruple mots avec une retenue en sélectionnant l'opérande destination et source et une valeur immédiate pour sélectionner les critères. | INTEL AES+
PCMPEQB | Cette instruction permet d'effectuer une comparaison sur un paquet d'octets et fixe la valeur de chacun d'eux à FFh s'ils sont égales sinon à 00h. | INTEL Pentium Pro+
PCMPEQD | Cette instruction permet d'effectuer une comparaison sur un paquet de double mots et fixe la valeur de chacun d'eux à FFFFFFFFh s'ils sont égales sinon à 00000000h. | INTEL Pentium Pro+
PCMPEQQ | Cette instruction permet d'effectuer une comparaison d'égalité SIMD d'un paquet de quadruple mots de l'opérande destination et de l'opérande source. | SSE4.1+
PCMPEQW | Cette instruction permet d'effectuer une comparaison sur un paquet de mots et fixe la valeur de chacun d'eux à FFFFh s'ils sont égales sinon à 0000h. | INTEL Pentium Pro+
PCMPESTRI | Cette instruction permet d'effectuer une comparaison ainsi qu'un processus de fragments de deux chaine de caractères basé sur une valeur d'encodage indiquer par un opérande immédiate et génère un index entreposé dans le registre ECX. | Nehalem (SSE4.2)+
PCMPESTRM | Cette instruction permet d'effectuer une comparaison ainsi qu'un processus de fragments de deux chaine de caractères basé sur une valeur d'encodage indiquer par un opérande immédiate et génère un masque entreposé dans le registre XMM0. | Nehalem (SSE4.2)+
PCMPGTB | Cette instruction permet d'effectuer une comparaison sur un paquet d'octets et fixe la valeur de chacun d'eux à FFh si l'opérande destinataire est supérieur à l'opérande source sinon à 00h. | INTEL Pentium Pro+
PCMPGTD | Cette instruction permet d'effectuer une comparaison sur un paquet de double mots et fixe la valeur de chacun d'eux à FFFFFFFFFh si l'opérande destinataire est supérieur à l'opérande source sinon à 00000000h. | INTEL Pentium Pro+
PCMPGTQ | Cette instruction permet d'effectuer une comparaison sur un paquet de quadruple mots et fixe la valeur de chacun d'eux à FFFFFFFFFFFFFFFFh si l'opérande destinataire est supérieur à l'opérande source sinon à 0000000000000000h. | Nehalem (SSE4.2)+
PCMPGTW | Cette instruction permet d'effectuer une comparaison sur un paquet de mots et fixe la valeur de chacun d'eux à FFFFFh si l'opérande destinataire est supérieur à l'opérande source sinon à 0000h. | INTEL Pentium Pro+
PCMPISTRI | Cette instruction permet d'effectuer une comparaison ainsi qu'un processus de fragments de deux chaines de caractères basé sur une valeur d'encodage implicite indiquer par un opérande immédiate et génère un index entreposé dans le registre ECX. | Nehalem (SSE4.2)+
PCMPISTRM | Cette instruction permet d'effectuer une comparaison ainsi qu'un processus de fragments de deux chaine de caractères basé sur une valeur d'encodage implicite indiquer par un opérande immédiate et génère un masque entreposé dans le registre XMM0. | Nehalem (SSE4.2)+
PDISTIB | Cette instruction permet d'effectuer le calcul de la distance entre des octets de deux opérandes, le résultat de l'addition d'octet de l'opérande de destination et la saturation du résultat. | Cyrix 6x86MX (EMMX)+
PEXTRB | Cette instruction permet de copier l'octet de l'opérande source spécifié par un compteur d'opérande dans l'opérande de destination. | SSE4.1+
PEXTRD | Cette instruction permet de copier le double mot de l'opérande source spécifié par un compteur d'opérande dans l'opérande de destination. | SSE4.1+
PEXTRQ | Cette instruction permet de copier le quadruple mot de l'opérande source spécifié par un compteur d'opérande dans l'opérande de destination. | SSE4.1+
PEXTRW | Cette instruction permet de copier le mot de l'opérande source spécifié par un compteur d'opérande dans l'opérande de destination. | INTEL Pentium III (KNI/MMX2)+
PF2ID | Cette instruction permet de convertir un double mots d'un format réel à un format d'entier 32 bits. | AMD 3DNow!
PF2IW | Cette instruction permet de convertir un double mots d'un format réel à un format d'entier 16 bits. | AMD 3DNow!
PFACC | Cette instruction permet d'effectuer l'accumulation de double mots. | AMD 3DNow!
PFADD | Cette instruction permet d'effectuer l'addition de double mots. | AMD 3DNow!
PFCMPEQ | Cette instruction permet d'effectuer la comparaison d'égalité d'un paquet de double mots contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFCMPGE | Cette instruction permet d'effectuer la comparaison d'égalité ou de supériorité d'un paquet de double mots contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFCMPGT | Cette instruction permet d'effectuer la comparaison de supériorité d'un paquet de double mots contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFMAX | Cette instruction permet de retourner la valeur maximal de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFMIN | Cette instruction permet de retourner la valeur minimal de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFMUL | Cette instruction permet d'effectuer la multiplication de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFNACC | Cette instruction permet d'effectuer l'accumulation négative de double mots. | AMD 3DNow!
PFPNACC | Cette instruction permet d'effectuer un mixe d'accumulation positive et négative de double mots. | AMD 3DNow!
PFRCP | Cette instruction permet d'effectuer la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFRCPIT1 | Cette instruction permet d'effectuer la première étape d'itération de la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFRCPIT2 | Cette instruction permet d'effectuer la deuxième étape d'itération de la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFRSQIT1 | Cette instruction permet d'effectuer la première étape d'itération de la racine carré de la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFRSQRT | Cette instruction permet d'effectuer la racine carré approximative de la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFSUB | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PFSUBR | Cette instruction permet d'effectuer la soustraction inversé de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | AMD 3DNow!
PHADDD | Cette instruction permet d'effectuer l'addition de double mot entier horizontalement adjacent d'un opérande source et opérande destination et met le résultat dans l'opérande destination. | SSSE3+
PHADDSW | Cette instruction permet d'effectuer l'addition de mot entier horizontalement adjacent avec saturation d'un opérande source et opérande destination et met le résultat dans l'opérande destination. | SSSE3+
PHADDW | Cette instruction permet d'effectuer l'addition de mot entier horizontalement adjacent d'un opérande source et opérande destination et met le résultat dans l'opérande destination. | SSSE3+
PHMINPOSUW | Cette instruction permet de demander le minimum des valeurs de mot de l'opérande source et place dans la partie basse de l'opérande le mot. | SSE4.1+
PHSUBD | Cette instruction permet d'effectuer la soustraction de double mot entier horizontalement adjacent d'un opérande source et opérande destination et met le résultat dans l'opérande destination. | SSSE3+
PHSUBSW | Cette instruction permet d'effectuer la soustraction de mot entier horizontalement adjacent avec saturation d'un opérande source et opérande destination et met le résultat dans l'opérande destination. | SSSE3+
PHSUBW | Cette instruction permet d'effectuer la soustraction de mot entier horizontalement adjacent d'un opérande source et opérande destination et met le résultat dans l'opérande destination. | SSSE3+
PI2FD | Cette instruction permet de convertir un paquet de format d'entier 32 bits à double mots d'un format réel. | AMD 3DNow!
PI2FW | Cette instruction permet de convertir un paquet de format d'entier 16 bits à double mots d'un format réel. | AMD 3DNow!
PINSRB | Cette instruction permet d'effectuer une copie d'un octet d'un opérande source et de l'insérer dans l'opérande de destination de l'emplacement spécifié par un compteur d'opérande. | SSE4.1+
PINSRD | Cette instruction permet d'effectuer une copie d'un double mot d'un opérande source et de l'insérer dans l'opérande de destination de l'emplacement spécifié par un compteur d'opérande. | SSE4.1+
PINSRQ | Cette instruction permet d'effectuer une copie d'un quadruple mot d'un opérande source et de l'insérer dans l'opérande de destination de l'emplacement spécifié par un compteur d'opérande. | SSE4.1+
PINSRW | Cette instruction permet d'effectuer une copie d'un mot d'un opérande source et de l'insérer dans l'opérande de destination de l'emplacement spécifié par un compteur d'opérande. | INTEL Pentium III (KNI/MMX2)+
PMACHRIW | Cette instruction permet d'effectuer une multiplication de 2 opérandes sources en utilisant la méthode décrite par PMULHRW et accumule le résultat avec la valeur dans un registre de destination en utilisant un arrondissement arithmétique. | Cyrix 6x86MX (EMMX)+
PMADDUBSW | Cette instruction permet d'effectuer une multiplication vertical de chacun des octets d'un opérande de destination avec les octets (entier) d'un opérande source et produit des entiers 16 bits intermédiaire. | SSSE3+
PMADDWD | Cette instruction permet d'effectuer une multiplication de 2 registres MMX contenant dans un paquet de mots d'un emplacement/mémoire. | INTEL Pentium Pro+
PMAGW | Cette instruction permet d'effectuer la comparaison de la valeur absolue d'un paquet de mots de l'opérande source et de l'ensemble des mots de destination et fixe l'opérande de destination avec la valeur de la plus large magnétude. | Cyrix 6x86MX (EMMX)+
PMAXSB | Cette instruction permet de retourner la valeur maximal de chacun des octets (entier) des paquets contenu dans deux opérandes. | SSE4.1+
PMAXSD | Cette instruction permet de retourner la valeur maximal de chacun des doubles mots des paquets contenu dans deux opérandes. | SSE4.1+
PMAXSW | Cette instruction permet de retourner la valeur maximal de chacun des mots (entier) des paquets contenu dans deux opérandes. | INTEL Pentium III (KNI/MMX2)+
PMAXUB | Cette instruction permet de retourner la valeur maximal de chacun des octets des paquets contenu dans deux opérandes. | INTEL Pentium III (KNI/MMX2)+
PMAXUD | Cette instruction permet de retourner la valeur maximal de chacun des doubles mots (naturel) des paquets contenu dans deux opérandes. | SSE4.1+
PMAXUW | Cette instruction permet de retourner la valeur maximal de chacun des mots (naturel) des paquets contenu dans deux opérandes. | SSE4.1+
PMINSB | Cette instruction permet de retourner la valeur minimal de chacun des octets (entier) des paquets contenu dans deux opérandes. | SSE4.1+
PMINSD | Cette instruction permet de retourner la valeur minimal de chacun des doubles mots des paquets contenu dans deux opérandes. | SSE4.1+
PMINSW | Cette instruction permet de retourner la valeur minimal de chacun des mots des paquets contenu dans deux opérandes. | INTEL Pentium III (KNI/MMX2)+
PMINUB | Cette instruction permet de retourner la valeur minimal de chacun des octets des paquets contenu dans deux opérandes. | INTEL Pentium III (KNI/MMX2)+
PMINUD | Cette instruction permet de retourner la valeur minimal de chacun des doubles mots (naturel) des paquets contenu dans deux opérandes. | SSE4.1+
PMOVMSKB | Cette instruction permet de copiés les masques de chacun des octets d'un paquet contenu dans une opérande. | INTEL Pentium III (KNI/MMX2)+
PMOVSXBD | Cette instruction permet d'étendre les signes du paquet des entiers de 8 bits de la partie basse de l'opérande source en entiers 32 bits dans l'opérande de destination. | SSE4.1+
PMOVSXBQ | Cette instruction permet d'étendre les signes du paquet des entiers de 8 bits de la partie basse de l'opérande source en entiers 64 bits dans l'opérande de destination. | SSE4.1+
PMOVSXBW | Cette instruction permet d'étendre les signes du paquet des entiers de 8 bits de la partie basse de l'opérande source en entiers 16 bits dans l'opérande de destination. | SSE4.1+
PMOVSXDQ | Cette instruction permet d'étendre les signes du paquet des entiers de 32 bits de la partie basse de l'opérande source en entiers 64 bits dans l'opérande de destination. | SSE4.1+
PMOVSXWD | Cette instruction permet d'étendre les signes du paquet des entiers de 16 bits de la partie basse de l'opérande source en entiers 32 bits dans l'opérande de destination. | SSE4.1+
PMOVSXWQ | Cette instruction permet d'étendre les signes du paquet des entiers de 16 bits de la partie basse de l'opérande source en entiers 64 bits dans l'opérande de destination. | SSE4.1+
PMOVZXBD | Cette instruction permet d'étendre les zéros du paquet des entiers de 8 bits de la partie basse de l'opérande source en entiers 32 bits dans l'opérande de destination. | SSE4.1+
PMOVZXBQ | Cette instruction permet d'étendre les zéros du paquet des entiers de 8 bits de la partie basse de l'opérande source en entiers 64 bits dans l'opérande de destination. | SSE4.1+
PMOVZXBW | Cette instruction permet d'étendre les zéros du paquet des entiers de 8 bits de la partie basse de l'opérande source en entiers 16 bits dans l'opérande de destination. | SSE4.1+
PMOVZXDQ | Cette instruction permet d'étendre les zéros du paquet des entiers de 32 bits de la partie basse de l'opérande source en entiers 64 bits dans l'opérande de destination. | SSE4.1+
PMOVZXWD | Cette instruction permet d'étendre les zéros du paquet des entiers de 16 bits de la partie basse de l'opérande source en entiers 32 bits dans l'opérande de destination. | SSE4.1+
PMOVZXWQ | Cette instruction permet d'étendre les zéros du paquet des entiers de 16 bits de la partie basse de l'opérande source en entiers 64 bits dans l'opérande de destination. | SSE4.1+
PMULDQ | Cette instruction permet d'effectuer la multiplication de deux valeurs signés de deux paires de double mots entier et entrepose les résultats dans un opérande en paquet de 64 bits. | SSE4.1+
PMULHRIW | Cette instruction permet de retourner le résultat d'une matrice de 16x16 bits avec un arrondissement LSB avant de tronquer les 16 bits et place ce résultat dans un registre MMX. | Cyrix 6x86MX (EMMX)+
PMULHRSW | Cette instruction permet d'effectuer multiplication vertical de chaque entier de 16 bits de l'opérande de destination avec l'opérande source et produit un résultat d'entiers de 32 bits dans l'opérande de destination. | SSSE3+
PMULHRW | Cette instruction permet de retourner le résultat d'une matrice de 16x16 bits avec un arrondissement LSB avant de tronquer les 16 bits. | Cyrix 6x86MX (EMMX)+
PMULHUW | Cette instruction permet d'effectuer la multiplication de la partie haute de chacun des entiers des 2 paquets d'opérandes. | INTEL Pentium III (KNI/MMX2)+
PMULHW | Cette instruction permet d'effectuer la multiplication de la partie haute de chacun des mots des 2 paquets d'opérandes. | INTEL Pentium Pro+
PMULLD | Cette instruction permet d'effectuer la multiplication de la partie basse de chacun des double mots des 2 paquets d'opérandes. | SSE4.1+
PMULLW | Cette instruction permet d'effectuer la multiplication de la partie basse de chacun des mots des 2 paquets d'opérandes. | INTEL Pentium Pro+
PMULUDQ | Cette instruction permet d'effectuer la multiplication de paquets d'opérandes de double mots. | INTEL Pentium 4 (SSE2)+
PMVGEZB | Cette instruction permet de copier l'octet de paquet correspondant de l'opérande source dans l'opérande de destination si l'octet de l'opérande destination est supérieur à 0 et effectue se traitement pour chacun des 8 octets du paquet. | Cyrix 6x86MX (EMMX)+
PMVLZB | Cette instruction permet de copier l'octet de paquet correspondant de l'opérande source dans l'opérande de destination si l'octet de l'opérande destination est inférieur à 0 et effectue se traitement pour chacun des 8 octets du paquet. | Cyrix 6x86MX (EMMX)+
PMVNZB | Cette instruction permet de copier l'octet de paquet correspondant de l'opérande source dans l'opérande de destination si l'octet de l'opérande destination ne vaut pas 0 et effectue se traitement pour chacun des 8 octets du paquet. | Cyrix 6x86MX (EMMX)+
PMVZB | Cette instruction permet de copier l'octet de paquet correspondant de l'opérande source dans l'opérande de destination si l'octet de l'opérande destination vaut 0 et effectue se traitement pour chacun des 8 octets du paquet. | Cyrix 6x86MX (EMMX)+
POP | Cette instruction permet de désempiler de la pile un mot ou un double mot et la met dans une opérande. | INTEL 8086+
POPA | Cette instruction permet de désempiler de la pile respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX. | INTEL 80286+
POPAD | Cette instruction permet de désempiler de la pile respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX. | INTEL 80386+
POPCNT | Cette instruction permet de compter le nombre de bits à 1 que possède une opérande source et place le résultat dans un registre destinataire. | AMD K10 (SSE4a)+
POPF | Cette instruction permet de désempiler de la pile le registre 16 bits de drapeau contenant les indicateurs d'état. | INTEL 8086+
POPFD | Cette instruction permet de désempiler de la pile le registre 32 bits de drapeau contenant les indicateurs d'état. | INTEL 80386+
POPFQ | Cette instruction permet de désempiler de la pile le registre 64 bits de drapeau (RFLAGS) contenant les indicateurs d'état. | x86-64+
POR | Cette instruction permet d'effectuer un «OU BINAIRE» d'un quadruple mot d'une opérande source avec une opérande destination dans le cas des registres XMM. | INTEL Pentium MMX+
PREFETCH | Cette instruction permet d'effectuer le chargement de l'entrée d'une séquence d'alignement de mémoire de 64 bits de l'adresse mémoire spécifié dans le cache de données L1 du microprocesseur. | AMD K6-2+
PREFETCH0 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T0 du microprocesseur. Alias de PREFETCHT0. | INTEL Pentium III (SSE)+
PREFETCH1 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T1 du microprocesseur. Alias de PREFETCHT1. | INTEL Pentium III (SSE)+
PREFETCH2 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T2 du microprocesseur. Alias de PREFETCHT2. | INTEL Pentium III (SSE)+
PREFETCHNTA | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données NTA du microprocesseur. | INTEL Pentium III (SSE)+
PREFETCHT0 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T0 du microprocesseur. Alias de PREFETCH0. | INTEL Pentium III (SSE)+
PREFETCHT1 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T1 du microprocesseur. Alias de PREFETCH1. | INTEL Pentium III (SSE)+
PREFETCHT2 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T2 du microprocesseur. Alias de PREFETCH2. | INTEL Pentium III (SSE)+
PREFETCHW | Cette instruction permet d'effectuer le chargement de l'entrée d'une séquence d'alignement de mémoire de 64 bits de l'adresse mémoire spécifié dans le cache de données L1 du microprocesseur dans un état de modification. | AMD K6-2+
PSADBW | Cette instruction permet d'effectuer le calcul la valeur de absolue de la différence des octets de paquet contenu dans une opérande source et destination. | INTEL Pentium III (SSE)+
PSHUFB | Cette instruction permet d'effectuer un mélange des octets en place dans l'opérande de destination avec un masque de contrôle dans l'opérande source. | SSSE3+
PSHUFD | Cette instruction permet de copier un double mots d'une opérande source avec emplacement spécifié par un opérande immédiate dans un opérande de destination. | INTEL Pentium 4 (SSE2)+
PSHUFHW | Cette instruction permet de copier un mot d'une opérande source avec emplacement spécifié par un opérande immédiate dans la partie haute d'un opérande de destination. | INTEL Pentium 4 (SSE2)+
PSHUFLW | Cette instruction permet de copier un mot d'une opérande source avec emplacement spécifié par un opérande immédiate dans la partie basse d'un opérande de destination. | INTEL Pentium 4 (SSE2)+
PSHUFW | Cette instruction permet de copier une double mots d'un opérande source avec emplacement spécifié par un opérande immédiate dans un opérande de destination. | INTEL Pentium III (SSE)+
PSIGNB | Cette instruction permet d'effectuer la négation de chaque octets de l'opérande de destination si la valeur du signe de l'entier des octets correspondant à l'opérande source est inférieur à 0. | SSSE3+
PSIGND | Cette instruction permet d'effectuer la négation de chaque double mots de l'opérande de destination si la valeur du signe de l'entier des double mots correspondant à l'opérande source est inférieur à 0. | SSSE3+
PSIGNW | Cette instruction permet d'effectuer la négation de chaque mots de l'opérande de destination si la valeur du signe de l'entier des mots correspondant à l'opérande source est inférieur à 0. | SSSE3+
PSLLD | Cette instruction permet d'effectuer le décalage de bits vers la gauche d'un paquet de double mots. | INTEL Pentium Pro+
PSLLDQ | Cette instruction permet d'effectuer le décalage de bits vers la gauche d'un paquet de double quadruple mots. | INTEL Pentium 4 (SSE2)+
PSLLQ | Cette instruction permet d'effectuer le décalage de bits vers la gauche d'un quadruple mot. | INTEL Pentium Pro+
PSLLW | Cette instruction permet d'effectuer le décalage de bits vers la gauche d'un paquet de mots. | INTEL Pentium Pro+
PSRAD | Cette instruction permet d'effectuer le décalage arithmétique de bits vers la droite d'un paquet de double mots. | INTEL Pentium Pro+
PSRAW | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un paquet de mots. | INTEL Pentium Pro+
PSRLD | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un paquet de double mots. | INTEL Pentium Pro+
PSRLDQ | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un paquet de double quadruple mots. | INTEL Pentium 4 (SSE2)+
PSRLQ | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un quadruple mot. | INTEL Pentium Pro+
PSRLW | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un paquet de mots. | INTEL Pentium Pro+
PSUBB | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des octets d'un paquet contenu dans des opérandes de 64 bits. | INTEL Pentium Pro+
PSUBD | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits. | INTEL Pentium Pro+
PSUBQ | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des quadruples mots d'un paquet contenu dans des opérandes. | INTEL Pentium 4 (SSE2)+
PSUBSB | Cette instruction permet d'effectuer la soustraction avec saturation de la valeur de chacun des octets signés d'un paquet contenu dans des opérandes de 64 bits. | INTEL Pentium Pro+
PSUBSIW | Cette instruction permet d'effectuer la soustraction du mot de format entier de l'opérande source au mot de format entier de l'opérande de destination et écrit le résultat dans le registre MMX. | Cyrix 6x86MX (EMMX)+
PSUBSW | Cette instruction permet d'effectuer la soustraction du mot de format entier de l'opérande source au mot de format entier de l'opérande de destination et écrit le résultat dans l'opérande destinataire. | INTEL Pentium Pro+
PSUBUSB | Cette instruction permet d'effectuer la soustraction avec saturation de la valeur de chacun des octets d'un paquet contenu dans des opérandes de 64 bits. | INTEL Pentium Pro+
PSUBUSW | Cette instruction permet d'effectuer la soustraction avec saturation de la valeur de chacun des mots d'un paquet contenu dans des opérandes de destinations. | INTEL Pentium Pro+
PSUBW | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des mots d'un paquet contenu dans des opérandes de 64 bits. | INTEL Pentium Pro+
PSWAPD | Cette instruction permet d'effectuer l'échange de la partie basse de 32 bits avec la partie haute de 32 bits dans des opérandes source de 64 bits et met le résultat dans une opérande 64 bits destinataire. | 3DNow!
PTEST | Cette instruction permet d'effectuer une comparaison de paquet avec un «Et binaire» sans modifier les opérandes. | SSE4.1+
PUNPCKHBW | Cette instruction permet de décompacter des octets en mots dans le haut d'un paquets de 64 bits. | INTEL Pentium Pro+
PUNPCKHDQ | Cette instruction permet de décompacter des doubles mots en quadruples mots dans le haut d'un paquets de 64 bits. | INTEL Pentium Pro+
PUNPCKHQDQ | Cette instruction permet de décompacter des doubles mots en quadruples mots dans le haut d'un paquets de 128 bits. | INTEL Pentium 4 (SSE2)+
PUNPCKHWD | Cette instruction permet de décompacter des mots en double mots dans le haut d'un paquets de 64 bits. | INTEL Pentium Pro+
PUNPCKLBW | Cette instruction permet de décompacter des octets en mots dans le bas d'un paquets de 64 bits. | INTEL Pentium Pro+
PUNPCKLDQ | Cette instruction permet de décompacter des doubles mots en quadruples mots dans le bas d'un paquets de 64 bits. | INTEL Pentium Pro+
PUNPCKLQDQ | Cette instruction permet de décompacter des doubles mots en quadruples mots dans le bas d'un paquets de 128 bits. | INTEL Pentium 4 (SSE2)+
PUNPCKLWD | Cette instruction permet de décompacter des mots en double mots dans le bas d'un paquets de 64 bits. | INTEL Pentium Pro+
PUSH | Cette instruction permet d'empiler un mot ou un double mot dans la pile. | INTEL 8086+
PUSHA | Cette instruction permet d'empiler respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX dans la pile. | INTEL 80286+
PUSHAD | Cette instruction permet d'empiler respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX dans la pile. | INTEL 80386+
PUSHF | Cette instruction permet d'empiler respectivement le registre 16 bits de drapeau des indicateurs d'état dans la pile. | INTEL 8086+
PUSHFD | Cette instruction permet d'empiler respectivement le registre 32 bits de drapeau des indicateurs d'état dans la pile. | INTEL 80386+
PUSHFQ | Cette instruction permet d'empiler respectivement le registre 64 bits de drapeau (RFLAGS) des indicateurs d'état dans la pile. | x86-64+
PXOR | Cette instruction permet d'effectuer un ou exclusif binaire d'un quadruple mot d'une opérande source avec une opérande destination dans le cas des registres XMM. | INTEL Pentium MMX+
RCL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | INTEL 8088+
RCPPS | Cette instruction permet d'effectuer le calcul de la réciproque d'un paquet de valeurs de réel de simple précision. | INTEL Pentium III (KNI/MMX2)+
RCPSS | Cette instruction permet d'effectuer le calcul de la réciproque d'une valeur de réel de simple précision. | INTEL Pentium III (KNI/MMX2)+
RCR | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | INTEL 8088+
RDMSR | Cette instruction permet de charger le contenu du modèle de registre 64-bits (MSR) indiquer par le registre ECX dans le couple de registre EDX:EAX. | INTEL Pentium+
RDPMC | Cette instruction permet d'effectuer la lecture du compteur du moniteur de performance. | INTEL Pentium Pro+
RDSHR | Cette instruction permet d'effectuer la lecture du registre de pointeur vers l'entête SMM. | Cyrix CX6x86MX+
RDTSC | Cette instruction permet de charger la valeur courante du compteur de temps du microprocesseur dans le couple de registres EDX:EAX. | INTEL Pentium+
RDTSCP | Cette instruction permet de charger la valeur courante du compteur de temps du microprocesseur dans le couple de registres EDX:EAX et la valeur du TSC_AUX dans le registre ECX. | x86-64+
REP | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions tant que CX ne vaut pas 0. | INTEL 8086+
REPE | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0. | INTEL 8086+
REPNE | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1. | INTEL 8086+
REPNZ | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1. | INTEL 8086+
REPZ | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0. | INTEL 8086+
RES3 | Cette instruction permet d'effectuer le chargement de tous les registres de descripteur de cache pour les 386. | AMD Am386SXLV, Am386DXLV
RES4 | Cette instruction permet d'effectuer le chargement de tous les registres de descripteur de cache pour les 486. | AMD Am486SXLV, Am486DXLV
RET | Cette instruction permet de quitter une procédure. | INTEL 8086+
RETF | Cette instruction permet de quitter une procédure ayant lieu avec un appel long (FAR CALL). | INTEL 8086+
RETN | Cette instruction permet de quitter une procédure ayant lieu avec un appel court (NEAR CALL). | INTEL 8086+
ROL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | INTEL 8088+
ROR | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | INTEL 8088+
ROUNDPD | Cette instruction permet d'effectuer l'arrondissement de 2 valeurs réel de double précision dans l'opérande source en utilisant le mode spécifié par l'opérande immédiate et place le résultat dans l'opérande de destination. | SSE4.1+
ROUNDPS | Cette instruction permet d'effectuer l'arrondissement de 4 valeurs réel de simple précision dans l'opérande source en utilisant le mode spécifié par l'opérande immédiate et place le résultat dans l'opérande de destination. | SSE4.1+
ROUNDSD | Cette instruction permet d'effectuer l'arrondissement scalaire de valeurs réel de double précision, dans sa partie basse du quadruple mot, dans l'opérande source en utilisant le mode spécifié par l'opérande immédiate et place le résultat dans l'opérande de destination. | SSE4.1+
ROUNDSS | Cette instruction permet d'effectuer l'arrondissement scalaire de valeurs réel de simple précision, dans sa partie basse du quadruple mot, dans l'opérande source en utilisant le mode spécifié par l'opérande immédiate et place le résultat dans l'opérande de destination. | SSE4.1+
RSDC | Cette instruction permet d'effectuer le restauration de la structure des registres et des descripteurs. | Quelques 486
RSLDT | Cette instruction permet d'effectuer la restauration des LDTR et des descripteurs. | Quelques 486
RSM | Cette instruction permet de retourner le contrôle du programme du mode de gestion système (SMM) pour le programme d'application ou la procédure du système d'exploitation ayant été interrompu lorsque le microprocesseur à recu un signal SSM. | INTEL 80486+
RSQRTPS | Cette instruction permet de calculer la réciproque approximative de la racine carré d'un paquet de simple précision. | INTEL Pentium III (KNI/MMX2)+
RSQRTSS | Cette instruction permet de calculer la réciproque approximative de la racine carré d'un scalaire de simple précision. | INTEL Pentium III (KNI/MMX2)+
RSTS | Cette instruction permet d'effectuer le restauration des TR et des descripteurs. | Quelques 486
SAHF | Cette instruction permet de copier les bits du registre AH dans l'octet de poids faible dans le registre des drapeaux (les indicateurs d'état). | INTEL 8088+
SAL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | INTEL 8088+
SAR | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | INTEL 8088+
SBB | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande. | INTEL 8088+
SCAS | Cette instruction permet de comparer un octet, un mot ou un double mot avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | INTEL 8086+
SCASB | Cette instruction permet de comparer le registre AL avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction. | INTEL 8086+
SCASD | Cette instruction permet de comparer le registre EAX avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
SCASW | Cette instruction permet de comparer le registre AX avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction. | INTEL 8086+
SET | Ces instructions permettent de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | INTEL 80386+
SETALC | Cette instruction permet de copier la valeur du drapeau de retenue dans le registre AL en la multipliant par 0FFh. | INTEL 8086+
SFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant emmagasiner du SFENCE et les instructions suivant le SFENCE. | Pentium III (SSE)+
SGDT | Cette instruction permet d'entreposer le sélecteur de segment dans le registre GDTR (registre de table global de descripteur) dans l'opérande de destination. | INTEL 80386+
SHL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | INTEL 8088+
SHLD | Cette instruction permet d'effectuer une rotation des bits d'un double mot vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | INTEL 80386+
SHR | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | INTEL 8088+
SHRD | Cette instruction permet d'effectuer une rotation des bits d'un double mot vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | INTEL 80386+
SHUFPD | Cette instruction permet de copier 4 paquets de valeurs de format réel de double précision dans un opérande destinataire dans la partie basse d'un quadruple mot de celle-ci et copie 2 des 4 paquets de valeurs de format réel de simple précision dans l'opérande source dans la partie haute d'un quadruple mot de l'opérande destinataire. | INTEL Pentium 4 (SSE2)+
SHUFPS | Cette instruction permet de copier 4 paquets de valeurs de format réel de simple précision dans une opérande destinataire dans la partie basse d'un quadruple mot de celle-ci et copie 2 des 4 paquets de valeurs de format réel de simple précision dans l'opérande source dans la partie haute d'un quadruple mot de l'opérande destinataire. | INTEL Pentium III (KNI/MMX2)+
SIDT | Cette instruction permet d'entreposer le registre de descripteur de table d'interruption (IDTR) dans l'opérande de destination. | INTEL 80386+
SKINIT | Cette instruction permet de réinitialiser de façon sécuritaire le microprocesseur et de démarrer un logiciel de confiance comme un VMM. | AMD-V
SLDT | Cette instruction permet d'entreposer le sélecteur de segment dans le registre LDTR (registre de table local de descripteur) dans l'opérande de destination. | INTEL 80386+
SMI | Cette instruction permet de gérer les interruptions systèmes en mode de déboguage. | AMD Am386SXLV,Am386DXLV
SMINT | Cette instruction permet de faire entrée le microprocesseur en mode SMM (System Management Mode). | P6, Cyrix
SMINTOLD | Cette instruction permet de faire entrée le microprocesseur en mode SMM (System Management Mode). | Quelques 486
SMSW | Cette instruction permet d'entreposer le mot des états (soit les bits de 0 à 15 du registre de contrôle CR0) à partir du registre de tâche (TR) dans l'opérande cible. | INTEL 80386+
SQRTPD | Cette instruction permet d'effectuer le calcul de la racine carré d'un paquet de valeur de double précision réel de l'opérande source et de mettre son résultat dans l'opérande de destination sous forme d'un réel de double précision. | INTEL Pentium 4 (SSE2)+
SQRTPS | Cette instruction permet d'effectuer le calcul de la racine carré d'un paquet de valeur de simple précision réel de l'opérande source et de mettre son résultat dans l'opérande de destination sous forme d'un réel de simple précision. | INTEL Pentium III (KNI/MMX2)+
SQRTSD | Cette instruction permet d'effectuer le calcul de la racine carré d'une valeur de double précision réel de l'opérande source et de mettre son résultat dans l'opérande de destination sous forme d'un réel de double précision. | INTEL Pentium 4 (SSE2)+
SQRTSS | Cette instruction permet d'effectuer le calcul de la racine carré d'une valeur de simple précision réel de l'opérande source et de mettre son résultat dans l'opérande de destination sous forme d'un réel de simple précision. | INTEL Pentium III (KNI/MMX2)+
SS: | Ce préfixe permet d'indiquer à une instruction d'utiliser le Segment de Pile (Stack Segment) pour adresse dans l'opérande. | INTEL 8088+
STC | Cette instruction permet de fixer l'indicateur de retenue (CF) à la valeur 1. | INTEL 8088+
STD | Cette instruction permet de fixer l'indicateur de direction (DF) à la valeur 1. | INTEL 8088+
STGI | Cette instruction permet de fixer les drapeaux global d'interruption (GIF). Quand le GIF est à 1, les interruptions externes sont réactivés. | AMD-V
STI | Cette instruction permet de fixer l'indicateur d'interruption (IF) à la valeur 1. | INTEL 8088+
STMXCSR | Cette instruction permet de copier le MXCSR dans un emplacement mémoire de 32 bits. | INTEL Pentium III (KNI/MMX2)+
STOS | Cette instruction permet de copier un octet, un mot ou un double mot dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | INTEL 8086+
STOSB | Cette instruction permet de copier le registre AL dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction. | INTEL 8086+
STOSD | Cette instruction permet de copier le registre EAX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
STOSQ | Cette instruction permet de copier le registre RAX dans la cellule mémoire à l'adresse ES:[(R)DI] et incrémente/décrémente le registre (R)DI de 8 en fonction de l'état du drapeau de direction. | x86-64+
STOSW | Cette instruction permet de copier le registre AX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction. | INTEL 8086+
STR | Cette instruction permet d'entreposer le sélecteur de segment à partir du registre de tâche (TR) à l'opérande cible | INTEL 80286+
SUB | Cette instruction permet de soustraire une valeur à une opérande. | INTEL 8088+
SUBPD | Cette instruction permet d'effectuer une soustraction de 2 paquets de valeurs réels de double précision d'un opérande source et d'un opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de double précision. | INTEL Pentium 4 (SSE2)+
SUBPS | Cette instruction permet d'effectuer une soustraction de 4 paquets de valeurs réels de simple précision d'une opérande source et d'une opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de simple précision. | INTEL Pentium III (KNI/MMX2)+
SUBSD | Cette instruction permet d'effectuer une soustraction de la partie basse d'une valeur réel de double précision d'un opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de double précision. | INTEL Pentium 4 (SSE2)+
SUBSS | Cette instruction permet d'effectuer une soustraction de la partie basse d'une valeur réel de simple précision d'une opérande source et destination et entrepose le résultat dans une opérande de destination de valeur réel de simple précision. | INTEL Pentium III (KNI/MMX2)+
SVDC | Cette instruction permet de sauvegarder le registre et le descripteur. | Quelques 486
SVLDT | Cette instruction permet de sauvegarder le LDTR et le descripteur. | Quelques 486
SVTS | Cette instruction permet de sauvegarder le TR et le descripteur. | Quelques 486
SWAPGS | Cette instruction permet de fournir une méthode à un logiciel système pour charger un pointeur sur une structure de données système. | x86-64+
SYSCALL | Cette instruction permet d'effectuer le transfert du contrôle d'un point d'entrée fixe au système d'exploitation. | AMD K6-2+
SYSENTER | Cette instruction permet d'effectuer le transférer du contrôle d'un point d'entrée au système d'exploitation. | INTEL Pentium Pro+
SYSEXIT | Cette instruction permet de retourner du système d'exploitation à une application. | INTEL Pentium Pro+
SYSRET | Cette instruction permet de retourner du système d'exploitation à une application. | AMD K6-2+
TEST | Cette instruction permet d'effectuer un «Et binaire» sur une opérande cible sans modifier sa valeur. | INTEL 8088+
UCOMISD | Cette instruction permet d'effectuer une comparaison désordonnée de valeurs réels de double précision dans la partie basse d'un double mot du premier opérande et du deuxième opérande, et fixe les drapeaux ZF, PF et FC dans le registre EFLAGS selon le résultat (non-ordonnée, supérieur à, inférieur ou égal) | INTEL Pentium III+
UCOMISS | Cette instruction permet d'effectuer une comparaison désordonnée de valeurs réels de simple précision dans la partie basse d'un double mot du premier opérande et du deuxième opérande, et fixe les drapeaux ZF, PF et FC dans le registre EFLAGS selon le résultat (non-ordonnée, supérieur à, inférieur ou égal) | INTEL Pentium III+
UD | Cette instruction permet de provoquer l'exécution d'un code indéfinie. | AMD Am5k86 (SSA/5, K5)
UD2 | Cette instruction permet de provoquer l'exécution d'un code indéfinie. | INTEL Pentium Pro+
UMOV | Cette instruction permet de copier un opérande source dans une emplacement mémoire principal. | AMD Am386SXLV, Am386DXLV, 486s, IBM 486SLC2
UNPCKHPD | Cette instruction permet d'effectuer un dépaquetage de la partie haute d'un réel de double précision d'un opérande source et destination et met le résultat dans l'opérande de destination. | INTEL Pentium 4 (SSE2)+
UNPCKHPS | Cette instruction permet d'effectuer un dépaquetage de la partie haute d'un réel de simple précision d'un opérande source et destination et met le résultat dans l'opérande de destination. | INTEL Pentium III (KNI/MMX2)+
UNPCKLPD | Cette instruction permet d'effectuer un dépaquetage de la partie basse d'un réel de double précision d'un opérande source et destination et met le résultat dans l'opérande de destination. | INTEL Pentium 54 (SSE2)+
UNPCKLPS | Cette instruction permet d'effectuer un dépaquetage de la partie basse d'un réel de simple précision d'une opérande source et destination et met le résultat dans l'opérande de destination. | INTEL Pentium III (KNI/MMX2)+
VBROADCASTF128 | Cette instruction permet d'effectuer le chargement de valeurs réels de 128 bits d'une opérande source et de se diffuser dans tous les éléments de l'opérande de destination. | AVX (AMD ou INTEL)
VBROADCASTSD | Cette instruction permet d'effectuer le chargement de valeurs réels de double précision d'une opérande source et de se diffuser dans tous les éléments de l'opérande de destination. | AVX (AMD ou INTEL)
VBROADCASTSS | Cette instruction permet d'effectuer le chargement de valeurs réels de simple précision d'une opérande source et de se diffuser dans tous les éléments de l'opérande de destination. | AVX (AMD ou INTEL)
VERR | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode lecture à partir du niveau de privilège courant (CPL). | INTEL 80286+
VERW | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode écriture à partir du niveau de privilège courant (CPL). | INTEL 80286+
VEXTRACTF128 | Cette instruction permet d'effectuer l'extraction de paquet de valeurs réel de 128 bits d'une opérande source dans l'opérande de destination en tenant compte de la position d'extraction avec une opérande de destination. | AVX (AMD ou INTEL)
VFMADD132PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un premier opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire au résultat de deux ou quatres paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD132PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un premier opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire au résultat de quatre ou huit paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD132SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un premier opérande source avec la partie basse de paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire au résultat de la partie basse de paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD132SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un premier opérande source avec la partie basse de paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire au résultat de la partie basse de paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD213PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un second opérande source avec les deux ou quatres paquets de valeurs réels de double précision du premier opérande source, ajoute la précision infinie intermédiaire au résultat de deux ou quatres paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD213PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un second opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du premier opérande source, ajoute la précision infinie intermédiaire au résultat de quatre ou huit paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD213SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un second opérande source avec la partie basse de paquets de valeurs réels de double précision du premier opérande source, ajoute la précision infinie intermédiaire au résultat de la partie basse de paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD213SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de simple précision du premier opérande source, ajoute la précision infinie intermédiaire au résultat de la partie basse de paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD231PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un second opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire au résultat de deux ou quatres paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD231PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un second opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire au résultat de quatre ou huit paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD231SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un second opérande source avec la partie basse de paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire au résultat de la partie basse de paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADD231SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire au résultat de la partie basse de paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADDSUB132PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un premier opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire impaire et soustrait la précision intermédiaire paire au résultat de deux ou quatres paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADDSUB132PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un premier opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire impaire et soustrait la précision intermédiaire paire au résultat de quatre ou huit paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADDSUB213PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du premier opérande source, ajoute la précision infinie intermédiaire impaire et soustrait la précision intermédiaire paire au résultat de deux ou quatres paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADDSUB213PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxème opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du premier opérande source, ajoute la précision infinie intermédiaire impaire et soustrait la précision intermédiaire paire au résultat de quatre ou huit paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADDSUB231PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire impaire et soustrait la précision intermédiaire paire au résultat de deux ou quatres paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMADDSUB231PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire impaire et soustrait la précision intermédiaire paire au résultat de quatre ou huit paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUBADD132PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un premier opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire impaire et ajoute la précision intermédiaire paire au résultat de deux ou quatres paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUBADD132PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un premier opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire impaire et ajoute la précision intermédiaire paire au résultat de quatre ou huit paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUBADD213PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du premier opérande source, soustrait la précision infinie intermédiaire impaire et ajoute la précision intermédiaire paire au résultat de deux ou quatres paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUBADD213PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du premier opérande source, soustrait la précision infinie intermédiaire impaire et ajoute la précision intermédiaire paire au résultat de quatre ou huit paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUBADD231PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire impaire et ajoute la précision intermédiaire paire au résultat de deux ou quatres paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUBADD231PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire impaire et ajoute la précision intermédiaire paire au résultat de quatre ou huit paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB132PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un premier opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire au résultat de deux ou quatres paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB132PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un premier opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire au résultat de quatre ou huit paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB132SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un premier opérande source avec la partie basse de paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire au résultat de la partie basse de paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB132SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un premier opérande source avec la partie basse de paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire au résultat de la partie basse de paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB213PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du premier opérande source, soustrait la précision infinie intermédiaire au résultat de deux ou quatres paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB213PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du premier opérande source, soustrait la précision infinie intermédiaire au résultat de quatre ou huit paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB213SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de double précision du premier opérande source, soustrait la précision infinie intermédiaire au résultat de la partie basse de paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB213SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de simple précision du premier opérande source, soustrait la précision infinie intermédiaire au résultat de la partie basse de paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB231PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire au résultat de deux ou quatres paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB231PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire au résultat de quatre ou huit paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB231SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire au résultat de la partie basse de paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFMSUB231SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire au résultat de la partie basse de paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD132PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un premier opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire négative au résultat de deux ou quatres paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD132PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un premier opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire négative au résultat de quatre ou huit paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD132SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un premier opérande source avec la partie basse de paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD132SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un premier opérande source avec la partie basse de paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD213PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du premier opérande source, ajoute la précision infinie intermédiaire négative au résultat de deux ou quatres paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD213PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du premier opérande source, ajoute la précision infinie intermédiaire négative au résultat de quatre ou huit paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD213SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de double précision du premier opérande source, ajoute la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD213SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de simple précision du premier opérande source, ajoute la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD231PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire négative au résultat de deux ou quatres paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD231PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire négative au résultat de quatre ou huit paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD231SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de double précision du troisième opérande source, ajoute la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMADD231SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de simple précision du troisième opérande source, ajoute la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB132PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un premier opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire négative au résultat de deux ou quatres paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB132PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un premier opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire négative au résultat de quatre ou huit paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB132SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un premier opérande source avec la partie basse de paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB132SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un premier opérande source avec la partie basse de paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le deuxième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB213PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du premier opérande source, soustrait la précision infinie intermédiaire négative au résultat de deux ou quatres paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB213PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du premier opérande source, soustrait la précision infinie intermédiaire négative au résultat de quatre ou huit paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB213SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de double précision du premier opérande source, soustrait la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB213SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de simple précision du premier opérande source, soustrait la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le troisième opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB231PD | Cette instruction permet d'effectuer la multiplication de deux ou quatre paquets de valeur réel de double précision d'un deuxième opérande source avec les deux ou quatres paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire négative au résultat de deux ou quatres paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de deux ou quatre paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB231PS | Cette instruction permet d'effectuer la multiplication de quatre ou huit paquets de valeur réel de simple précision d'un deuxième opérande source avec les quatre ou huit paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire négative au résultat de quatre ou huit paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de quatre ou huit paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB231SD | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de double précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de double précision du troisième opérande source, soustrait la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de double précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VFNMSUB231SS | Cette instruction permet d'effectuer la multiplication de la partie basse de paquets de valeur réel de simple précision d'un deuxième opérande source avec la partie basse de paquets de valeurs réels de simple précision du troisième opérande source, soustrait la précision infinie intermédiaire négative au résultat de la partie basse de paquets dans le premier opérande source, effectue l'arrondissement et entrepose le résultat de paquets de valeurs réel de simple précision dans un opérande de destination (premier opérande source). | FMA (INTEL)
VINSERTF128 | Cette instruction permet d'insérer une valeur réel de 128 bits d'un opérande source dans l'emplacement d'un registre d'opérande de destination et met des 0 dans les données en dehors du masque de destination. | AVX (AMD ou INTEL)
VLDMXCSR | Cette instruction permet d'effectuer le chargement du mot de contrôle (MXCSR) d'une opérande mémoire 32 bits pour l'AVX. | AVX (AMD ou INTEL)
VMASKMOVPD | Cette instruction permet d'effectuer un chargement conditionnel des valeurs réels de double précision de paquets d'une opérande de 128 ou 256 bits avec le masque de destination et entrepose le résultat dans l'opérande de destination. | AVX (AMD ou INTEL)
VMASKMOVPS | Cette instruction permet d'effectuer un chargement conditionnel des valeurs réels de simple précision de paquets d'une opérande de 128 ou 256 bits avec le masque d'opérande et entrepose le résultat dans l'opérande de destination. | AVX (AMD ou INTEL)
VMCALL | Cette instruction permet de fournir un mécanisme invité logiciel pour appeler un service dans un moniteur VM. | INTEL VMX (Virtualisation)
VMCLEAR | Cette instruction permet d'appliquer un VMCS à une région VMCS à l'adresse physique contenu dans l'opération spécifié. | INTEL VMX (Virtualisation)
VMLAUNCH | Cette instruction permet de gérer l'entrée VM par le VMCS courant, de façon à échoué si l'état de lancement VMCS courant n'est pas effacé. Si l'instruction est un succès, il définit l'état de lancement à relancer. | INTEL VMX (Virtualisation)
VMLOAD | Cette instruction permet d'effectuer le chargement d'un sous-ensemble d'état de microprocesseur dans un VMCB spécifié par une adresse physique contenu dans le registre RAX. | AMD-V
VMMCALL | Cette instruction permet de fournir un mécanisme invité pour communiquer explicitement avec le VMM en générant un #VMEXIT. | AMD-V
VMPTRLD | Cette instruction permet de marquer le pointeur VMCS courant valide et charge celui-ci avec une adresse physique dans l'opérande d'instruction. | INTEL VMX (Virtualisation)
VMPTRST | Cette instruction permet d'entreposer le pointeur VMCS courant dans l'adresse mémoire spécifié. | INTEL VMX (Virtualisation)
VMREAD | Cette instruction permet d'effectuer la lecture du champ spécifié dans le VMCS et l'entrepose dans l'opérande de destination spécifié. | INTEL VMX (Virtualisation)
VMRESUME | Cette instruction permet de gérer l'entrée VM par le VMCS courant, de façon à échoué si l'état le lancement VMCS courant n'est pas lancé. | INTEL VMX (Virtualisation)
VMRUN | Cette instruction permet de lancer l'exécution d'un flux d'instructions invité. | AMD-V
VMSAVE | Cette instruction permet d'entreposer un sous-ensemble d'état du microprocesseur dans un VMCB spécifié par une adresse physique contenu dans le registre RAX. | AMD-V
VMWRITE | Cette instruction permet d'effectuer l'écriture du champ spécifié du VMCS spécifié par l'opérande source secondaire (registre seulement) en utilisant le contenu de l'opérande source primaire (registre ou mémoire). | INTEL VMX (Virtualisation)
VMXOFF | Cette instruction permet d'utiliser le processeur logique en dehors de l'opération VMX, de débloquer le signal INIT, de conditionnellement réactiver le A20M et d'effacer tous les rangs d'adresse du moniteur. | INTEL VMX (Virtualisation)
VMXON | Cette instruction permet d'utiliser le processeur logique dans une opération VMX avec le VMCS non courant, le signal INIT bloqué, la désactivation A20M, et en effaçant n'importe quel rang d'adresse du moniteur établit avec l'instruction MONITOR. | INTEL VMX (Virtualisation)
VPERM2F128 | Cette instruction permet d'effectuer la permutation de valeurs réel de 128 bits d'un premier opérande source utilisant un champ de 8 bits de contrôle dans les octets bas d'un second opérande source et entrepose les résultats dans l'opérande de destination. | AVX (AMD ou INTEL)
VPERMILPD | Cette instruction permet d'effectuer la permutation de valeurs réels de double précision d'un premier opérande source utilisant un champ de 8 bits de contrôle dans les octets bas d'un second opérande source et entrepose les résultats dans l'opérande de destination. | AVX (AMD ou INTEL)
VPERMILPS | Cette instruction permet d'effectuer la permutation de valeurs réels de simple précision d'un premier opérande source utilisant un champ de 8 bits de contrôle dans les octets bas d'un second opérande source et entrepose les résultats dans l'opérande de destination. | AVX (AMD ou INTEL)
VZEROALL | Cette instruction permet de mettre la valeur 0 dans tous les registres XMM ou YMM. | AVX (AMD ou INTEL)
VZEROUPPER | Cette instruction permet de mettre la valeur 0 dans chacun des 128 bits de la partie haute de tous les registres XMM ou YMM. | AVX (AMD ou INTEL)
WAIT | Cette instruction permet de faire passer le microprocesseur en mode d'attente jusqu'à ce que la ligne de teste sur la carte mère s'active. | INTEL 8088+
WBINVD | Cette instruction permet de désactiver et de vider le tampon interne du micro-processeur. | INTEL 80486+
WRMSR | Cette instruction écrit les valeurs contenues dans le MSR (Model-Specific Register) en fonction du registre d'index ECX dans la paire des registres EDX:EAX. | INTEL Pentium+
WRSHR | Cette instruction écrit les valeurs contenues dans l'opérande source dans l'entête SMM. | Cyrix Cx6x86MX
XADD | Cette instruction permet d'échanger le premier opérande avec le deuxième opérande, et ensuite effectue la somme des valeurs dans le premier opérande. | INTEL 80486+
XBTS | Cette instruction permet de prendre des bits d'un opérande source et de les mettres dans une opérande destinataire. | INTEL 80386
XCHG | Cette instruction permet d'échanger la valeur de deux opérandes. | INTEL 8088+
XGETBV | Cette instruction permet d'effectuer la lecture du registre de contrôle étendue (XCR) spécifié par le registre ECX dans les registres EDX:EAX. | INTEL SDM (Core i7)+
XLAT | Cette instruction permet de remplacer le contenu du registre AL par un octet de la «tablesource». | INTEL 8088+
XLATB | Cette instruction permet de remplacer le contenu du registre AL par un octet de la «tablesource» sans opérande. | INTEL 8088+
XOR | Cette instruction permet d'effectuer un OU exclusif BINAIRE sur les 2 opérandes spécifiés. | INTEL 8086+
XORPD | Cette instruction permet d'effectuer un ou exclusif binaire de 2 paquets de valeurs réel de double précision dans un opérande source et destination et de mettre le résultat dans l'opérande de destination. | INTEL Pentium 4 (SSE2)+
XORPS | Cette instruction permet d'effectuer un ou exclusif binaire de 4 paquets de valeurs réel de simple précision dans une opérande source et destination et de mettre le résultat dans l'opérande de destination. | INTEL Pentium III+ (KNI/MMX2)
XRSTOR | Cette instruction permet d'effectuer une restauration complète ou partiel des états actifs du processeur en utilisant les informations entreposé dans les adresses de mémoire spécifié par l'opérande. | INTEL SDM (Core i7)+
XSAVE | Cette instruction permet d'effectuer une sauvegarde complète ou partiel des états actifs du processeur en utilisant les informations entreposé dans les adresses de mémoire spécifié par l'opérande. | INTEL SDM (Core i7)+
XSETBV | Cette instruction permet d'effectuer l'écriture du registre de contrôle étendue (XCR) spécifié par les registres EDX:EAX à l'aide du registre ECX. | INTEL SDM (Core i7)+


Voici la liste des opcodes en 16 et 32 bits :

Opcode | Instruction | Description
00h (r/m8) | ADD r/m8 | Cette instruction additionne 2 quantités numérique sur 8 bits.
01h (r/m16) | ADD r/m16 | Cette instruction additionne 2 quantités numérique sur 16 bits.
02h (r/m8) | ADD r/m8 | Cette instruction additionne 2 quantités numérique sur 8 bits.
03h (r/m16) | ADD r/m16 | Cette instruction additionne 2 quantités numérique sur 16 bits.
04h (xxh) | ADD AL,xxh | Cette instruction additionne une valeur 8 bits immédiate au registre AL.
05h (xxh) (yyh) | ADD AX,yyxxh | Cette instruction additionne une valeur 16 bits immédiate au registre AX.
06h | PUSH ES | Cette instruction permet d'empiler le registre ES dans la pile.
07h | POP ES | Cette instruction permet de désempiler de la pile une mot et la met dans le registre ES.
08h (r/m8) | OR r/m8 | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandes spécifiés 8 bits.
09h (r/m16) | OR r/m16 | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandes spécifiés 16 bits.
0Ah (r/m8) | OR r/m8 | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandes spécifiés 8 bits.
0Bh (r/m16) | OR r/m16 | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandes spécifiés 16 bits.
0Ch (xxh) | OR AL,xxh | Cette instruction permet d'effectuer un OU BINAIRE sur le registre AL avec une valeur immédiate 8 bits.
0Dh (xxh) (yyh) | OR AX,yyxxh | Cette instruction permet d'effectuer un OU BINAIRE sur le registre AX avec une valeur immédiate 16 bits.
0Eh | PUSH CS | Cette instruction permet d'empiler le registre CS dans la pile.
0Fh 01h C8h | MONITOR | Cette instruction permet d'indiquer au microprocesseur quel rangé d'adresse est à surveiller par l'instruction STORE.
0Fh 01h C9h | MWAIT | Cette instruction permet d'indiquer au microprocesseur que l'état de l'alimentation de la ligne de cache est en attente d'écriture dans la plage d'adresse, mettant fin à la plupart des activités dans le noyau en le faisant.
0Fh 01h D9h | VMMCALL | Cette instruction permet de fournir un mécanisme invité pour communiquer explicitement avec le VMM en générant un #VMEXIT.
0Fh 01h DCh | STGI | Cette instruction permet de fixer les drapeaux global d'interruption (GIF). Quand le GIF est à 1, les interruptions externes sont réactivés.
0Fh 01h DDh | CLGI | Cette instruction permet d'effacer le drapeau d'interruption global (GIF).
0Fh 01h DEh | SKINIT EAX | Cette instruction permet de réinitialiser de façon sécuritaire le microprocesseur et de démarrer un logiciel de confiance comme un VMM.
0Fh 01h DFh | INVLPGA RAX, ECX | Cette instruction permet d'invalider la cartographie TLB (Translation Lookaside Buffer) pour une page virtuel et un ASID spécifié.
0Fh 01h F8h | SWAPGS | Cette instruction permet de fournir une méthode à un logiciel système pour charger un pointeur sur une structure de données système.
0Fh 01h F9h | RDTSCP | Cette instruction permet de charger la valeur courante du compteur de temps du microprocesseur dans le couple de registres EDX:EAX et la valeur du TSC_AUX dans le registre ECX.
0Fh 05h | SYSCALL | Cette instruction permet d'effectuer le transfert du contrôle d'un point d'entrée fixe au système d'exploitation.
0Fh 06h | CLTS | Cette instruction permet de mettre à 0 le drapeau de l'indicateur de tâche (Task-Switch) du registre CR0.
0Fh 07h | LOADALL | Cette instruction permet d'effectuer le chargement de tous les registres de descripteur de cache.
0Fh 07h | SYSRET | Cette instruction permet de retourner du système d'exploitation à une application.
0Fh 08h | WBINVD | Cette instruction permet de désactiver et de vider le tampon interne du micro-processeur.
0Fh 0Bh | UD2 | Cette instruction permet de provoquer l'exécution d'un code indéfinie.
0Fh 0Eh | FEMMS | Cette instruction permet d'effacer les états MMX après le passage d'instructions MMX.
0Fh 2Ah /r | CVTPI2PS xmm,mm/m64 | Cette instruction permet de convertir un entier de format double mot en une valeur réel de simple précision compacté.
0Fh 2Ch /r | CVTTPS2PI mm,xmm/m64 | Cette instruction permet de convertir une valeur réel de simple précision compacté avec tronquage en un entier de format double mot compacté.
0Fh 2Dh /r | CVTPS2PI mm,xmm/m64 | Cette instruction permet de convertir une valeur réel de simple précision compacté en un entier de format double mot.
0Fh 2Fh /r | COMISS xmm1,xmm2/m32 | Cette instruction permet de comparer deux valeurs réel de simple-précision dans la partie faible du quadruple mot de deux opérande et fixe les drapeaux de ZF, PF et FC du registre EFLAGS en fonction du résultat (non-ordonnée, supérieur à, inférieur ou égal).
0Fh 30h | WRMSR | Cette instruction écrit les valeurs contenu dans le MSR (Model-Specific Register) en fonction du registre d'index ECX dans la paire des registres EDX:EAX.
0Fh 31h | RDTSC | Cette instruction permet de charger la valeur courante du compteur de temps du microprocesseur dans le couple de registres EDX:EAX.
0Fh 32h | RDMSR | Cette instruction permet de charger le contenu du modèle de registre 64-bits (MSR) indiquer par le registre ECX dans le couple de registre EDX:EAX.
0Fh 33h | RDPMC | Cette instruction permet d'effectuer la lecture du compteur du moniteur de performance.
0Fh 34h | SYSENTER | Cette instruction permet d'effectuer le transférer du contrôle d'un point d'entrée au système d'exploitation.
0Fh 35h | SYSEXIT | Cette instruction permet de retourner du système d'exploitation à une application.
0Fh 40h /r | CMOVO reg16, reg/mem16 | Copie si débordement (OF = 1)
0Fh 41h /r | CMOVNO reg16, reg/mem16 | Copie si pas de débordement (OF = 0)
0Fh 42h /r | CMOVB reg16, reg/mem16 | Copie si retenu (CF = 1)
0Fh 43h /r | CMOVNB reg16,reg/mem16 | Copie si pas retenu (CF = 0)
0Fh 44h /r | CMOVZ reg16, reg/mem16 | Copie si drapeau du zéro (ZF = 1)
0Fh 45h /r | CMOVNZ reg16, reg/mem16 | Copie si drapeau de pas de zéro (ZF = 0)
0Fh 46h /r | CMOVBE reg16, reg/mem16 | Copie si drapeau de zéro (ZF = 1) ou drapeau de retenu (CF = 1)
0Fh 47h /r | CMOVNBE reg16, reg/mem16 | Copie si drapeau de pas de zéro (ZF = 0) et drapeau de pas de retenu (CF = 0)
0Fh 48h /r | CMOVS reg16, reg/mem16 | Copie si drapeau de signe (SF = 1)
0Fh 49h /r | CMOVNS reg16, reg/mem16 | Copie si drapeau de pas de signe (SF = 0)
0Fh 4Ah /r | CMOVP reg16, reg/mem16 | Copie si drapeau de parité (PF = 1)
0Fh 4Bh /r | CMOVNP reg16, reg/mem16 | Copie si drapeau de pas de parité (PF = 0)
0Fh 4Ch /r | CMOVL reg16, reg/mem16 | Copie si SF <> OF
0Fh 4Dh /r | CMOVNL reg16, reg/mem16 | Copie si SF = OF
0Fh 4Eh /r | CMOVLE reg16, reg/mem16 | Copie si ZF = 1 ou SF <> OF
0Fh 4Fh /r | CMOVNLE reg16, reg/mem16 | Copie si ZF = 0 et SF = OF
0Fh 54h /r | ANDPS xmmreg,r/m128 | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes 128 bits spécifiés.
0Fh 55h /r | ANDNPS xmmreg,r/m128 | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes 128 bits spécifiés et inverse chacun des bits du résultat.
0Fh 58h /r | ADDPS xmm1, xmm2/m128 | Cette instruction permet d'ajouter le paquet de réel de simple précision de xmm2/m128 à xmm1
0Fh 5Ah /r | CVTPS2PD xmm1, xmm2/m64 | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de simple précision en paquet de valeurs réel de double précision.
0Fh 5Bh /r | CVTDQ2PS xmm1, xmm2/m128 | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de simple précision.
0Fh 5Eh /r | DIVPS xmm1,xmm2/m128 | Cette instruction permet d'effectuer une division de valeur réel de simple précision de registre XMM ou d'emplacement mémoire de 128 bits.
0Fh 77h | EMMS | Cette instruction permet de fixer les mots marqués du MPU de chacun un.
0Fh A0h | PUSH FS | Cette instruction permet d'empiler le registre FS dans la pile.
0Fh A1h | POP FS | Cette instruction permet de désempiler de la pile une mot et la met dans le registre FS.
0Fh A2h | CPUID | Cette instruction retourne le code d'identification du microprocesseur.
0Fh A3h /r | BT reg/mem16, reg16 | Copie la valeur de sélection de bit dans le drapeau de retenu
0Fh A8h | PUSH GS | Cette instruction permet d'empiler le registre GS dans la pile.
0Fh A9h | POP GS | Cette instruction permet de désempiler de la pile une mot et la met dans le registre GS.
0Fh AAh | RSM | Cette instruction permet de retourner le contrôle du programme du mode de gestion système (SMM) pour le programme d'application ou la procédure du système d'exploitation ayant été interrompu lorsque le microprocesseur à reçu un signal SSM.
0Fh ABh /r | BTS reg/mem16, reg16 | Copie la valeur du bit de sélection dans le drapeau de retenu et fixe le bit de sélection.
0Fh AEh /7 | CLFLUSH mem8 | Vide la ligne de cache contenu dans mem8.
0Fh AEh E8h | LFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant le LFENCE et les instructions de chargement suivant le LFENCE.
0Fh AEh F0h | MFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant le MFENCE et les instructions de chargement et d'entreposage précédent le MFENCE.
0Fh AEh F8h | SFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant emmagasiner du SFENCE et les instructions suivant le SFENCE.
0Fh B0h /r | CMPXCHG reg/mem8, reg8 | Compare de registre AL avec un emplacement 8 bits de registre ou mémoire. S'ils sont égale, le deuxième opérande est copié dans le première opérande.
0Fh B1h /r | CMPXCHG reg/mem16, reg16 | Compare de registre AX avec un emplacement 16 bits de registre ou mémoire. S'ils sont égale, le deuxième opérande est copié dans le première opérande.
0Fh B3h /r | BTR reg/mem16, reg16 | Copie la valeur du bit de sélection dans le drapeau de retenu et efface le bit de sélection.
0Fh BAh /4 ib | BT reg/mem16, imm8 | Copie la valeur de sélection de bit dans le drapeau de retenu
0Fh BAh /5 ib | BTS reg/mem16, imm8 | Copie la valeur du bit de sélection dans le drapeau de retenu et fixe le bit de sélection.
0Fh BAh /6 ib | BTR reg/mem16, imm8 | Copie la valeur du bit de sélection dans le drapeau de retenu et efface le bit de sélection.
0Fh BAh /7 ib | BTC reg/mem16, imm8 | Copie la valeur du bit de sélection dans le drapeau de retenu et complémente le bit de sélection.
0Fh BBh /r | BTC reg/mem16, reg16 | Copie la valeur du bit de sélection dans le drapeau de retenu et complémente le bit de sélection.
0Fh BCh /r | BSF reg16, reg/mem16 | Balayage de bit vers l'avant du contenu du registre/mémoire 16 bits
0Fh BDh /r | BSR reg16, reg/mem16 | Balayage de bit vers l'arrière du contenu du registre/mémoire 16 bits
0Fh C2h /r imm8 | CMPPS xmm1,xmm2/m128,imm8 | Cette instruction permet d'effectuer une comparaison SIMD de 4 paquets de valeurs réels de simple précision d'une opérande source et d'une opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination.
0Fh C7h /1 m64 | CMPXCHG8B mem64 | Compare la paire de registres EDX:EAX à l'emplacement mémoire de 64 bits. S'ils sont égale, alors fixe le drapeau de zéro à 1 et copie ECX:EBX dans l'emplacement mémoire. Autrement, copie l'emplacement mémoire dans EDX:EAX et efface le drapeau de zéro.
0Fh C8h +rd | BSWAP reg32 | Cette instruction permet d'inverser l'ordre des octets du registre 32 bits
0Fh FFh | OIO | Cette instruction permet de provoquer l'exécution d'un code indéfinie.
10h (r/m8) | ADC r/m8 | Cette instruction additionne 2 quantités numérique sur 8 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu.
11h (r/m16) | ADC r/m16 | Cette instruction additionne 2 quantités numérique sur 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu.
12h (r/m8) | ADC r/m8 | Cette instruction additionne 2 quantités numérique sur 8 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu.
13h (r/m16) | ADC r/m16 | Cette instruction additionne 2 quantités numérique sur 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu.
14h (xxh) | ADC AL,xxh | Cette instruction additionne une valeur 8 bits immédiate au registre AL et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu.
15h (xxh) (yyh) | ADC AX,yyxxh | Cette instruction additionne une valeur 16 bits immédiate au registre AX et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu.
16h | PUSH SS | Cette instruction permet d'empiler le registre SS dans la pile.
17h | POP SS | Cette instruction permet de désempiler de la pile une mot et la met dans le registre SS.
18h (r/m8) | SBB r/m8 | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande.
19h (r/m16) | SBB r/m16 | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande.
1Ah (r/m8) | SBB r/m16 | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande.
1Bh (r/m16) | SBB r/m16 | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande.
1Ch (xxh) | SBB AL,xxh | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande.
1Dh (xxh) (yyh) | SBB AX,yyxxh | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande.
1Eh | PUSH DS | Cette instruction permet d'empiler le registre DS dans la pile.
1Fh | POP DS | Cette instruction permet de désempiler de la pile une mot et la met dans le registre DS.
20h (r/m8) | AND r/m8 | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés 8 bits.
21h (r/m16) | AND r/m16 | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés 16 bits.
22h (r/m8) | AND r/m8 | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés 8 bits.
23h (r/m16) | AND r/m16 | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés 16 bits.
24h (xxh) | AND AL,xxh | Cette instruction permet d'effectuer un ET BINAIRE sur le registre AL avec une valeur immédiate 8 bits.
25h (xxh) (yyh) | AND AX,yyxxh | Cette instruction permet d'effectuer un ET BINAIRE sur le registre AX avec une valeur immédiate 16 bits.
26h | ES: | Cette instruction permet d'indiquer un préfixe au registre segment ES.
27h | DAA | Ajuste les décimal du registre AL
2Eh | CS: | Cette instruction permet d'indiquer un préfixe au registre segment CS.
2Fh | DAS | Ajuste les décimal du registre AL après soustraction
36h | SS: | Cette instruction permet d'indiquer un préfixe au registre segment SS.
37h | AAA | Cette instruction permet de créer un nombre dépaqueté BCD
38h /r | CMP reg/mem8, reg8 | Compare le contenu d'une opérande mémoire ou d'un registre 8 bits avec un registre 8 bits.
39h /r | CMP reg/mem16, reg16 | Compare le contenu d'une opérande mémoire ou d'un registre 16 bits avec un registre 16 bits.
3Bh /r | CMP reg16, reg/mem16 | Compare le contenu d'une opérande mémoire ou d'un registre 16 bits avec un registre 16 bits.
3Ch ib | CMP AL, imm8 | Compare une valeur 8 bits immédiate avec le contenu du registre AL.
3Dh iw | CMP AX, imm16 | Compare une valeur 16 bits immédiate avec le contenu du registre AX.
3Eh | DS: | Cette instruction permet d'indiquer un préfix au registre segment DS.
3Fh | AAS | Cette instruction permet de créer un nombre dépacter BCD à partir du contenu du registre AL
40h | INC AX | Cette instruction permet d'incrémenter le registre AX.
41h | INC CX | Cette instruction permet d'incrémenter le registre CX.
42h | INC DX | Cette instruction permet d'incrémenter le registre DX.
43h | INC BX | Cette instruction permet d'incrémenter le registre BX.
44h | INC SP | Cette instruction permet d'incrémenter le registre SP.
45h | INC BP | Cette instruction permet d'incrémenter le registre BP.
46h | INC SI | Cette instruction permet d'incrémenter le registre SI.
47h | INC DI | Cette instruction permet d'incrémenter le registre DI.
48h | DEC AX | Cette instruction permet de décrémenter le registre AX.
49h | DEC CX | Cette instruction permet de décrémenter le registre CX.
4Ah | DEC DX | Cette instruction permet de décrémenter le registre DX.
4Bh | DEC BX | Cette instruction permet de décrémenter le registre BX.
4Ch | DEC SP | Cette instruction permet de décrémenter le registre SP.
4Dh | DEC BP | Cette instruction permet de décrémenter le registre BP.
4Eh | DEC SI | Cette instruction permet de décrémenter le registre SI.
4Fh | DEC DI | Cette instruction permet de décrémenter le registre DI.
50h | PUSH AX | Cette instruction permet d'empiler le registre AX dans la pile.
51h | PUSH CX | Cette instruction permet d'empiler le registre CX dans la pile.
52h | PUSH DX | Cette instruction permet d'empiler le registre DX dans la pile.
53h | PUSH BX | Cette instruction permet d'empiler le registre BX dans la pile.
54h | PUSH SP | Cette instruction permet d'empiler le registre SP dans la pile.
55h | PUSH BP | Cette instruction permet d'empiler le registre BP dans la pile.
56h | PUSH SI | Cette instruction permet d'empiler le registre SI dans la pile.
57h | PUSH DI | Cette instruction permet d'empiler le registre DI dans la pile.
58h | POP AX | Cette instruction permet de désempiler de la pile une mot et la met dans le registre AX.
59h | POP CX | Cette instruction permet de désempiler de la pile une mot et la met dans le registre CX.
5Ah | POP DX | Cette instruction permet de désempiler de la pile une mot et la met dans le registre DX.
5Bh | POP BX | Cette instruction permet de désempiler de la pile une mot et la met dans le registre BX.
5Ch | POP SP | Cette instruction permet de désempiler de la pile une mot et la met dans le registre SP.
5Dh | POP BP | Cette instruction permet de désempiler de la pile une mot et la met dans le registre BP.
5Eh | POP SI | Cette instruction permet de désempiler de la pile une mot et la met dans le registre SI.
5Fh | POP DI | Cette instruction permet de désempiler de la pile une mot et la met dans le registre DI.
61h | POPA | Cette instruction permet de désempiler de la pile respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX.
62h /r | BOUND reg16, mem16&mem16 | Test avec un index de tableau 16 bits spécifié deux valeurs 16 bits
63h /r | ARPL reg/mem16, reg16 | Ajuste le RPL du sélecteur de segment de destination au niveau inférieur du RPL du sélecteur de segment spécifié dans le registre source 16 bits.
64h | FS: | Cette instruction permet d'indiquer un préfixe au registre segment FS.
65h | GS: | Cette instruction permet d'indiquer un préfixe au registre segment GS.
66h 0Fh 2Ah /r | CVTPI2PD xmm, mm/m64 | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de double précision compacté.
66h 0Fh 2Ch /r | CVTTPD2PI mm, xmm/m128 | Cette instruction permet de convertir une valeur réel de double précision compacté avec tronquage en un entier de format double mot compacté.
66h 0Fh 2Dh /r | CVTPD2PI mm, xmm/m128 | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en double mot entier.
66h 0Fh 2Fh /r | COMISD xmm1,xmm2/m64 | Cette instruction permet de comparer deux valeurs réel de double-précision dans la partie faible du quadruple mot de deux opérande et fixe les drapeaux de ZF, PF et FC du registre EFLAGS en fonction du résultat (non-ordonnée, supérieur à, inférieur ou égal).
66h 0Fh 38h 14h /r | BLENDVPS xmm1,xmm2/m128,xmm0 | Cette instruction permet de copier le paquet de valeurs réel de simple précisions de l'opérande source dans l'opérande de destination si la condition de masque de l'opérande du troisième opérande en registre est rempli.
66h 0Fh 38h 15h /r | BLENDVPD xmm1,xmm2/m128,xmm0 | Cette instruction permet de copier le paquet de valeurs réel de double précisions de l'opérande source dans l'opérande de destination si la condition de masque de l'opérande du troisième opérande en registre est rempli.
66h 0Fh 38h DBh /r | AESIMC xmm1,xmm2/m128 | Cette instruction permet d'effectuer une transformation InvMixColumns de l'opérande source et enregistre le résultat dans l'opérande de destination.
66h 0Fh 38h DCh /r | AESENC xmm1,xmm2/m128 | Cette instruction permet d'effectuer un arrondissement d'encryptage AES en utilisant la clef arrondie pour le deuxième opérande source, opération dans une données de 128 bits du premier opérande source, et enregistre le résultat dans l'opérande de destination.
66h 0Fh 38h DDh /r | AESENCLAST xmm1,xmm2/m128 | Cette instruction permet d'effectuer le dernier arrondissement d'encryptage AES en utilisant la clef arrondie pour le deuxième opérande source, opération dans une données de 128 bits du premier opérande source, et enregistre le résultat dans l'opérande de destination.
66h 0Fh 38h DEh /r | AESDEC xmm1,xmm2/m128 | Cette instruction permet d'effectuer un arrondissement du décryptage AES en utilisant l'équivalence de Cipher inversé, avec un clef arrondie pour le deuxième opérande source, opération dans une données de 128 bits du premier opérande source, et enregistre le résultat dans l'opérande de destination.
66h 0Fh 38h DFh /r | AESDECLAST xmm1,xmm2/m128 | Cette instruction permet d'effectuer le dernier arrondissement du décryptage AES en utilisant l'équivalence de Cipher inversé, avec un clef arrondie pour le deuxième opérande source, opération dans une données de 128 bits du premier opérande source, et enregistre le résultat dans l'opérande de destination.
66h 0Fh 3Ah 0Ch /r ib | BLENDPS xmm1,xmm2/m128,imm8 | Cette instruction permet de copier le paquet de valeurs réel de simple précisions de l'opérande source dans l'opérande de destination si la condition de masque de l'opérande immédiate est rempli.
66h 0Fh 3Ah 0Dh /r ib | BLENDPD xmm1,xmm2/m128,imm8 | Cette instruction permet de copier le paquet de valeurs réel de double précisions de l'opérande source dans l'opérande de destination si la condition de masque de l'opérande immédiate est rempli.
66h 0Fh 3Ah 40h /r ib | DPPS xmm1,xmm2/m128,imm8 | Cette instruction permet d'effectuer une multiplication conditionnel d'un paquet de valeurs réel de simple précision dans l'opérande de destination avec le paquet de valeurs réel de l'opérande source et effectue un masque des bits extrait d'un opérande immédiat.
66h 0Fh 3Ah 41h /r ib | DPPD xmm1,xmm2/m128,imm8 | Cette instruction permet d'effectuer une multiplication conditionnel d'un paquet de valeurs réel de double précision dans l'opérande de destination avec le paquet de valeurs réel de l'opérande source et effectue un masque des bits extrait d'un opérande immédiat.
66h 0Fh 3Ah DFh /r ib | AESKEYGENASSIST xmm1,xmm2/m128,imm8 | Cette instruction permet d'effectuer l'expansion de clef AES Cipher, en calculant la génération des clefs arrondies pour l'encryption, en utilisant les données 128 bits spécifiés de l'opérande source et de la constante arrondie arrondie 8 bits spécifié immédiate et enregistre le résultat dans l'opérande de destination.
66h 0Fh 54h /r | ANDPD xmm1, xmm2/m128 | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 paquets d'opérandes de valeur de format réel de double précision.
66h 0Fh 55h /r | ANDNPD xmm1, xmm2/m128 | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 paquets d'opérandes de valeur de format réel de double précision et inverse chacun des bits du résultat.
66h 0Fh 58h /r | ADDPD xmm1, xmm2/m128 | Cette instruction permet d'effectuer une addition de 2 paquets de valeurs réels de double précision d'une opérande source et d'une opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de double précision.
66h 0Fh 5Ah /r | CVTPD2PS xmm1, xmm2/m128 | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en valeurs réel de simple précision et fixe à 0 le reste du paquet.
66h 0Fh 5Bh /r | CVTPS2DQ xmm1, xmm2/m128 | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de simple précision en paquet de double mots entiers.
66h 0Fh 5Eh /r | DIVPD xmm1, xmm2/m128 | Cette instruction permet d'effectuer une division de valeur réel de double précision de registre XMM ou d'emplacement mémoire de 128 bits.
66h 0Fh C2h /r ib | CMPPD xmm1,xmm2/m128,imm8 | Cette instruction permet d'effectuer une comparaison SIMD de 2 paquets de valeurs réels de double précision d'un opérande source et d'un opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination.
66h 0Fh D0h /r | ADDSUBPD xmm1, xmm2/m128 | Cette instruction permet d'effectuer une soustraction de la partie basse d'une valeur réel de double précision d'une opérande source et destination et entrepose le résultat dans une opérande de destination de valeur réel de double précision et d'effectuer une addition de la partie haute d'une valeur réel de double précision d'une opérande source et destination et entrepose le résultat dans une opérande de destination de valeur réel de double précision.
66h 0Fh E6h /r | CVTTPD2DQ xmm1, xmm2/m128 | Cette instruction permet de convertir un paquet de valeur réel de double précision avec en un paquet d'entier de format double mot tronquer et fixe à 0 le reste du paquet.
66h 60h | PUSHAD | Cette instruction permet d'empiler respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX dans la pile.
66h 61h | POPAD | Cette instruction permet de désempiler de la pile respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX.
66h 6Ch | INSD | Cette instruction permet de demander un double mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction.
66h 6Fh | OUTSD | Cette instruction permet d'envoyer un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 4 en fonction de l'état du drapeau de direction.
66h 98h | CWDE | Cette instruction est l'alternative pour convertir le mot du registre AX en un double mot contenu dans le registre EAX par extension du signe.
66h 99h | CDQ | Cette instruction permet de convertir le double mot en un quadruple mot, le résultat tient sur une taille de 64 bits.
66h 9Ch | PUSHFD | Cette instruction permet d'empiler respectivement le registre 32 bits de drapeau des indicateurs d'état dans la pile.
66h 9Dh | POPFD | Cette instruction permet de désempiler de la pile le registre 32 bits de drapeau contenant les indicateurs d'état.
66h A5h | MOVSD | Cette instruction permet de copier un double mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 4 en fonction de l'état du drapeau de direction.
66h A7h | CMPSD | Cette instruction permet d'effectuer la comparaison d'un double mot avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison.
66h ABh | STOSD | Cette instruction permet de copier le registre EAX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction.
66h ADh | LODSD | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 4 en fonction de l'état du drapeau de direction.
66h AFh | SCASD | Cette instruction permet de comparer le registre EAX avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction.
6Ch | INSB | Cette instruction permet de demander un octet du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction.
6Dh | INSW | Cette instruction permet de demander un mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction.
6Eh | OUTSB | Cette instruction permet d'envoyer un octet contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 1 en fonction de l'état du drapeau de direction.
6Fh | OUTSW | Cette instruction permet d'envoyer un mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 2 en fonction de l'état du drapeau de direction.
70h (rel8) | JO rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
71h (rel8) | JNO rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
72h (rel8) | JB/JNAE/JC rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
73h (rel8) | JNB/JAE/JNC rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
74h (rel8) | JZ/JE rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
75h (rel8) | JNZ/JNE rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
76h (rel8) | JBE/JNA rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
77h (rel8) | JNBE/JA rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
78h (rel8) | JS rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
79h (rel8) | JNS rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
7Ah (rel8) | JP/JPE rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
7Bh (rel8) | JNP/JPO rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
7Ch (rel8) | JL/JNGE rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
7Dh (rel8) | JNL/JGE rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
7Eh (rel8) | JLE/JNG rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
7Fh (rel8) | JNLE/JG rel8 | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
80h /0 ib | ADD reg/mem8, imm8 | Ajout immédiate de 8 bits à registre/mémoire 8 bits
80h /2 ib | ADC reg/mem8, imm8 | Cette instruction permet d'ajouter un immédiat de 8 bits à un registre/mémoire + CF
80h /4 ib | AND reg/mem8, imm8 | Et binaire sur le contenu du registre/mémoire 8 bits avec une valeur immédiate 8 bits
80h /7 ib | CMP reg/mem8, imm8 | Compare une valeur 8 bits immédiate avec le contenu d'une opérande mémoire ou d'un registre 8 bits.
81h /0 iw | ADD reg/mem16, imm16 | Ajout immédiate de 16 bits à registre/mémoire 16 bits
81h /2 iw | ADC reg/mem16, imm16 | Cette instruction permet d'ajouter un immédiat de 16 bits à registre/mémoire 16 bits + CF
81h /4 iw | AND reg/mem16, imm16 | Et binaire sur le contenu du registre/mémoire 16 bits avec une valeur immédiate 16 bits
81h /7 iw | CMP reg/mem16, imm16 | Compare une valeur 16 bits immédiate avec le contenu d'une opérande mémoire ou d'un registre 16 bits.
83h /0 ib | ADD reg/mem16, imm8 | Ajout entier immédiate de 8 bits à registre/mémoire 16 bits
83h /2 ib | ADC reg/mem16, imm8 | Cette instruction permet d'ajouter un immédiat de 8 bits entier à registre/mémoire 16 bits + CF
83h /4 ib | AND reg/mem16, imm8 | Et binaire sur le contenu du registre/mémoire 16 bits avec une valeur entière immédiate 8 bits
90h | NOP | Cette instruction ne fait rien.
91h | XCHG AX,CX | Cette instruction permet d'échanger les valeurs des registres AX et CX
92h | XCHG AX,DX | Cette instruction permet d'échanger les valeurs des registres AX et DX
94h | XCHG AX,SP | Cette instruction permet d'échanger les valeurs des registres AX et SP
95h | XCHG AX,BP | Cette instruction permet d'échanger les valeurs des registres AX et BP
96h | XCHG AX,SI | Cette instruction permet d'échanger les valeurs des registres AX et SI
97h | XCHG AX,DI | Cette instruction permet d'échanger les valeurs des registres AX et DI
98h | CBW | Cette instruction permet de convertir un nombre contenu dans le registre AL en un format sur 16 bits pour se retrouver dans le registre AX en appliquant une extension du signe.
99h | CWD | Cette instruction est l'alternative pour convertir le mot du registre AX en un double mot contenu dans le couple de registre DX et AX par extension du signe.
9Ah {immW2} {immW1} | CALL immW1:immW2 | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse d'appel avant de continuer.
9Bh | WAIT | Cette instruction permet de faire passer le microprocesseur en mode d'attente jusqu'à ce que la ligne de teste sur la carte mère s'active.
9Bh DBh E0h | FENI | Cette instruction permet d'autoriser les interruptions.
9Bh DBh E1h | FDISI | Cette instruction permet de désactiver les interruptions.
9Bh DBh E2h | FCLEX | Cette instruction permet d'effacer toutes les exceptions contenu dans les drapeaux de registres du coprocesseur mathématique.
9Ch | PUSHF | Cette instruction permet d'empiler respectivement le registre 16 bits de drapeau des indicateurs d'état dans la pile.
9Dh | POPF | Cette instruction permet de désempiler de la pile le registre 16 bits de drapeau contenant les indicateurs d'état.
9Eh | SAHF | Cette instruction permet de copier les bits du registre AH dans l'octet de poids faible dans le registre des drapeaux (les indicateurs d'état).
9Fh | LAHF | Cette instruction permet de transférer les bits d'indicateurs du registre d'état vers le registre AH.
A0h xxh yyh | MOV AL,[yyxxh] | ...
A1h xxh yyh | MOV AX,[yyxxh] | ...
A2h xxh yyh | MOV [yyxxh],AL | ...
A3h xxh yyh | MOV [yyxxh],AX | ...
A4h | MOVSB | Cette instruction permet de copier un octet de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 1 en fonction de l'état du drapeau de direction.
A5h | MOVSW | Cette instruction permet de copier un mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 2 en fonction de l'état du drapeau de direction.
A6h | CMPSB | Cette instruction permet d'effectuer la comparaison d'un octet avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison.
A7h | CMPSW | Cette instruction permet d'effectuer la comparaison d'un mot avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison.
A8h xxh | TEST AL,xxh | Cette instruction permet d'effectuer un test de «Et binaire» avec une valeur immédiate de 8 bits sur le registre AL et indique le résultat de la comparaison sur le registre des drapeaux.
A9h xxh yyh | TEST AX,yyxxh | Cette instruction permet d'effectuer un test de «Et binaire» avec une valeur immédiate de 16 bits sur le registre AX et indique le résultat de la comparaison sur le registre des drapeaux.
AAh | STOSB | Cette instruction permet de copier le registre AL dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction.
ABh | STOSW | Cette instruction permet de copier le registre AX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction.
ACh | LODSB | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 1 en fonction de l'état du drapeau de direction.
ADh | LODSW | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 2 en fonction de l'état du drapeau de direction.
AEh | SCASB | Cette instruction permet de comparer le registre AL avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction.
AFh | SCASW | Cette instruction permet de comparer le registre AX avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction.
B0h xxh | MOV AL,xxh | Cette instruction permet de copier une valeur immédiate de 8 bits dans le registre AL.
B1h xxh | MOV CL,xxh | Cette instruction permet de copier une valeur immédiate de 8 bits dans le registre CL.
B2h xxh | MOV DL,xxh | Cette instruction permet de copier une valeur immédiate de 8 bits dans le registre DL.
B3h xxh | MOV BL,xxh | Cette instruction permet de copier une valeur immédiate de 8 bits dans le registre BL.
B4h xxh | MOV AH,xxh | Cette instruction permet de copier une valeur immédiate de 8 bits dans le registre AH.
B5h xxh | MOV CH,xxh | Cette instruction permet de copier une valeur immédiate de 8 bits dans le registre CH.
B6h xxh | MOV DH,xxh | Cette instruction permet de copier une valeur immédiate de 8 bits dans le registre DH.
B7h xxh | MOV BH,xxh | Cette instruction permet de copier une valeur immédiate de 8 bits dans le registre BH.
B8h xxh yyh | MOV AX,yyxxh | Cette instruction permet de copier une valeur immédiate de 16 bits dans le registre AX.
B9h xxh yyh | MOV CX,yyxxh | Cette instruction permet de copier une valeur immédiate de 16 bits dans le registre CX.
BAh xxh yyh | MOV DX,yyxxh | Cette instruction permet de copier une valeur immédiate de 16 bits dans le registre DX.
BBh xxh yyh | MOV BX,yyxxh | Cette instruction permet de copier une valeur immédiate de 16 bits dans le registre BX.
BCh xxh yyh | MOV SP,yyxxh | Cette instruction permet de copier une valeur immédiate de 16 bits dans le registre SP.
BDh xxh yyh | MOV BP,yyxxh | Cette instruction permet de copier une valeur immédiate de 16 bits dans le registre BP.
BEh xxh yyh | MOV SI,yyxxh | Cette instruction permet de copier une valeur immédiate de 16 bits dans le registre SI.
BFh xxh yyh | MOV DI,yyxxh | Cette instruction permet de copier une valeur immédiate de 16 bits dans le registre DI.
C3h | RETN | Cette instruction permet de quitter une procédure ayant lieu avec un appel court (NEAR CALL).
C8h iw ib | ENTER imm16, imm8 | Crée un cadre de pile pour une procédure
C9h | LEAVE | Cette instruction permet de libérer une zone de mémoire attribué par l'instruction «ENTER» lorsqu'on utilise des procédures dans des langages de programmation de haut niveau.
CAh xxh yyh | RETF yyxxh | Cette instruction permet de quitter une procédure ayant lieu avec un appel long (FAR CALL).
CBh | RETF | Cette instruction permet de quitter une procédure ayant lieu avec un appel long (FAR CALL).
CCh | INT 03h | Cette instruction permet d'exécuter l'interruption avec le numéro 03h.
CDh xxh | INT xxh | Cette instruction permet d'exécuter l'interruption avec le numéro spécifié.
CEh | INTO | Cette instruction permet d'exécuter l'interruption numéro 4 si le drapeau de débordement (OF) est fixé sur 1.
CFh | IRET | Cette instruction permet d'effectuer un retour précédemment provoquer par une interruption.
D4h 0Ah | AAM | Cette instruction offre la possibilité de convertir le produit de la multiplication de 2 valeurs de format DCB en un format DCB.
D5h 0Ah | AAD | Cette instruction permet de convertir une valeur de format DCB non compactée.
D6h | SETALC (SALC) | Cette instruction permet de copier la valeur du drapeau de retenue dans le registre AL en la multipliant par 0FFh.
D7h | XLAT | Cette instruction permet de remplacer le contenu du registre AL par un octet de la «tablesource».
D8h /0 | FADD mem32 | Cette instruction permet d'ajouter le nombre réel de valeur positive «source» à «cible» et enregistre la somme dans «cible».
D8h /2 | FCOM mem32 | Cette instruction permet de comparer le nombre réel de valeur positive source avec le registre mathématique ST(0) et mettre les indicateurs d'état C0 à C3 avec la valeur 1.
D8h /3 | FCOMP mem32 | Cette instruction permet de comparer le nombre réel de valeur positive «source» avec le registre mathématique ST(0), mettre les indicateurs d'état C0 à C3 avec la valeur 1 et dépile le registre mathématique ST(0) de la pile de registres.
D8h /6 | FDIV mem32 | Cette instruction permet d'effectuer des divisions de nombre réel de valeur positive source par cible et enregistrer le résultat dans cible.
D8h /7 | FDIVR mem32 | Cette instruction permet d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».
D8h 06h yyh xxh imm8 | ESC [xxyy],imm8 | Cette instruction active le coprocesseur, lequel se permettra d'utiliser les méthodes d'adressage du processeur principal (CPU).
D8h (C0h+r) | FADD fpureg | Cette instruction permet d'ajouter le nombre réel de valeur positive «source» à «cible» et enregistre la somme dans «cible».
D8h (D0h+r) | FCOM fpureg | Cette instruction permet de comparer le nombre réel de valeur positive source avec le registre mathématique ST(0) et mettre les indicateurs d'état C0 à C3 avec la valeur 1.
D8h (D8h+r) | FCOMP fpureg | Cette instruction permet de comparer le nombre réel de valeur positive «source» avec le registre mathématique ST(0), mettre les indicateurs d'état C0 à C3 avec la valeur 1 et dépile le registre mathématique ST(0) de la pile de registres.
D8h (F0h+r) | FDIV fpureg | Cette instruction permet d'effectuer des divisions de nombre réel de valeur positive source par cible et enregistrer le résultat dans cible.
D8h (F8h+r) | FDIVR fpureg | Cette instruction permet d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».
D9h E0h | FCHS | Cette instruction permet d'inverser le signe du registre mathématique ST(0).
D9h E1h | FABS | Cette instruction permet de convertir le nombre réel contenu dans le registre mathématique ST(0) en sa valeur absolue.
D9h F0h | F2XM1 | Cette instruction permet de remplacer ST(0) avec 2 à la (ST(0) - 1).
D9h F6h | FDECSTP | Cette instruction permet de décrémenter le pointeur de pile de registres.
D9h FFh | FCOS | Cette instruction permet de calculer le cosinus du registre mathématique ST(0) et l'enregistrer dans le registre mathématique ST(1); ensuite met dans le registre mathématique ST(0) à la valeur 1,0.
DAh /0 | FIADD mem32 | Cette instruction permet d'ajouter le nombre réel source à cible et enregistre la somme dans cible.
DAh (C0h+i) | FCMOVB ST,STi | Cette instruction permet de déplacé des nombres réel si inférieur.
DAh (C8h+i) | FCMOVE ST,STi | Cette instruction permet de déplacé des nombres réel si égale.
DAh (D0h+i) | FCMOVBE ST,STi | Cette instruction permet de déplacé des nombres réel si inférieur ou égale.
DAh (D8h+i) | FCMOVU ST,STi | Cette instruction permet de déplacé des nombres réel si désordonné.
DBh (C0h+i) | FCMOVNB ST,STi | Cette instruction permet de déplacé des nombres réel si pas inférieur.
DBh (C8h+i) | FCMOVNE ST,STi | Cette instruction permet de déplacé des nombres réel si pas égale.
DBh (D0h+i) | FCMOVNBE ST,STi | Cette instruction permet de déplacé des nombres réel si pas inférieur ou égale.
DBh (D8h+i) | FCMOVNU ST,STi | Cette instruction permet de déplacé des nombres réel si pas désordonné.
DBh E4h | FSETPM | Cette instruction permet de faire passer le coprocesseur mathématique en mode protégé.
DBh (E8h+i) | FUCOMI ST, ST(i) | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et vérifie l'ordre des valeurs et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats.
DBh (F0h+i) | FCOMI ST, ST(i) | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats.
DCh /0 | FADD mem64 | Cette instruction permet d'ajouter le nombre réel de valeur positive «source» à «cible» et enregistre la somme dans «cible».
DCh /2 | FCOM mem64 | Cette instruction permet de comparer le nombre réel de valeur positive source avec le registre mathématique ST(0) et mettre les indicateurs d'état C0 à C3 avec la valeur 1.
DCh /3 | FCOMP mem64 | Cette instruction permet de comparer le nombre réel de valeur positive «source» avec le registre mathématique ST(0), mettre les indicateurs d'état C0 à C3 avec la valeur 1 et dépile le registre mathématique ST(0) de la pile de registres.
DCh /6 | FDIV mem64 | Cette instruction permet d'effectuer des divisions de nombre réel de valeur positive source par cible et enregistrer le résultat dans cible.
DCh /7 | FDIVR mem64 | Cette instruction permet d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».
DCh (C0h+r) | FADD fpureg,ST0 | Cette instruction permet d'ajouter le nombre réel de valeur positive «source» à «cible» et enregistre la somme dans «cible».
DCh (F0h+r) | FDIVR fpureg,ST0 | Cette instruction permet d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».
DCh (F8h+r) | FDIV fpureg,ST0 | Cette instruction permet d'effectuer des divisions de nombre réel de valeur positive source par cible et enregistrer le résultat dans cible.
DDh (C0h+r) | FFREE fpureg | Cette instruction permet de libérer le registre «cible» devant représenté un des registres de la pile.
DEh /0 | FIADD mem16 | Cette instruction permet d'ajouter le nombre réel source à cible et enregistre la somme dans cible.
DEh (C0h+r) | FADDP fpureg | Cette instruction complémentaire ajoute le nombre réel source au nombre réel cible et enregistrer la somme dans cible puis prendre le registre mathématique ST(0) et le dépile.
DEh D9h | FCOMPP | Cette instruction permet de comparer les nombres réels du registre mathématique ST(1) avec le registre mathématique ST(0), ensuite de mettre les indicateurs d'état C0 à C3 à la valeur 1 et prendre le couple de registre mathématique ST(1) et ST(0) dans la pile de registres (2 dépilages).
DEh (F0h+r) | FDIVRP fpureg | Cette instruction permet d'effectuer des divisions de nombre réel avec les registres inversés «cible» par «source» et place ST(0) dans la pile.
DEh F1h | FDIVRP | Cette instruction permet d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».
DEh (F8h+r) | FDIVP fpureg | Cette instruction permet d'effectuer des division de nombre réel et place ST(0) dans la pile.
DFh /4 | FBLD mem80 | Cette instruction charge la valeur de format DCB compactée après le registre mathématique ST(0).
DFh /6 | FBSTP mem80 | Cette instruction extrait la valeur de format DCB compactée du registre mathématique ST(0), l'enregistrer dans cible et prendre le registre mathématique ST(0) et sort de la pile.
DFh (C0h+r) | FFREEP fpureg | Cette instruction permet de libérer un des registres de la pile et d'ensuite de désempiler le registre de la pile.
DFh (E8h+i) | FUCOMIP ST, ST(i) | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et vérifie l'ordre des valeurs et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats et désempile de la pile la valeur dans le registre.
DFh (F0h+i) | FCOMIP ST, ST(i) | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats et désempile de la pile la valeur dans le registre.
E8h iw | CALL rel16off | Appel court avec une destination spécifié par une adresse 16 bits
EBh (rel8) | JMP rel8 | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié.
ECh | IN AL,DX | Cette instruction permet de lire un octet dans un port d'entrée/sortie à l'adresse spécifié par le registre DX et met le résultat dans le registre AL.
EDh | IN AX,DX | Cette instruction permet de lire un mot dans un port d'entrée/sortie à l'adresse spécifié par le registre DX et met le résultat dans le registre AX.
EEh | OUT DX,AL | Cette instruction permet de mettre un octet contenu dans le registre AL dans le port spécifié par le registre DX.
EFh | OUT DX,AX | Cette instruction permet de mettre un mot contenu dans le registre AX dans le port spécifié par le registre DX.
F0h | LOCK | Cette instruction est utilisé comme préfixe avec d'autres instructions pour amener le microprocesseur à émettre un signal de verrouillage (Lock) sur le bus lors du traitement de l'instruction suivante.
F1h | SMI | Cette instruction permet de gérer les interruptions systèmes en mode de débogage.
F1h | ICEBP | Cette instruction permet de passer en mode d'instruction ICE (In-Circuit Emulator) si le bit 12 du registre DR7 vaut 1 sinon il exécute l'interruption 1.
F2h | REPNE | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1.
F2h 0Fh 2Ah /r | CVTSI2SD xmm, r/m32 | Cette instruction permet de convertir un entier de format double mot en une valeur réel de double précision.
F2h 0Fh 2Ch /r | CVTTSD2SI r32, xmm/m64 | Cette instruction permet de convertir une valeur réel de double précision avec en un entier de format double mot tronquer.
F2h 0Fh 2Dh /r | CVTSD2SI r32, xmm/m64 | Cette instruction permet d'effectuer la conversion d'une valeur réel de simple précision en valeur entier de double mots.
F2h 0Fh 38h F0h /r | CRC32 r32, r/m8 | Cette instruction débute avec une valeur initiale dans l'opérande de destination, accumule une valeur de code CRC-32 (polynomial de 11EDC6F41h) dans l'opérande source et enregistre le résultat dans l'opérande de destination.
F2h 0Fh 38h F1h /r | CRC32 r32, r/m16 | Cette instruction débute avec une valeur initiale dans l'opérande de destination, accumule une valeur de code CRC-32 (polynomial de 11EDC6F41h) dans l'opérande source et enregistre le résultat dans l'opérande de destination.
F2h 0Fh 58h /r | ADDSD xmm1, xmm2/m128 | Cette instruction permet d'effectuer une addition de la partie basse d'une valeur réel de double précision d'une opérande source et destination et entrepose le résultat dans une opérande de destination de valeur réel de double précision.
F2h 0Fh 5Ah /r | CVTSD2SS xmm1, xmm2/m64 | Cette instruction permet d'effectuer la conversion d'une valeur réel de double précision en valeur réel de simple précision.
F2h 0Fh 5Eh /r | DIVSD xmm1, xmm2/m64 | Cette instruction permet d'effectuer une division scalaire de valeur réel de double précision de registre XMM ou d'emplacement mémoire de 128 bits.
F2h 0Fh C2h /r ib | CMPSD xmm1,xmm2/m64, imm8 | Cette instruction permet d'effectuer une comparaison de la partie basse de valeurs réelles de double précision d'un opérande source et d'un opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination.
F2h 0Fh D0h /r | ADDSUBPS xmm1, xmm2/m128 | Cette instruction permet d'effectuer une soustraction de la partie basse d'un paquet de valeur réel de simple précision d'une opérande source et destination et entrepose le résultat dans une opérande de destination de valeur réel de simple précision et d'effectuer une addition de la partie haute d'un paquet de valeur réel de simple précision d'une opérande source et destination et entrepose le résultat dans une opérande de destination de valeur réel de simple précision.
F2h 0Fh E6h | CVTPD2DQ xmm1, xmm2/m128 | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en double mot entier et fixe à 0 le reste du paquet.
F3h | REP | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions tant que CX ne vaut pas 0.
F3h 0Fh 2Ah /r | CVTSI2SS xmm,r/m32 | Cette instruction permet de convertir un entier de format double mot en une valeur réel de simple précision.
F3h 0Fh 2Ch /r | CVTTSS2SI r32,xmm/m32 | Cette instruction permet de convertir un entier de format double mot avec tronquage en une valeur réel de simple précision.
F3h 0Fh 2Dh /r | CVTSS2SI r32,xmm/m32 | Cette instruction permet de convertir une valeur réel de simple précision en un entier de format double mot.
F3h 0Fh 58h /r | ADDSS xmm1, xmm2/m32 | Cette instruction permet d'ajouter la partie basse d'une valeur réel de simple précision de xmm2/m32 to xmm1.
F3h 0Fh 5Ah /r | CVTSS2SD xmm1, xmm2/m32 | Cette instruction permet de convertir une valeur réel de simple précision en une valeur réel de double précision.
F3h 0Fh 5Bh /r | CVTTPS2DQ xmm1, xmm2/m128 | Cette instruction permet de convertir un paquet de valeur réel de simple précision avec en un paquet d'entier de format double mot tronquer.
F3h 0Fh 5Eh /r | DIVSS xmm1,xmm2/m128 | Cette instruction permet d'effectuer une division scalaire de valeur réel de simple précision de registre XMM ou d'emplacement mémoire de 128 bits.
F3h 0Fh B8h /r | POPCNT reg16, reg/mem16 | Cette instruction permet de compter le nombre de bits à 1 que possède une opérande source et place le résultat dans un registre destinataire.
F3h 0Fh C2h /r imm8 | CMPSS xmm1,xmm2/m128,imm8 | Cette instruction permet d'effectuer une comparaison de la partie basse de valeurs réels de simple précision d'une opérande source et d'une opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination.
F3h 0Fh E6h | CVTDQ2PD xmm1, xmm2/m64 | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de double précision.
F3h 90h | PAUSE | Cette instruction permet d'améliorer les performances des boucles de «SPIN», en fournissant une indication pour le microprocesseur que le code courant est dans une boucle en «SPIN».
F4h | HLT | Cette instruction permet de faire passer le microprocesseur en mode d'arrêt. Toutefois, le processeur peut quitter cet état lorsqu'une ligne matérielle RESET ou lorsqu'une interruption non-masquable (NMI) reçoit un signal.
F5h | CMC | Cette instruction offre la possibilité d'inverser la valeur de l'indicateur de retenue. Si ce dernier vaut 1, elle le met à 0 et inversement.
F6h /6 | DIV reg/mem8 | Division naturel de AX par le contenu d'un emplacement mémoire ou registre 8 bits et entrepose le quotient dans AL et restant dans AH.
F7h /6 | DIV reg/mem16 | Division naturel de DX:AX par le contenu d'un emplacement mémoire ou registre 16 bits et entrepose le quotient dans AX et restant dans DX.
F8h | CLC | Cette instruction permet de mettre l'indicateur d'état de retenu CF à 0.
F9h | STC | Cette instruction permet de fixer l'indicateur de retenue (CF) à la valeur 1.
FAh | CLI | Cette instruction met l'indicateur d'état IF à 0, soit l'interdiction des interruptions.
FBh | STI | Cette instruction permet de fixer l'indicateur d'interruption (IF) à la valeur 1.
FCh | CLD | Cette instruction met l'indicateur d'état DF à 0, soit la direction croissante.
FDh | STD | Cette instruction permet de fixer l'indicateur de direction (DF) à la valeur 1.
FEh /1 | DEC reg/mem8 | Décrémente de 1 le contenu d'un emplacement de registre ou mémoire 8 bits
FFh /1 | DEC reg/mem16 | Décrémente de 1 le contenu d'un emplacement de registre ou mémoire 16 bits
FFh /2 | CALL reg/mem16 | Appel court avec une destination spécifié par un registre/mémoire 16 bits
FFh /3 | CALL FAR mem16:16 | Appel long indirect, avec un destination spécifié par un pointeur long en mémoire.
... | ... | ...

Références

Assembleur - Référence, Edition Micro Application, Pierre Maurette, 2003, ISBN: 2-7429-3061-2.
The Undocumented PC: A programmer's Guide to I/O, CPUs, and Fixed Memory Areas - Second Edition, Edition Addison-Wesley, Frank van Gilluwe, 1997, ISBN: 0-201-47950-8.
Dernière mise à jour : Samedi, le 21 décembre 2013


8086 et 8088

Voici la liste des instructions d'origines des 8086 et 8088 :

Instruction | Signification | Description
AAA | ASCII adjust AL after addition | Cette instruction permet d'adapter le résultat obtenu par l'addition de 2 valeur en format DCB.
AAD | ASCII adjust AX before division | Cette instruction permet de convertir une valeur de format DCB non compactée.
AAM | ASCII adjust AX after multiplication | Cette instruction offre la possibilité de convertir le produit de la multiplication de 2 valeurs de format DCB en un format DCB.
AAS | ASCII adjust AL after subtraction | Cette instruction permet d'adapter le résultat de la soustraction de nombre de format DCB.
ADC | Add with carry | Cette instruction additionne 2 quantités numériques sur 8 ou 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu.
ADD | Add | Cette instruction additionne 2 quantités numérique sur 8, 16 ou 32 bits.
AND | And | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés.
CALL | Call procedure | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse d'appel avant de continuer.
CBW | Convert byte to word | Cette instruction permet de convertir un nombre contenu dans le registre AL en un format sur 16 bits pour se retrouver dans le registre AX en appliquant une extension du signe.
CLC | Clear carry flag | Cette instruction permet de mettre l'indicateur d'état de retenu CF à 0.
CLD | Clear direction flag | Cette instruction met l'indicateur d'état DF à 0, soit la direction croissante.
CLI | Clear interrupt flag | Cette instruction met l'indicateur d'état IF à 0, soit l'interdiction des interruptions.
CMC | Complement carry flag | Cette instruction offre la possibilité d'inverser la valeur de l'indicateur de retenue. Si ce dernier vaut 1, elle le met à 0 et inversement.
CMP | Compare operands | Cette instruction offre la possibilité essentielle de comparer 2 registres ou emplacements de mémoire.
CMPS | Compare String | Cette instruction permet d'effectuer la comparaison d'un octet, d'un mot ou double mot spécifié avec l'opérande source et destination spécifié et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison.
CMPSB | Compare String Byte | Cette instruction permet d'effectuer la comparaison d'un octet avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison.
CMPSW | Compare String Word | Cette instruction permet d'effectuer la comparaison d'un mot avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison.
CWD | Convert word to doubleword | Cette instruction est l'alternative pour convertir le mot du registre AX en un double mot contenu dans le couple de registre DX et AX par extension du signe.
DAA | Decimal adjust AL after addition | Cette instruction corrige après coup les retenues lors de la manipulation de valeur DCB.
DAS | Decimal adjust AL after subtraction | Cette instruction offre l'intéressante possibilité de corrige le résultat d'une soustraction de 2 nombres de format DCB compactées.
DEC | Decrement by 1 | Cette instruction décrément de 1 le registre ou l'adresse mémoire spécifié.
DIV | Unsigned divide | Cette instruction permet d'effectuer une division non-signée (nombre naturel).
ESC | Escape | Cette instruction active le coprocesseur, lequel se permettra d'utiliser les méthodes d'adressage du processeur principal (CPU).
HLT | Halt | Cette instruction permet de faire passer le microprocesseur en mode d'arrêt. Toutefois, le processeur peut quitter cet état lorsqu'une ligne matérielle RESET ou lorsqu'une interruption non-masquable (NMI) reçoit un signal.
IDIV | Integer divide | Cette instruction permet d'effectuer une division signée (nombre entier).
IMUL | Integer multiply | Cette instruction permet d'effectuer une multiplication signée (nombre entier).
IN | Input from port | Cette instruction permet de demander un octet, un mot ou un double mot provenant du port d'entrée/sortie et le retourne dans le registre accumulateur (AL, AX, EAX).
INC | Increment by 1 | Cette instruction permet d'incrémenter un registre ou un emplacement mémoire.
INT | Interrupt | Cette instruction permet d'exécuter l'interruption avec le numéro spécifié.
INTO | Interrupt if overflow | Cette instruction permet d'exécuter l'interruption numéro 4 si le drapeau de débordement (OF) est fixé sur 1é
IRET | Return from interrupt | Cette instruction permet d'effectuer un retour précédemment provoquer par une interruption.
Jcc | Jump if condition | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié.
JMP | Jump | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié.
LAHF | Load flags into AH register | Cette instruction permet de transférer les bits d'indicateurs du registre d'état vers le registre AH.
LDS | Load pointer using DS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment DS et dans un registre d'offset spécifié.
LEA | Load Effective Address | Cette instruction permet de copier l'offset d'une adresse de mémoire contenu dans un registre spécifié.
LES | Load ES with pointer | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment ES et dans un registre d'offset spécifié.
LOCK | Assert BUS LOCK# signal | Cette instruction est utilisé comme préfixe avec d'autres instructions pour amener le microprocesseur à émettre un signal de verrouillage (Lock) sur le bus lors du traitement de l'instruction suivante.
LODS | Load String | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction.
LODSB | Load String Byte | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 1 en fonction de l'état du drapeau de direction.
LODSW | Load String Word | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 2 en fonction de l'état du drapeau de direction.
LOOP | Loop | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0.
LOOPE | Loop equal | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1.
LOOPNE | Loop not equal | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0.
MOV | Move | Cette instruction permet de copier opérande source dans une opérande destinataire.
MOVS | Move String | Cette instruction permet de copier un élément de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction.
MOVSB | Move Byte from string to string | Cette instruction permet de copier un octet de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 1 en fonction de l'état du drapeau de direction.
MOVSW | Move Word from string to string | Cette instruction permet de copier un mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 2 en fonction de l'état du drapeau de direction.
MUL | Unsigned multiply | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel).
NEG | Negation | Cette instruction permet d'effectuer le complément à 2 d'une opérande.
NOP | No operation | Cette instruction ne fait rien.
NOT | Not | Cette instruction permet d'inverser la valeur de chacun des bits d'une opérande.
OR | Or | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandes spécifiés.
OUT | Output to port | Cette instruction permet d'envoyer un octet, un mot ou un double mot sur le port d'entrée/sortie.
POP | Pop data from stack | Cette instruction permet de désempiler de la pile une mot ou un double mot et la met dans une opérande.
POPF | Pop data into Flags register | Cette instruction permet de désempiler de la pile le registre 16 bits de drapeau contenant les indicateurs d'état.
PUSH | Push data onto stack | Cette instruction permet d'empiler une mot ou un double mot dans la pile.
PUSHF | Push flags onto stack | Cette instruction permet d'empiler respectivement le registre 16 bits de drapeau des indicateurs d'état dans la pile.
RCL 1 | Rotate left (with carry) | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré.
RCR 1 | Rotate right (with carry) | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré.
REP | Repeat | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions tant que CX ne vaut pas 0.
REPE | Repeat equal | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0.
REPNE | Repeat not equal | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1.
RET | Return from procedure | Cette instruction permet de quitter une procédure.
RETF | Return from far procedure | Cette instruction permet de quitter une procédure ayant lieu avec un appel long (FAR CALL).
RETN | Return from near procedure | Cette instruction permet de quitter une procédure ayant lieu avec un appel court (NEAR CALL).
ROL 1 | Rotate left | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré.
ROR 1 | Rotate right | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré.
SAHF | Store AH into flags | Cette instruction permet de copier les bits du registre AH dans l'octet de poids faible dans le registre des drapeaux (les indicateurs d'état).
SAL 1 | Shift Arithmetically left | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF).
SAR 1 | Shift Arithmetically right | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF).
SBB | Subtraction with borrow | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande.
SCAS | String Compare String | Cette instruction permet de comparer un octet, un mot ou un double mot avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction.
SCASB | String Compare String Byte | Cette instruction permet de comparer le registre AL avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction.
SCASW | String Compare String Word | Cette instruction permet de comparer le registre AX avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction.
SEG | Segment | Cette directive permet de demander la partie segment de l'adresse d'une opérande.
SETALC | Set AL Carry | Cette instruction permet de copier la valeur du drapeau de retenue dans le registre AL en la multipliant par 0FFh.
SHL 1 | Shift left | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF).
SHR 1 | Shift right | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF).
STC | Set carry flag | Cette instruction permet de fixer l'indicateur de retenue (CF) à la valeur 1.
STD | Set direction flag | Cette instruction permet de fixer l'indicateur de direction (DF) à la valeur 1.
STI | Set interrupt flag | Cette instruction permet de fixer l'indicateur d'interruption (IF) à la valeur 1.
STOS | Store in string | Cette instruction permet de copier un octet, un mot ou un double mot dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction.
STOSB | Store in string Byte | Cette instruction permet de copier le registre AL dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction.
STOSW | Store in string Word | Cette instruction permet de copier le registre AX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction.
SUB | Subtraction | Cette instruction permet de soustraire une valeur à une opérande.
TEST | Test | Cette instruction permet d'effectuer un «Et binaire» sur une opérande cible sans modifier sa valeur.
WAIT | Wait | Cette instruction permet de faire passer le microprocesseur en mode d'attente jusqu'à ce que la ligne de teste sur la carte mère s'active.
XCHG | Exchange | Cette instruction permet d'échanger la valeur de deux opérandes.
XLAT | Table look-up translation | Cette instruction permet de remplacer le contenu du registre AL par un octet de la «tablesource».
XOR | Exclusive OR | Cette instruction permet d'effectuer un OU exclusif BINAIRE sur les 2 opérandes spécifiés.

80186 et 80188

Voici la liste des instructions ajouter au 80186 et 80188 :

Instruction | Signification | Description
BOUND | Bounds | Cette instruction permet de vérifier la validité pouvant exister entre avec un tableau et son indexation.
ENTER | Enter stack frame | Cette instruction permet de créer les structures de paramètres nécessaires aux procédures des langages de haut niveau.
INS | Input from port to string | Cette instruction permet de demander un octet, un mot ou un double mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction.
INSB | Input from port to string Byte | Cette instruction permet de demander un octet du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction.
INSW | Input from port to string Word | Cette instruction permet de demander un mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction.
LEAVE | Leave stack frame | Cette instruction permet de libérer une zone de mémoire attribué par l'instruction «ENTER» lorsqu'on utilise des procédures dans des langages de programmation de haut niveau.
OUTS | Output string to port | Cette instruction permet d'envoyer un octet, un mot ou un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction.
OUTSB | Output String Byte to port | Cette instruction permet d'envoyer un octet contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 1 en fonction de l'état du drapeau de direction.
OUTSW | Output String Word to port | Cette instruction permet d'envoyer un mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 2 en fonction de l'état du drapeau de direction.
POPA | Pop All | Cette instruction permet de désempiler de la pile respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX.
PUSHA | Push All | Cette instruction permet d'empiler respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX dans la pile.

80286

Voici la liste des instructions ajouter au 80286 :

Instruction | Signification | Description
ARPL | Adjust RPL field of selector | Cette instruction permet de contrôler et corriger le niveau de privilège du segment de code en mode protégée.
CLTS | Clear task-switched flag in register CR0 | Cette instruction permet de mettre à 0 le drapeau de l'indicateur de tâche (Task-Switch) du registre CR0.
LAR | Load access rights byte | Cette instruction permet de charger le registre des indicateurs d'un descripteur.
LGDT | Load global descriptor table | Cette instruction permet de charger un descripteur de tables globale.
LIDT | Load interrupt descriptor table | Cette instruction permet de charger un descripteur de tables d'interruption.
LLDT | Load local descriptor table | Cette instruction permet de charger un descripteur de tables local.
LMSW | Load machine status word | Cette instruction permet de copier 4 des bits d'une opérande vers les 4 bits de registre de contrôle CR0.
LOADALL | Load all CPU registers | Cette instruction permet d'effectuer le chargement de tous les registres de descripteur de cache.
LSL | Load segment limit | Cette instruction permet de charger la limite de segment d'un descripteur de segment spécifié avec l'opérande source dans l'opérande de destination et fixe le drapeau ZF du registre EFLAGS.
LTR | Load task register | Cette instruction permet de charger l'opérande source dans le champ du sélecteur de segment du registre de tâche.
SGDT | Store global descriptor table | Cette instruction permet d'entreposer le sélecteur de segment dans le registre GDTR (registre de table global de descripteur) dans l'opérande de destination.
SIDT | Store interrupt descriptor table | Cette instruction permet d'entreposer le registre de descripteur de table d'interruption (IDTR) dans l'opérande de destination.
SLDT | Store local descriptor table | Cette instruction permet d'entreposer le sélecteur de segment dans le registre LDTR (registre de table local de descripteur) dans l'opérande de destination.
SMSW | Store machine status word | Cette instruction permet d'entreposer le mot des états (soit les bits de 0 à 15 du registre de contrôle CR0) à partir du registre de tâche (TR) dans l'opérande cible.
STR | Store task register | Cette instruction permet d'entreposer le sélecteur de segment à partir du registre de tâche (TR) à l'opérande cible
VERR | Verify a segment for reading | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode lecture à partir du niveau de privilège courant (CPL).
VERW | Verify a segment for writing | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode écriture à partir du niveau de privilège courant (CPL).

80386

Voici la liste des instructions ajouter au 80386 :

Instruction | Signification | Description
BSF | Bit scan forward | Cette instruction permet d'effectuer une comparaison binaire de la droite vers la gauche.
BSR | Bit scan reverse | Cette instruction permet d'effectuer une comparaison binaire de la gauche vers la droite.
BT | Bit test | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue.
BTC | Bit test and complement | Cette instruction transfère une Opérande vers l'indicateur de retenue le bits spécifié et inverser la valeur du bit correspondant.
BTR | Bit test and reset | Cette instruction permet de transférer l'Opérande vers l'indicateur de retenue le bits spécifié puis met le bits correspondant de l'Opérande à 0.
BTS | Bit test and set | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue le bits spécifié puis ensuite met le bits correspondant dans Opérande à 1.
CDQ | Convert double-word to quad-word | Cette instruction permet de convertir le double mot en un quadruple mot, le résultat tient sur une taille de 64 bits.
CMPSD | Compare string double-word | Cette instruction permet d'effectuer la comparaison d'un double mot avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison.
CWDE | Compare string double-word | Cette instruction est l'alternative pour convertir le mot du registre AX en un double mot contenu dans le registre EAX par extension du signe.
INSD | Input from port to string double-word | Cette instruction permet de demander un double mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction.
IRETD | Interrupt Return Doubleword | Cette instruction permet d'effectuer un retour 32-bits précédemment provoquer par une interruption.
JECXZ | Jump if register ECX is zero | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié si le registre ECX vaut 0.
LFS | Load pointer using FS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment FS et dans un registre d'offset spécifié.
LGS | Load pointer using GS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment GS et dans un registre d'offset spécifié.
LODSD | Load String Doubleword | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 4 en fonction de l'état du drapeau de direction.
LOOPD | Loop Double | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0.
LOOPED | Loop Equal Double | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0 et si le drapeau ZF vaut 1.
LOOPNED | Loop Not Equal Double | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0 et si le drapeau ZF vaut 0.
LOOPNZD | Loop Not Zero Double | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0 et si le drapeau ZF vaut 0.
LOOPZD | Loop Zero Double | Cette instruction de boucle permet de décrémenter le registre ECX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre ECX ne vaut pas 0 et si le drapeau ZF vaut 1.
LSS | Load pointer using SS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment SS (Segment de pile) et dans un registre d'offset spécifié.
MOVSD | Move String Doubleword | Cette instruction permet de copier un double mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 4 en fonction de l'état du drapeau de direction.
MOVSX | Move with sign-extend | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires avec l'extension des signes.
MOVZX | Move with zero-extend | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires par des 0.
OUTSD | Output String Doubleword | Cette instruction permet d'envoyer un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 4 en fonction de l'état du drapeau de direction.
POPAD | Pop all double-word | Cette instruction permet de désempiler de la pile respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX.
POPFD | Pop data into EFLAGS register | Cette instruction permet de désempiler de la pile le registre 32 bits de drapeau contenant les indicateurs d'état.
PUSHAD | Push all double-word | Cette instruction permet d'empiler respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX dans la pile.
PUSHFD | Push EFLAGS | Cette instruction permet d'empiler respectivement le registre 32 bits de drapeau des indicateurs d'état dans la pile.
SCASD | Scan string double-word | Cette instruction permet de comparer le registre EAX avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction.
SETcc | Set byte to one on condition | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0.
SHLD | Shift left double-word | Cette instruction permet d'effectuer une rotation des bits d'un double mot vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF).
SHRD | Shift right double-word | Cette instruction permet d'effectuer une rotation des bits d'un double mot vers la droite en réinsérant le bit dans l'indicateur de retenue (CF).
STOSD | Store string double-word | Cette instruction permet de copier le registre EAX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction.

80486

Voici la liste des instructions ajouter au 80486 :

Instruction | Signification | Description
BSWAP | Byte Swap | Cette instruction permet d'inverse l'ordre des 4 octets d'un registre de taille de 32 bits.
CMPXCHG | CoMPare and eXCHanGe | Cette instruction compare la destination avec l'accumulateur (AL, AX ou EAX) et les échanges si la condition est vrai.
INVD | Invalidate Internal Caches | Cette instruction permet de désactiver et de vider le tampon interne du micro-processeur.
INVLPG | Invalidate TLB Entry | Cette instruction permet d'invalider les transferts du TLB (Translation Lookaside Buffer) du micro-processeur
WBINVD | Write Back and Invalidate Cache | Cette instruction permet de désactiver et de vider le tampon interne du micro-processeur.
XADD | Exchange and Add | Cette instruction permet d'échanger le premier opérande avec le deuxième opérande, et ensuite effectue la somme des valeurs dans le première opérande.

Cyrix 6x86MX (EMMX)

Voici la liste des instructions ajouter au Cyrix 6x86MX (EMMX):

Instruction | Signification | Description
PADDSIW | Packed Add with Saturation | Cette instruction permet d'effectuer l'addition du mot de format entier de l'opérande source au mot de format entier de l'opérande de destination et écrit le résultat dans le registre MMX.
PAVEB | Packed Average Bits | Cette instruction permet d'effectuer le calcul de la moyenne des paquets spécifiés.
PDISTIB | Packed Distribution | Cette instruction permet d'effectuer le calcul de la distance entre des octets de deux opérandes, le résultat de l'addition d'octet de l'opérande de destination et la saturation du résultat.
PMACHRIW | Packed Multiply and Accumulate with Rounding | Cette instruction permet d'effectuer une multiplication de 2 opérandes sources en utilisant la méthode décrite par PMULHRW et accumule le résultat avec la valeur dans un registre de destination en utilisant un arrondissement arithmétique.
PMAGW | Packed Magnitude | Cette instruction permet d'effectuer la comparaison de la valeur absolue d'un paquet de mots de l'opérande source et de l'ensemble des mots de destination et fixe l'opérande de destination avec la valeur de la plus large magnitude.
PMULHRIW | Packed Multiply High with Rounding, result to Implied Register | Cette instruction permet de retourner le résultat d'une matrice de 16x16 bits avec un arrondissement LSB avant de tronquer les 16 bits et place ce résultat dans un registre MMX.
PMULHRW | Packed Multiply High with Rounding | Cette instruction permet de retourner le résultat d'une matrice de 16x16 bits avec un arrondissement LSB avant de tronquer les 16 bits.
PMVGEZB | Packed Conditional Move Great Zero Byte | Cette instruction permet de copier l'octet de paquet correspondant de l'opérande source dans l'opérande de destination si l'octet de l'opérande destination est supérieur à 0 et effectue se traitement pour chacun des 8 octets du paquet.
PMVLZB | Packed Conditional Move Less Zero Byte | Cette instruction permet de copier l'octet de paquet correspondant de l'opérande source dans l'opérande de destination si l'octet de l'opérande destination est inférieur à 0 et effectue se traitement pour chacun des 8 octets du paquet.
PMVNZB | Packed Conditional Move Not Zero Byte | Cette instruction permet de copier l'octet de paquet correspondant de l'opérande source dans l'opérande de destination si l'octet de l'opérande destination ne vaut pas 0 et effectue se traitement pour chacun des 8 octets du paquet.
PMVZB | Packed Conditional Move Zero Byte | Cette instruction permet de copier l'octet de paquet correspondant de l'opérande source dans l'opérande de destination si l'octet de l'opérande destination vaut 0 et effectue se traitement pour chacun des 8 octets du paquet.
PSUBSIW | Packed Subtract with Saturation | Cette instruction permet d'effectuer la soustraction du mot de format entier de l'opérande source au mot de format entier de l'opérande de destination et écrit le résultat dans le registre MMX.

Pentium

Voici la liste des instructions ajouter au Pentium:

Instruction | Signification | Description
CMPXCHG8B | CoMPare and eXCHanGe 8 bytes | Cette instruction compare un nombre de 64 bits et les échanges si la condition est vrai.
CPUID | CPU IDentification | Cette instruction retourne le code d'identification du microprocesseur.
RDMSR | ReaD from Model-Specific Register | Cette instruction permet de charger le contenu du modèle de registre 64-bits (MSR) indiquer par le registre ECX dans le couple de registre EDX:EAX.
RDTSC | ReaD Time Stamp Counter | Cette instruction permet de charger la valeur courante du compteur de temps du microprocesseur dans le couple de registres EDX:EAX.
RSM | Resume operation of interrupted program | Cette instruction permet de retourner le contrôle du programme du mode de gestion système (SMM) pour le programme d'application ou la procédure du système d'exploitation ayant été interrompu lorsque le microprocesseur à reçu un signal SSM.
WRMSR | WRite to Model-Specific Register | Cette instruction écrit les valeurs contenu dans le MSR (Model-Specific Register) en fonction du registre d'index ECX dans la paire des registres EDX:EAX.

Pentium MMX

Voici la liste des instructions ajouter au Pentium MMX:

Instruction | Signification | Description
EMMS | Empty MMX State | Cette instruction fixe les mots marqués du MPU de chacun un.
MOVD | Move Doubleword | Cette instruction permet de copier l'opérande dans un registre XMM ou vice-versa.
MOVQ | Move Quadword | Cette instruction permet de copier un quadruple mot d'une opérande source vers une opérande destination dans le cas des registres XMM.
PACKSSDW | Pack with Signed Saturation DoubleWord | Cette instruction permet de compacté 8 paquets de double mots en mots.
PACKSSDW | Pack with Signed Saturation DoubleWord | Cette instruction permet de compacté 8 paquets de double mots en mots.
PACKSSWB | Pack with Signed Saturation Word Byte | Cette instruction permet de compacté 8 paquets d'entier en octets.
PACKUSWB | Pack with Signed Saturation Unsigned Word Byte | Cette instruction permet de compacté 8 paquets de mots en octets.
PADDB | Packed Add Byte | Cette instruction permet d'effectuer une addition scalaire sur un paquet de 8 octets.
PADDD | Packed Add Double | Cette instruction permet d'effectuer une addition scalaire sur un paquet de 2 double mots.
PADDSB | Packed Add with Saturation Byte | Cette instruction permet d'effectuer une addition scalaire avec saturation sur un paquet de 8 octets signés.
PADDSW | Packed Add with Saturation Word | Cette instruction permet d'effectuer une addition scalaire avec saturation sur un paquet de 4 entiers.
PADDUSB | Packed Add Unsigned with Saturation Byte | Cette instruction permet d'effectuer une addition scalaire avec saturation sur un paquet de 8 octets.
PADDUSW | Packed Add Unsigned with Saturation Word | Cette instruction permet d'effectuer une addition scalaire avec saturation sur un paquet de 4 mots.
PADDW | Packed Add Word | Cette instruction permet d'effectuer une addition scalaire sur un paquet de 4 mots.
PAND | Bitwise Logical AND | Cette instruction permet d'effectuer un «ET BINAIRE» d'un quadruple mot d'une opérande source avec une opérande destination dans le cas des registres XMM.
PANDN | Bitwise Logical AND | Cette instruction permet d'effectuer un «ET BINAIRE» et une «NEGATION» de chacun des bits d'un quadruple mot d'une opérande source avec une opérande destination dans le cas des registres XMM.
PCMPEQB | Packed Compare for Equal Byte | Cette instruction permet d'effectuer une comparaison sur un paquet d'octets et fixe la valeur de chacun d'eux à FFh s'ils sont égales sinon à 00h.
PCMPEQD | Packed Compare for Equal Byte | Cette instruction permet d'effectuer une comparaison sur un paquet de double mots et fixe la valeur de chacun d'eux à FFFFFFFFh s'ils sont égales sinon à 00000000h.
PCMPEQW | Packed Compare for Equal Word | Cette instruction permet d'effectuer une comparaison sur un paquet de mots et fixe la valeur de chacun d'eux à FFFFh s'ils sont égales sinon à 0000h.
PCMPGTB | Packed Compare for Greater Than Byte | Cette instruction permet d'effectuer une comparaison sur un paquet d'octets et fixe la valeur de chacun d'eux à FFh si l'opérande destinataire est supérieur à l'opérande source sinon à 00h.
PCMPGTD | Packed Compare for Greater Than Doubleword | Cette instruction permet d'effectuer une comparaison sur un paquet de double mots et fixe la valeur de chacun d'eux à FFFFFFFFFh si l'opérande destinataire est supérieur à l'opérande source sinon à 00000000h.
PCMPGTW | Packed Compare for Greater Than Word | Cette instruction permet d'effectuer une comparaison sur un paquet de mots et fixe la valeur de chacun d'eux à FFFFFh si l'opérande destinataire est supérieur à l'opérande source sinon à 0000h.
PMADDWD | Packed Multiply and Add Word | Cette instruction permet d'effectuer une multiplication de 2 registres MMX contenant dans un paquet de mots d'un emplacement/mémoire.
PMULHW | Packed Multiply and Add Word | Cette instruction permet d'effectuer la multiplication de la partie haute de chacun des mots des 2 paquets d'opérandes.
PMULLW | Packed Multiply and Add Word | Cette instruction permet d'effectuer la multiplication de la partie basse de chacun des mots des 2 paquets d'opérandes.
POR | Bitwise Logical OR | Cette instruction permet d'effectuer un «OU BINAIRE» d'un quadruple mot d'une opérande source avec une opérande destination dans le cas des registres XMM.
PSLLD | Packed Shift Left Logical Doubleword | Cette instruction permet d'effectuer le décalage de bits vers la gauche d'un paquet de double mots.
PSLLQ | Packed Shift Left Logical Quadword | Cette instruction permet d'effectuer le décalage de bits vers la gauche d'un quadruple mot.
PSLLW | Packed Shift Left Logical Word | Cette instruction permet d'effectuer le décalage de bits vers la gauche d'un paquet de mots.
PSRAD | Packed Shift Right Arithmetic Doubleword | Cette instruction permet d'effectuer le décalage arithmétique de bits vers la droite d'un paquet de double mots.
PSRAW | Packed Shift Right Arithmetic Word | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un paquet de mots.
PSRLD | Packed Shift Right Logical Doubleword | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un paquet de double mots.
PSRLQ | Packed Shift Right Logical Quadword | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un quadruple mot.
PSRLW | Packed Shift Right Logical Word | Cette instruction permet d'effectuer le décalage de bits vers la droite d'un paquet de mots.
PSUBB | Packed Subtract Byte | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des octets d'un paquet contenu dans des opérandes de 64 bits.
PSUBD | Packed Subtract Byte | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PSUBSB | Packed Subtract with Saturation Byte | Cette instruction permet d'effectuer la soustraction avec saturation de la valeur de chacun des octets signés d'un paquet contenu dans des opérandes de 64 bits.
PSUBSW | Packed Subtract with Saturation Word | Cette instruction permet d'effectuer la soustraction du mot de format entier de l'opérande source au mot de format entier de l'opérande de destination et écrit le résultat dans l'opérande destinataire.
PSUBUSB | Packed Subtract with Saturation Unsigned Byte | Cette instruction permet d'effectuer la soustraction avec saturation de la valeur de chacun des octets d'un paquet contenu dans des opérandes de 64 bits.
PSUBUSW | Packed Subtract Unsigned with Saturation Word | Cette instruction permet d'effectuer la soustraction avec saturation de la valeur de chacun des mots d'un paquet contenu dans des opérandes de destinations.
PSUBW | Packed Subtract Words | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des mots d'un paquet contenu dans des opérandes de 64 bits.
PUNPCKHBW | Unpack High Bytes to Words | Cette instruction permet de décompacter des octets en mots dans le haut d'un paquets de 64 bits.
PUNPCKHDQ | Unpack High Dwords to Qwords | Cette instruction permet de décompacter des doubles mots en quadruples mots dans le haut d'un paquets de 64 bits.
PUNPCKHWD | Unpack High Words to Dwords | Cette instruction permet de décompacter des mots en double mots dans le haut d'un paquets de 64 bits.
PUNPCKLBW | Unpack Low Bytes to Words | Cette instruction permet de décompacter des octets en mots dans le bas d'un paquets de 64 bits.
PUNPCKLDQ | Unpack Low Dwords to Qwords | Cette instruction permet de décompacter des doubles mots en quadruples mots dans le bas d'un paquets de 64 bits.
PUNPCKLWD | Unpack Low Words to Dwords | Cette instruction permet de décompacter des mots en double mots dans le bas d'un paquets de 64 bits.
PXOR | Bitwise Logical Exclusive OR | Cette instruction permet d'effectuer un ou exclusif binaire d'un quadruple mot d'une opérande source avec une opérande destination dans le cas des registres XMM.
RDPMC | Read the Performance Monitoring Counter | Cette instruction permet d'effectuer la lecture du compteur du moniteur de performance.

Pentium Pro

Voici la liste des instructions ajouter au Pentium Pro:

Instruction | Description
CMOV | Cette instruction copie des données d'une source (valeur) à une destination (registre) à la condition que la condition demandé soit remplie.
FCOMI | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats.
FCOMIP | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats et désempile de la pile la valeur dans le registre.
FUCOMI | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et vérifie l'ordre des valeurs et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats.
FUCOMIP | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et vérifie l'ordre des valeurs et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats et désempile de la pile la valeur dans le registre.
FCMOV | Cette instruction permet de déplacé des nombres réel (virgule flottante) si la condition en question est satisfaite.
SYSENTER | Cette instruction permet d'effectuer le transférer du contrôle d'un point d'entrée au système d'exploitation.
SYSEXIT | Cette instruction permet de retourner du système d'exploitation à une application.
UD2 | Cette instruction permet de provoquer l'exécution d'un code indéfinie.

AMD K6-2

Voici la liste des instructions ajouter au AMD K6-2:

Instruction | Description
FEMMS | Cette instruction permet d'effacer les états MMX après le passage d'instructions MMX.
PAVGUSB | Cette instruction permet d'effectuer le calcul de la moyenne de paquets de 8 octets spécifiés.
PF2ID | Cette instruction permet de convertir un double mots d'un format réel à un format d'entier 32 bits.
PFACC | Cette instruction permet d'effectuer l'accumulation de double mots.
PFADD | Cette instruction permet d'effectuer l'addition de double mots.
PFCMPEQ | Cette instruction permet d'effectuer la comparaison d'égalité d'un paquet de double mots contenu dans des opérandes de 64 bits.
PFCMPGE | Cette instruction permet d'effectuer la comparaison d'égalité ou de supériorité d'un paquet de double mots contenu dans des opérandes de 64 bits.
PFCMPGT | Cette instruction permet d'effectuer la comparaison de supériorité d'un paquet de double mots contenu dans des opérandes de 64 bits.
PFMAX | Cette instruction permet de retourner la valeur maximal de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFMIN | Cette instruction permet de retourner la valeur minimal de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFMUL | Cette instruction permet d'effectuer la multiplication de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFRCP | Cette instruction permet d'effectuer la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFRCPIT1 | Cette instruction permet d'effectuer la première étape d'itération de la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFRCPIT2 | Cette instruction permet d'effectuer la deuxième étape d'itération de la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFRSQIT1 | Cette instruction permet d'effectuer la première étape d'itération de la racine carré de la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFRSQRT | Cette instruction permet d'effectuer la racine carré approximative de la réciproque de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFSUB | Cette instruction permet d'effectuer la soustraction de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PFSUBR | Cette instruction permet d'effectuer la soustraction inversé de la valeur de chacun des doubles mots d'un paquet contenu dans des opérandes de 64 bits.
PI2FD | Cette instruction permet de convertir un paquet de format d'entier 32 bits à double mots d'un format réel.
PMULHRW | Cette instruction permet de retourner le résultat d'une matrice de 16x16 bits avec un arrondissement LSB avant de tronquer les 16 bits.
PREFETCH | Cette instruction permet d'effectuer le chargement de l'entrée d'une séquence d'alignement de mémoire de 64 bits de l'adresse mémoire spécifié dans le cache de données L1 du microprocesseur.
PREFETCHW | Cette instruction permet d'effectuer le chargement de l'entrée d'une séquence d'alignement de mémoire de 64 bits de l'adresse mémoire spécifié dans le cache de données L1 du microprocesseur dans un état de modification.
SYSCALL | Cette instruction permet d'effectuer le transfert du contrôle d'un point d'entrée fixe au système d'exploitation.
SYSRET | Cette instruction permet de retourner du système d'exploitation à une application.

Pentium III (SSE)

Voici la liste des instructions ajouter au Pentium III (SSE):

Instruction | Description
ADDPS | Cette instruction permet d'effectuer une addition SIMD de 4 paquets de valeurs réels de simple précision d'une opérande source et d'une opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de simple précision.
ADDSS | Cette instruction permet d'effectuer une addition de la partie basse d'une valeur réel de simple précision d'une opérande source et destination et entrepose le résultat dans une opérande de destination de valeur réel de simple précision.
ANDNPS | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes 128 bits spécifiés et inverse chacun des bits du résultat.
ANDPS | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes 128 bits spécifiés.
CMPPS | Cette instruction permet d'effectuer une comparaison SIMD de 4 paquets de valeurs réels de simple précision d'une opérande source et d'une opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination.
CMPSS | Cette instruction permet d'effectuer une comparaison de la partie basse de valeurs réels de simple précision d'une opérande source et d'une opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination.
COMISS | Cette instruction permet de comparer deux valeurs réel de simple-précision dans la partie faible du quadruple mot de deux opérande et fixe les drapeaux de ZF, PF et FC du registre EFLAGS en fonction du résultat (non-ordonnée, supérieur à, inférieur ou égal).
CVTPI2PS | Cette instruction permet de convertir un entier de format double mot en une valeur réel de simple précision compacté.
CVTPS2PI | Cette instruction permet de convertir une valeur réel de simple précision compacté en un entier de format double mot.
CVTSI2SS | Cette instruction permet de convertir un entier de format double mot en une valeur réel de simple précision.
CVTSS2SI | Cette instruction permet de convertir une valeur réel de simple précision en un entier de format double mot.
CVTTPS2PI | Cette instruction permet de convertir une valeur réel de simple précision compacté avec tronquage en un entier de format double mot compacté.
CVTTSS2SI | Cette instruction permet de convertir un entier de format double mot avec tronquage en une valeur réel de simple précision.
DIVPS | Cette instruction permet d'effectuer une division de valeur réel de simple précision de registre XMM ou d'emplacement mémoire de 128 bits.
DIVSS | Cette instruction permet d'effectuer une division scalaire de valeur réel de simple précision de registre XMM ou d'emplacement mémoire de 128 bits.
LDMXCSR | Cette instruction permet d'effectuer le chargement du mot de contrôle et d'état du flux d'extension SIMD d'une opérande mémoire 32 bits.
MASKMOVQ | Cette instruction permet d'entreposer les octets sélectionner de l'opérande source dans un emplacement mémoire de 64 bits.
MAXPS | Cette instruction permet de retourner la valeur maximal de chacune des paires de valeur entre l'opérande source et l'opérande de destination.
MAXSS | Cette instruction permet de retourner la valeur maximal entre l'opérande source et destination.
MINPS | Cette instruction permet de retourner la valeur minimal de chacune des paires de valeur entre l'opérande source et l'opérande de destination.
MINSS | Cette instruction permet de retourner la valeur minimal entre l'opérande source et destination.
MOVAPS | Cette instruction permet de copier le contenu de 4 paquets alignés de valeurs réel de simple précision (4 x 32 bits).
MOVHLPS | Cette instruction permet de copier le contenu du haut d'un paquet de valeurs réel de simple précision dans sa partie basse.
MOVHPS | Cette instruction permet de copier le contenu du haut de deux paquets de valeurs réel de simple précision dans une opérande de destination.
MOVLHPS | Cette instruction permet de copier le contenu du bas d'un paquet de valeurs réel de simple précision dans sa partie haute.
MOVLPS | Cette instruction permet de copier le contenu du bas de deux paquets de valeurs réel de simple précision dans un opérande de destination.
MOVMSKPS | Cette instruction permet de copier les bits de signes de quatre paquets de valeurs réels de simple précision d'un registre XMM dans les 4 bits les plus bas d'un registre 32 bits. Les autres bits du registres 32 bits sont fixés à 0.
MOVNTPS | Cette instruction permet de copier le contenu de 4 paquets alignés de valeurs réel de simple précision sans utiliser la méthode temporel pour minimiser la pollution du cache.
MOVNTQ | Cette instruction permet de copier une valeur 64 bits sans utiliser la méthode temporel pour minimiser la pollution du cache.
MOVSS | Cette instruction permet de copier une valeur réel de simple précision d'une opérande source vers une opérande de destination.
MOVUPS | Cette instruction permet de copier le contenu de 4 paquets désalignés de valeurs réel de simple précision (4 x 32 bits).
MULPS | Cette instruction permet d'effectuer la multiplication de chacune des paires de valeur de l'opérande source et l'opérande de destination.
MULSS | Cette instruction permet d'effectuer la multiplication scalaire de l'opérande source et l'opérande de destination.
ORPS | Cette instruction permet d'effectuer un OU BINAIRE de 128 bits sur les 2 opérandes spécifiés.
PAVGB | Cette instruction permet d'effectuer le calcul de la moyenne des paquets d'octets spécifiés.
PAVGW | Cette instruction permet d'effectuer le calcul de la moyenne des paquets des mots spécifiés.
PEXTRW | Cette instruction permet de copier le mot de l'opérande source spécifié par un compteur d'opérande dans l'opérande de destination.
PINSRW | Cette instruction permet d'effectuer une copie d'un mot d'un opérande source et de l'insérer dans l'opérande de destination de l'emplacement spécifié par un compteur d'opérande.
PMAXSW | Cette instruction permet de retourner la valeur maximal de chacun des mots (entier) des paquets contenu dans deux opérandes.
PMAXUB | Cette instruction permet de retourner la valeur maximal de chacun des octets des paquets contenu dans deux opérandes.
PMINSW | Cette instruction permet de retourner la valeur minimal de chacun des mots des paquets contenu dans deux opérandes.
PMINUB | Cette instruction permet de retourner la valeur minimal de chacun des octets des paquets contenu dans deux opérandes.
PMOVMSKB | Cette instruction permet de copiés les masques de chacun des octets d'un paquet contenu dans une opérande.
PMULHUW | Cette instruction permet d'effectuer la multiplication de la partie haute de chacun des entiers des 2 paquets d'opérandes.
PREFETCH0 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T0 du microprocesseur. Alias de PREFETCHT0.
PREFETCH1 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T1 du microprocesseur. Alias de PREFETCHT1.
PREFETCH2 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T2 du microprocesseur. Alias de PREFETCHT2.
PREFETCHNTA | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données NTA du microprocesseur.
PREFETCHT0 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T0 du microprocesseur. Alias de PREFETCH0.
PREFETCHT1 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T1 du microprocesseur. Alias de PREFETCH1.
PREFETCHT2 | Cette instruction permet d'effectuer le chargement de la ligne de cache de l'adresse mémoire spécifié dans le cache de données T2 du microprocesseur. Alias de PREFETCH2.
PSADBW | Cette instruction permet d'effectuer le calcul la valeur de absolue de la différence des octets de paquet contenu dans une opérande source et destination.
PSHUFW | Cette instruction permet de copier une double mots d'un opérande source avec emplacement spécifié par un opérande immédiate dans un opérande de destination.
RCPPS | Cette instruction permet d'effectuer le calcul de la réciproque d'un paquet de valeurs de réel de simple précision.
RCPSS | Cette instruction permet d'effectuer le calcul de la réciproque d'une valeur de réel de simple précision.
RSQRTPS | Cette instruction permet de calculer la réciproque approximative de la racine carré d'un paquet de simple précision.
RSQRTSS | Cette instruction permet de calculer la réciproque approximative de la racine carré d'un scalaire de simple précision.
SFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant emmagasiner du SFENCE et les instructions suivant le SFENCE.
SHUFPS | Cette instruction permet de copier 4 paquets de valeurs de format réel de simple précision dans une opérande destinataire dans la partie basse d'un quadruple mot de celle-ci et copie 2 des 4 paquets de valeurs de format réel de simple précision dans l'opérande source dans la partie haute d'un quadruple mot de l'opérande destinataire.
SQRTPS | Cette instruction permet d'effectuer le calcul de la racine carré d'un paquet de valeur de simple précision réel de l'opérande source et de mettre son résultat dans l'opérande de destination sous forme d'un réel de simple précision.
SQRTSS | Cette instruction permet d'effectuer le calcul de la racine carré d'une valeur de simple précision réel de l'opérande source et de mettre son résultat dans l'opérande de destination sous forme d'un réel de simple précision.
STMXCSR | Cette instruction permet de copier le MXCSR dans un emplacement mémoire de 32 bits.
SUBPS | Cette instruction permet d'effectuer une soustraction de 4 paquets de valeurs réels de simple précision d'une opérande source et d'une opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de simple précision.
SUBSS | Cette instruction permet d'effectuer une soustraction de la partie basse d'une valeur réel de simple précision d'une opérande source et destination et entrepose le résultat dans une opérande de destination de valeur réel de simple précision.
UCOMISD | Cette instruction permet d'effectuer une comparaison désordonnée de valeurs réels de double précision dans la partie basse d'un double mot du premier opérande et du deuxième opérande, et fixe les drapeaux ZF, PF et FC dans le registre EFLAGS selon le résultat (non-ordonnée, supérieur à, inférieur ou égal)
UCOMISS | Cette instruction permet d'effectuer une comparaison désordonnée de valeurs réels de simple précision dans la partie basse d'un double mot du premier opérande et du deuxième opérande, et fixe les drapeaux ZF, PF et FC dans le registre EFLAGS selon le résultat (non-ordonnée, supérieur à, inférieur ou égal)
UNPCKHPS | Cette instruction permet d'effectuer un dépaquetage de la partie haute d'un réel de simple précision d'un opérande source et destination et met le résultat dans l'opérande de destination.
UNPCKLPS | Cette instruction permet d'effectuer un dépaquetage de la partie basse d'un réel de simple précision d'une opérande source et destination et met le résultat dans l'opérande de destination.
XORPS | Cette instruction permet d'effectuer un ou exclusif binaire de 4 paquets de valeurs réel de simple précision dans une opérande source et destination et de mettre le résultat dans l'opérande de destination.

Pentium 4 (SSE2)

Voici la liste des instructions ajouter au Pentium 4 (SSE2):

Instruction | Description
ADDPD | Cette instruction permet d'effectuer une addition de 2 paquets de valeurs réels de double précision d'un opérande source et d'un opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de double précision.
ADDSD | Cette instruction permet d'effectuer une addition de la partie basse d'une valeur réel de double précision d'un opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de double précision.
ANDNPD | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 paquets d'opérandes de valeur de format réel de double précision et inverse chacun des bits du résultat.
ANDPD | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 paquets d'opérandes de valeur de format réel de double précision.
CLFLUSH | Cette instruction permet de vider la ligne de cache d'une adresse linéaire.
CMPPD | Cette instruction permet d'effectuer une comparaison SIMD de 2 paquets de valeurs réels de double précision d'un opérande source et d'un opérande destination et entrepose le résultat de la comparaison dans l'opérande de destination.
COMISD | Cette instruction permet de comparer deux valeurs réel de double-précision dans la partie faible du quadruple mot de deux opérande et fixe les drapeaux de ZF, PF et FC du registre EFLAGS en fonction du résultat (non-ordonnée, supérieur à, inférieur ou égal).
CVTDQ2PD | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de double précision.
CVTDQ2PS | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de simple précision.
CVTPD2DQ | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en double mot entier et fixe à 0 le reste du paquet.
CVTPD2PI | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en double mot entier.
CVTPD2PS | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de double précision en valeurs réel de simple précision et fixe à 0 le reste du paquet.
CVTPI2PD | Cette instruction permet d'effectuer la conversion d'un paquet de double mot entier en valeurs réel de double précision compacté.
CVTPS2DQ | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de simple précision en paquet de doubles mots entiers.
CVTPS2PD | Cette instruction permet d'effectuer la conversion d'un paquet de valeurs réel de simple précision en paquet de valeurs réel de double précision.
CVTSD2SI | Cette instruction permet d'effectuer la conversion d'une valeur réel de simple précision en valeur entier de double mots.
CVTSD2SS | Cette instruction permet d'effectuer la conversion d'une valeur réel de double précision en valeur réel de simple précision.
CVTSS2SD | Cette instruction permet de convertir une valeur réel de simple précision en une valeur réel de double précision.
CVTTPD2DQ | Cette instruction permet de convertir un paquet de valeur réel de double précision avec en un paquet d'entier de format double mot tronquer et fixe à 0 le reste du paquet.
CVTTPD2PI | Cette instruction permet de convertir une valeur réel de double précision compacté avec tronquage en un entier de format double mot compacté.
CVTTPS2DQ | Cette instruction permet de convertir un paquet de valeur réel de simple précision avec en un paquet d'entier de format double mot tronquer.
CVTTSD2SI | Cette instruction permet de convertir une valeur réel de double précision avec en un entier de format double mot tronquer.
DIVPD | Cette instruction permet d'effectuer une division de valeur réel de double précision de registre XMM ou d'emplacement mémoire de 128 bits.
DIVSD | Cette instruction permet d'effectuer une division scalaire de valeur réel de double précision de registre XMM ou d'emplacement mémoire de 128 bits.
LFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant le LFENCE et les instructions de chargement suivant le LFENCE.
MASKMOVDQU | Cette instruction permet d'entreposer les octets sélectionnés par l'opérande source dans une emplacement mémoire de 128 bits.
MAXPD | Cette instruction permet de retourner la valeur maximal de chacune des paires de valeur entre l'opérande source et l'opérande de destination de nombre réel de double précision.
MAXSD | Cette instruction permet de retourner la valeur maximal entre l'opérande source et destination de nombre réel de simple précision.
MFENCE | Cette instruction permet d'agir comme une barrière pour forcer une priorité en mémoire (sérialisation) entre les instructions précédant le MFENCE et les instructions de chargement et d'entreposage précédent le MFENCE.
MINPD | Cette instruction permet de retourner la valeur minimal de chacune des paires de valeur entre l'opérande source et l'opérande de destination de nombre réel de double précision.
MINSD | Cette instruction permet de retourner la valeur minimal entre l'opérande source et destination de nombre réel de simple précision.
MOVAPD | Cette instruction permet de copier le contenu de 2 paquets alignés de valeurs réel de double précision.
MOVHPD | Cette instruction permet de copier le contenu du haut de deux paquets de valeurs réel de double précision dans une opérande de destination.
MOVLPD | Cette instruction permet de copier le contenu du bas de deux paquets de valeurs réel de double précision dans un opérande de destination.
MOVMSKPD | Cette instruction permet de copier les bits de signes de deux paquets de valeurs réels de double précision d'un registre XMM dans les 2 bits les plus bas d'un registre 32 bits. Les autres bits du registres 32 bits sont fixés à 0.
MOVNTI | Cette instruction permet de copier une valeur 32 ou 64 bits dans un emplacement mémoire afin de minimiser la pollution du cache dans un processus léger.
MOVNTDQ | Cette instruction permet de copier le contenu de double quadruple mots d'un opérande source vers un opérande de destination sans utiliser la méthode temporel pour minimiser la pollution du cache.
MOVNTPD | Cette instruction permet de copier le contenu de valeur réel de double précision d'un opérande source vers un opérande de destination sans utiliser la méthode temporel pour minimiser la pollution du cache.
MOVSD | Cette instruction permet de copier un scalaire de valeur de double précision d'un opérande source vers un opérande destination.
MOVUPD | Cette instruction permet de copier le contenu de 2 paquets désalignés de valeurs réel de double précision.
MULPD | Cette instruction permet d'effectuer la multiplication de chacune des paires de valeur de double précision de l'opérande source et l'opérande de destination.
MULSD | Cette instruction permet d'effectuer la multiplication scalaire de valeurs réel de double précision de l'opérande source et l'opérande de destination.
ORPD | Cette instruction permet d'effectuer un OU BINAIRE de 128 bits sur les 2 opérandes réels de double précisions spécifiés.
PAUSE | Cette instruction permet d'améliorer les performances des boucles de «SPIN», en fournissant une indication pour le microprocesseur que le code courant est dans une boucle en «SPIN».
SHUFPD | Cette instruction permet de copier 4 paquets de valeurs de format réel de double précision dans un opérande destinataire dans la partie basse d'un quadruple mot de celle-ci et copie 2 des 4 paquets de valeurs de format réel de simple précision dans l'opérande source dans la partie haute d'un quadruple mot de l'opérande destinataire.
SQRTPD | Cette instruction permet d'effectuer le calcul de la racine carré d'un paquet de valeur de double précision réel de l'opérande source et de mettre son résultat dans l'opérande de destination sous forme d'un réel de double précision.
SQRTSD | Cette instruction permet d'effectuer le calcul de la racine carré d'une valeur de double précision réel de l'opérande source et de mettre son résultat dans l'opérande de destination sous forme d'un réel de double précision.
SUBPD | Cette instruction permet d'effectuer une soustraction de 2 paquets de valeurs réels de double précision d'un opérande source et d'un opérande destination et entrepose le résultat dans l'opérande de destination sous le format d'un paquet de valeurs réels de double précision.
SUBSD | Cette instruction permet d'effectuer une soustraction de la partie basse d'une valeur réel de double précision d'un opérande source et destination et entrepose le résultat dans un opérande de destination de valeur réel de double précision.
UCOMISD | Cette instruction permet d'effectuer une comparaison désordonnée de valeurs réels de double précision dans la partie basse d'un double mot du premier opérande et du deuxième opérande, et fixe les drapeaux ZF, PF et FC dans le registre EFLAGS selon le résultat (non-ordonnée, supérieur à, inférieur ou égal)
UNPCKHPD | Cette instruction permet d'effectuer un dépaquetage de la partie haute d'un réel de double précision d'un opérande source et destination et met le résultat dans l'opérande de destination.
UNPCKLPD | Cette instruction permet d'effectuer un dépaquetage de la partie basse d'un réel de double précision d'un opérande source et destination et met le résultat dans l'opérande de destination.
XORPD | Cette instruction permet d'effectuer un ou exclusif binaire de 2 paquets de valeurs réel de double précision dans un opérande source et destination et de mettre le résultat dans l'opérande de destination.

Pentium 4 (SSE3)

Voici la liste des instructions ajouter au Pentium 4 (SSE3):

Instruction | Description
LDDQU | Cette instruction permet de copier un quadruple mot d'une opérande source vers une opérande destination.
MONITOR | Cette instruction permet d'indiquer au microprocesseur quel rangé d'adresse est à serveiller par l'instruction STORE.
MWAIT | Cette instruction permet d'indiquer au microprocesseur que l'état de l'alimentation de la ligne de cache est en attente d'écriture dans la plage d'adresse, mettant fin à la plupart des activités dans le noyau en le faisant.

VMX

Voici la liste des instructions ajouter pour la virtualisation par INTEL sous le nom VMX :

Instruction | Description
INVEPT | Cette instruction permet d'invalider la cartographie dans translation des tampons (TLB) et des caches de pagination structuré dérivé des tables de pages étendue (EPT).
INVVPID | Cette instruction permet d'invalider la cartographie dans translation des tampons (TLB) et des caches de pagination structuré basé sur l'identificateur de processeur virtuel (VPID).
VMCALL | Cette instruction permet de fournir un mécanisme invité logiciel pour appeler un service dans un moniteur VM.
VMCLEAR | Cette instruction permet d'appliquer un VMCS à une région VMCS à l'adresse physique contenu dans l'opération spécifié.
VMLAUNCH | Cette instruction permet de gérer l'entrée VM par le VMCS courant, de façon à échoué si l'état de lancement VMCS courant n'est pas effacé. Si l'instruction est un succès, il définit l'état de lancement à relancer.
VMPTRLD | Cette instruction permet de marquer le pointeur VMCS courant valide et charge celui-ci avec une adresse physique dans l'opérande d'instruction.
VMPTRST | Cette instruction permet d'entreposer le pointeur VMCS courant dans l'adresse mémoire spécifié.
VMREAD | Cette instruction permet d'effectuer la lecture du champ spécifié dans le VMCS et l'entrepose dans l'opérande de destination spécifié.
VMRESUME | Cette instruction permet de gérer l'entrée VM par le VMCS courant, de façon à échoué si l'état le lancement VMCS courant n'est pas lancé.
VMWRITE | Cette instruction permet d'effectuer l'écriture du champ spécifié du VMCS spécifié par l'opérande source secondaire (registre seulement) en utilisant le contenu de l'opérande source primaire (registre ou mémoire).
VMXOFF | Cette instruction permet d'utiliser le processeur logique en dehors de l'opération VMX, de débloquer le signal INIT, de conditionnellement réactiver le A20M et d'effacer tous les rangs d'adresse du moniteur.
VMXON | Cette instruction permet d'utiliser le processeur logique dans une opération VMX avec le VMCS non courant, le signal INIT bloqué, la désactivation A20M, et en effaçant n'importe quel rang d'adresse du moniteur établit avec l'instruction MONITOR.

AMD-V

Voici la liste des instructions ajouter au AMD-V:

Instruction | Description
CLGI | Cette instruction permet d'effacer les drapeaux global d'interruption (GIF). Quand le GIF est à 0, toutes les interruptions externes sont désactivés.
SKINIT | Cette instruction permet de réinitialiser de façon sécuritaire le microprocesseur et de démarrer un logiciel de confiance comme un VMM.
STGI | Cette instruction permet de fixer les drapeaux global d'interruption (GIF). Quand le GIF est à 1, les interruptions externes sont réactivés.
VMLOAD | Cette instruction permet d'effectuer le chargement d'un sous-ensemble d'état de microprocesseur dans un VMCB spécifié par une adresse physique contenu dans le registre RAX.
VMMCALL | Cette instruction permet de fournir un mécanisme invité pour communiquer explicitement avec le VMM en générant un #VMEXIT.
VMRUN | Cette instruction permet de lancer l'exécution d'un flux d'instructions invité.
VMSAVE | Cette instruction permet d'entreposer un sous-ensemble d'état du microprocesseur dans un VMCB spécifié par une adresse phyisque contenu dans le registre RAX.

x86-64

Voici la liste des instructions ajouter au x86-64:

Instruction | Description
CMPXCHG16B | Cette instruction permet de comparer un nombre de 128 bits et les échanges si la condition est vrai.
CMPSQ | Cette instruction permet d'effectuer la comparaison d'un quadruple mot avec l'opérande source (DS:(R)SI) et destination (ES:(R)DI) et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison.
INVLPGA | Cette instruction permet d'invalider la cartographie TLB (Translation Lookaside Buffer) pour une page virtual et un ASID spécifié.
IRETQ | Cette instruction permet d'effectuer un retour 64-bits précédemment provoquer par une interruption.
LODSQ | Cette instruction permet de copier un élément de l'adresse DS:(R)SI dans le registre accumulateur et incrémente/décrémente le registre (R)SI de 8 en fonction de l'état du drapeau de direction.
PUSHFQ | Cette instruction permet d'empiler respectivement le registre 64 bits de drapeau (RFLAGS) des indicateurs d'état dans la pile.
RDTSCP | Cette instruction permet de charger la valeur courante du compteur de temps du microprocesseur dans le couple de registres EDX:EAX et la valeur du TSC_AUX dans le registre ECX.
MOVSQ | Cette instruction permet de copier un quadruple mot de l'adresse DS:(R)SI dans l'adresse ES:(R)DI et incrémente/décrémente les registres (R)DI et (R)SI de 8 en fonction de l'état du drapeau de direction.
MOVSXD | Cette instruction permet de copier un registre de taille inférieur dans un registre 64 bits en remplissant les bits supplémentaires avec l'extension des signes.
POPFQ | Cette instruction permet de désempiler de la pile le registre 64 bits de drapeau (RFLAGS) contenant les indicateurs d'état.
STOSQ | Cette instruction permet de copier le registre RAX dans la cellule mémoire à l'adresse ES:[(R)DI] et incrémente/décrémente le registre (R)DI de 8 en fonction de l'état du drapeau de direction.
SWAPGS | Cette instruction permet de fournir une méthode à un logiciel système pour charger un pointeur sur une structure de données système.

AMD K10 (SSE4a)

Voici la liste des instructions ajouter au AMD K10 (SSE4a):

Instruction | Description
LZCNT | Cette instruction permet de compter le nombre de bits à 0 dans un registre 16, 32 ou 64 bits contenu dans l'opérande source.
POPCNT | Cette instruction permet de compter le nombre de bits à 1 que possède une opérande source et place le résultat dans un registre destinataire.

Références

Assembleur - Référence, Edition Micro Application, Pierre Maurette, 2003, ISBN: 2-7429-3061-2.
The Undocumented PC: A programmer's Guide to I/O, CPUs, and Fixed Memory Areas - Second Edition, Edition Addison-Wesley, Frank van Gilluwe, 1997, ISBN: 0-201-47950-8.

Dernière mise à jour : Samedi, le 21 décembre 2013


Voici la liste des instructions en se basant sur leur affectation des drapeaux du registres «EFLAGS»:

Instruction | Description | OF | SF | ZF | AF | PF | CF | TF | IF | DF | NT | RF
AAA | Cette instruction permet d'adapter le résultat obtenu par l'addition de 2 valeur en format DCB. | — | — | — | TM | — | M |  |  |  |  |
AAD | Cette instruction permet de convertir une valeur de format DCB non compactée. | — | M | M | — | M | — |  |  |  |  |
AAM | Cette instruction offre la possibilité de convertir le produit de la multiplication de 2 valeurs de format DCB en un format DCB. | — | M | M | — | M | — |  |  |  |  |
AAS | Cette instruction permet d'adapter le résultat de la soustraction de nombre de format DCB. | — | — | — | TM | — | M |  |  |  |  |
ADC | Cette instruction additionne 2 quantités numériques sur 8 ou 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF (CARRY FLAG), à la somme obtenu. | M | M | M | M | M | TM |  |  |  |  |
ADD | Cette instruction additionne 2 quantités numérique sur 8, 16 ou 32 bits. | M | M | M | M | M | M |  |  |  |  |
AND | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés. | 0 | M | M | — | M | 0 |  |  |  |  |
ARPL | Cette instruction permet de contrôler et corriger le niveau de privilège du segment de code en mode protégée. |  |  | M |  |  |  |  |  |  |  |
BOUND | Cette instruction permet de vérifier la validité pouvant exister entre avec un tableau et son indexation. |  |  |  |  |  |  |  |  |  |  |
BSF | Cette instruction permet d'effectuer une comparaison binaire de la droite vers la gauche. | — | — | M | — | — | — |  |  |  |  |
BSR | Cette instruction permet d'effectuer une comparaison binaire de la gauche vers la droite. | — | — | M | — | — | — |  |  |  |  |
BSWAP | Cette instruction permet d'inverse l'ordre des 4 octets d'un registre de taille de 32 bits. |  |  |  |  |  |  |  |  |  |  |
BT | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue. | — | — | — | — | — | M |  |  |  |  |
BTC | Cette instruction transfère une Opérande vers l'indicateur de retenue le bits spécifié et inverser la valeur du bit correspondant. | — | — | — | — | — | M |  |  |  |  |
BTR | Cette instruction permet de transférer l'Opérande vers l'indicateur de retenue le bits spécifié puis met le bits correspondant de l'Opérande à 0. | — | — | — | — | — | M |  |  |  |  |
BTS | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue le bits spécifié puis ensuite met le bits correspondant dans Opérande à 1. | — | — | — | — | — | M |  |  |  |  |
CALL | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse d'appel avant de continuer. |  |  |  |  |  |  |  |  |  |  |
CBW | Cette instruction permet de convertir un nombre contenu dans le registre AL en un format sur 16 bits pour se retrouver dans le registre AX en appliquant une extension du signe. |  |  |  |  |  |  |  |  |  |  |
CLC | Cette instruction permet de mettre l'indicateur d'état de retenu CF à 0. |  |  |  |  |  | 0 |  |  |  |  |
CLD | Cette instruction met l'indicateur d'état DF à 0, soit la direction croissante. |  |  |  |  |  |  |  |  | 0 |  |
CLI | Cette instruction met l'indicateur d'état IF à 0, soit l'interdiction des interruptions. |  |  |  |  |  |  |  | 0 |  |  |
CLTS | Cette instruction permet de mettre à 0 le drapeau de l'indicateur de tâche (Task-Switch) du registre CR0. |  |  |  |  |  |  |  |  |  |  |
CMC | Cette instruction offre la possibilité d'inverser la valeur de l'indicateur de retenue. Si ce dernier vaut 1, elle le met à 0 et inversement. |  |  |  |  |  | M |  |  |  |  |
CMOVcc | Cette instruction copie des données d'une source (valeur) à une destination (registre) à la condition que la condition demandé soit remplie. | T | T | T |  | T | T |  |  |  |  |
CMP | Cette instruction offre la possibilité essentielle de comparer 2 registres ou emplacements de mémoire. | M | M | M | M | M | M |  |  |  |  |
CMPS | Cette instruction permet d'effectuer la comparaison d'un octet, d'un mot ou double mot spécifié avec l'opérande source et destination spécifié et fixe l'état des drapeaux du registres EFLAGS en fonction des résultats de la comparaison. | M | M | M | M | M | M |  |  | T |  |
CMPXCHG | Cette instruction compare la destination avec l'accumulateur (AL, AX ou EAX) et les échanges si la condition est vrai. | M | M | M | M | M | M |  |  |  |  |
CMPXCHG8B | Cette instruction compare un nombre de 64 bits et les échanges si la condition est vrai. |  |  | M |  |  |  |  |  |  |  |
COMISD | Cette instruction permet de comparer deux valeurs réel de double-précision dans la partie faible du quadruple mot de deux opérande et fixe les drapeaux de ZF, PF et FC du registre EFLAGS en fonction du résultat (non-ordonnée, supérieur à, inférieur ou égal). | 0 | 0 | M | 0 | M | M |  |  |  |  |
COMISS | Cette instruction permet de comparer deux valeurs réel de simple-précision dans la partie faible du quadruple mot de deux opérande et fixe les drapeaux de ZF, PF et FC du registre EFLAGS en fonction du résultat (non-ordonnée, supérieur à, inférieur ou égal). | 0 | 0 | M | 0 | M | M |  |  |  |  |
CPUID | Cette instruction retourne le code d'identification du microprocesseur. |  |  |  |  |  |  |  |  |  |  |
CWD | Cette instruction est l'alternative pour convertir le mot du registre AX en un double mot contenu dans le couple de registre DX et AX par extension du signe. |  |  |  |  |  |  |  |  |  |  |
DAA | Cette instruction corrige après coup les retenues lors de la manipulation de valeur DCB. | — | M | M | TM | M | TM |  |  |  |  |
DAS | Cette instruction offre l'intéressante possibilité de corrige le résultat d'une soustraction de 2 nombres de format DCB compactées. | — | M | M | TM | M | TM |  |  |  |  |
DEC | Cette instruction décrément de 1 le registre ou l'adresse mémoire spécifié. | M | M | M | M | M |  |  |  |  |  |
DIV | Cette instruction permet d'effectuer une division non-signée (nombre naturel). | — | — | — | — | — | — |  |  |  |  |
ENTER | Cette instruction permet de créer les structures de paramètres nécessaires aux procédures des langages de haut niveau. |  |  |  |  |  |  |  |  |  |  |
ESC | Cette instruction active le coprocesseur, lequel se permettra d'utiliser les méthodes d'adressage du processeur principal (CPU). |  |  |  |  |  |  |  |  |  |  |
FCMOVcc | Cette instruction permet de déplacé des nombres réel (virgule flottante) si la condition en question est satisfaite. |  |  | T |  | T | T |  |  |  |  |
FCOM | Cette instruction permet de comparer le nombre réel de valeur positive source avec le registre mathématique ST(0) et mettre les indicateurs d'état C0 à C3 avec la valeur 1. |  |  | M |  | M | M |  |  |  |  |
FCOMI | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats. |  |  | M |  | M | M |  |  |  |  |
FCOMIP | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats et désempile de la pile la valeur dans le registre. |  |  | M |  | M | M |  |  |  |  |
FUCOMI | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et vérifie l'ordre des valeurs et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats. |  |  | M |  | M | M |  |  |  |  |
FUCOMIP | Cette instruction permet d'effectuer la comparaison de ST(0) avec ST(i) et vérifie l'ordre des valeurs et fixe la valeur drapeaux ZF, PF et CF du registre EFLAGS en fonction des résultats et désempile de la pile la valeur dans le registre. |  |  | M |  | M | M |  |  |  |  |
HLT | Cette instruction permet de faire passer le microprocesseur en mode d'arrêt. Toutefois, le processeur peut quitter cet état lorsqu'une ligne matérielle RESET ou lorsqu'une interruption non-masquable (NMI) reçoit un signal. |  |  |  |  |  |  |  |  |  |  |
IDIV | Cette instruction permet d'effectuer une division signée (nombre entier). | — | — | — | — | — | — |  |  |  |  |
IMUL | Cette instruction permet d'effectuer une multiplication signée (nombre entier). | M | — | — | — | — | M |  |  |  |  |
IN | Cette instruction permet de demander un octet, un mot ou un double mot provenant du port d'entrée/sortie et le retourne dans le registre accumulateur (AL, AX, EAX). |  |  |  |  |  |  |  |  |  |  |
INC | Cette instruction permet d'incrémenter un registre ou un emplacement mémoire. | M | M | M | M | M |  |  |  |  |  |
INS | Cette instruction permet de demander un octet, un mot ou un double mot du port d'entrée/sortie et retourne le résultat dans l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. |  |  |  |  |  |  |  |  | T |  |
INT | Cette instruction permet d'exécuter l'interruption avec le numéro spécifié. |  |  |  |  |  |  | 0 |  |  | 0 |
INTO | Cette instruction permet d'exécuter l'interruption numéro 4 si le drapeau de débordement (OF) est fixé sur 1é | T |  |  |  |  |  | 0 |  |  | 0 |
INVD | Cette instruction permet de désactiver et de vider le tampon interne du micro-processeur. |  |  |  |  |  |  |  |  |  |  |
INVLPG | Cette instruction permet d'invalider les transferts du TLB (Translation Lookaside Buffer) du micro-processeur |  |  |  |  |  |  |  |  |  |  |
IRET | Cette instruction permet d'effectuer un retour précédemment provoquer par une interruption. | R | R | R | R | R | R | R | R | R | T |
Jcc | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié. | T | T | T |  | T | T |  |  |  |  |
JCXZ | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié si le registre CX vaut 0. |  |  |  |  |  |  |  |  |  |  |
JMP | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. |  |  |  |  |  |  |  |  |  |  |
LAHF | Cette instruction permet de transférer les bits d'indicateurs du registre d'état vers le registre AH. |  |  |  |  |  |  |  |  |  |  |
LAR | Cette instruction permet de charger le registre des indicateurs d'un descripteur. |  |  | M |  |  |  |  |  |  |  |
LDS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment DS et dans un registre d'offset spécifié. |  |  |  |  |  |  |  |  |  |  |
LEA | Cette instruction permet de copier l'offset d'une adresse de mémoire contenu dans un registre spécifié. |  |  |  |  |  |  |  |  |  |  |
LEAVE | Cette instruction permet de libérer une zone de mémoire attribué par l'instruction «ENTER» lorsqu'on utilise des procédures dans des langages de programmation de haut niveau. |  |  |  |  |  |  |  |  |  |  |
LES | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment ES et dans un registre d'offset spécifié. |  |  |  |  |  |  |  |  |  |  |
LFS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment FS et dans un registre d'offset spécifié. |  |  |  |  |  |  |  |  |  |  |
LGDT | Cette instruction permet de charger un descripteur de tables globale. |  |  |  |  |  |  |  |  |  |  |
LGS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment GS et dans un registre d'offset spécifié. |  |  |  |  |  |  |  |  |  |  |
LIDT | Cette instruction permet de charger un descripteur de tables d'interruption. |  |  |  |  |  |  |  |  |  |  |
LLDT | Cette instruction permet de charger un descripteur de tables local. |  |  |  |  |  |  |  |  |  |  |
LMSW | Cette instruction permet de copier 4 des bits d'une opérande vers les 4 bits de registre de contrôle CR0. |  |  |  |  |  |  |  |  |  |  |
LOCK | Cette instruction est utilisé comme préfixe avec d'autres instructions pour amener le microprocesseur à émettre un signal de vérouillage (Lock) sur le bus lors du traitement de l'instruction suivante. |  |  |  |  |  |  |  |  |  |  |
LODS | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction. |  |  |  |  |  |  |  |  | T |  |
LOOP | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0. |  |  |  |  |  |  |  |  |  |  |
LOOPE | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1. |  |  | T |  |  |  |  |  |  |  |
LOOPNE | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0. |  |  | T |  |  |  |  |  |  |  |
LSL | Cette instruction permet de charger la limite de segment d'un descripteur de segment spécifié avec l'opérande source dans l'opérande de destination et fixe le drapeau ZF du registre EFLAGS. |  |  | M |  |  |  |  |  |  |  |
LSS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment SS (Segment de pile) et dans un registre d'offset spécifié. |  |  |  |  |  |  |  |  |  |  |
LTR | Cette instruction permet de charger l'opérande source dans le champ du sélecteur de segment du registre de tâche. |  |  |  |  |  |  |  |  |  |  |
MONITOR | Cette instruction permet d'indiquer au microprocesseur quel rangé d'adresse est à serveiller par l'instruction STORE. |  |  |  |  |  |  |  |  |  |  |
MOV | Cette instruction permet de copier opérande source dans une opérande destinataire. |  |  |  |  |  |  |  |  |  |  |
MOV control, debug, test | Cette instruction permet de copier opérande source dans une opérande destinataire. | — | — | — | — | — | — |  |  |  |  |
MOVS | Cette instruction permet de copier un élément de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction. |  |  |  |  |  |  |  |  | T |  |
MOVSX | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires avec l'extension des signes. |  |  |  |  |  |  |  |  |  |  |
MOVZX | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires par des 0. |  |  |  |  |  |  |  |  |  |  |
MUL | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). | M | — | — | — | — | M |  |  |  |  |
MWAIT | Cette instruction permet d'indiquer au microprocesseur que l'état de l'alimentation de la ligne de cache est en attente d'écriture dans la plage d'adresse, mettant fin à la plupart des activités dans le noyau en le faisant. |  |  |  |  |  |  |  |  |  |  |
NEG | Cette instruction permet d'effectuer le complément à 2 d'une opérande. | M | M | M | M | M | M |  |  |  |  |
NOP | Cette instruction ne fait rien. |  |  |  |  |  |  |  |  |  |  |
NOT | Cette instruction permet d'inverser la valeur de chacun des bits d'une opérande. |  |  |  |  |  |  |  |  |  |  |
OR | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandessp écifiés. | 0 | M | M | — | M | 0 |  |  |  |  |
OUT | Cette instruction permet d'envoyer un octet, un mot ou un double mot sur le port d'entrée/sortie. |  |  |  |  |  |  |  |  |  |  |
OUTS | Cette instruction permet d'envoyer un octet, un mot ou un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. |  |  |  |  |  |  |  |  | T |  |
POP | Cette instruction permet de désempiler de la pile une mot ou un double mot et la met dans une opérande. |  |  |  |  |  |  |  |  |  |  |
POPA | Cette instruction permet de désempiler de la pile respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX. |  |  |  |  |  |  |  |  |  |  |
POPF | Cette instruction permet de désempiler de la pile le registre 16 bits de drapeau contenant les indicateurs d'état. | R | R | R | R | R | R | R | R | R | R |
PUSH | Cette instruction permet d'empiler une mot ou un double mot dans la pile. |  |  |  |  |  |  |  |  |  |  |
PUSHA | Cette instruction permet d'empiler respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX dans la pile. |  |  |  |  |  |  |  |  |  |  |
PUSHF | Cette instruction permet d'empiler respectivement le registre 16 bits de drapeau des indicateurs d'état dans la pile. |  |  |  |  |  |  |  |  |  |  |
RCL 1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | M |  |  |  |  | TM |  |  |  |  |
RCL compteur | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | — |  |  |  |  | TM |  |  |  |  |
RCR 1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | M |  |  |  |  | TM |  |  |  |  |
RCR compteur | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | — |  |  |  |  | TM |  |  |  |  |
RDMSR | Cette instruction permet de charger le contenu du modèle de registre 64-bits (MSR) indiquer par le registre ECX dans le couple de registre EDX:EAX. |  |  |  |  |  |  |  |  |  |  |
RDPMC | Cette instruction permet d'effectuer la lecture du compteur du moniteur de performance. |  |  |  |  |  |  |  |  |  |  |
RDTSC | Cette instruction permet de charger la valeur courante du compteur de temps du microprocesseur dans le couple de registres EDX:EAX. |  |  |  |  |  |  |  |  |  |  |
REP | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions tant que CX ne vaut pas 0. |  |  |  |  |  |  |  |  |  |  |
REPE | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0. |  |  |  |  |  |  |  |  |  |  |
REPNE | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1. |  |  |  |  |  |  |  |  |  |  |
RET | Cette instruction permet de quitter une procédure. |  |  |  |  |  |  |  |  |  |  |
ROL 1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | M |  |  |  |  | M |  |  |  |  |
ROL compteur | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | — |  |  |  |  | M |  |  |  |  |
ROR 1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | M |  |  |  |  | M |  |  |  |  |
ROR compteur | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | — |  |  |  |  | M |  |  |  |  |
RSM | Cette instruction permet de retourner le contrôle du programme du mode de gestion système (SMM) pour le programme d'application ou la procédure du système d'exploitation ayant été interrompu lorsque le microprocesseur à reçu un signal SSM. | M | M | M | M | M | M | M | M | M | M | M
SAHF | Cette instruction permet de copier les bits du registre AH dans l'octet de poids faible dans le registre des drapeaux (les indicateurs d'état). |  | R | R | R | R | R |  |  |  |  |
SAL 1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | M | M | M | — | M | M |  |  |  |  |
SAL compteur | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | — | M | M | — | M | M |  |  |  |  |
SAR 1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | M | M | M | — | M | M |  |  |  |  |
SAR compteur | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | — | M | M | — | M | M |  |  |  |  |
SBB | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande. | M | M | M | M | M | TM |  |  |  |  |
SCAS | Cette instruction permet de comparer un octet, un mot ou un double mot avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | M | M | M | M | M | M |  |  | T |  |
SETcc | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | T | T | T |  | T | T |  |  |  |  |
SGDT | Cette instruction permet d'entreposer le sélecteur de segment dans le registre GDTR (registre de table global de descripteur) dans l'opérande de destination. |  |  |  |  |  |  |  |  |  |  |
SHL 1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | M | M | M | — | M | M |  |  |  |  |
SHL compteur | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | — | M | M | — | M | M |  |  |  |  |
SHLD | Cette instruction permet d'effectuer une rotation des bits d'un double mot vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | — | M | M | — | M | M |  |  |  |  |
SHR 1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | M | M | M | — | M | M |  |  |  |  |
SHR compteur | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | — | M | M | — | M | M |  |  |  |  |
SHRD | Cette instruction permet d'effectuer une rotation des bits d'un double mot vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | — | M | M | — | M | M |  |  |  |  |
SIDT | Cette instruction permet d'entreposer le registre de descripteur de table d'interruption (IDTR) dans l'opérande de destination. |  |  |  |  |  |  |  |  |  |  |
SLDT | Cette instruction permet d'entreposer le sélecteur de segment dans le registre LDTR (registre de table local de descripteur) dans l'opérande de destination. |  |  |  |  |  |  |  |  |  |  |
SMSW | Cette instruction permet d'entreposer le mot des états (soit les bits de 0 à 15 du registre de contrôle CR0) à partir du registre de tâche (TR) dans l'opérande cible. |  |  |  |  |  |  |  |  |  |  |
STC | Cette instruction permet de fixer l'indicateur de retenue (CF) à la valeur 1. |  |  |  |  |  | 1 |  |  |  |  |
STD | Cette instruction permet de fixer l'indicateur de direction (DF) à la valeur 1. |  |  |  |  |  |  |  |  | 1 |  |
STI | Cette instruction permet de fixer l'indicateur d'interruption (IF) à la valeur 1. |  |  |  |  |  |  |  | 1 |  |  |
STOS | Cette instruction permet de copier un octet, un mot ou un double mot dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. |  |  |  |  |  |  |  |  | T |  |
STR | Cette instruction permet d'entreposer le sélecteur de segment à partir du registre de tâche (TR) à l'opérande cible |  |  |  |  |  |  |  |  |  |  |
SUB | Cette instruction permet de soustraire une valeur à une opérande. | M | M | M | M | M | M |  |  |  |  |
TEST | Cette instruction permet d'effectuer un «Et binaire» sur une opérande cible sans modifier sa valeur. | 0 | M | M | — | M | 0 |  |  |  |  |
UCOMISD | Cette instruction permet d'effectuer une comparaison désordonnée de valeurs réels de double précision dans la partie basse d'un double mot du premier opérande et du deuxième opérande, et fixe les drapeaux ZF, PF et FC dans le registre EFLAGS selon le résultat (non-ordonnée, supérieur à, inférieur ou égal) | 0 | 0 | M | 0 | M | M |  |  |  |  |
UCOMISS | Cette instruction permet d'effectuer une comparaison désordonnée de valeurs réels de simple précision dans la partie basse d'un double mot du premier opérande et du deuxième opérande, et fixe les drapeaux ZF, PF et FC dans le registre EFLAGS selon le résultat (non-ordonnée, supérieur à, inférieur ou égal) | 0 | 0 | M | 0 | M | M |  |  |  |  |
UD2 | Cette instruction permet de provoquer l'exécution d'un code indéfinie. |  |  |  |  |  |  |  |  |  |  |
VERR | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode lecture à partir du niveau de privilège courant (CPL). |  |  | M |  |  |  |  |  |  |  |
VERW | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode écriture à partir du niveau de privilège courant (CPL). |  |  | M |  |  |  |  |  |  |  |
WAIT | Cette instruction permet de faire passer le microprocesseur en mode d'attente jusqu'à ce que la ligne de teste sur la carte mère s'active. |  |  |  |  |  |  |  |  |  |  |
WBINVD | Cette instruction permet de désactiver et de vider le tampon interne du micro-processeur. |  |  |  |  |  |  |  |  |  |  |
WRMSR | Cette instruction écrit les valeurs contenu dans le MSR (Model-Specific Register) en fonction du registre d'index ECX dans la paire des registres EDX:EAX. |  |  |  |  |  |  |  |  |  |  |
XADD | Cette instruction permet d'échanger le premier opérande avec le deuxième opérande, et ensuite effectue la somme des valeurs dans le première opérande. | M | M | M | M | M | M |  |  |  |  |
XCHG | Cette instruction permet d'échanger la valeur de deux opérandes. |  |  |  |  |  |  |  |  |  |  |
XLAT | Cette instruction permet de remplacer le contenu du registre AL par un octet de la «tablesource». |  |  |  |  |  |  |  |  |  |  |
XOR | Cette instruction permet d'effectuer un OU exclusif BINAIRE sur les 2 opérandes spécifiés. | 0 | M | M | — | M | 0 |  |  |  |  |

Légende

Cette case vide permet d'indiquer que l'instruction n'affecte pas le drapeau.
— Ce symbole permet d'indiquer une instruction fixant une valeur indéfini.
0 Ce chiffre permet d'indiquer une instruction fixant la valeur du drapeau à 0.
1 Ce chiffre permet d'indiquer une instruction fixant la valeur du drapeau à 1.
M Cette lettre permet d'indiquer une instruction de modification de drapeau.
R Cette lettre permet d'indiquer une instruction restaurant la valeur du drapeau.
T Cette lettre permet d'indiquer une instruction de test de drapeau.

Références

Assembleur - Référence, Edition Micro Application, Pierre Maurette, 2003, ISBN: 2-7429-3061-2.
The Undocumented PC: A programmer's Guide to I/O, CPUs, and Fixed Memory Areas - Second Edition, Edition Addison-Wesley, Frank van Gilluwe, 1997, ISBN: 0-201-47950-8.
Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 1: Basic Architecture, Order Number: 253665-032US, Septembre 2009, volume I, A-1.

Dernière mise à jour : Samedi, le 21 décembre 2013


Ce tableau indique en fonction de l'opérande le nombre de cycle d'horloge que prend le micro-processeur pour effectuer l'opération. La taille minimum et maximum est exprimé en octets; chaque "X" représente 1 octet, il faut donc additionner la somme ou regarder le chiffre à côté.

Opérandes | Description | 8088 | 8086 | 80286 | 80386DX | Taille minimum | Taille maximum
AAA | Cette instruction permet d'adapter le résultat obtenu par l'addition de 2 valeur en format DCB. | 8 | 8 | 3 | 4 | X | X
AAD | Cette instruction permet de convertir une valeur de format DCB non compactée. | 60 | 60 | 14 | 19 | XX | XX
AAM | Cette instruction offre la possibilité de convertir le produit de la multiplication de 2 valeurs de format DCB en un format DCB. | 83 | 83 | 16 | 17 | XX | XX
AAS | Cette instruction permet d'adapter le résultat de la soustraction de nombre de format DCB. | 8 | 8 | 3 | 4 | X | X
ADC registre,registre | Cette instruction additionne 2 quantités numériques sur 8 ou 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu. | 3 | 3 | 2 | 2 | XX | XX
ADC mémoire,registre | Cette instruction additionne 2 quantités numériques sur 8 ou 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu. | 24+EA | 16+EA | 7 | 7 | XX | XXXX
ADC registre,mémoire | Cette instruction additionne 2 quantités numériques sur 8 ou 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu. | 13+EA | 9+EA | 7 | 6 | XX | XXXX
ADC registre,immédiat | Cette instruction additionne 2 quantités numériques sur 8 ou 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu. | 4 | 4 | 3 | 2 | XXX | XXXX
ADC mémoire,immédiat | Cette instruction additionne 2 quantités numériques sur 8 ou 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu. | 23+EA | 17+EA | 7 | 7 | XXX | XXXXXX
ADC accumulateur,immédiat | Cette instruction additionne 2 quantités numériques sur 8 ou 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF(CARRY FLAG), à la somme obtenu. | 4 | 4 | 3 | 2 | XX | XXX
ADD registre,registre | Cette instruction additionne 2 quantités numérique sur 8, 16 ou 32 bits. | 3 | 3 | 2 | 2 | XX | XXX
ADD mémoire,registre | Cette instruction additionne 2 quantités numérique sur 8, 16 ou 32 bits. | 24+EA | 16+EA | 7 | 7 | XX | XXXX
ADD registre,mémoire | Cette instruction additionne 2 quantités numérique sur 8, 16 ou 32 bits. | 13+EA | 9+EA | 7 | 6 | XX | XXXX
ADD registre,immédiat | Cette instruction additionne 2 quantités numérique sur 8, 16 ou 32 bits. | 4 | 4 | 3 | 2 | XXX | XXXX
ADD mémoire,immédiat | Cette instruction additionne 2 quantités numérique sur 8, 16 ou 32 bits. | 23+EA | 17+EA | 7 | 7 | XXX | XXXXXX
ADD accumulateur,immédiat | Cette instruction additionne 2 quantités numérique sur 8, 16 ou 32 bits. | 4 | 4 | 3 | 2 | XX | XXX
AND registre,registre | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés. | 3 | 3 | 2 | 2 | XX | XX
AND mémoire,registre | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés. | 24+EA | 16+EA | 7 | 7 | XX | XXXX
AND registre,mémoire | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés. | 13+EA | 9+EA | 7 | 6 | XX | XXXX
AND registre,immédiat | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés. | 4 | 4 | 3 | 2 | XXX | XXXX
AND mémoire,immédiat | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés. | 23+EA | 17+EA | 7 | 7 | XXX | XXXXXX
AND accumulateur,immédiat | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés. | 4 | 4 | 3 | 2 | XX | XXX
ARPL registre,registre | Cette instruction permet de contrôler et corriger le niveau de privilège du segment de code en mode protégée. | - | - | 10 | 20 | XX | XX
ARPL mémoire,registre | Cette instruction permet de contrôler et corriger le niveau de privilège du segment de code en mode protégée. | - | - | 11 | 21 | XXXX | XXXX
BOUND registre16,mém32 | Cette instruction permet de vérifier la validité pouvant exister entre avec un tableau et son indexation. | - | - | ~13 | ~10 | XX | XX
BOUND registre32,mém64 | Cette instruction permet de vérifier la validité pouvant exister entre avec un tableau et son indexation. | - | - | ~13 | ~10 | XX | XX
BSF registre,registre | Cette instruction permet d'effectuer une comparaison binaire de la droite vers la gauche. | - | - | - | 10+3nano | XXX | XXX
BSF registre,mémoire | Cette instruction permet d'effectuer une comparaison binaire de la droite vers la gauche. | - | - | - | 10+3nano | XXX | XXXXXX
BSR registre,registre | Cette instruction permet d'effectuer une comparaison binaire de la gauche vers la droite. | - | - | - | 10+3nano | XXX | XXX
BSR registre,mémoire | Cette instruction permet d'effectuer une comparaison binaire de la gauche vers la droite. | - | - | - | 10+3nano | XXX | XXXXXX
BT registre16,immédiat8 | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue. | - | - | - | 3 | XXXX | XXXXXXXX
BT mémoire16,immédiat8 | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue. | - | - | - | 6 | XXXX | XXXXXXXX
BT registre16,registre16 | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue. | - | - | - | 3 | XXX | XXXXXXX
BT mémoire16,registre16 | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue. | - | - | - | 12 | XXX | XXXXXXX
BTC registre16,immédiat8 | Cette instruction transfére une Opérande vers l'indicateur de retenue le bits spécifié et inverser la valeur du bit correspondant. | - | - | - | 3 | XXXX | XXXXXXXX
BTC mémoire16,immédiat8 | Cette instruction transfére une Opérande vers l'indicateur de retenue le bits spécifié et inverser la valeur du bit correspondant. | - | - | - | 6 | XXXX | XXXXXXXX
BTC registre16,registre16 | Cette instruction transfére une Opérande vers l'indicateur de retenue le bits spécifié et inverser la valeur du bit correspondant. | - | - | - | 3 | XXX | XXXXXXX
BTC mémoire16,registre16 | Cette instruction transfére une Opérande vers l'indicateur de retenue le bits spécifié et inverser la valeur du bit correspondant. | - | - | - | 1 | XXX | XXXXXXX
BTR registre16,immédiat8 | Cette instruction permet de transférer l'Opérande vers l'indicateur de retenue le bits spécifié puis met le bits correspondant de l'Opérande à 0. | - | - | - | 6 | XXXX | XXXXXXXX
BTR mémoire16,immédiat8 | Cette instruction permet de transférer l'Opérande vers l'indicateur de retenue le bits spécifié puis met le bits correspondant de l'Opérande à 0. | - | - | - | 8 | XXXX | XXXXXXXX
BTR registre16,registre16 | Cette instruction permet de transférer l'Opérande vers l'indicateur de retenue le bits spécifié puis met le bits correspondant de l'Opérande à 0. | - | - | - | 6 | XXX | XXXXXXX
BTR mémoire16,registre16 | Cette instruction permet de transférer l'Opérande vers l'indicateur de retenue le bits spécifié puis met le bits correspondant de l'Opérande à 0. | - | - | - | 1 | XXX | XXXXXXX
BTS registre16,immédiat8 | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue le bits spécifié puis ensuite met le bits correspondant dans Opérande à 1. | - | - | - | 6 | XXXX | XXXXXXXX
BTS mémoire16,immédiat8 | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue le bits spécifié puis ensuite met le bits correspondant dans Opérande à 1. | - | - | - | 8 | XXXX | XXXXXXXX
BTS registre16,registre16 | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue le bits spécifié puis ensuite met le bits correspondant dans Opérande à 1. | - | - | - | 6 | XXX | XXXXXXX
BTS mémoire16,registre16 | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue le bits spécifié puis ensuite met le bits correspondant dans Opérande à 1. | - | - | - | 1 | XXX | XXXXXXX
CALL Near Procedure | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse d'appel en fonction de l'instruction de segment avant de continuer. | 23 | 19 | 7+m | 7+m | XXX | XXX
CALL Far Procedure | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse d'appel avant de continuer. | 36 | 28 | 13+m | 17+m | XXXXX | XXXXX
CALL registre | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse définit par le registre et l'instruction de segment avant de continuer. | 20 | 16 | 7+m | 7+m | XX | XX
CALL mémoire16 | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse définit par l'emplacement mémoire et l'instruction de segment avant de continuer. | 29+EA | 21+EA | 11+m | 10+m | XX | XXXX
CALL mémoire32 | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse définit par l'emplacement mémoire et l'instruction de segment avant de continuer. | 53+EA | 37+EA | 11+m | 10+m | XX | XXXX
CBW | Cette instruction permet de convertir un nombre contenu dans le registre AL en un format sur 16 bits pour se retrouver dans le registre AX en appliquant une extension du signe. | 2 | 2 | 2 | 3 | X | X
CDQ | Transforme un double mot en quadruple mot | - | - | - | 2 | X | X
CLC | Cette instruction permet de mettre l'indicateur d'état de retenu CF à 0. | 2 | 2 | 2 | 2 | X | X
CLD | Cette instruction met l'indicateur d'état DF à 0, soit la direction croissante. | 2 | 2 | 2 | 2 | X | X
CLI | Cette instruction met l'indicateur d'état IF à 0, soit l'interdiction des interruptions. | 2 | 2 | 2 | 3 | X | X
CLTS | Cette instruction permet de mettre à 0 le drapeau de l'indicateur de tâche (Task-Switch) du registre CR0. | - | - | 2 | 5 | X | X
CMC | Cette instruction offre la possibilité d'inverser la valeur de l'indicateur de retenue. Si ce dernier vaut 1, elle le met à 0 et inversement. | 2 | 2 | 2 | 3 | X | X
CMP registre,registre | Cette instruction offre la possibilité essentielle de comparer 2 registres. | 3 | 2 | 2 | 2 | XX | XX
CMP mémoire,registre | Cette instruction offre la possibilité essentielle de comparer 2 registres ou emplacements de mémoire. | 13+EA | 9+EA | 7 | 5 | XX | XXXX
CMP registre,mémoire | Cette instruction offre la possibilité essentielle de comparer 2 registres ou emplacements de mémoire. | 13+EA | 9+EA | 7 | 5 | XX | XXXX
CMP registre,immédiat | Comparaison | 4 | 4 | 3 | 2 | XXX | XXXX
CMP mémoire,immédiat | Comparaison | 14+EA | 10+EA | 6 | 5 | XXX | XXXXXX
CMP accumulateur,immédiat | Comparaison | 4 | 4 | 3 | 2 | XX | XXX
CMPS destination,source | Comparaison de chaîne de caractères | 22 | 22 | 8 | 10 | X | X
CWD | Conversion d'un mot en double mot | 5 | 5 | 2 | 2 | X | X
CWDE | Conversion d'un double mot en quadruple mot | - | - | - | 3 | X | X
DAA | Cette instruction corrige après coup les retenues lors de la manipulation de valeur DCB. | 4 | 4 | 3 | 4 | X | X
DAS | Cette instruction offre l'intéressante possibilité de corrige le résultat d'une soustraction de 2 nombres de format DCB compactées. | 4 | 4 | 3 | 4 | X | X
DEC registre8 | Décrémentation | 3 | 3 | 2 | 2 | XX | XX
DEC mémoire | Décrémentation | 15+EA | 15+EA | 7 | 6 | XX | XXXX
DEC registre16/32 | Décrémentation | 3 | 3 | 2 | 2 | X | X
DIV registre8 | Division naturel | 90 | 80 | 14 | 14 | XX | XX
DIV registre16 | Division naturel | 162 | 144 | 22 | 22 | XX | XX
DIV registre32 | Division naturel | - | - | - | 8 | XX | XX
DIV mémoire8 | Division naturel | 96+EA | 86+EA | 17 | 17 | XX | XX
DIV mémoire16 | Division naturel | 176+EA | 158+EA | 25 | 25 | XX | XX
DIV mémoire32 | Division naturel | - | - | - | 41 | XX | XX
ENTER immédiat16,0 | Empiler dans la pile | - | - | 11 | 10 | XXXX | XXXX
ENTER immédiat16,1 | Empiler dans la pile | - | - | 15 | 12 | XXXX | XXXX
ESC immédiat,registre | Cette instruction active le coprocesseur, lequel se permettra d'utiliser les méthodes d'adressage du processeur principal (CPU). | 2 | 2 | 9 | 20 | XXXX | XXXX
ESC immédiat,mémoire | Cette instruction active le coprocesseur, lequel se permettra d'utiliser les méthodes d'adressage du processeur principal (CPU). | 2 | 2 | 9 | 20 | XXXX | XXXX
HLT | Arrêter le microprocesseur | 2 | 2 | 2 | 5 | X | X
IDIV registre8 | Division entière | 112 | 101 | 17 | 19 | XX | XX
IDIV registre16 | Division entière | 184 | 165 | 25 | 27 | XX | XX
IDIV registre32 | Division entière | - | - | - | 4 | XX | XX
IDIV mémoire8 | Division entière | 118+EA | 107+EA | 20 | 22 | XX | XXXX
IDIV mémoire16 | Division entière | 194+EA | 175+EA | 38 | 30 | XX | XXXX
IDIV mémoire32 | Division entière | - | - | - | 46 | XXX | XXXXX
IMUL registre8 | Multiplication entière | 98 | 80 | 13 | 9 à 14 | XX | XX
IMUL registre16 | Multiplication entière | 154 | 128 | 21 | 9 à 22 | XX | XX
IMUL registre32 | Multiplication entière | - | - | - | 9 à 38 | XXX | XXX
IMUL mémoire8 | Multiplication entière | 104 | 86 | 16 | 12 à 17 | XX | XXXX
IMUL mémoire16 | Multiplication entière | 160 | 134 | 24 | 12 à 25 | XX | XXXX
IMUL mémoire32 | Multiplication entière | - | - | - | 12 à 41 | XX | XXXX
IMUL registre8,immédiat | Multiplication entière | - | - | 21 | 9 à 14 | XXX | XXX
IMUL registre16,immédiat | Multiplication entière | - | - | 21 | 9 à 22 | XXX | XXX
IMUL registre32,immédiat | Multiplication entière | - | - | - | 9 à 38 | XXX | XXXXXX
IMUL registre8,registre8,immédiat | Multiplication entière | - | - | 21 | 9 à 14 | XXX | XXXXXX
IMUL registre16,registre16,immédiat | Multiplication entière | - | - | 21 | 9 à 22 | XXX | XXXXXX
IMUL registre32,registre32,immédiat | Multiplication entière | - | - | - | 9 à 18 | XXX | XXXXXX
IMUL registre8,mémoire8,immédiat | Multiplication entière | - | - | 24 | 12 à 17 | XXX | XXXXXX
IMUL registre16,mémoire16,immédiat | Multiplication entière | - | - | 24 | 12 à 25 | XXX | XXXXXX
IMUL registre32,mémoire32,immédiat | Multiplication entière | - | - | - | 12 à 41 | XXX | XXXXXX
IMUL registre16,registre16 | Multiplication entière | - | - | - | 9 à 22 | XXX | XXXXXX
IMUL registre32,registre32 | Multiplication entière | - | - | - | 9 à 18 | XXX | XXXXX
IMUL registre16,mémoire16 | Multiplication entière | - | - | - | 12 à 25 | XXX | XXXXX
IMUL registre32,registre32 | Multiplication entière | - | - | - | 12 à 41 | XXX | XXXXX
IN accumulateur,immédiat8 | Lecture d'un port | 14 | 10 | 5 | 12 | XX | XX
IN accumulateur,DX | Lecture d'un port | 12 | 8 | 5 | 13 | X | X
INC registre8 | Incrémentation | 3 | 3 | 2 | 2 | XX | XX
INC registre16 | Incrémentation | 3 | 3 | 2 | 2 | X | X
INC registre32 | Incrémentation | 3 | 3 | 2 | 2 | XX | XX
INC mémoire | Incrémentation | 23+EA | 15+EA | 7 | 6 | XX | XXXX
INS destination,port | Lecture d'un port vers une chaîne de caractères | - | - | 5 | 15 | X | X
INT immédiat | Appel d'une interruption | 71 | 51 | 23+m | 33 | XX | XX
INT/3 (constante) | Appel de l'interruption de point d'arrêt | 72 | 52 | 23 | 33 | X | X
INTO | Appel d'une interruption de débordement | 73 | 53 | 24+m | 35 | X | X
INTO (si pas de saut) | Appel d'une interruption de débordement | 4 | 4 | 3 | 3 | X | X
IRET | Retour d'interruption | 44 | 32 | 17+m | 22 | X | X
IRETD | Retour d'interruption en mode protégé 32 bits | - | - | - | 22 | X | X
JA label | Cette instruction saut si supérieur sur des valeurs naturel | 16 | 16 | 7+m | 7+m | XX | XX
JA label (si pas de saut) | Cette instruction saut si supérieur sur des valeurs naturel | 4 | 4 | 3 | 3 | XX | XX
JA label near | Cette instruction saut si supérieur sur des valeurs naturel | - | - | - | 7+m | XXXX | XXXX
JAE label | Cette instruction saut si Supérieur ou égal sur des valeurs naturel | 16 | 16 | 7+m | 7+m | XX | XX
JAE label (si pas de saut) | Cette instruction saut si Supérieur ou égal sur des valeurs naturel | 4 | 4 | 3 | 3 | XX | XX
JAE label near | Cette instruction saut si Supérieur ou égal sur des valeurs naturel | - | - | - | 7+m | XXXX | XXXX
JB label | Cette instruction saut si inférieur sur des valeurs naturel | 16 | 16 | 7+m | 7+m | XX | XX
JB label (si pas de saut) | Cette instruction saut si inférieur sur des valeurs naturel | 4 | 4 | 3 | 3 | XX | XX
JB label near | Cette instruction saut si inférieur sur des valeurs naturel | - | - | - | 7+m | XXXX | XXXX
JBE label | Cette instruction saut si inférieur ou égal sur des valeurs naturel | 16 | 16 | 7+m | 7+m | XX | XX
JBE label (si pas de saut) | Cette instruction saut si inférieur ou égal sur des valeurs naturel | 4 | 4 | 3 | 3 | XX | XX
JBE label near | Cette instruction saut si inférieur ou égal sur des valeurs naturel | - | - | - | 7+m | XXXX | XXXX
JC label | Cette instruction saut si indicateur de retenue à égal à 1 | 16 | 16 | 7+m | 7+m | XX | XX
JC label (si pas de saut) | Cette instruction saut si indicateur de retenue à égal à 1 | 4 | 4 | 3 | 3 | XX | XX
JC label near | Cette instruction saut si indicateur de retenue à égal à 1 | - | - | - | 7+m | XXXX | XXXX
JCXZ label | Cette instruction saut si le registre CX est égal à 0 | 18 | 16 | 7+m | 7+m | XX | XX
JCXZ label (si pas saut) | Cette instruction saut si le registre CX est égal à 0 | 6 | 6 | 4 | 5 | XX | XX
JE label | Cette instruction saut si égal | 16 | 16 | 7+m | 7+m | XX | XX
JE label (si pas de saut) | Cette instruction saut si égal | 4 | 4 | 3 | 3 | XX | XX
JE label near | Cette instruction saut si égal | - | - | - | 7+m | XXXX | XXXX
JG label | Cette instruction saut si supérieur sur des valeurs entière | 16 | 16 | 7+m | 7+m | XX | XX
JG label (si pas de saut) | Cette instruction saut si supérieur sur des valeurs entière | 4 | 4 | 3 | 3 | XX | XX
JG label near | Cette instruction saut si supérieur sur des valeurs entière | - | - | - | 7+m | XXXX | XXXX
JGE label | Cette instruction saut si supérieur ou égal sur des valeurs entière | 16 | 16 | 7+m | 7+m | XX | XX
JGE label (si pas de saut) | Cette instruction saut si supérieur ou égal sur des valeurs entière | 4 | 4 | 3 | 3 | XX | XX
JGE label near | Cette instruction saut si supérieur ou égal sur des valeurs entière | - | - | - | 7+m | XXXX | XXXX
JL label | Cette instruction saut si inférieur sur des valeurs entière | 16 | 16 | 7+m | 7+m | XX | XX
JL label (si pas de saut) | Cette instruction saut si inférieur sur des valeurs entière | 4 | 4 | 3 | 3 | XX | XX
JL label near | Cette instruction saut si inférieur sur des valeurs entière | - | - | - | 7+m | XXXX | XXXX
JLE label | Cette instruction saut si inférieur ou égal sur des valeurs entière | 16 | 16 | 7+m | 7+m | XX | XX
JLE label (si pas de saut) | Cette instruction saut si inférieur ou égal sur des valeurs entière | 4 | 4 | 3 | 3 | XX | XX
JLE label near | Cette instruction saut si inférieur ou égal sur des valeurs entière | - | - | - | 7+m | XXXX | XXXX
JMP short-label | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | 15 | 15 | 7+m | 7+m | XX | XX
JMP near-label | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | 15 | 15 | 7+m | 7+m | XXX | XXXXXXX
JMP FAR label | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | 15 | 15 | 11+m | 12+m | XXXXX | XXXXX
JMP registre16 | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | 11 | 11 | 7+m | 7+m | XX | XX
JMP registre32 | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | - | - | - | 7+m | XX | XX
JMP mémoire16 | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | 18+EA | 18+EA | 11+m | 10+m | XX | XX
JMP mémoire32 | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | - | - | - | 10+m | XX | XX
JMP mémoire32 | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | 24+EA | 15+m | 12+m | 12+m | XX | XX
JMP mémoire48 | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | - | - | - | 12+m | XX | XX
JNA label | Cette instruction saut si pas supérieur sur des valeurs naturel | 16 | 16 | 7+m | 7+m | XX | XX
JNA label (si pas de saut) | Cette instruction saut si pas supérieur sur des valeurs naturel | 4 | 4 | 3 | 3 | XX | XX
JNA label near | Cette instruction saut si pas supérieur sur des valeurs naturel | - | - | - | 7+m | XXXX | XXXX
JNAE label | Cette instruction saut si pas supérieur ou égal sur des valeurs naturel | 16 | 16 | 7+m | 7+m | XX | XX
JNAE label (si pas saut) | Cette instruction saut si pas supérieur ou égal sur des valeurs naturel | 4 | 4 | 3 | 3 | XX | XX
JNAE label near | Cette instruction saut si pas supérieur ou égal sur des valeurs naturel | - | - | - | 7+m | XXXX | XXXX
JNB label | Cette instruction saut si pas inférieur sur des valeurs naturel | 16 | 16 | 7+m | 7+m | XX | XX
JNB label (si pas de saut) | Cette instruction saut si pas inférieur sur des valeurs naturel | 4 | 4 | 3 | 3 | XX | XX
JNB label near | Cette instruction saut si pas inférieur sur des valeurs naturel | - | - | - | 7+m | XXXX | XXXX
JNBE label | Cette instruction saut si pas inférieur ou égal sur des valeurs naturel | 16 | 16 | 7+m | 7+m | XX | XX
JNBE label (si pas saut) | Cette instruction saut si pas inférieur ou égal sur des valeurs naturel | 4 | 4 | 3 | 3 | XX | XX
JNBE label near | Cette instruction saut si pas inférieur ou égal sur des valeurs naturel | - | - | - | 7+m | XXXX | XXXX
JNC label | Cette instruction saut si l'indicateur de retenue est égal à 0 | 16 | 16 | 7+m | 7+m | XX | XX
JNC label (si pas de saut) | Cette instruction saut si l'indicateur de retenue est égal à 0 | 4 | 4 | 3 | 3 | XX | XX
JNC label near | Cette instruction saut si l'indicateur de retenue est égal à 0 | - | - | - | 7+m | XXXX | XXXX
JNE label | Cette instruction saut si pas égal | 16 | 16 | 7+m | 7+m | XX | XX
JNE label (si pas de saut) | Cette instruction saut si pas égal | 4 | 4 | 3 | 3 | XX | XX
JNE label near | Cette instruction saut si pas égal | - | - | - | 7+m | XXXX | XXXX
JNG label | Cette instruction saut si pas supérieur sur des valeurs entières | 16 | 16 | 7+m | 7+m | XX | XX
JNG label (si pas de saut) | Cette instruction saut si pas supérieur sur des valeurs entières | 4 | 4 | 3 | 3 | XX | XX
JNG label near | Cette instruction saut si pas supérieur sur des valeurs entières | - | - | - | 7+m | XXXX | XXXX
JNGE label | Cette instruction saut si pas supérieur ou égal sur des valeurs entières | 16 | 16 | 7+m | 7+m | XX | XX
JNGE label (si pas saut) | Cette instruction saut si pas supérieur ou égal sur des valeurs entières | 4 | 4 | 3 | 3 | XX | XX
JNGE label near | Cette instruction saut si pas supérieur ou égal sur des valeurs entières | - | - | - | 7+m | XXXX | XXXX
JNL label | Cette instruction saut si pas inférieur sur des valeurs entières | 16 | 16 | 7+m | 7+m | XX | XX
JNL label (si pas de saut) | Cette instruction saut si pas inférieur sur des valeurs entières | 4 | 4 | 3 | 3 | XX | XX
JNL label near | Cette instruction saut si pas inférieur sur des valeurs entières | - | - | - | 7+m | XXXX | XXXX
JNLE label | Cette instruction saut si pas inférieur ou égal sur des valeurs entières | 16 | 16 | 7+m | 7+m | XX | XX
JNLE label (si pas saut) | Cette instruction saut si pas inférieur ou égal sur des valeurs entières | 4 | 4 | 3 | 3 | XX | XX
JNLE label near | Cette instruction saut si pas inférieur ou égal sur des valeurs entières | - | - | - | 7+m | XXXX | XXXX
JNO label | Cette instruction saut si pas de débordement | 16 | 16 | 7+m | 7+m | XX | XX
JNO label (si pas de saut) | Cette instruction saut si pas de débordement | 4 | 4 | 3 | 3 | XX | XX
JNO label near | Cette instruction saut si pas de débordement | - | - | - | 7+m | XXXX | XXXX
JNP label | Cette instruction saut si pas de parité | 16 | 16 | 7+m | 7+m | XX | XX
JNP label (si pas de saut) | Cette instruction saut si pas de parité | 4 | 4 | 3 | 3 | XX | XX
JNP label near | Cette instruction saut si pas de parité | - | - | - | 7+m | XXXX | XXXX
JNS label | Cette instruction saut si pas de signe | 16 | 16 | 7+m | 7+m | XX | XX
JNS label (si pas de saut) | Cette instruction saut si pas de signe | 4 | 4 | 3 | 3 | XX | XX
JNS label near | Cette instruction saut si pas de signe | - | - | - | 7+m | XXXX | XXXX
JNZ label | Cette instruction saut si pas zéro | 16 | 16 | 7+m | 7+m | XX | XX
JNZ label (si pas de saut) | Cette instruction saut si pas zéro | 4 | 4 | 3 | 3 | XX | XX
JNZ label near | Cette instruction saut si pas zéro | - | - | - | 7+m | XXXX | XXXX
JO label | Cette instruction saut si débordement | 16 | 16 | 7+m | 7+m | XX | XX
JO label (si pas de saut) | Cette instruction saut si débordement | 4 | 4 | 3 | 3 | XX | XX
JO label near | Cette instruction saut si débordement | - | - | - | 7+m | XXXX | XXXX
JPO label | Cette instruction saut si parité impaire | 16 | 16 | 7+m | 7+m | XX | XX
JPO label (si pas de saut) | Cette instruction saut si parité impaire | 4 | 4 | 3 | 3 | XX | XX
JPO label near | Cette instruction saut si parité impaire | - | - | - | 7+m | XXXX | XXXX
JP label | Cette instruction saut si parité | 16 | 16 | 7+m | 7+m | XX | XX
JP label (si pas de saut) | Cette instruction saut si parité | 4 | 4 | 3 | 3 | XX | XX
JP label near | Cette instruction saut si parité | - | - | - | 7+m | XXXX | XXXX
JPE label | Cette instruction saut si parité paire | 16 | 16 | 7+m | 7+m | XX | XX
JPE label (si pas de saut) | Cette instruction saut si parité paire | 4 | 4 | 3 | 3 | XX | XX
JPE label near | Cette instruction saut si parité paire | - | - | - | 7+m | XXXX | XXXX
JS label | Cette instruction saut si signé | 16 | 16 | 7+m | 7+m | XX | XX
JS label (si pas de saut) | Cette instruction saut si signé | 4 | 4 | 3 | 3 | XX | XX
JS label near | Cette instruction saut si signé | - | - | - | 7+m | XXXX | XXXX
JZ label | Cette instruction saut si zéro | 16 | 16 | 7+m | 7+m | XX | XX
JZ label (si pas de saut) | Cette instruction saut si zéro | 4 | 4 | 3 | 3 | XX | XX
JZ label near | Cette instruction saut si zéro | - | - | - | 7+m | XXXX | XXXX
LAHF | Cette instruction permet de transférer les bits d'indicateurs du registre d'état vers le registre AH. | 4 | 4 | 2 | 2 | X | X
LAR registre16,registre16 | Cette instruction permet de charger le registre des indicateurs d'un descripteur. | - | - | 14 | 15 | XXX | XXX
LAR registre32,registre32 | Cette instruction permet de charger le registre des indicateurs d'un descripteur. | - | - | - | 15 | XXX | XXX
LAR registre16,mémoire16 | Cette instruction permet de charger le registre des indicateurs d'un descripteur. | - | - | 16 | 16 | XXX | XXXXXXX
LAR registre32,mémoire32 | Cette instruction permet de charger le registre des indicateurs d'un descripteur. | - | - | - | 16 | XXX | XXXXXXX
LDS destination,source | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment DS et dans un registre d'offset spécifié. | 16+EA | 16+EA | 7 | 7 | XX | XXXX
LEA destination,source | Cette instruction permet de copier l'offset d'une adresse de mémoire contenu dans un registre spécifié. | 2+EA | 2+EA | 3 | 2 | XX | XXXX
LEAVE | Cette instruction permet de libérer une zone de mémoire attribué par l'instruction «ENTER» lorsqu'on utilise des procédures dans des langages de programmation de haut niveau. | - | - | 5 | 4 | X | X
LES destination,mémoire | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment ES et dans un registre d'offset spécifié. | 24+EA | 16+EA | 7 | 7 | XX | XXXX
LFS destination,mémoire | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment FS et dans un registre d'offset spécifié. | - | - | - | 7 | XXXXX | XXXXXXX
LGDT source | Cette instruction permet de charger un descripteur de tables globale. | - | - | 11 | 11 | XXXXX | XXXXX
LGS destination,mémoire | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment GS et dans un registre d'offset spécifié. | - | - | - | 7 | XXXXX | XXXXXXX
LIDT source | Cette instruction permet de charger un descripteur de tables d'interruption. | - | - | 12 | 11 | XXXXX | XXXXX
LIDT registre16 | Cette instruction permet de charger un descripteur de tables d'interruption. | - | - | 17 | 20 | XXX | XXX
LLDT mémoire16 | Cette instruction permet de charger un descripteur de tables local. | - | - | 19 | 24 | XXXXX | XXXXX
LMSW registre16 | Cette instruction permet de copier 4 des bits d'une opérande vers les 4 bits de registre de contrôle CR0. | - | - | 3 | 10 | XXX | XXX
LMSW mémoire16 | Cette instruction permet de copier 4 des bits d'une opérande vers les 4 bits de registre de contrôle CR0. | - | - | 6 | 13 | XXXXX | XXXXX
LOCK | Cette instruction est utilisé comme préfixe avec d'autres instructions pour amener le microprocesseur à émettre un signal de vérouillage (Lock) sur le bus lors du traitement de l'instruction suivante. | 2 | 2 | 0 | 0 | X | X
LODS source | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction. | 16 | 12 | 5 | 5 | X | X
LOOP label | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0. | 17 | 17 | 8+m | 11+m | XX | XX
LOOP pas de saut | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0. | 5 | 5 | 4 | ? | XX | XX
LOOPE label | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1. | 18 | 18 | 8+m | 11+m | XX | XX
LOOPE pas de saut | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1. | 6 | 6 | 4 | ? | XX | XX
LOOPNE label | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0. | 19 | 19 | 8+m | 11+m | XX | XX
LOOPNE pas de saut | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0. | 5 | 5 | 4 | ? | XX | XX
LOOPNZ label | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0. | 19 | 19 | 8+m | 11+m | XX | XX
LOOPNZ pas de saut | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0. | 5 | 5 | 4 | ? | XX | XX
LOOPZ label | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1. | 18 | 18 | 8+m | 11+m | XX | XX
LOOPZ pas de saut | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1. | 6 | 6 | 4 | ? | XX | XX
LSL registre16,registre16 | Cette instruction permet de charger la limite de segment d'un descripteur de segment spécifié avec l'opérande source dans l'opérande de destination et fixe le drapeau ZF du regsistre EFLAGS. | - | - | 14 | 20 à 25 | XXX | XXX
LSL registre32,registre32 | Cette instruction permet de charger la limite de segment d'un descripteur de segment spécifié avec l'opérande source dans l'opérande de destination et fixe le drapeau ZF du regsistre EFLAGS. | - | - | - | 20 à 25 | XXX | XXX
LSL registre16,mémoire16 | Cette instruction permet de charger la limite de segment d'un descripteur de segment spécifié avec l'opérande source dans l'opérande de destination et fixe le drapeau ZF du regsistre EFLAGS. | - | - | 16 | 21 à 26 | XXXXX | XXXXX
LSL registre32,mémoire32 | Cette instruction permet de charger la limite de segment d'un descripteur de segment spécifié avec l'opérande source dans l'opérande de destination et fixe le drapeau ZF du regsistre EFLAGS. | - | - | - | 21 à 26 | XXXXX | XXXXX
LSS destination,mémoire | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment SS (Segment de pile) et dans un registre d'offset spécifié. | - | - | - | 7 | XXXXX | XXXXXXX
LTR registre16 | Cette instruction permet de charger l'opérande source dans le champ du sélecteur de segment du registre de tâche. | - | - | 17 | 23 | XXX | XXX
LTR mémoire16 | Cette instruction permet de charger l'opérande source dans le champ du sélecteur de segment du registre de tâche. | - | - | 18 | 27 | XXXXX | XXXXX
MOV registre,registre | Cette instruction permet de copier opérande source dans une opérande destinataire. | 2 | 2 | 2 | 2 | XX | XX
MOV mémoire,registre | Cette instruction permet de copier opérande source dans une opérande destinataire. | 13+EA | 9+EA | 3 | 2 | XX | XX
MOV registre,mémoire | Cette instruction permet de copier opérande source dans une opérande destinataire. | 12+EA | 8+EA | 5 | 4 | XX | XXXX
MOV mémoire,immédiat | Cette instruction permet de copier opérande source dans une opérande destinataire. | 14+EA | 10+EA | 3 | 2 | XXX | XXXXXX
MOV registre,immédiat | Cette instruction permet de copier opérande source dans une opérande destinataire. | 4 | 4 | 2 | 2 | XX | XXX
MOV mémoire,accumulateur | Cette instruction permet de copier opérande source dans une opérande destinataire. | 14 | 10 | 3 | 2 | XXX | XXX
MOV accumulateur,mémoire | Cette instruction permet de copier opérande source dans une opérande destinataire. | 14 | 10 | 5 | 4 | XXX | XXX
MOV registre segment,reg16 | Cette instruction permet de copier opérande source dans une opérande destinataire. | 2 | 2 | 2 | 2 | XX | XX
MOV RegistreSeg,mémoire | Cette instruction permet de copier opérande source dans une opérande destinataire. | 12+EA | 8+EA | 5 | 5 | XX | XXXX
MOV registre16,SegRegistre | Cette instruction permet de copier opérande source dans une opérande destinataire. | 2 | 2 | 2 | 2 | XX | XX
MOV mémoire16,segregistre | Cette instruction permet de copier opérande source dans une opérande destinataire. | 13+EA | 9+EA | 3 | 2 | XX | XXXX
MOV Reg32,controlRegistre | Cette instruction permet de copier opérande source dans une opérande destinataire. | - | - | - | 6 | XXX | XXX
MOV Registre32,DebugReg | Cette instruction permet de copier opérande source dans une opérande destinataire. | - | - | - | 10 | XXX | XXX
MOV DebugReg,Registre32 | Cette instruction permet de copier opérande source dans une opérande destinataire. | - | - | - | 22/14 | XXX | XXX
MOV registr32,teste registre | Cette instruction permet de copier opérande source dans une opérande destinataire. | - | - | - | 22/16 | XXX | XXX
MOV TestReg,Registre32 | Cette instruction permet de copier opérande source dans une opérande destinataire. | - | - | - | 12 | XXX | XXX
MOV destination,source | Cette instruction permet de copier opérande source dans une opérande destinataire. | 26 | 18 | 5 | 7 | X | X
MOVSX registre,registre | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires avec l'extension des signes.. | - | - | - | 3 | XXX | XXX
MOVSX registre,mémoire | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires avec l'extension des signes. | - | - | - | 6 | XXX | XXXXXXX
MOVZX registre,registre | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires par des 0. | - | - | - | 3 | XXX | XXX
MOVZX registre,mémoire | Cette instruction permet de copier un registre de taille inférieur dans un registre de plus grande taille en remplissant les bits supplémentaires par des 0. | - | - | - | 6 | XXX | XXXXXXX
MUL registre8 | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). | 77 | 70 | 13 | 9 à 14 | XX | XX
MUL registre16 | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). | 118 | 113 | 21 | 9 à 22 | XX | XX
MUL registre32 | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). | - | - | - | 9 à 38 | XX | XXXX
MUL mémoire8 | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). | 83+EA | 76+EA | 16 | 12 à 17 | XX | XXXX
MUL mémoire16 | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). | 139+EA | 124+EA | 24 | 12 à 25 | XX | XXXX
MUL mémoire32 | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). | - | - | - | 12 à 21 | XX | XXXX
NEG registre | Cette instruction permet d'effectuer le complément à 2 d'une opérande. | 3 | 3 | 2 | 2 | XX | XX
NEG mémoire | Cette instruction permet d'effectuer le complément à 2 d'une opérande. | 24+EA | 16+EA | 7 | 6 | XX | XXXX
NOP | Cette instruction ne fait rien. | 3 | 3 | 3 | 3 | X | X
NOT registre | Cette instruction permet d'inverser la valeur de chacun des bits d'une opérande. | 3 | 3 | 2 | 2 | XX | XX
NOT mémoire | Cette instruction permet d'inverser la valeur de chacun des bits d'une opérande. | 24+EA | 16+EA | 7 | 6 | XX | XXXX
OR registre,registre | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandessp écifiés. | 3 | 3 | 2 | 2 | XX | XX
OR mémoire,registre | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandessp écifiés. | 24+EA | 16+EA | 7 | 7 | XX | XXXX
OR registre,méoire | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandessp écifiés. | 13+EA | 9+EA | 7 | 6 | XX | XXXX
OR registre,immédiat | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandessp écifiés. | 4 | 4 | 3 | 2 | XX | XXX
OR mémoire8,immmédiat8 | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandessp écifiés. | 17+EA | 17+EA | 7 | 7 | XXX | XXXXXX
OR mémoire16,immédiat16 | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandessp écifiés. | 25+EA | 25+EA | 7 | 7 | XXX | XXXXXX
OR accumulateur,immédiat | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandessp écifiés. | 4 | 4 | 3 | 2 | XX | XXX
OUT immédiat8,accumulateur | Cette instruction permet d'envoyer un octet, un mot ou un double mot sur le port d'entrée/sortie. | 14 | 10 | 3 | 10 | XX | XX
OUT DX,accumulateur | Cette instruction permet d'envoyer un octet, un mot ou un double mot sur le port d'entrée/sortie. | 12 | 8 | 3 | 11 | X | X
OUTS port,source | Cette instruction permet d'envoyer un octet, un mot ou un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | - | - | 5 | 14 | X | X
POP registre16 | Cette instruction permet de désempiler de la pile une mot ou un double mot et la met dans une opérande. | 12 | 8 | 5 | 4 | X | X
POP registre32 | Cette instruction permet de désempiler de la pile une mot ou un double mot et la met dans une opérande. | - | - | - | 4 | XX | XX
POP mémoire16 | Cette instruction permet de désempiler de la pile une mot ou un double mot et la met dans une opérande. | 25+EA | 17+EA | 5 | 5 | XX | XXXX
POP mémoire32 | Cette instruction permet de désempiler de la pile une mot ou un double mot et la met dans une opérande. | - | - | - | 5 | XXX | XXXXX
POP RegistreSegment | Cette instruction permet de désempiler de la pile une mot ou un double mot et la met dans une opérande. | 12 | 8 | 5 | 7 | X | X
POPA | Cette instruction permet de désempiler de la pile respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX. | - | - | 19 | 24 | X | X
POPAD | Cette instruction permet de désempiler de la pile respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX. | - | - | - | 24 | XX | XX
POPF | Cette instruction permet de désempiler de la pile le registre 16 bits de drapeau contenant les indicateurs d'état. | 12 | 8 | 5 | 5 | X | X
POPFD | Cette instruction permet de désempiler de la pile le registre 32 bits de drapeau contenant les indicateurs d'état. | - | - | - | 5 | XX | XX
PUSH registre16 | Cette instruction permet d'empiler une mot ou un double mot dans la pile. | 15 | 11 | 3 | 2 | X | X
PUSH registre32 | Cette instruction permet d'empiler une mot ou un double mot dans la pile. | - | - | - | 2 | XX | XX
PUSH mémoire16 | Cette instruction permet d'empiler une mot ou un double mot dans la pile. | 24+EA | 16+EA | 5 | 5 | XX | XXXX
PUSH mémoire32 | Cette instruction permet d'empiler une mot ou un double mot dans la pile. | - | - | - | 5 | XXX | XXXXX
PUSH RegistreSegment | Cette instruction permet d'empiler une mot ou un double mot dans la pile. | 14 | 10 | 3 | 2 | X | X
PUSH Immédiat | Cette instruction permet d'empiler une mot ou un double mot dans la pile. | - | - | 3 | 2 | XX | XXX
PUSHA | Cette instruction permet d'empiler respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX dans la pile. | - | - | 17 | 18 | X | X
PUSHAD | Cette instruction permet d'empiler respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX dans la pile. | - | - | - | 18 | XX | XX
PUSHF | Cette instruction permet d'empiler respectivement le registre 16 bits de drapeau des indicateurs d'état dans la pile. | 14 | 10 | 3 | 4 | X | X
PUSHFD | Cette instruction permet d'empiler respectivement le registre 32 bits de drapeau des indicateurs d'état dans la pile. | - | - | - | 4 | XX | XX
RCL registre,1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | 2 | 2 | 2 | 9 | XX | XX
RCL mémoire,1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | 23+EA | 15+EA | 7 | 10 | XX | XXXX
RCL registre,CL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | 8+4n | 8+4n | 5+n | 9 | XX | XX
RCL mémoire,CL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | 28+EA+4n | 20+EA+4n | 8+n | 10 | XX | XXXX
RCL registre,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | - | - | 5+n | 9 | XXX | XXX
RCL mémoire,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | - | - | 8+n | 10 | XXX | XXXXX
RCR registre,1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | 2 | 2 | 2 | 9 | XX | XX
RCR mémoire,1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | 23+EA | 15+EA | 7 | 10 | XX | XXXX
RCR registre,CL | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | 8+4n | 8+4n | 5+n | 9 | XX | XX
RCR m‚moire,CL | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | 28+EA+4n | 20+EA+4n | 8+n | 10 | XX | XXXX
RCR registre,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | - | - | 5+n | 9 | XXX | XXX
RCR mémoire,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | - | - | 8+n | 10 | XXX | XXXXX
REP | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions tant que CX ne vaut pas 0. | 2 | 2 | 2 | 2 | X | X
REPE | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0. | 2 | 2 | 2 | 2 | X | X
REPNE | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1. | 2 | 2 | 2 | 2 | X | X
REPNZ | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1. | 2 | 2 | 2 | 2 | X | X
REPZ | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0. | 2 | 2 | 2 | 2 | X | X
RETF | Cette instruction permet de quitter une procédure ayant lieu avec un appel long (FAR CALL). | 34 | 26 | 15+m | 18+m | X | X
RETF immédiat | Cette instruction permet de quitter une procédure ayant lieu avec un appel long (FAR CALL). | 33 | 25 | 15+m | 18+m | XXX | XXX
RETN | Cette instruction permet de quitter une procédure ayant lieu avec un appel court (NEAR CALL). | 20 | 16 | 11+m | 10+m | X | X
RETN immédiat8 | Cette instruction permet de quitter une procédure ayant lieu avec un appel court (NEAR CALL). | 24 | 20 | 11+m | 10+m | XXX | XXX
ROL registre,1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | 2 | 2 | 2 | 3 | XX | XX
ROL mémoire,1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | 23+EA | 15+EA | 7 | 7 | XX | XXXX
ROL registre,CL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | 8+4n | 8+4n | 5+n | 3 | XX | XX
ROL mémoire,CL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | 28+EA+4n | 20+EA+4n | |8+n | 7 | XX | XXXX
ROL registre,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | - | - | 5+n | 3 | XXX | XXX
ROL mémoire,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | - | - | 8+n | 7 | XXX | XXXXX
ROR registre,1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | 2 | 2 | 2 | 3 | XX | XX
ROR mémoire,1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | 23+EA | 15+EA | 7 | 7 | XX | XXXX
ROR registre,CL | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | 8+4n | 8+4n | 5+n | 3 | XX | XX
ROR mémoire,CL | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | 28+EA+4n | 20+EA+4n | 8+n | 7 | XX | XXXX
ROR registre,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | - | - | 5+n | 3 | XXX | XXX
ROR mémoire,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | - | - | 8+n | 7 | XXX | XXXXX
SAHF | Cette instruction permet de copier les bits du registre AH dans l'octet de poids faible dans le registre des drapeaux (les indicateurs d'état). | 4 | 4 | 2 | 3 | X | X
SAL registre,1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | 2 | 2 | 2 | 3 | XX | XX
SAL mémoire,1 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | 23+EA | 15+EA | 7 | 7 | XX | XXXX
SAL registre,CL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | 8+4n | 8+4n | 5+n | 3 | XX | XX
SAL mémoire,CL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | 28+EA+4n | 20+EA+4n | 8+n | 7 | XX | XXXX
SAL registre,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | - | - | 5+n | 3 | XXX | XXX
SAL mémoire,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | - | - | 8+n | 7 | XXX | XXXXX
SAR registre,1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | 2 | 2 | 2 | 3 | XX | XX
SAR mémoire,1 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | 23+EA | 15+EA | 7 | 7 | XX | XXXX
SAR registre,CL | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | 8+4n | 8+4n | 5+n | 3 | XX | XX
SAR mémoire,CL | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | 28+EA+4n | 20+EA+4n | 8+n | 7 | XX | XXXX
SAR registre,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | - | - | 5+n | 3 | XXX | XXX
SAR mémoire,immédiat8 | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | - | - | 8+n | 7 | XXX | XXXXX
SBB registre,registre | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande. | 3 | 3 | 2 | 2 | XX | XX
SBB mémoire,registre | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande. | 24+EA | 16+EA | 7 | 6 | XX | XXXX
SBB registre,mémoire | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande. | 13+EA | 9+EA | 7 | 7 | XX | XXXX
SBB registre,immédiat | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande. | 4 | 4 | 3 | 2 | XXX | XXXX
SBB mémoire,immédiat | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande. | 25+EA | 17+EA | 7 | 7 | XXX | XXXXXX
SBB accumulateur,immédiat | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande. | 4 | 4 | 3 | 2 | XX | XXX
SCAS chaine | Cette instruction permet de comparer un octet, un mot ou un double mot avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | 15 | 15 | 7 | 7 | X | X
SETAE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETAE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETB registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETB mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETBE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETBE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETC registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETC mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETG registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETG mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETGE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETGE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETL registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETL mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETLE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETLE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNA registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNA mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNAE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNAE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNB registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNB mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNC registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNC mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNG registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNG mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNGE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNGE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNL registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNL mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNLE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNLE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNO registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNO mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNP registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNP mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNS registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNS mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETNZ registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETNZ mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETO registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETO mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETP registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETP mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETPE registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETPE mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETPO registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETPO mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETS registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETS mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SETZ registre8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 4 | XXX | XXX
SETZ mémoire8 | Cette directive permet de fixer la valeur d'une opérande 1 si la condition d'indicateur d'état du registre 32 bits de drapeau est vrai sinon fixe la valeur à 0. | - | - | - | 5 | XXX | XXX
SGDT mémoire64 | Cette instruction permet d'entreposer le sélecteur de segment dans le registre GDTR (registre de table global de descripteur) dans l'opérande de destination. | - | - | 11 | 9 | XXXXX | XXXXX
SHL registre,1 | Décalage de bits à gauche | 2 | 2 | 2 | 3 | XX | XX
SHL mémoire,1 | Décalage de bits à gauche | 23+EA | 15+EA | 7 | 7 | XX | XXXX
SHL registre,CL | Décalage de bits à gauche | 8+4n | 8+4n | 5+n | 3 | XX | XX
SHL mémoire,CL | Décalage de bits à gauche | 28+EA+4n | 20+EA+4n | 8+n | 7 | XX | XXXX
SHL registre,immédiat8 | Décalage de bits à gauche | - | - | 5+n | 3 | XXX | XXX
SHL mémoire,immédiat8 | Décalage de bits à gauche | - | - | 8+n | 7 | XXX | XXXXX
SHLD reg16,reg16,immédiat8 | Décalage de bits à gauche | - | - | - | 3 | XXX | XXX
SHLD reg32,reg32,immédiat8 | Décalage de bits à gauche | - | - | - | 3 | XXXX | XXXX
SHLD mém16,reg16,immédiat8 | Décalage de bits à gauche | - | - | - | 7 | XXXXXX | XXXXXX
SHLD mém32,reg32,immédiat8 | Décalage de bits à gauche | - | - | - | 7 | XXXXXX | XXXXXX
SHLD registre16,reg16,CL | Décalage de bits à gauche | - | - | - | 3 | XXX | XXX
SHLD registre32,reg32,CL | Décalage de bits à gauche | - | - | - | 3 | XXX | XXX
SHLD mémoire16,reg16,CL | Décalage de bits à gauche | - | - | - | 7 | XXXXX | XXXXX
SHLD mémoire32,reg32,CL | Décalage de bits à gauche | - | - | - | 7 | XXXXX | XXXXX
SHR registre,1 | Décalage de bits à droite | 2 | 2 | 2 | 3 | XX | XX
SHR mémoire,1 | Décalage de bits à droite | 23+EA | 15+EA | 7 | 7 | XX | XXXX
SHR registre,CL | Décalage de bits à droite | 8+4n | 8+4n | 5+n | 3 | XX | XX
SHR mémoire,CL | Décalage de bits à droite | 28+EA+4n | 20+EA+4n | 8+n | 7 | XX | XXXX
SHR registre,immédiat8 | Décalage de bits à droite | - | - | 5+n | 3 | XXX | XXX
SHR mémoire,immédiat8 | Décalage de bits à droite | - | - | 8+n | 7 | XXX | XXXXX
SHRD reg16,reg16,immédiat8 | Décalage de bits à droite | - | - | - | 3 | XXX | XXX
SHRD reg32,reg32,immédiat8 | Décalage de bits à droite | - | - | - | 3 | XXXX | XXXX
SHRD mém16,reg16,immédiat8 | Décalage de bits à droite | - | - | - | 7 | XXXXXX | XXXXXX
SHRD mém32,reg32,immédiat8 | Décalage de bits à droite | - | - | - | 7 | XXXXXX | XXXXXX
SHRD registre16,reg16,CL | Décalage de bits à droite | - | - | - | 3 | XXX | XXX
SHRD registre|2,reg|2,CL | Décalage de bits à droite | - | - | - | 3 | XXX | XXX
SHRD mémoire16,reg16,CL | Décalage de bits à droite | - | - | - | 7 | XXXXX | XXXXX
SHRD mémoire32,reg32,CL | Décalage de bits à droite | - | - | - | 7 | XXXXX | XXXXX
SIDT mémoire64 | Cette instruction permet d'entreposer le registre de descripteur de table d'interruption (IDTR) dans l'opérande de destination. | - | - | 12 | 9 | XXXXX | XXXXX
SLDT registre16 | Cette instruction permet d'entreposer le sélecteur de segment dans le registre LDTR (registre de table local de descripteur) dans l'opérande de destination. | - | - | 2 | 2 | XXX | XXX
SLDT mémoire16 | Cette instruction permet d'entreposer le sélecteur de segment dans le registre LDTR (registre de table local de descripteur) dans l'opérande de destination. | - | - | 2 | 2 | XXXXX | XXXXX
SMSW registre16 | Cette instruction permet d'entreposer le mot des états (soit les bits de 0 à 15 du registre de contrôle CR0) à partir du registre de tâche (TR) dans l'opérande cible. | - | - | 2 | 10 | XXX | XXX
SMSW mémoire16 | Cette instruction permet d'entreposer le mot des états (soit les bits de 0 à 15 du registre de contrôle CR0) à partir du registre de tâche (TR) dans l'opérande cible. | - | - | 3 | 3 | XXXXX | XXXXX
STC | Cette instruction permet de fixer l'indicateur de retenue (CF) à la valeur 1. | 2 | 2 | 2 | 2 | X | X
STD | Cette instruction permet de fixer l'indicateur de direction (DF) à la valeur 1. | 2 | 2 | 2 | 2 | X | X
STI | Cette instruction permet de fixer l'indicateur de direction (DF) à la valeur 1. | 2 | 2 | 2 | 2 | X | X
STOS destination | Cette instruction permet de copier un octet, un mot ou un double mot dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | 15 | 11 | 3 | 4 | X | X
STR registre16 | Cette instruction permet d'entreposer le sélecteur de segment à partir du registre de tâche (TR) à l'opérande cible | - | - | 2 | 2 | XXX | XXX
STR mémoire16 | Cette instruction permet d'entreposer le sélecteur de segment à partir du registre de tâche (TR) à l'opérande cible | - | - | 3 | 2 | XXXXX | XXXXX
SUB registre,registre | Soustraction | 3 | 3 | 2 | 2 | XX | XX
SUB mémoire,registre | Soustraction | 24+EA | 16+EA | 7 | 6 | XX | XXXX
SUB registre,mémoire | Soustraction | 13+EA | 9+EA | 7 | 7 | XX | XXXX
SUB registre,immédiat | Soustraction | 4 | 4 | 3 | 2 | XXX | XXXX
SUB mémoire,immédiat | Soustraction | 25+EA | 17+EA | 7 | 7 | XXX | XXXXXX
SUB accumulateur,immédiat | Soustraction | 4 | 4 | 3 | 2 | XX | XXX
TEST registre,registre | Teste et binaire | 3 | 3 | 2 | 1 | XX | XX
TEST registre,mémoire | Teste et binaire | 13+EA | 9+EA | 6 | 5 | XX | XXXX
TEST mémoire,registre | Teste et binaire | 13+EA | 9+EA | 6 | 5 | XX | XXXX
TEST registre,immédiat | Teste et binaire | 5 | 5 | 3 | 2 | XXX | XXXX
TEST mémoire,immédiat | Teste et binaire | 11+EA | 11+EA | 6 | 5 | XXX | XXXXXX
TEST accumulateur,immédiat | Teste et binaire | 4 | 4 | 3 | 2 | XX | XXX
VERR registre16 | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode lecture à partir du niveau de privilège courant (CPL). | - | - | 14 | 10 | XXX | XXX
VERR mémoire16 | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode lecture à partir du niveau de privilège courant (CPL). | - | - | 16 | 11 | XXXXX | XXXXX
VERW registre16 | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode écriture à partir du niveau de privilège courant (CPL). | - | - | 14 | 15 | XXX | XXX
VERW mémoire16 | Cette instruction permet de vérifier si le code ou le segment de données spécifié est en mode écriture à partir du niveau de privilège courant (CPL). | - | - | 16 | 16 | XXXXX | XXXXX
WAIT | Cette instruction permet de faire passer le microprocesseur en mode d'attente jusqu'à ce que la ligne de teste sur la carte mère s'active. | 4 | 4 | 3 | 6 | X | X
XCHG registre,registre | Échange les deux éléments | 4 | 4 | 3 | 3 | XX | XX
XCHG mémoire,registre | Échange les deux éléments | 25+EA | 17+EA | 5 | 5 | XX | XXXX
XCHG registre,mémoire | Échange les deux éléments | 25+EA | 17+EA | 5 | 5 | XX | XXXX
XCHG accumulateur,registre | Échange les deux éléments | 3 | 3 | 3 | 3 | X | X
XCHG registre,accumulateur | Échange les deux éléments | 3 | 3 | 3 | 3 | X | X
XLAT | Cette instruction permet de remplacer le contenu du registre AL par un octet de la «tablesource». | 11 | 11 | 5 | 5 | X | X
XLATB | Cette instruction permet de remplacer le contenu du registre AL par un octet de la «tablesource» sans opérande. | 11 | 11 | 5 | 5 | X | X
XOR registre,registre | Ou exclusif | 3 | 3 | 2 | 2 | XX | XX
XOR mémoire,registre | Ou exclusif | 24+EA | 16+EA | 7 | 6 | XX | XXXX
XOR registre,mémoire | Ou exclusif | 13+EA | 9+EA | 7 | 7 | XX | XXXX
XOR registre,immédiat | Ou exclusif | 4 | 4 | 3 | 2 | XXX | XXXX
XOR mémoire,immédiat | Ou exclusif | 25+EA | 17+EA | 7 | 7 | XXX | XXXXXX
XOR accumulateur,immédiat | Ou exclusif | 4 | 4 | 3 | 2 | XX | XXX


Instructions par catégories

Voici les instructions assembleur classés par catégorie :

Catégorie | Description
Boucle | Cette catégorie référence les instructions permettant d'effectuer des répétitions d'instructions.
Chaine | Cette catégorie référence les instructions permettant la gestion en bloc de mémoire.
Comparaison | Cette catégorie référence les instructions permettant d'effectuer différents types de comparaisons
Conversions | Cette catégorie référence les instructions permettant la conversion ASCII, BCD,...
Décalage de bits | Cette catégorie référence les instructions permettant des décalages de bits
Drapeaux | Cette catégorie référence les instructions permettant la manipulations des drapeaux du registre du microprocesseur
Opérateurs | Cette catégorie référence les instructions permettant des opérations arithmétiques
Saut conditionnel | Cette catégorie référence les instructions permettant d'effectuer des branchements selon une ou des condition(s)
Saut inconditionnel | Cette catégorie référence les instructions permettant d'effectuer des branchements inconditionnel
Transferts de données | Cette catégorie référence les instructions permettant le transfert de bloc de données.
Utilisation de la pile | Cette catégorie référence les instructions permettant l'utilisation de la pile (empile/dépile).

Dernière mise à jour : Samedi, le 2 août 2014


Voici les instructions assembleur classés par catégorie de boucle :

Instruction | Description | CPU/MPU
JCXZ | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié. | INTEL 8086+
LOOP | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0. | INTEL 8086+
LOOPE | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1. | INTEL 8086+
LOOPNE | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0. | INTEL 8086+
LOOPNZ | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0. | INTEL 8086+
LOOPZ | Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1. | INTEL 8086+

Dernière mise à jour : Vendredi, le 4 mars 2016


Assembleur 80x86

J??
INTEL 8086+ Jump if ??

Syntaxe

J?? destination

Paramètres

Nom | Description
destination | Ce paramètre permet d'indiquer l'emplacement ou doit être poursuivi l'exécution si la condition correspond.

Description

Cette instruction permet d'effectuer un branchement conditionnel à un emplacement mémoire spécifié.

Il est a noter que les combinaisons de lettres permettant de représenter la condition sont indiquées dans le tableau suivant :

Instruction | Condition | Description | CPU/MPU
JA | A | Supérieur | INTEL 8086+
JAE | AE | Supérieur ou égal | INTEL 8086+
JB | B | Inférieur | INTEL 8086+
JBE | BE | Inférieur ou égal | INTEL 8086+
JC | C | Indicateur de retenue à égal à 1 | INTEL 8086+
JCXZ | CXZ | Si CX = 0 | INTEL 8086+
JE | E | Zéro (Egal) | INTEL 8086+
JECXZ | ECXZ | Si ECX = 0 | INTEL 80386+
JG | G | Supérieur | INTEL 8086+
JGE | GE | Supérieur ou égal | INTEL 8086+
JL | L | Inférieur | INTEL 8086+
JLE | LE | Inférieur ou égal | INTEL 8086+
JNA | NA | Pas supérieur | INTEL 8086+
JNAE | NAE | Ni supérieur ni égal | INTEL 8086+
JNB | NB | Pas inférieur | INTEL 8086+
JNC | NC | Indicateur de retenue égal à 0 | INTEL 8086+
JNE | NE | Pas égal (Zéro) | INTEL 8086+
JNG | NG | Pas supérieur | INTEL 8086+
JNGE | NGE | Ni supérieur ni égal | INTEL 8086+
JNL | NL | Pas inférieur | INTEL 8086+
JNLE | NLE | Ni inférieur ni égal | INTEL 8086+
JNO | NO | Pas de débordement (indicateur de débordement égal à 0) | INTEL 8086+
JNP | NP | Pas de parité | INTEL 8086+
JNS | NS | Pas de signe | INTEL 8086+
JNZ | NZ | Pas zéro | INTEL 8086+
JO | O | Débordement (indicateur de débordement égal à 1) | INTEL 8086+
JP | P | Parité | INTEL 8086+
JPE | PE | Parité paire | INTEL 8086+
JPO | PO | Parité impaire | INTEL 8086+
JRCXZ | RCXZ | Si RCX = 0 | x86-64+
JS | S | Signe | INTEL 8086+
JZ | Z | Zéro | INTEL 8086+

Remarque

  • Contrairement à ce que l'on pourrait le croire, l'utilisation de cette instruction n'est pas uniquement en combinaison avec l'instruction CMP. En effet, beaucoup d'instructions comme ADD, AND, OR, SUB, XOR,... affectent également les drapeaux du microprocesseur et cette instruction peut également être utiliser pour connaitre le résultat de l'opération.

Algorithme

SI condition ALORS
EIP ← EIP + SignExtend(destination)
SI taille de l'opérande = 16 bits ALORS
EIP ← EIP ∩ 0000FFFFh
FIN SI
FIN SI

Mnémonique

Instruction | Opcode | Description
JO rel8off | 70h cb | Saut si drapeau de débordement vaut 1 (OF = 1).
JO rel16off | 0Fh 80h cw | Saut si drapeau de débordement vaut 1 (OF = 1).
JO rel32off | 0Fh 80h cd | Saut si drapeau de débordement vaut 1 (OF = 1).
JNO rel8off | 71h cb | Saut si drapeau de débordement vaut 0 (OF = 0).
JNO rel16off | 0Fh 81h cw | Saut si drapeau de débordement vaut 0 (OF = 0).
JNO rel32off | 0Fh 81h cd | Saut si drapeau de débordement vaut 0 (OF = 0).
JB rel8off | 72h cb | Saut si drapeau de retenue vaut 1 (CF = 1).
JB rel16off | 0Fh 82h cw | Saut si drapeau de retenue vaut 1 (CF = 1).
JB rel32off | 0Fh 82h cd | Saut si drapeau de retenue vaut 1 (CF = 1).
JC rel8off | 72h cb | Saut si drapeau de retenue vaut 1 (CF = 1).
JC rel16off | 0Fh 82h cw | Saut si drapeau de retenue vaut 1 (CF = 1).
JC rel32off | 0Fh 82h cd | Saut si drapeau de retenue vaut 1 (CF = 1).
JNAE rel8off | 72h cb | Saut si drapeau de retenue vaut 1 (CF = 1).
JNAE rel16off | 0Fh 82h cw | Saut si drapeau de retenue vaut 1 (CF = 1).
JNAE rel32off | 0Fh 82h cd | Saut si drapeau de retenue vaut 1 (CF = 1).
JNB rel8off | 73h cb | Saut si drapeau de retenue vaut 0 (CF = 0).
JNB rel16off | 0Fh 83h cw | Saut si drapeau de retenue vaut 0 (CF = 0).
JNB rel32off | 0Fh 83h cd | Saut si drapeau de retenue vaut 0 (CF = 0).
JNC rel8off | 73h cb | Saut si drapeau de retenue vaut 0 (CF = 0).
JNC rel16off | 0Fh 83h cw | Saut si drapeau de retenue vaut 0 (CF = 0).
JNC rel32off | 0Fh 83h cd | Saut si drapeau de retenue vaut 0 (CF = 0).
JAE rel8off | 73h cb | Saut si drapeau de retenue vaut 0 (CF = 0).
JAE rel16off | 0Fh 83h cw | Saut si drapeau de retenue vaut 0 (CF = 0).
JAE rel32off | 0Fh 83h cd | Saut si drapeau de retenue vaut 0 (CF = 0).
JZ rel8off | 74h cb | Saut si drapeau du zéro vaut 1 (ZF = 1).
JZ rel16off | 0Fh 84h cw | Saut si drapeau du zéro vaut 1 (ZF = 1).
JZ rel32off | 0Fh 84h cd | Saut si drapeau du zéro vaut 1 (ZF = 1).
JE rel8off | 74h cb | Saut si drapeau du zéro vaut 1 (ZF = 1).
JE rel16off | 0Fh 84h cw | Saut si drapeau du zéro vaut 1 (ZF = 1).
JE rel32off | 0Fh 84h cd | Saut si drapeau du zéro vaut 1 (ZF = 1).
JNZ rel8off | 75h cb | Saut si drapeau du zéro vaut 0 (ZF = 0).
JNZ rel16off | 0Fh 85h cw | Saut si drapeau du zéro vaut 0 (ZF = 0).
JNZ rel32off | 0Fh 85h cd | Saut si drapeau du zéro vaut 0 (ZF = 0).
JNE rel8off | 75h cb | Saut si drapeau du zéro vaut 0 (ZF = 0).
JNE rel16off | 0Fh 85h cw | Saut si drapeau du zéro vaut 0 (ZF = 0).
JNE rel32off | 0Fh 85h cd | Saut si drapeau du zéro vaut 0 (ZF = 0).
JBE rel8off | 76h cb | Saut si drapeau du zéro vaut 1 ou drapeau de retenue vaut 1 (CF = 1 ou ZF = 1).
JBE rel16off | 0Fh 86h cw | Saut si drapeau du zéro vaut 1 ou drapeau de retenue vaut 1 (CF = 1 ou ZF = 1).
JBE rel32off | 0Fh 86h cd | Saut si drapeau du zéro vaut 1 ou drapeau de retenue vaut 1 (CF = 1 ou ZF = 1).
JNA rel8off | 76h cb | Saut si drapeau du zéro vaut 1 ou drapeau de retenue vaut 1 (CF = 1 ou ZF = 1).
JNA rel16off | 0Fh 86h cw | Saut si drapeau du zéro vaut 1 ou drapeau de retenue vaut 1 (CF = 1 ou ZF = 1).
JNA rel32off | 0Fh 86h cd | Saut si drapeau du zéro vaut 1 ou drapeau de retenue vaut 1 (CF = 1 ou ZF = 1).
JNBE rel8off | 77h cb | Saut si drapeau du zéro vaut 0 et drapeau de retenue vaut 0 (CF = 0 et ZF = 0).
JNBE rel16off | 0Fh 87h cw | Saut si drapeau du zéro vaut 0 et drapeau de retenue vaut 0 (CF = 0 et ZF = 0).
JNBE rel32off | 0Fh 87h cd | Saut si drapeau du zéro vaut 0 et drapeau de retenue vaut 0 (CF = 0 et ZF = 0).
JA rel8off | 77h cb | Saut si drapeau du zéro vaut 0 et drapeau de retenue vaut 0 (CF = 0 et ZF = 0).
JA rel16off | 0Fh 87h cw | Saut si drapeau du zéro vaut 0 et drapeau de retenue vaut 0 (CF = 0 et ZF = 0).
JA rel32off | 0Fh 87h cd | Saut si drapeau du zéro vaut 0 et drapeau de retenue vaut 0 (CF = 0 et ZF = 0).
JS rel8off | 78h cb | Saut si drapeau de signe vaut 1 (SF = 1).
JS rel16off | 0Fh 88h cw | Saut si drapeau de signe vaut 1 (SF = 1).
JS rel32off | 0Fh 88h cd | Saut si drapeau de signe vaut 1 (SF = 1).
JNS rel8off | 79h cb | Saut si drapeau de signe vaut 0 (SF = 0).
JNS rel16off | 0Fh 89h cw | Saut si drapeau de signe vaut 0 (SF = 0).
JNS rel32off | 0Fh 89h cd | Saut si drapeau de signe vaut 0 (SF = 0).
JP rel8off | 7Ah cb | Saut si drapeau de parité vaut 1 (PF = 1).
JP rel16off | 0Fh 8Ah cw | Saut si drapeau de parité vaut 1 (PF = 1).
JP rel32off | 0Fh 8Ah cd | Saut si drapeau de parité vaut 1 (PF = 1).
JPE rel8off | 7Ah cb | Saut si drapeau de parité vaut 1 (PF = 1).
JPE rel16off | 0Fh 8Ah cw | Saut si drapeau de parité vaut 1 (PF = 1).
JPE rel32off | 0Fh 8Ah cd | Saut si drapeau de parité vaut 1 (PF = 1).
JNP rel8off | 7Bh cb | Saut si drapeau de parité vaut 0 (PF = 0).
JNP rel16off | 0Fh 8Bh cw | Saut si drapeau de parité vaut 0 (PF = 0).
JNP rel32off | 0Fh 8Bh cd | Saut si drapeau de parité vaut 0 (PF = 0).
JPO rel8off | 7Bh cb | Saut si drapeau de parité vaut 0 (PF = 0).
JPO rel16off | 0Fh 8Bh cw | Saut si drapeau de parité vaut 0 (PF = 0).
JPO rel32off | 0Fh 8Bh cd | Saut si drapeau de parité vaut 0 (PF = 0).
JL rel8off | 7Ch cb | Saut si SF <> OF.
JL rel16off | 0Fh 8Ch cw | Saut si SF <> OF.
JL rel32off | 0Fh 8Ch cd | Saut si SF <> OF.
JNGE rel8off | 7Ch cb | Saut si SF <> OF.
JNGE rel16off | 0Fh 8Ch cw | Saut si SF <> OF.
JNGE rel32off | 0Fh 8Ch cd | Saut si SF <> OF.
JNL rel8off | 7Dh cb | Saut si SF = OF.
JNL rel16off | 0Fh 8Dh cw | Saut si SF = OF.
JNL rel32off | 0Fh 8Dh cd | Saut si SF = OF.
JGE rel8off | 7Dh cb | Saut si SF = OF.
JGE rel16off | 0Fh 8Dh cw | Saut si SF = OF.
JGE rel32off | 0Fh 8Dh cd | Saut si SF = OF.
JLE rel8off | 7Eh cb | Saut si ZF = 1 ou SF <> OF.
JLE rel16off | 0Fh 8Eh cw | Saut si ZF = 1 ou SF <> OF.
JLE rel32off | 0Fh 8Eh cd | Saut si ZF = 1 ou SF <> OF.
JNG rel8off | 7Eh cb | Saut si ZF = 1 ou SF <> OF.
JNG rel16off | 0Fh 8Eh cw | Saut si ZF = 1 ou SF <> OF.
JNG rel32off | 0Fh 8Eh cd | Saut si ZF = 1 ou SF <> OF.
JNLE rel8off | 7Fh cb | Saut si ZF = 0 et SF = OF.
JNLE rel16off | 0Fh 8Fh cw | Saut si ZF = 0 et SF = OF.
JNLE rel32off | 0Fh 8Fh cd | Saut si ZF = 0 et SF = OF.
JG rel8off | 7Fh cb | Saut si ZF = 0 et SF = OF.
JG rel16off | 0Fh 8Fh cw | Saut si ZF = 0 et SF = OF.
JG rel32off | 0Fh 8Fh cd | Saut si ZF = 0 et SF = OF.
JCXZ rel8off | E3h cb | Saut si le registre CX vaut zéro.
JECXZ rel8off | E3h cb | Saut si le registre ECX vaut zéro.
JRCXZ rel8off | E3h cb | Saut si le registre RCX vaut zéro.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique

Exemples

L'exemple suivant permet de vérifier si le registre AX vaut 0 :

  1. OR AX,AX
  2. JE @axvautzero
  3. ; AX ne vaut pas 0
  4. ; ...
  5. @axvautzero
  6. ; AX vaut 0
  7. ; ...

Cet exemple permet de vérifier si la touche ESC a été enfoncé :

  1. @Restart:
  2. MOV AH,00h
  3. INT 16h
  4. CMP AX,011Bh
  5. JNE @Restart
  6. ; La touche ESC a été enfoncé

Cet exemple permet de vérifier si un pilote d'imprimante est installé :

  1. MOV AX,0100h
  2. INT 2Fh
  3. JC @Erreur
  4. CMP AL,0FFh
  5. JE @Installer
  6. @Erreur:
  7. ; Pas installé
  8. ; ...
  9. @Installer:
  10. ; Le pilote est installé
  11. ; ...

Cet exemple permet de vérifier si la touche Ctrl est enfoncé :

  1. Program CtrlPressedSamples;
  3. Function CtrlPressed: Boolean ;Assembler; ASM
  4. XOR AX,AX
  5. MOV ES,AX
  6. CLI
  7. MOV AL,ES:[417h]
  8. STI
  9. AND AL,4
  10. JZ @@End
  11. MOV AL,True
  12. @@End:
  13. END;
  15. BEGIN
  16. If (CtrlPressed)Then WriteLn ('Ctrl enfoncé') Else WriteLn ('Ctrl relâché');
  17. END .

Voir également

Instruction assembleur 80x86 - Instruction JMP

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 815
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 405 à 409
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 130 à 134.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 611 à 618.


Assembleur 80x86

LOOP
INTEL 8088+ Boucle

Syntaxe

LOOP étiquette

Description

Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0.

Algorithme

CX ← CX - 1
SI CX <> 0 ALORS
IP ← IP + Offset
FIN SI

Mnémonique

Instruction | Opcode | Description
LOOP rel8off | E2h cb | Décrémente (R)CX, si (R)CX ne vaut pas 0 alors effectuer un saut court.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique

Exemple

Voici un exemple en Turbo Pascal 7 montrant une utilisation de cette instruction :

  1. Program AsmLoopSamples;
  3. Const
  4. Source: Array [0..5]of Word = (256,1,257,2,258,3);
  6. Var
  7. Target: Array [0..5]of Byte ;
  8. I: Byte ;
  10. Procedure MoveWord2Byte( Const Source; Var Dest;Count: Word );Assembler; ASM
  11. CLD
  12. PUSH DS
  13. LDS SI,Source
  14. LES DI,Dest
  15. MOV CX,Count
  16. JCXZ @End
  17. @Count:
  18. LODSW
  19. STOSB
  20. LOOP @Count
  21. @End:
  22. POP DS
  23. END;
  25. BEGIN
  26. MoveWord2Byte(Source,Target, SizeOf (Target));
  27. WriteLn ('Après transformation : ');
  28. For I:=0 to SizeOf (Target)-1 do Begin
  29. Write (Target[I],',');
  30. End ;
  31. WriteLn ;
  32. END .

on obtiendra le résultat suivant :

Après transformation :
0,1,1,2,2,3,

Voir également

Instruction assembleur 80x86 - Instruction LOOPE
Instruction assembleur 80x86 - Instruction LOOPNE
Instruction assembleur 80x86 - Instruction LOOPNZ
Instruction assembleur 80x86 - Instruction LOOPZ

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 819
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 410
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 151.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 668 à 669.


Assembleur 80x86

LOOPE
INTEL 8088+ LOOP Equal

Syntaxe

LOOPE étiquette

Description

Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1.

Algorithme

CX ← CX - 1
SI CX <> 0 ET ZF = 1 ALORS
IP ← IP + Offset
FIN SI

Mnémonique

Instruction | Opcode | Description
LOOPE rel8off | E1h cb | Décrémente (R)CX, si (R)CX ne vaut pas 0 et ZF vaut 1 alors effectuer un saut court.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 819
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 410
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 151.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 668 à 669.


Assembleur 80x86

LOOPNE
INTEL 8088+ LOOP No Equal

Syntaxe

LOOPNE étiquette

Description

Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0.

Algorithme

CX ← CX - 1
SI CX <> 0 ET ZF = 0 ALORS
IP ← IP + Offset
FIN SI

Mnémonique

Instruction | Opcode | Description
LOOPNE rel8off | E0h cb | Décrémente (R)CX, si (R)CX ne vaut pas 0 et que ZF vaut 0 alors effectuer un saut court.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 820
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 411
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 151.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 668 à 669.


Assembleur 80x86

LOOPNZ
INTEL 8088+ LOOP Non Zero

Syntaxe

LOOPNZ étiquette

Description

Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 0.

Algorithme

CX ← CX - 1
SI CX <> 0 ET ZF = 0 ALORS
IP ← IP + Offset
FIN SI

Mnémonique

Instruction | Opcode | Description
LOOPNZ rel8off | E0h cb | Décrémente (R)CX, si (R)CX ne vaut pas 0 et ZF ne vaut pas 0 alors effectuer un saut court.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 820
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 411
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 151.


Assembleur 80x86

LOOPZ
INTEL 8088+ LOOP Zero

Syntaxe

LOOPZ étiquette

Description

Cette instruction de boucle permet de décrémenter le registre CX (compteur de boucle) de 1 et par la suite de donner le contrôle à une étiquette destinataire tant que le registre CX ne vaut pas 0 et si le drapeau ZF vaut 1.

Algorithme

CX ← CX - 1
SI CX <> 0 ET ZF = 1 ALORS
IP ← IP + Offset
FIN SI

Mnémonique

Instruction | Opcode | Description
LOOPZ rel8off | E1h cb | Décrémente (R)CX, si (R)CX ne vaut pas 0 et que ZF vaut 1 alors effectuer un saut court.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 820
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 411
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 151.


Voici les instructions assembleur classés par catégorie de chaine :

Instruction | Description | CPU/MPU
LODS | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction. | INTEL 8086+
LODSB | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 1 en fonction de l'état du drapeau de direction. | INTEL 8086+
LODSD | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
LODSW | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 2 en fonction de l'état du drapeau de direction. | INTEL 8086+
MOVS | Cette instruction permet de copier un élément de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction. | INTEL 8086+
MOVSB | Cette instruction permet de copier un octet de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 1 en fonction de l'état du drapeau de direction. | INTEL 8086+
MOVSD | Cette instruction permet de copier un double mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
MOVSW | Cette instruction permet de copier un mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 2 en fonction de l'état du drapeau de direction. | INTEL 8086+
OUTS | Cette instruction permet d'envoyer un octet, un mot ou un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | INTEL 80286+
OUTSB | Cette instruction permet d'envoyer un octet contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 1 en fonction de l'état du drapeau de direction. | INTEL 80286+
OUTSD | Cette instruction permet d'envoyer un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
OUTSW | Cette instruction permet d'envoyer un mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 2 en fonction de l'état du drapeau de direction. | INTEL 80286+
REP | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions tant que CX ne vaut pas 0. | INTEL 8086+
REPE | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0. | INTEL 8086+
REPNE | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1. | INTEL 8086+
REPNZ | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1. | INTEL 8086+
REPZ | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0. | INTEL 8086+
SCAS | Cette instruction permet de comparer un octet, un mot ou un double mot avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | INTEL 8086+
SCASB | Cette instruction permet de comparer le registre AL avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction. | INTEL 8086+
SCASD | Cette instruction permet de comparer le registre EAX avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
SCASW | Cette instruction permet de comparer le registre AX avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction. | INTEL 8086+
STOS | Cette instruction permet de copier un octet, un mot ou un double mot dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | INTEL 8086+
STOSB | Cette instruction permet de copier le registre AL dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction. | INTEL 8086+
STOSD | Cette instruction permet de copier le registre EAX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
STOSW | Cette instruction permet de copier le registre AX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction. | INTEL 8086+

Dernière mise à jour : Vendredi, le 4 mars 2016


Assembleur 80x86

LODS
INTEL 8088+ LOaD String

Syntaxe

LODS chainesource

Description

Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction.

Algorithme

SI (charge un octet) ALORS
AL ← chainesource
SI DF = 0 ALORS
(E)SI ← (E)SI + 1
SINON
(E)SI ← (E)SI - 1
FIN SI
SINON SI (charge un mot) ALORS
AX ← chainesource
SI DF = 0 ALORS
(E)SI ← (E)SI + 2
SINON
(E)SI ← (E)SI - 2
FIN SI
SINON SI (charge un double mot) ALORS
EAX ← chainesource
SI DF = 0 ALORS
(E)SI ← (E)SI + 4
SINON
(E)SI ← (E)SI - 4
FIN SI
SINON
RAX ← chainesource
SI DF = 0 ALORS
(E)SI ← (E)SI + 8
SINON
(E)SI ← (E)SI - 8
FIN SI
FIN SI

Mnémonique

Instruction | Opcode | Description
LODS mem8 | ACh | Charge l'octet de DS:(R)SI dans AL et incrémente ou décrément (R)SI.
LODS mem16 | ADh | Charge le mot de DS:(R)SI dans AX et incrémente ou décrément (R)SI.
LODS mem32 | ADh | Charge le double mot de DS:(R)SI dans EAX et incrémente ou décrément (R)SI.
LODS mem64 | ADh | Charge le quadruple mot de DS:(R)SI dans RAX et incrémente ou décrément (R)SI.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction MOVS
Instruction assembleur 80x86 - Instruction STOS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 818
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 149.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 664 à 667.


Assembleur 80x86

LODSB
INTEL 8088+ LOad String Byte

Syntaxe

LODSB

Description

Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction.

Algorithme

AL ← chainesource
SI DF = 0 ALORS
(E)SI ← (E)SI + 1
SINON
(E)SI ← (E)SI - 1
FIN SI

Mnémonique

Instruction | Opcode | Description
LODSB | ACh | Charge l'octet de DS:(R)SI dans AL et incrémente ou décrément (R)SI.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction MOVS
Instruction assembleur 80x86 - Instruction STOS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 818
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 410
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 149.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 664 à 667.


Assembleur 80x86

LODSD
INTEL 80386+ LOaD String Double word

Syntaxe

LODSD

Description

Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 4 en fonction de l'état du drapeau de direction.

Algorithme

EAX ← chainesource
SI DF = 0 ALORS
(E)SI ← (E)SI + 4
SINON
(E)SI ← (E)SI - 4
FIN SI

Mnémonique

Instruction | Opcode | Description
LODSD | ADh | Charge le double mot de DS:(R)SI dans EAX et incrémente ou décrément (R)SI.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction MOVS
Instruction assembleur 80x86 - Instruction STOS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 818
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 149.


Assembleur 80x86

LODSW
INTEL 8088+ LOaD String Word

Syntaxe

LODSW

Description

Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 2 en fonction de l'état du drapeau de direction.

Algorithme

AX ← chainesource
SI DF = 0 ALORS
(E)SI ← (E)SI + 2
SINON
(E)SI ← (E)SI - 2
FIN SI

Mnémonique

Instruction | Opcode | Description
LODSW | ADh | Charge le mot de DS:(R)SI dans AX et incrémente ou décrément (R)SI.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction MOVS
Instruction assembleur 80x86 - Instruction STOS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 819
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 410
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 149.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 664 à 667.


Assembleur 80x86

MOVS
INTEL 8088+ MOVe String

Syntaxe

MOVS opérandecible,opérandesource

Description

Cette instruction permet de copier un élément de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction.

Algorithme

opérandecible ← opérandesource
SI opérande est un octet ALORS
SI DF = 0 ALORS
(E)SI ← (E)SI + 1
(E)DI ← (E)DI + 1
SINON
(E)SI ← (E)SI - 1
(E)DI ← (E)DI - 1
FIN SI
SINON SI opérande est un mot ALORS
SI DF = 0 ALORS
(E)SI ← (E)SI + 2
(E)DI ← (E)DI + 2
SINON
(E)SI ← (E)SI - 2
(E)DI ← (E)DI - 2
FIN SI
SINON SI opérande est un double mot ALORS
SI DF = 0 ALORS
(E)SI ← (E)SI + 4
(E)DI ← (E)DI + 4
SINON
(E)SI ← (E)SI - 4
(E)DI ← (E)DI - 4
FIN SI
SINON
SI DF = 0 ALORS
(E)SI ← (E)SI + 8
(E)DI ← (E)DI + 8
SINON
(E)SI ← (E)SI - 8
(E)DI ← (E)DI - 8
FIN SI
FIN SI

Mnémonique

Instruction | Opcode | Description
MOVS mem8, mem8 | A4h | Copie l'octet de DS:(R)SI à ES:(R)DI, et alors incrémente ou décrément le registre (R)SI et (R)DI.
MOVS mem16, mem16 | A5h | Copie le mot de DS:(R)SI à ES:(R)DI, et alors incrémente ou décrément le registre (R)SI et (R)DI.
MOVS mem32, mem32 | A5h | Copie le double mot de DS:(R)SI à ES:(R)DI, et alors incrémente ou décrément le registre (R)SI et (R)DI.
MOVS mem64, mem64 | A5h | Copie le double mot de DS:(R)SI à ES:(R)DI, et alors incrémente ou décrément le registre (R)SI et (R)DI.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction MOV
Instruction assembleur 80x86 - Instruction LODS
Instruction assembleur 80x86 - Instruction STOS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 821
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 411
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 168.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 792 à 796.


Assembleur 80x86

MOVSB
INTEL 8088+ MOVe String Byte

Syntaxe

MOVSB

Description

Cette instruction permet de copier un octet de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 1 en fonction de l'état du drapeau de direction.

Algorithme

opérandecible ← opérandesource
SI DF = 0 ALORS
(E)SI ← (E)SI + 1
(E)DI ← (E)DI + 1
SINON
(E)SI ← (E)SI - 1
(E)DI ← (E)DI - 1
FIN SI

Mnémonique

Instruction | Opcode | Description
MOVSB | A4h | Copie l'octet de DS:(R)SI à ES:(R)DI, et alors incrémente ou décrément le registre (R)SI et (R)DI.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction MOV
Instruction assembleur 80x86 - Instruction LODS
Instruction assembleur 80x86 - Instruction STOS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 821
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 168.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 792 à 796.


Assembleur 80x86

MOVSD
INTEL 80386+ MOVe String Double word

Syntaxe

MOVSD

Description

Cette instruction permet de copier un double mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 4 en fonction de l'état du drapeau de direction.

Algorithme

opérandecible ← opérandesource
SI DF = 0 ALORS
(E)SI ← (E)SI + 4
(E)DI ← (E)DI + 4
SINON
(E)SI ← (E)SI - 4
(E)DI ← (E)DI - 4
FIN SI

Mnémonique

Instruction | Opcode | Description
MOVSD | A5h | Copie le double mot de DS:(R)SI à ES:(R)DI, et alors incrémente ou décrément le registre (R)SI et (R)DI.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction MOV
Instruction assembleur 80x86 - Instruction LODS
Instruction assembleur 80x86 - Instruction STOS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 822
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 168.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 792 à 796.


Assembleur 80x86

MOVSW
INTEL 8088+ MOV String Word

Syntaxe

MOVSW

Description

Cette instruction permet de copier un mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 2 en fonction de l'état du drapeau de direction.

Algorithme

opérandecible ← opérandesource
SI DF = 0 ALORS
(E)SI ← (E)SI + 2
(E)DI ← (E)DI + 2
SINON
(E)SI ← (E)SI - 2
(E)DI ← (E)DI - 2
FIN SI

Mnémonique

Instruction | Opcode | Description
MOVSW | A5h | Copie le mot de DS:(R)SI à ES:(R)DI, et alors incrémente ou décrément le registre (R)SI et (R)DI.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction MOV
Instruction assembleur 80x86 - Instruction LODS
Instruction assembleur 80x86 - Instruction STOS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 822
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 168.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 792 à 796.


Assembleur 80x86

OUTS
INTEL 80286+ Output String

Syntaxe

OUTS opérandesource

Description

Cette instruction permet d'envoyer un octet, un mot ou un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction.

Algorithme

SI ((PE = 1) ET ((CPL > IOPL) ET (VM = 1))) ALORS * Mode protégé avec CPL > IOPL ou mode virtuel 8086
SI (n'importe quel permission de bit d'E/S pour un port d'E/S à un accès = 1) ALORS
EXCEPTION #GP(0)
SINON
Port(adresse) ← accumulateur
FIN SI
SINON
Port(adresse) ← accumulateur
FIN SI
SI (taille de l'opérande_cible = octet) ALORS
SI DF = 0 ALORS
(E)DI ← (E)DI + 1
SINON
(E)DI ← (E)DI - 1
FIN SI
SINON SI (taille de l'opérande_cible = mot) ALORS
SI DF = 0 ALORS
(E)DI ← (E)DI + 2
SINON
(E)DI ← (E)DI - 2
FIN SI
SINON
SI DF = 0 ALORS
(E)DI ← (E)DI + 4
SINON
(E)DI ← (E)DI - 4
FIN SI
FIN SI

Mnémonique

Instruction | Opcode | Description
OUTS DX, mem8 | 6Eh | Envoi un octet de l'adresse DS:(R)SI au port spécifié par DX et ensuite, incrémente ou décrémente le registre (R)SI.
OUTS DX, mem16 | 6Fh | Envoi un mot de l'adresse DS:(R)SI au port spécifié par DX et ensuite, incrémente ou décrémente le registre (R)SI.
OUTS DX, mem32 | 6Fh | Envoi un double mot de l'adresse DS:(R)SI au port spécifié par DX et ensuite, incrémente ou décrémente le registre (R)SI.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Sélecteur) | X | X | X | Un registre de segment est chargé, mais le descripteur de segment dépasse la limite de la table du descripteur.
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
 |  | X |  | Un ou plusieurs bits de permission d'entrée/sortie sont fixer par le TSS pour un accès au port.
 |  |  | X | Le CPL est plus grand que le IOPL et une ou plusieurs bits de permission sont fixer par le TSS pour un accès au port.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Référence des ports d'entrée/sortie 80x86
Instruction assembleur 80x86 - Instruction OUT
Instruction assembleur 80x86 - Instruction IN
Instruction assembleur 80x86 - Instruction INS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 824
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 182.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 27 à 31.


Assembleur 80x86

OUTSB
INTEL 80286+ Output String Byte

Syntaxe

OUTSB

Description

Cette instruction permet d'envoyer un octet contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 1 en fonction de l'état du drapeau de direction.

Algorithme

SI ((PE = 1) ET ((CPL > IOPL) ET (VM = 1))) ALORS * Mode protégé avec CPL > IOPL ou mode virtual 8086
SI (n'importe quel permission de bit d'E/S pour un port d'E/S à un accès = 1) ALORS
EXCEPTION #GP(0)
SINON
Port(adresse) ← accumulateur
FIN SI
SINON
Port(adresse) ← accumulateur
FIN SI
SI DF = 0 ALORS
(E)DI ← (E)DI + 1
SINON
(E)DI ← (E)DI - 1
FIN SI

Mnémonique

Instruction | Opcode | Description
OUTSB | 6Eh | Envoi un octet de l'adresse DS:(R)SI au port spécifié par DX et ensuite, incrémente ou décrémente le registre (R)SI.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Sélecteur) | X | X | X | Un registre de segment est chargé, mais le descripteur de segment dépasse la limite de la table du descripteur.
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
 |  | X |  | Un ou plusieurs bits de permission d'entrée/sortie sont fixer par le TSS pour un accès au port.
 |  |  | X | Le CPL est plus grand que le IOPL et une ou plusieurs bits de permission sont fixer par le TSS pour un accès au port.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Référence des ports d'entrée/sortie 80x86
Instruction assembleur 80x86 - Instruction OUT
Instruction assembleur 80x86 - Instruction IN
Instruction assembleur 80x86 - Instruction INS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 825
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 182.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 27 à 31.


Assembleur 80x86

OUTSD
INTEL 80386+ Output String Double word

Syntaxe

OUTSD

Description

Cette instruction permet d'envoyer un double mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 4 en fonction de l'état du drapeau de direction.

Algorithme

SI ((PE = 1) ET ((CPL > IOPL) ET (VM = 1))) ALORS * Mode protégé avec CPL > IOPL ou mode virtuel 8086
SI (n'importe quel permission de bit d'E/S pour un port d'E/S à un accès = 1) ALORS
EXCEPTION #GP(0)
SINON
Port(adresse) ← accumulateur
FIN SI
SINON
Port(adresse) ← accumulateur
FIN SI
SI DF = 0 ALORS
(E)DI ← (E)DI + 4
SINON
(E)DI ← (E)DI - 4
FIN SI

Mnémonique

Instruction | Opcode | Description
OUTSD | 6Fh | Envoi un double mot de l'adresse DS:(R)SI au port spécifié par DX et ensuite, incrémente ou décrémente le registre (R)SI.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Sélecteur) | X | X | X | Un registre de segment est chargé, mais le descripteur de segment dépasse la limite de la table du descripteur.
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
 |  | X |  | Un ou plusieurs bits de permission d'entrée/sortie sont fixer par le TSS pour un accès au port.
 |  |  | X | Le CPL est plus grand que le IOPL et une ou plusieurs bits de permission sont fixer par le TSS pour un accès au port.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Référence des ports d'entrée/sortie 80x86
Instruction assembleur 80x86 - Instruction OUT
Instruction assembleur 80x86 - Instruction IN
Instruction assembleur 80x86 - Instruction INS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 825
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 182.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 27 à 31.


Assembleur 80x86

OUTSW
INTEL 80286+ Output String Word

Syntaxe

OUTSW

Description

Cette instruction permet d'envoyer un mot contenu dans l'adresse DS:[SI] du port d'entrée/sortie et incrémente/décrémente le registre SI de 2 en fonction de l'état du drapeau de direction.

Algorithme

SI ((PE = 1) ET ((CPL > IOPL) ET (VM = 1))) ALORS * Mode protégé avec CPL > IOPL ou mode virtuel 8086
SI (n'importe quel permission de bit d'E/S pour un port d'E/S à un accès = 1) ALORS
EXCEPTION #GP(0)
SINON
Port(adresse) ← accumulateur
FIN SI
SINON
Port(adresse) ← accumulateur
FIN SI
SI DF = 0 ALORS
(E)DI ← (E)DI + 2
SINON
(E)DI ← (E)DI - 2
FIN SI

Mnémonique

Instruction | Opcode | Description
OUTSW | 6Fh | Envoi un mot de l'adresse DS:(R)SI au port spécifié par DX et ensuite, incrémente ou décrémente le registre (R)SI.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Sélecteur) | X | X | X | Un registre de segment est chargé, mais le descripteur de segment dépasse la limite de la table du descripteur.
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
 |  | X |  | Un ou plusieurs bits de permission d'entrée/sortie sont fixer par le TSS pour un accès au port.
 |  |  | X | Le CPL est plus grand que le IOPL et une ou plusieurs bits de permission sont fixer par le TSS pour un accès au port.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Référence des ports d'entrée/sortie 80x86
Instruction assembleur 80x86 - Instruction OUT
Instruction assembleur 80x86 - Instruction IN
Instruction assembleur 80x86 - Instruction INS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 825
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 182.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 27 à 31.


Assembleur 80x86

REP
INTEL 8088+ Repeat String Prefix

Syntaxe

REP chaine_d'instruction_paramètre

Description

Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions tant que CX ne vaut pas 0.

Algorithme

SI OpCode est [ INS, INSB, INSD, INSW, LODS, LODSB, LODSD, LODSQ, LODSW, MOVS, MOVSB, MOVSD, MOVSQ, MOVSW, OUTS, OUTSB, OUTSD, OUTSW, STOS, STOSB, STOSD, STOSQ, STOSW ] ALORS
FAIRE TANT QUE CX <> 0
Exécute instruction_paramètre
CX ← CX - 1
FIN DE FAIRE
FIN SI
SI OpCode est [ CMPS, CMPSB, CMPSD, CMPSQ, CMPSW, SCAS, SCASB, SCASD, SCASW ] ALORS
FAIRE TANT QUE CX <> 0
Exécute instruction_paramètre
CX ← CX - 1
SI ZF = 0 ALORS Fin de boucle
FIN DE FAIRE
FIN SI

Mnémonique

Instruction | Opcode | Description
REP autreinstruction | F3h autreinstruction | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions tant que CX ne vaut pas 0.

Exemple

Voici un exemple en Turbo Pascal 7 montrant une utilisation de cette instruction :

  1. Program AsmRepSamples;
  3. Const
  4. X: Array [0..10]of Byte =(0,1,2,3,4,5,6,7,8,9,10);
  6. Var
  7. I: Byte ;
  9. Procedure MoveRight( Const Source; Var Dest;Count: Word );Assembler; ASM
  10. STD
  11. PUSH DS
  12. LDS SI,Source
  13. LES DI,Dest
  14. MOV CX,Count
  15. ADD SI,CX
  16. DEC SI
  17. ADD DI,CX
  18. DEC DI
  19. REP MOVSB
  20. POP DS
  21. END;
  23. BEGIN
  24. MoveRight(X[3],X[5],5);
  25. For I:=0 to 10 do Begin
  26. Write (X[I],',');
  27. End ;
  28. WriteLn ;
  29. END .

on obtiendra le résultat suivant :

0,1,2,3,4,3,4,5,6,7,10,

Références

Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 413
Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 828
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 361 à 365.


Assembleur 80x86

REPE
INTEL 8088+ Repeat equal

Syntaxe

REPE chaine_d'instruction_paramètre

Description

Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0.

Algorithme

SI OpCode est [ INS, INSB, INSD, INSW, LODS, LODSB, LODSD, LODSQ, LODSW, MOVS, MOVSB, MOVSD, MOVSQ, MOVSW, OUTS, OUTSB, OUTSD, OUTSW, STOS, STOSB, STOSD, STOSQ, STOSW ] ALORS
FAIRE TANT QUE CX ≠ 0 OU ZF ≠ 0
Exécute instruction_paramètre
CX ← CX - 1
FIN DE FAIRE
FIN SI
SI OpCode est [ CMPS, CMPSB, CMPSD, CMPSQ, CMPSW, SCAS, SCASB, SCASD, SCASW ] ALORS
FAIRE TANT QUE CX ≠ 0 OU ZF ≠ 0
Exécute instruction_paramètre
CX ← CX - 1
SI ZF = 0 ALORS Fin de boucle
FIN DE FAIRE
FIN SI

Mnémonique

Instruction | Opcode | Description
REPE autreinstruction | F3h autreinstruction | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0.

Exemple

Voici un exemple, en Turbo Pascal, permettant d'effectuer la comparaison de chaine de caractères à l'aide de l'instruction «REPE» :

  1. Program RepeSamples;
  3. Const
  4. X: String ='ABC';
  5. Y: String ='ABC';
  6. Z: String ='DEF';
  8. Function Compare( Const Source,Dest;Len: Word ): Boolean ;Assembler; ASM
  9. MOV CX,Len
  10. JCXZ @0
  11. PUSH DS
  12. LDS SI,Source
  13. LES DI,Dest
  14. CLD
  15. REPE CMPSB
  16. POP DS
  17. JZ @0
  18. MOV CL,1
  19. @0:
  20. XCHG AX,CX
  21. XOR AL,1
  22. END;
  24. BEGIN
  25. WriteLn (Compare(X,Y,4));
  26. WriteLn (Compare(X,Z,4));
  27. END .

on obtiendra le résultat suivant :

TRUE
FLASE

Voir également

Instruction assembleur 80x86 - Instruction REPZ

Références

Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 414
Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 828
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 361 à 365.


Assembleur 80x86

REPNE
INTEL 8088+ Repeat Not Equal

Syntaxe

REPNE chaine_d'instruction_paramètre

Description

Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1.

Algorithme

SI OpCode est [ INS, INSB, INSD, INSW, LODS, LODSB, LODSD, LODSQ, LODSW, MOVS, MOVSB, MOVSD, MOVSQ, MOVSW, OUTS, OUTSB, OUTSD, OUTSW, STOS, STOSB, STOSD, STOSQ, STOSW ] ALORS
FAIRE TANT QUE CX ≠ 0 OU ZF ≠ 1
Exécute instruction_paramètre
CX ← CX - 1
FIN DE FAIRE
FIN SI
SI OpCode est [ CMPS, CMPSB, CMPSD, CMPSQ, CMPSW, SCAS, SCASB, SCASD, SCASW ] ALORS
FAIRE TANT QUE CX ≠ 0 OU ZF ≠ 1
Exécute instruction_paramètre
CX ← CX - 1
SI ZF = 0 ALORS Fin de boucle
FIN DE FAIRE
FIN SI

Mnémonique

Instruction | Opcode | Description
REPNE autreinstruction | F2h autreinstruction | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 1.

Références

Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 414
Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 829
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 361 à 365.


Assembleur 80x86

REPZ
INTEL 8088+ Repeat Zero

Syntaxe

REPZ chaine_d'instruction_paramètre

Description

Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0.

Algorithme

SI OpCode est [ INS, INSB, INSD, INSW, LODS, LODSB, LODSD, LODSQ, LODSW, MOVS, MOVSB, MOVSD, MOVSQ, MOVSW, OUTS, OUTSB, OUTSD, OUTSW, STOS, STOSB, STOSD, STOSQ, STOSW ] ALORS
FAIRE TANT QUE CX ≠ 0 OU ZF ≠ 0
Exécute instruction_paramètre
CX ← CX - 1
FIN DE FAIRE
FIN SI
SI OpCode est [ CMPS, CMPSB, CMPSD, CMPSQ, CMPSW, SCAS, SCASB, SCASD, SCASW ] ALORS
FAIRE TANT QUE CX ≠ 0 OU ZF ≠ 0
Exécute instruction_paramètre
CX ← CX - 1
SI ZF = 0 ALORS Fin de boucle
FIN DE FAIRE
FIN SI

Mnémonique

Instruction | Opcode | Description
REPZ autreinstruction | F3h autreinstruction | Cette instruction est utilisé comme préfixe avec d'autres instructions pour effectuer des répétitions d'instructions jusqu'à ce que CX = 0 ou tant que l'indicateur ZF = 0.

Références

Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 414
Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 829
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 361 à 365.


Assembleur 80x86

SCAS
INTEL 8088+ Scan String

Syntaxe

SCAS chainecible

Description

Cette instruction permet de comparer un octet, un mot ou un double mot avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction.

Algorithme

SI chainecible est un octet ALORS
temp ← AL - chainecible
SetStatusFlags(temp)
SI DF = 0 ALORS
(E)DI ← (E)DI + 1
SINON
(E)DI ← (E)DI - 1
FIN SI
SINON SI chainecible est un mot ALORS
temp ← AX - chainecible
SetStatusFlags(temp)
SI DF = 0 ALORS
(E)DI ← (E)DI + 2
SINON
(E)DI ← (E)DI - 2
FIN SI
SINON SI chainecible est un double mot ALORS
temp ← EAX - chainecible
SetStatusFlags(temp)
SI DF = 0 ALORS
(E)DI ← (E)DI + 4
SINON
(E)DI ← (E)DI - 4
FIN SI
SINON
temp ← EAX - chainecible
SetStatusFlags(temp)
SI DF = 0 ALORS
(E)DI ← (E)DI + 8
SINON
(E)DI ← (E)DI - 8
FIN SI
FIN SI

Mnémonique

Instruction | Opcode | Description
SCAS mem8 | AEh | Compare le contenu d'un registre AL avec l'octet ES:(R)DI et incrémente ou décrémente R(DI).
SCAS mem16 | AFh | Compare le contenu d'un registre AX avec le mot ES:(R)DI et incrémente ou décrémente R(DI).
SCAS mem32 | AFh | Compare le contenu d'un registre EAX avec le double mot ES:(R)DI et incrémente ou décrémente R(DI).
SCAS mem64 | AFh | Compare le contenu d'un registre RAX avec le double mot ES:(R)DI et incrémente ou décrémente R(DI).

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment ES ou n'est pas canonique
 |  |  | X | Un segment ES nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction CMP
Instruction assembleur 80x86 - Instruction CMPS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 832
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 223.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 413 à 417.


Assembleur 80x86

SCASB
INTEL 8088+ Scan String Byte

Syntaxe

SCASB

Description

Cette instruction permet de comparer le registre AL avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction.

Algorithme

temp ← AL - chainecible
SetStatusFlags(temp)
SI DF = 0 ALORS
(E)DI ← (E)DI + 1
SINON
(E)DI ← (E)DI - 1
FIN SI

Mnémonique

Instruction | Opcode | Description
SCASB | AEh | Compare le contenu d'un registre AL avec l'octet ES:(R)DI et incrémente ou décrémente R(DI).

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment ES ou n'est pas canonique
 |  |  | X | Un segment ES nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 833
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 416
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 223.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 413 à 417.


Assembleur 80x86

SCASD
INTEL 80386+ Scan String Doubleword

Syntaxe

SCASD

Description

Cette instruction permet de comparer le registre EAX avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction.

Algorithme

temp ← EAX - chainecible
SetStatusFlags(temp)
SI DF = 0 ALORS
(E)DI ← (E)DI + 4
SINON
(E)DI ← (E)DI - 4
FIN SI

Mnémonique

Instruction | Opcode | Description
SCASD | AFh | Compare le contenu d'un registre EAX avec le double mot ES:(R)DI et incrémente ou décrémente R(DI).

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment ES ou n'est pas canonique
 |  |  | X | Un segment ES nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 833
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 223.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 413 à 417.


Assembleur 80x86

SCASW
INTEL 8088+ Scan String Word

Syntaxe

SCASW

Description

Cette instruction permet de comparer le registre AX avec la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction.

Algorithme

temp ← AX - chainecible
SetStatusFlags(temp)
SI DF = 0 ALORS
(E)DI ← (E)DI + 2
SINON
(E)DI ← (E)DI - 2
FIN SI

Mnémonique

Instruction | Opcode | Description
SCASW | AFh | Compare le contenu d'un registre AX avec le mot ES:(R)DI et incrémente ou décrémente R(DI).

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment ES ou n'est pas canonique
 |  |  | X | Un segment ES nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 834
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 417
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 223.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 413 à 417.


Assembleur 80x86

STOS
INTEL 8088+ Store String Data

Syntaxe

STOS chainecible

Description

Cette instruction permet de copier un octet, un mot ou un double mot dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction.

Algorithme

SI chainecible est octet ALORS
chainecible ← AL
SI DF = 0 ALORS
(E)DI ← (E)DI + 1
SINON
(E)DI ← (E)DI - 1
FIN SI
SINON SI chainecible est un mot ALORS
chainecible ← AX
SI DF = 0 ALORS
(E)DI ← (E)DI + 2
SINON
(E)DI ← (E)DI - 2
FIN SI
SINON SI chainecible est un double mot ALORS
chainecible ← EAX
SI DF = 0 ALORS
(E)DI ← (E)DI + 4
SINON
(E)DI ← (E)DI - 4
FIN SI
SINON
chainecible ← RAX
SI DF = 0 ALORS
(E)DI ← (E)DI + 8
SINON
(E)DI ← (E)DI - 8
FIN SI
FIN SI

Mnémonique

Instruction | Opcode | Description
STOS mem8 | AAh | Entrepose le contenu du registre AL dans ES:(R)DI et incrémente ou décrémente (R)DI.
STOS mem16 | ABh | Entrepose le contenu du registre AX dans ES:(R)DI et incrémente ou décrémente (R)DI.
STOS mem32 | ABh | Entrepose le contenu du registre EAX dans ES:(R)DI et incrémente ou décrémente (R)DI.
STOS mem64 | ABh | Entrepose le contenu du registre RAX dans ES:(R)DI et incrémente ou décrémente (R)DI.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment ES ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment ES non écrivable
 |  |  | X | Un segment ES nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction LODS
Instruction assembleur 80x86 - Instruction MOVS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 837
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 237.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 468 à 472.


Assembleur 80x86

STOSB
INTEL 8088+ Store String Byte

Syntaxe

STOSB

Description

Cette instruction permet de copier le registre AL dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction.

Algorithme

chainecible ← AL
SI DF = 0 ALORS
(E)DI ← (E)DI + 1
SINON
(E)DI ← (E)DI - 1
FIN SI

Mnémonique

Instruction | Opcode | Description
STOSB | AAh | Entrepose le contenu du registre AL dans ES:(R)DI et incrémente ou décrémente (R)DI.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment ES ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment ES non écrivable
 |  |  | X | Un segment ES nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemples

Cet exemple suivant, destiné au 8088 mais peu performante, permet de remplir avec la valeur de la variable «Valeur» un tampon d'octets spécifié par la variable «Tampon» de la longueur spécifié par la variable «Longueur» avec une cadence de 8 bits à la fois :

  1. CLD
  2. LES DI,Tampon
  3. MOV CX,Longueur
  4. MOV AL,Valeur
  5. REP STOSB

Cet exemple suivant, destiné au 8086 et très performante, permet de remplir avec la valeur de la variable «Valeur» un tampon d'octets spécifié par la variable «Tampon» de la longueur spécifié par la variable «Longueur» avec une cadence de 16 bits à la fois :

  1. CLD
  2. LES DI,Tampon
  3. MOV CX,Longueur
  4. MOV AL,Valeur
  5. MOV AH,AL
  6. SHR CX,1
  7. REP STOSW
  8. ADC CX,CX
  9. REP STOSB

Cet exemple suivant, destiné au 80386 ou plus, permet de remplir avec la valeur de la variable «Valeur» un tampon d'octets spécifié par la variable «Tampon» de la longueur spécifié par la variable «Longueur» avec une cadence de 32 bits à la fois :

  1. CLD
  2. LES DI,Tampon
  3. MOV CX,Longueur
  4. MOV AL,Valeur
  5. MOV AH,AL
  6. ; EAX := AX:AX
  7. PUSH AX
  8. PUSH AX
  9. POP EAX
  10. MOV BX,CX
  11. AND BX,3
  12. SHR CX,2
  13. REP STOSD
  14. MOV CX,BX
  15. REP STOSB

Voir également

Instruction assembleur 80x86 - Instruction STOSD
Instruction assembleur 80x86 - Instruction STOSQ
Instruction assembleur 80x86 - Instruction STOSW

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 837
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 418
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 237.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 468 à 472.


Assembleur 80x86

STOSD
INTEL 80386+ Store String Doubleword

Syntaxe

STOSD

Description

Cette instruction permet de copier le registre EAX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction.

Algorithme

chainecible ← EAX
SI DF = 0 ALORS
(E)DI ← (E)DI + 4
SINON
(E)DI ← (E)DI - 4
FIN SI

Mnémonique

Instruction | Opcode | Description
STOSD | ABh | Entrepose le contenu du registre EAX dans ES:(R)DI et incrémente ou décrémente (R)DI.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment ES ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment ES non écrivable
 |  |  | X | Un segment ES nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 837
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 237.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 468 à 472.


Assembleur 80x86

STOSW
INTEL 8088+ Store String Word

Syntaxe

STOSW

Description

Cette instruction permet de copier le registre AX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction.

Algorithme

chainecible ← AX
SI DF = 0 ALORS
(E)DI ← (E)DI + 2
SINON
(E)DI ← (E)DI - 2
FIN SI

Mnémonique

Instruction | Opcode | Description
STOSW | ABh | Entrepose le contenu du registre AX dans ES:(R)DI et incrémente ou décrémente (R)DI.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment ES ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment ES non écrivable
 |  |  | X | Un segment ES nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

L'exemple suivant, s'adressant au mode réel sous un système d'exploitation DOS, permet d'entreposer dans des pointeurs de variables le contenu de la date :

  1. MOV AH,2Ah
  2. INT 21h
  3. CLD
  4. LES DI,DayOfWeek
  5. STOSB
  6. MOV AL,DL
  7. LES DI,Day
  8. STOSB
  9. MOV AL,DH
  10. LES DI,Month
  11. STOSB
  12. XCHG AX,CX
  13. LES DI,Year
  14. STOSW

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 838
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 418
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 237.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 468 à 472.


Voici les instructions assembleur classés par catégorie de comparaison :

Instruction | Description | CPU/MPU
CMP | Cette instruction offre la possibilité essentielle de comparer 2 registres ou emplacements de mémoire. | INTEL 8088+
CMPXCHG | Cette instruction compare la destination avec l'accumulateur (AL, AX ou EAX) et les échanges si la condition est vrai. | INTEL Pentium
CMPXCHG8B | Cette instruction compare un nombre de 64 bits et les échanges si la condition est vrai. | INTEL Pentium
TEST | Cette instruction permet d'effectuer un «Et binaire» sur une opérande cible sans modifier sa valeur. | INTEL 8088+

Dernière mise à jour : Vendredi, le 4 mars 2016


Assembleur 80x86

CMP
INTEL 8088+ Compare two operands

Syntaxe

CMP Opérande Cible, Opérande Source

Paramètres

Nom | Description
Opérande Cible | Ce paramètre permet d'indiquer l'opérande de base sur lequel l'opération de comparaison est effectuée.
Opérande Source | Ce paramètre permet d'indiquer l'opérande supplémentaire avec laquelle la comparaison est effectué

Description

Cette instruction offre la possibilité essentielle de comparer 2 registres ou emplacements de mémoire. Le résultat de la comparaison est indiqué par les indicateurs (registre drapeau du microprocesseur).

Algorithme

Drapeau ← opérande1 = opérande2

Mnémonique

Instruction | Opcode | Description
CMP AL, imm8 | 3Ch ib | Compare une valeur 8 bits immédiate avec le contenu du registre AL.
CMP AX, imm16 | 3Dh iw | Compare une valeur 16 bits immédiate avec le contenu du registre AX.
CMP EAX, imm32 | 3Dh iw | Compare une valeur 32 bits immédiate avec le contenu du registre EAX.
CMP RAX, imm32 | 3Dh id | Compare une valeur 32 bits immédiate avec le contenu du registre RAX.
CMP reg/mem8, imm8 | 80h /7 ib | Compare une valeur 8 bits immédiate avec le contenu d'une opérande mémoire ou d'un registre 8 bits.
CMP reg/mem16, imm16 | 81h /7 iw | Compare une valeur 16 bits immédiate avec le contenu d'une opérande mémoire ou d'un registre 16 bits.
CMP reg/mem32, imm32 | 81h /7 id | Compare une valeur 32 bits immédiate avec le contenu d'une opérande mémoire ou d'un registre 32 bits.
CMP reg/mem64, imm32 | 81h /7 id | Compare une valeur 32 bits immédiate avec le contenu d'une opérande mémoire ou d'un registre 64 bits.
CMP reg/mem16, imm8 | 83h /7 ib | Compare une valeur 8 bits immédiate avec le contenu d'une opérande mémoire ou d'un registre 16 bits.
CMP reg/mem32, imm8 | 83h /7 ib | Compare une valeur 8 bits immédiate avec le contenu d'une opérande mémoire ou d'un registre 32 bits.
CMP reg/mem64, imm8 | 83h /7 ib | Compare une valeur 8 bits immédiate avec le contenu d'une opérande mémoire ou d'un registre 64 bits.
CMP reg/mem8, reg8 | 38h /r | Compare le contenu d'une opérande mémoire ou d'un registre 8 bits avec un registre 8 bits.
CMP reg/mem16, reg16 | 39h /r | Compare le contenu d'une opérande mémoire ou d'un registre 16 bits avec un registre 16 bits.
CMP reg/mem32, reg32 | 39h /r | Compare le contenu d'une opérande mémoire ou d'un registre 32 bits avec un registre 32 bits.
CMP reg/mem64, reg64 | 39h /r | Compare le contenu d'une opérande mémoire ou d'un registre 64 bits avec un registre 64 bits.
CMP reg8, reg/mem8 | 39h /r | Compare le contenu d'une opérande mémoire ou d'un registre 8 bits avec un registre 8 bits.
CMP reg16, reg/mem16 | 3Bh /r | Compare le contenu d'une opérande mémoire ou d'un registre 16 bits avec un registre 16 bits.
CMP reg32, reg/mem32 | 3Bh /r | Compare le contenu d'une opérande mémoire ou d'un registre 32 bits avec un registre 32 bits.
CMP reg64, reg/mem64 | 3Bh /r | Compare le contenu d'une opérande mémoire ou d'un registre 64 bits avec un registre 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

L'exemple suivant permet de retourner 1 si le caractère spécifié par la variable «Chr» est une lettre de l'alphabet (majuscule ou minucule) ou 0 s'il ne l'est pas :

  1. XOR AL,AL
  2. MOV CL,Chr
  3. AND CL,0DFh
  4. CMP CL,'A'
  5. JB @1
  6. CMP CL,'Z'
  7. JA @1
  8. INC AL
  9. @1:

Voir également

Instruction assembleur 80x86 - Instruction SUB
Instruction assembleur 80x86 - Instruction CMPS
Instruction assembleur 80x86 - Instruction SCAS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 808
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 403
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 94 à 96.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 206 à 208.


Assembleur 80x86

CMPXCHG
INTEL 80486+ CoMPare and eXCHanGe

Syntaxe

CMPXCHG Opérande Destination, Opérande Source

Description

A l'aide de l'instruction CMPXCHG, on peut comparer la destination avec l'accumulateur (AL, AX ou EAX). S'ils sont égaux, l'opérande de destination reçoit le contenu de l'opérande source, tandis que s'ils sont différents, l'accumulation (AL, AX ou EAX) reçoit le contenu de l'opérande de destination.

Algorithme

SI accumulateur = Opérande Destination ALORS
drapeau ZF ← 1
Opérande Destination ← Opérande Source
SINON
drapeau ZF ← 0
accumulateur ← Opérande Destination
FIN SI

Mnémonique

Instruction | Opcode | Description
CMPXCHG reg/mem8, reg8 | 0Fh B0h /r | Compare de registre AL avec un emplacement 8 bits de registre ou mémoire. S'ils sont égale, le deuxième opérande est copié dans le première opérande.
CMPXCHG reg/mem16, reg16 | 0Fh B1h /r | Compare de registre AX avec un emplacement 16 bits de registre ou mémoire. S'ils sont égale, le deuxième opérande est copié dans le première opérande.
CMPXCHG reg/mem32, reg32 | 0Fh B1h /r | Compare de registre EAX avec un emplacement 32 bits de registre ou mémoire. S'ils sont égale, le deuxième opérande est copié dans le première opérande.
CMPXCHG reg/mem64, reg64 | 0Fh B1h /r | Compare de registre RAX avec un emplacement 64 bits de registre ou mémoire. S'ils sont égale, le deuxième opérande est copié dans le première opérande.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction CMPXCHG8B
Instruction assembleur 80x86 - Instruction CMPXCHG16B

Références

Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 233 à 235.


Assembleur 80x86

CMPXCHG8B
INTEL Pentium CoMPare and eXCHanGe 8 Bytes

Syntaxe

CMPXCHG8B registre, mémoire

Description

L'instruction CMPXCHG8B compare un nombre de 64 bits formée par le couple registre de EDX:EAX avec une valeur 64 bits se trouvant en mémoire. Si ces valeurs sont équivalente, les 64 bits se trouvant en mémoire sont remplacés par les 64 bits formés par le couple de registre ECX:EBX. Dans le cas contraire, les 64 bits formés par les registres EDX:EAX sont remplacés par les 64 bits se trouvant en mémoire.

Algorithme

SI EDX:EAX = Opérande Destination ALORS
drapeau ZF ← 1
Opérande Destination ← ECX:EBX
SINON
drapeau ZF ← 0
EDX:EAX ← Opérande Destination
FIN SI

Mnémonique

Instruction | Opcode | Description
CMPXCHG8B mem64 | 0Fh C7h /1 m64 | Compare la paire de registres EDX:EAX à l'emplacement mémoire de 64 bits. S'ils sont égale, alors fixe le drapeau de zéro à 1 et copie ECX:EBX dans l'emplacement mémoire. Autrement, copie l'emplacement mémoire dans EDX:EAX et efface le drapeau de zéro.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) | X | X | X | L'instruction CMPXCHG8B n'est pas supporté, lequel est indiquer par le bit 8 du registre EDX de l'instruction CPUID, fonction 0000_0001h ou 8000_0001h.
 |  |  | X | L'opérande est un registre.
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction CMPXCHG

Références

Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 236 à 238.


Assembleur 80x86

TEST
INTEL 8088+ Test

Syntaxe

TEST opérandecible,opérandesource

Description

Cette instruction permet d'effectuer un «Et binaire» sur une opérande cible sans modifier sa valeur.

Algorithme

TEMP ← opérandecible ∩ opérandesource
SF ← MSB(TEMP)
SI TEMP = 0 ALORS
ZF ← 1
SINON
ZF ← 0
FIN SI
PF ← BitwiseXNOR(TEMP(0 à 7))
CF ← 0
OF ← 0

Mnémonique

Instruction | Opcode | Description
TEST AL, imm8 | A8h ib | Effectue un test de «Et binaire» avec une valeur immédiate de 8 bits sur le registre AL et indique le résultat de la comparaison sur le registre des drapeaux.
TEST AX, imm16 | A9h iw | Effectue un test de «Et binaire» avec une valeur immédiate de 16 bits sur le registre AX et indique le résultat de la comparaison sur le registre des drapeaux.
TEST EAX, imm32 | A9h id | Effectue un test de «Et binaire» avec une valeur immédiate de 32 bits sur le registre EAX et indique le résultat de la comparaison sur le registre des drapeaux.
TEST RAX, imm32 | A9h id | Effectue un test de «Et binaire» avec une valeur immédiate de 32 bits sur le registre RAX et indique le résultat de la comparaison sur le registre des drapeaux.
TEST reg/mem8, imm8 | F6h /0 ib | Effectue un test de «Et binaire» avec une valeur immédiate de 8 bits sur l'opérande registre ou mémoire 8 bits et indique le résultat de la comparaison sur le registre des drapeaux.
TEST reg/mem16, imm16 | F7h /0 iw | Effectue un test de «Et binaire» avec une valeur immédiate de 16 bits sur l'opérande registre ou mémoire 16 bits et indique le résultat de la comparaison sur le registre des drapeaux.
TEST reg/mem32, imm32 | F7h /0 id | Effectue un test de «Et binaire» avec une valeur immédiate de 32 bits sur l'opérande registre ou mémoire 32 bits et indique le résultat de la comparaison sur le registre des drapeaux.
TEST reg/mem64, imm32 | F7h /0 id | Effectue un test de «Et binaire» avec une valeur immédiate de 32 bits sur l'opérande registre ou mémoire 64 bits et indique le résultat de la comparaison sur le registre des drapeaux.
TEST reg/mem8, reg8 | 84h /r | Effectue un test de «Et binaire» avec un registre de 8 bits sur l'opérande registre ou mémoire 8 bits et indique le résultat de la comparaison sur le registre des drapeaux.
TEST reg/mem16, reg16 | 85h /r | Effectue un test de «Et binaire» avec un registre de 16 bits sur l'opérande registre ou mémoire 16 bits et indique le résultat de la comparaison sur le registre des drapeaux.
TEST reg/mem32, reg32 | 85h /r | Effectue un test de «Et binaire» avec un registre de 32 bits sur l'opérande registre ou mémoire 32 bits et indique le résultat de la comparaison sur le registre des drapeaux.
TEST reg/mem64, reg64 | 85h /r | Effectue un test de «Et binaire» avec un registre de 64 bits sur l'opérande registre ou mémoire 64 bits et indique le résultat de la comparaison sur le registre des drapeaux.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé


Voici les instructions assembleur classés par catégorie de conversions :

Instruction | Description | CPU/MPU
AAA | Cette instruction permet d'adapter le résultat obtenu par l'addition de 2 valeur en format DCB. | INTEL 8088+
AAD | Cette instruction permet de convertir une valeur de format DCB non compactée. | INTEL 8088+
AAM | Cette instruction offre la possibilité de convertir le produit de la multiplication de 2 valeurs de format DCB en un format DCB. | INTEL 8088+
AAS | Cette instruction permet d'adapter le résultat de la soustraction de nombre de format DCB. | INTEL 8088+
CBW | Cette instruction permet de convertir un nombre contenu dans le registre AL en un format sur 16 bits pour se retrouver dans le registre AX en appliquant une extension du signe. | INTEL 8088+
CDQ | Cette instruction permet de convertir le double mot en un quadruple mot, le résultat tient sur une taille de 64 bits. | INTEL 80386+
CWD | Cette instruction est l'alternative pour convertir le mot du registre AX en un double mot contenu dans le couple de registre DX et AX par extension du signe. | INTEL 8088+
CWDE | Cette instruction est l'alternative pour convertir le mot du registre AX en un double mot contenu dans le registre EAX par extension du signe. | INTEL 80386+
DAA | Cette instruction corrige après coup les retenues lors de la manipulation de valeur DCB. | INTEL 8088+
DAS | Cette instruction offre l'intéressante possibilité de corrige le résultat d'une soustraction de 2 nombres de format DCB compactées. | INTEL 8088+

Dernière mise à jour : Vendredi, le 4 mars 2016


Assembleur 80x86

AAA
INTEL 8088+ Ascii Adjust after Addition

Syntaxe

AAA

Description

Cette instruction permet d'adapter le résultat obtenu par l'addition de 2 valeurs en format DCB. Puisque le processeur additionne ces valeurs comme s'il s'agissait de nombres normaux, des débordements peuvent se produire dans les sommes. Afin de remédier à ce problème, la commande AAA offre de convertir le résultat de l'addition de 2 valeurs de format DCB non compactées en une valeur de format DCB non compactée. Elle cherche la somme de l'addition dans le registre AL. Pour que cette instruction réagisse correctement, il faut qu'elle soit lancée directement après l'addition de 2 valeurs de format DCB, étant donné que la valeur des indicateurs du micro-processeur revêt une importance particulière lors de l'exécution de cette commande.

Algorithme

* Vaut 1 si c'est vrai
retenue d'AL ← AL > 0F9h
SI ( ( AL ∩ 0Fh > 9 ) U ( AF = 1 ) ALORS
AL ← ( AL + 6 ) ∩ 0Fh
AH ← AH + 1 + retenue d'AL
Drapeau AF ← 1
Drapeau CF ← 1
SINON
AL ← 0Fh
Drapeau AF ← 0
Drapeau CF ← 0
FIN SI

Mnémonique

Instruction | Opcode | Description
AAA | 37h | Cette instruction permet de créer un nombre dépaqueté BCD (invalide en mode 64-bits)

Cycles d'horloge

Instruction | Opcode | 8086 | 8088 | 80186 | 80286 | 80386 | i486 | Pentium | Cx486SLC | Cx486DX | IBM 486BL3X | UMC U5S
AAA | 37h | 4 | 4 | 8 | 3 | 4 | 3 | 3 | 4 | 4 | 4 | 1

Affectations des registres de drapeaux

Drapeau | Position | Description
CF | 0 | Fixé à 1 si la décimale est retenue, sinon il est fixé à 0.
PF | 2 | Indéfini
AF | 4 | Fixé à 1 si la décimal est retenue, sinon il est fixé à 0.
ZF | 6 | Indéfini
SF | 7 | Indéfini
TF | 8 | Non affecté
IF | 9 | Non affecté
DF | 10 | Non affecté
OF | 11 | Indéfini
IOPL | 12 et 13 | Non affecté
NT | 14 | Non affecté
RF | 16 | Non affecté
WM | 17 | Non affecté
AC | 18 | Non affecté
VIF | 19 | Non affecté
VIP | 20 | Non affecté
ID | 21 | Non affecté

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) |  |  | X | Cette instruction est exécutée en mode 64-bits

Exemple

Cet exemple permet d'effectuer une addition BCD :

  1. MOV AX,0005h
  2. MOV CL,06h
  3. ADD AL,CL
  4. AAA

Ce programme retournera donc la valeur 0101h dans le registre AX.

Voir également

Instruction assembleur 80x86 - Instruction AAD
Instruction assembleur 80x86 - Instruction AAM
Instruction assembleur 80x86 - Instruction AAS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 801
Le grand livre pour programmer en Assembleur sur PC, Holger Schakel, 1995, ISBN: 2-7429-0442-5, page 144.
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 53.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 67 à 68.


Assembleur 80x86

AAD
INTEL 8088+ Ascii Adjust ax before Division

Syntaxe

AAD
AAD immédiat 8

Paramètres

Nom | Description
immédiat 8 | Ce paramètre permet une valeur statique de 8 bits

Description

Grâce à cette instruction, on peut convertir une valeur de format DCB non compactée se trouvant dans le registre AX (un chiffre dans le registre AH tandis que l'autre est dans le registre AL) en un nombre binaire étant placée dans le registre AL. Pour la division, on utilise l'instruction IDIV en veillant auparavant à ce que le registre AH soit vide.

Algorithme

AL ← AH x immédiat 8 bits + AL
AH ← 00h

Mnémonique

Instruction | Opcode | Description
AAD | D5h 0Ah | Ajuste 2 chiffres BCD dans les registres AL et AH (invalide en mode 64-bits)
aucun | D5h ib | Ajuste 2 chiffres BCD dans les registres AL et AH (invalide en mode 64-bits)

Cycles d'horloge

Instruction | Opcode | 8086 | 8088 | 80186 | 80286 | 80386 | i486 | Pentium | Cx486SLC | Cx486DX | IBM 486BL3X | UMC U5S
AAD | D5h 0Ah | 60 | 60 | 15 | 14 | 19 | 14 | 10 | 4 | 4 | 15 | 11

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) |  |  | X | Cette instruction est exécutée en mode 64-bits

Voir également

Instruction assembleur 80x86 - Instruction AAA
Instruction assembleur 80x86 - Instruction AAM
Instruction assembleur 80x86 - Instruction AAS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 801
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 54.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 69 à 70.


Assembleur 80x86

AAM
INTEL 8088+ Ascii adjust AX After Multiplication

Syntaxe

AAM
AAM immédiat 8

Paramètres

Nom | Description
immédiat 8 | Ce paramètre permet une valeur statique de 8 bits

Description

Cette instruction offre la possibilité de convertir le produit de la multiplication de 2 valeurs de format DCB en un format DCB. Étant donné que le microprocesseur multiplie ces valeurs comme s'il s'agissait de nombres normaux, des débordements peuvent éventuellement se produire dans les résultats. L'instruction AAM rectifie cela. Lors de l'exécution de cette commande, le contenu du registre AL est divisé en 2 chiffres de format DCB nom compactés : le chiffre le plus élevé est placé dans le registre AH tandis que le moins élevé est mis dans le registre AL.

Algorithme

AH ← AL ÷ immédiat 8
AL ← AL MOD immédiat 8

Mnémonique

Instruction | Opcode | Description
AAM | D4h 0Ah | Crée une paire des valeurs dépaqueter BCD dans les registres AL et AH (invalide en mode 64-bits)
aucun | D4h ib | Crée une paire des valeurs dépaqueter immédiatement dans l'octet de base (invalide en mode 64-bits)

Cycles d'horloge

Instruction | Opcode | 8086 | 8088 | 80186 | 80286 | 80386 | i486 | Pentium | Cx486SLC | Cx486DX | IBM 486BL3X | UMC U5S
AAM | D4h 0Ah | 83 | 83 | 19 | 16 | 17 | 15 | 18 | 16 | 16 | 17 | 12

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#DE(Division par zéro) | X | X | X | Valeur immédiate 8 bits contient 0
#UD(Opcode invalide) |  |  | X | Cette instruction est exécutée en mode 64-bits

Voir également

Instruction assembleur 80x86 - Instruction AAA
Instruction assembleur 80x86 - Instruction AAD
Instruction assembleur 80x86 - Instruction AAS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 802
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 55.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 71 à 72.


Assembleur 80x86

AAS
INTEL 8088+ Ascii Adjust al after Subtraction

Syntaxe

AAS

Description

A l'aide de cette instruction, on peut adapter le résultat de la soustraction de 2 nombre de format DCB. Étant donné que le processeur soustrait ces valeurs comme s'il s'agissait de chiffres normales, des débordements se produisent dans les résultats. La commande AAS rectifie cela. Cette instruction ne peut fonctionner qu'avec des nombres sur 8 bits. Elle transforme la valeur placée après la soustraction dans le registre AL en une valeur DCB acceptable.

Algorithme

* Vaut 1 si c'est vrai
AL inférieur ← AL < 6
SI ( AL ∩ 0Ah ) U ( AF = 1 ) ALORS
AL ← ( AL - 6 ) ∩ 0Fh
AH ← AH - 1 – AL inférieur
Drapeau CF ← 1
Drapeau AF ← 1
SINON
AL ← AL ∩ 0Fh
Drapeau CF ← 0
Drapeau AF ← 0
FIN SI

Mnémonique

Instruction | Opcode | Description
AAS | 3Fh | Crée un nombre dépacter BCD à partir du contenu du registre AL (invalide en mode 64-bits)

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) |  |  | X | Cette instruction est exécuté en mode 64-bits

Voir également

Instruction assembleur 80x86 - Instruction AAA
Instruction assembleur 80x86 - Instruction AAD
Instruction assembleur 80x86 - Instruction AAM

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 802
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 56.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 73 à 74.


Assembleur 80x86

CBW
INTEL 8088+ Convert Byte To Word

Syntaxe

CBW

Description

Cette instruction permet de convertir le nombre contenu dans le registre AL en un format sur 16 bits pour se retrouver dans le registre AX en appliquant une extension du signe. L'application des signes est appliquée de la façon suivante: le bit de signe de AL est copié dans les 8 bits du registre AH. Cette commande est destiné au conversion de valeur 8 à 16 bits uniquement.

Algorithme

SI AL ∩ 80h > 0 ALORS
AH ← 080h
AL ← AL ∩ 7Fh
SINON
AH ← 0
FIN SI

Mnémonique

Instruction | Opcode | Description
CBW | 98h | Étendre les signes de AL dans AX

Exceptions

Aucune

Voir également

Instruction assembleur 80x86 - Instruction CWD
Instruction assembleur 80x86 - Instruction CWDE
Instruction assembleur 80x86 - Instruction CDQ

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 806
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 402
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 84.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 187 à 188.


Assembleur 80x86

CDQ
INTEL 80386+ Convert Doubleword to Quadword

Syntaxe

CDQ

Description

L'instruction CDQ convertit le double mot (32 bits) se trouvant dans le registre EAX en un quadruple mot, le résultat tient sur une taille de 64 bits. Pour réussir à fournir la réponse en entier, on procédera comme suit: Le double mot de poids le plus fort est placé dans EDX, celui de poids le plus faible dans le registre EAX. Les 32 bits du registre EDX sont positionnés à la valeur du bit de poids le plus fort du registre EAX.

Algorithme

EDX ← extension des signes de EAX

Mnémonique

Instruction | Opcode | Description
CQO | 99h | Étendre les signes de EAX dans EDX:EAX

Exceptions

Aucune

Références

Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 349 à 350.


Assembleur 80x86

CWD
INTEL 8088+ Convert Word to Double word

Syntaxe

CWD

Description

Cette instruction est l'alternative pour convertir le mot du registre AX en un double mot contenu dans le couple de registre DX et AX par extension du signe. Le bit de signe du registre AX est recopié dans les 16 bits du registre DX. En somme, cette commande ne présente un intérêt particulier que lorsque l'on manipule des valeurs binaires signées étant donné que le signe du registre AX est conservé dans le double mot du couple de registre DX:AX.

Algorithme

SI AX < 8000h ALORS
DX ← 00000h
FIN SI
SI AX >= 8000h ALORS
DX ← 0FFFFh
FIN SI

Mnémonique

Instruction | Opcode | Description
CWD | 99h | Étendre les signes de AX dans DX:AX

Exceptions

Aucune

Voir également

Instruction assembleur 80x86 - Instruction CBW
Instruction assembleur 80x86 - Instruction CWDE
Instruction assembleur 80x86 - Instruction CDQ

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 809
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 404
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 85.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 349 à 350.


Assembleur 80x86

CWDE
INTEL 80386+ Convert WorD to Extended (double word)

Syntaxe

CWDE

Description

S'appuyant sur la technique utilisé par son frère CWD, l'instruction CWDE permet de convertir le mot se trouvant dans AX en un double mot, le résultat étant placé dans le registre 32 bits EAX. Les 16 bits de poids forts du registre EAX sont positionnés à la valeur du bit de poids le plus fort du registre AX.

Algorithme

SI EAX < 8000h ALORS
EAX ← EAX ∩ 00000FFFFh
FIN SI
SI EAX >= 8000h ALORS
EAX ← EAX U 0FFFF0000h
FIN SI

Mnémonique

Instruction | Opcode | Description
CWDE | 66h 98h | Étendre les signes de AX dans EAX

Exceptions

Aucune

Voir également

Instruction assembleur 80x86 - Instruction CWD
Instruction assembleur 80x86 - Instruction CBW
Instruction assembleur 80x86 - Instruction CDQ

Références

Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 187 à 188.


Assembleur 80x86

DAA
INTEL 8088+ Decimal Adjust for Addition

Syntaxe

DAA

Description

Cette instruction corrige après coup les retenues lors de la manipulation de valeur DCB. Pour y parvenir, la commande convertit le contenu dans le registre AL en une valeur DCB compactée (même chose dans le registre AL).

Algorithme

SI ( ( AL ∩ 0Fh ) > 9 U AF = 1 ) ALORS
AL ← AL + 6
drapeau AF ← 1
SINON
drapeau AF ← 0
SI ( ( AL > 9Fh) U CF = 1 ) ALORS
AL ← AL + 60h
drapeau CF ← 1
SINON
drapeau CF ← 0
FIN SI
FIN SI

Mnémonique

Instruction | Opcode | Description
DAA | 27h | Ajuste les décimal du registre AL (invalide en mode 64 bits)

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) |  |  | X | Cette instruction est exécuté en mode 64-bits

Voir également

Instruction assembleur 80x86 - Instruction DAS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 810
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 105.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 351 à 352.


Assembleur 80x86

DAS
INTEL 8088+ Decimal Adjust AL After Soustraction

Syntaxe

DAS

Description

Cette instruction offre l'intéressante possibilité de corrige le résultat d'une soustraction de 2 nombres de format DCB compactées. Étant donné que le microprocesseur soustrait ces valeurs comme s'il s'agissait de chiffres normales, des débordements se produisent dans les résultats. La commande DAS convertit le résultat de la soustraction de 2 valeurs DCB compactées en une valeur de format DCB compactée.

Algorithme

SI ( AF = 1 ) U ( AL ∩ 0Fh ) > 9 ALORS
AL ← AL - 6
drapeau AF ← 1
SINON
drapeau AF ← 0
FIN SI
SI ( CF = 1 ) U ( AL > 9Fh ) ALORS
AL ← AL - 60h
drapeau CF ← 1
SINON
drapeau CF ← 0
FIN SI

Mnémonique

Instruction | Opcode | Description
DAS | 2Fh | Ajuste les décimal du registre AL après soustraction (invalide en mode 64 bits)

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) |  |  | X | Cette instruction est exécuté en mode 64-bits

Voir également

Instruction assembleur 80x86 - Instruction DAA

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 810
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 106.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 353 à 354.


Voici les instructions assembleur classés par catégorie de décalage de bits :

Instruction | Description | CPU/MPU
RCL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré. | INTEL 8088+
RCR | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré. | INTEL 8088+
ROL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré. | INTEL 8088+
ROR | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré. | INTEL 8088+
SAL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | INTEL 8088+
SAR | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | INTEL 8088+
SHL | Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF). | INTEL 8088+
SHR | Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF). | INTEL 8088+

Dernière mise à jour : Vendredi, le 4 mars 2016


Assembleur 80x86

RCL
INTEL 8088+ Rotate Through Carry Left

Syntaxe

RCL opérandecible,nombredebits

Description

Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à droite libéré.

Algorithme

temp ← max (nombredebits, 31)
SI temp = 1 ALORS
OF ← highbit(opérandecible) <> CF
SINON
OF ← ?
FIN SI
Valeur ← concaténation ( CF, opérandecible )
FAIRE TANT QUE temp <> 0
X ← highbit ( valeur )
valeur ← ( valeur décalage à gauche 1 ) + X
temp ← temp - 1
FIN DE FAIRE
CF ← highbit ( valeur )
opérandecible ← valeur

Mnémonique

Instruction | Opcode | Description
RCL reg/mem8,1 | D0h /2 | Cette instruction effectue une rotation de 9 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 8 bits) d'un seul bit vers la gauche.
RCL reg/mem8, CL | D2h /2 | Cette instruction effectue une rotation de 9 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 8 bits) avec le nombre de bits spécifié par le registre CL vers la gauche.
RCL reg/mem8, imm8 | C0h /2 ib | Cette instruction effectue une rotation de 9 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 8 bits) avec le nombre de bits spécifié par la valeur immédiate vers la gauche.
RCL reg/mem16, 1 | D1h /2 | Cette instruction effectue une rotation de 17 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 16 bits) d'un seul bit vers la gauche.
RCL reg/mem16, CL | D3h /2 | Cette instruction effectue une rotation de 17 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 16 bits) avec le nombre de bits spécifié par le registre CL vers la gauche.
RCL reg/mem16, imm8 | C1h /2 ib | Cette instruction effectue une rotation de 17 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 16 bits) avec le nombre de bits spécifié par la valeur immédiate vers la gauche.
RCL reg/mem32, 1 | D1h /2 | Cette instruction effectue une rotation de 33 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 32 bits) d'un seul bit vers la gauche.
RCL reg/mem32, CL | D3h /2 | Cette instruction effectue une rotation de 33 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 32 bits) avec le nombre de bits spécifié par le registre CL vers la gauche.
RCL reg/mem32, imm8 | C1h /2 ib | Cette instruction effectue une rotation de 33 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 32 bits) avec le nombre de bits spécifié par la valeur immédiate vers la gauche.
RCL reg/mem64, 1 | D1h /2 | Cette instruction effectue une rotation de 65 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 64 bits) d'un seul bit vers la gauche.
RCL reg/mem64, CL | D3h /2 | Cette instruction effectue une rotation de 65 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 64 bits) avec le nombre de bits spécifié par le registre CL vers la gauche.
RCL reg/mem64, imm8 | C1h /2 ib | Cette instruction effectue une rotation de 65 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 64 bits) avec le nombre de bits spécifié par la valeur immédiate vers la gauche.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Voici un exemple en Turbo Pascal montrant l'utilisation de cette instruction :

  1. Program RClSamples;
  3. Function _Rcl(Value: Integer ;_Shift: Byte ): Integer ;Assembler; ASM
  4. MOV AX,Value
  5. MOV CL,_Shift
  6. RCL AX,CL
  7. END;
  9. BEGIN
  10. WriteLn ('1 RCL 0 = ',_Rcl(1,0));
  11. WriteLn ('1 RCL 1 = ',_Rcl(1,1));
  12. WriteLn ('1 RCL 2 = ',_Rcl(1,2));
  13. WriteLn ('1 RCL 3 = ',_Rcl(1,3));
  14. WriteLn ('1 RCL 4 = ',_Rcl(1,4));
  15. WriteLn ('2 RCL 0 = ',_Rcl(2,0));
  16. WriteLn ('2 RCL 1 = ',_Rcl(2,1));
  17. WriteLn ('2 RCL 2 = ',_Rcl(2,2));
  18. WriteLn ('2 RCL 3 = ',_Rcl(2,3));
  19. WriteLn ('2 RCL 4 = ',_Rcl(2,4));
  20. END .

on obtiendra le résultat suivant :

1 RCL 0 = 1
1 RCL 1 = 2
1 RCL 2 = 4
1 RCL 3 = 8
1 RCL 4 = 16
2 RCL 0 = 2
2 RCL 1 = 4
2 RCL 2 = 8
2 RCL 3 = 16
2 RCL 4 = 32

Voir également

Instruction assembleur 80x86 - Instruction RCR
Instruction assembleur 80x86 - Instruction ROL
Instruction assembleur 80x86 - Instruction ROR

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 827
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 413
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 202.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 334 à 341.


Assembleur 80x86

RCR
INTEL 8088+ Rotate Through Carry Right

Syntaxe

RCR opérandecible,nombredebits

Description

Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF) ainsi que dans le bit le plus à gauche libéré.

Algorithme

temp ← max (nombredebits, 31)
SI temp = 1 ALORS
OF ← highbit ( opérandecible ) <> highbit ( opérandecible ) décalage à droite ) )
SINON
OF ← ?
FIN SI
Valeur ← concaténation ( opérandecible, CF )
FAIRE TANT QUE temp <> 0
X ← valeur ∩ 1
valeur ← valeur décalage à droite de 1
highbit ( valeur ) ← x
temp ← temp - 1
FIN DE FAIRE
CF ← highbit ( valeur )
opérandecible ← valeur

Mnémonique

Instruction | Opcode | Description
RCR reg/mem8, 1 | D0h /3 | Cette instruction effectue une rotation de 9 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 8 bits) d'un seul bit vers la droite.
RCR reg/mem8,CL | D2h /3 | Cette instruction effectue une rotation de 9 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 8 bits) avec le nombre de bits spécifié par le registre CL vers la droite.
RCR reg/mem8,imm8 | C0h /3 ib | Cette instruction effectue une rotation de 9 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 8 bits) avec le nombre de bits spécifié par la valeur immédiate vers la droite.
RCR reg/mem16,1 | D1h /3 | Cette instruction effectue une rotation de 17 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 16 bits) d'un seul bit vers la droite.
RCR reg/mem16,CL | D3h /3 | Cette instruction effectue une rotation de 17 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 16 bits) avec le nombre de bits spécifié par le registre CL vers la droite.
RCR reg/mem16, imm8 | C1h /3 ib | Cette instruction effectue une rotation de 17 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 16 bits) avec le nombre de bits spécifié par la valeur immédiate vers la droite.
RCR reg/mem32,1 | D1h /3 | Cette instruction effectue une rotation de 33 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 32 bits) d'un seul bit vers la droite.
RCR reg/mem32,CL | D3h /3 | Cette instruction effectue une rotation de 33 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 32 bits) avec le nombre de bits spécifié par le registre CL vers la droite.
RCR reg/mem32, imm8 | C1h /3 ib | Cette instruction effectue une rotation de 33 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 32 bits) avec le nombre de bits spécifié par la valeur immédiate vers la droite.
RCR reg/mem64,1 | D1h /3 | Cette instruction effectue une rotation de 65 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 64 bits) d'un seul bit vers la droite.
RCR reg/mem64,CL | D3h /3 | Cette instruction effectue une rotation de 65 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 64 bits) d'un seul bit vers la droite.
RCR reg/mem64, imm8 | C1h /3 ib | Cette instruction effectue une rotation de 65 bits (drapeau de retenue 1 bit + emplacement registre ou mémoire 64 bits) avec le nombre de bits spécifié par la valeur immédiate vers la droite.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Voici un exemple en Turbo Pascal montrant l'utilisation de cette instruction :

  1. Program RcrSamples;
  3. Function _Rcr(Value: Integer ;_Shift: Byte ): Integer ;Assembler; ASM
  4. MOV AX,Value
  5. MOV CL,_Shift
  6. RCR AX,CL
  7. END;
  9. BEGIN
  10. WriteLn ('16 RCR 0 = ',_Rcr(16,0));
  11. WriteLn ('16 RCR 1 = ',_Rcr(16,1));
  12. WriteLn ('16 RCR 2 = ',_Rcr(16,2));
  13. WriteLn ('16 RCR 3 = ',_Rcr(16,3));
  14. WriteLn ('16 RCR 4 = ',_Rcr(16,4));
  15. WriteLn ('16 RCR 0 = ',_Rcr(32,0));
  16. WriteLn ('32 RCR 1 = ',_Rcr(32,1));
  17. WriteLn ('32 RCR 2 = ',_Rcr(32,2));
  18. WriteLn ('32 RCR 3 = ',_Rcr(32,3));
  19. WriteLn ('32 RCR 4 = ',_Rcr(32,4));
  20. WriteLn ('32 RCR 4 = ',_Rcr(32,4));
  21. END .

on obtiendra le résultat suivant :

16 RCR 0 = 16
16 RCR 1 = 8
16 RCR 2 = 4
16 RCR 3 = 2
16 RCR 4 = 1
16 RCR 0 = 32
32 RCR 1 = 16
32 RCR 2 = 8
32 RCR 3 = 4
32 RCR 4 = 2
32 RCR 4 = 2

Voir également

Instruction assembleur 80x86 - Instruction RCL
Instruction assembleur 80x86 - Instruction ROR
Instruction assembleur 80x86 - Instruction ROL

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 828
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 413
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 204.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 334 à 341.


Assembleur 80x86

ROL
INTEL 8088+ Rotate Left

Syntaxe

ROL opérandecible,nombredebits

Description

Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans le bit le plus à droite libéré.

Algorithme

temp ← max ( compteur, 31)
SI temp = 1 ALORS
OF ← highbit ( destination ) <> CF
SINON
OF ← ?
FIN SI
BOUCLE FAIRE TANT QUE temp <> 0
X ← highbit ( destination )
destination ← (destination décalage à gauche de 1 ) + x
temp ← temp - 1
FIN BOUCLE DE TANT QUE
CF ← highbit ( destination )

Mnémonique

Instruction | Opcode | Description
ROL reg/mem8, 1 | D0h /0 | Cette instruction effectue une rotation de 8 bits d'un opérande registre ou mémoire 8 bits d'un seul bit vers la gauche.
ROL reg/mem8, CL | D2h /0 | Cette instruction effectue une rotation de 8 bits d'un opérande registre ou mémoire 8 bits avec le nombre de bits spécifié par le registre CL vers la gauche.
ROL reg/mem8, imm8 | C0h /0 ib | Cette instruction effectue une rotation de 8 bits d'un opérande registre ou mémoire 8 bits avec le nombre de bits spécifié par la valeur immédiate vers la gauche.
ROL reg/mem16, 1 | D1h /0 | Cette instruction effectue une rotation de 16 bits d'un opérande registre ou mémoire 16 bits d'un seul bit vers la gauche.
ROL reg/mem16, CL | D3h /0 | Cette instruction effectue une rotation de 16 bits d'un opérande registre ou mémoire 16 bits avec le nombre de bits spécifié par le registre CL vers la gauche.
ROL reg/mem16, imm8 | C1h /0 ib | Cette instruction effectue une rotation de 16 bits d'un opérande registre ou mémoire 16 bits avec le nombre de bits spécifié par la valeur immédiate vers la gauche.
ROL reg/mem32, 1 | D1h /0 | Cette instruction effectue une rotation de 32 bits d'un opérande registre ou mémoire 32 bits d'un seul bit vers la gauche.
ROL reg/mem32, CL | D3h /0 | Cette instruction effectue une rotation de 32 bits d'un opérande registre ou mémoire 32 bits avec le nombre de bits spécifié par le registre CL vers la gauche.
ROL reg/mem32, imm8 | C1h /0 ib | Cette instruction effectue une rotation de 32 bits d'un opérande registre ou mémoire 32 bits avec le nombre de bits spécifié par la valeur immédiate vers la gauche.
ROL reg/mem64, 1 | D1h /0 | Cette instruction effectue une rotation de 64 bits d'un opérande registre ou mémoire 64 bits d'un seul bit vers la gauche.
ROL reg/mem64, CL | D3h /0 | Cette instruction effectue une rotation de 64 bits d'un opérande registre ou mémoire 64 bits avec le nombre de bits spécifié par le registre CL vers la gauche.
ROL reg/mem64, imm8 | C1h /0 ib | Cette instruction effectue une rotation de 64 bits d'un opérande registre ou mémoire 64 bits avec le nombre de bits spécifié par la valeur immédiate vers la gauche.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Voici un exemple en Turbo Pascal montrant l'utilisation de cette instruction :

  1. Program RolSamples;
  3. Function _Rol(Value: Integer ;_Shift: Byte ): Integer ;Assembler; ASM
  4. MOV AX,Value
  5. MOV CL,_Shift
  6. ROL AX,CL
  7. END;
  9. BEGIN
  10. WriteLn ('1 ROL 0 = ',_Rol(1,0));
  11. WriteLn ('1 ROL 1 = ',_Rol(1,1));
  12. WriteLn ('1 ROL 2 = ',_Rol(1,2));
  13. WriteLn ('1 ROL 3 = ',_Rol(1,3));
  14. WriteLn ('1 ROL 4 = ',_Rol(1,4));
  15. WriteLn ('2 ROL 0 = ',_Rol(2,0));
  16. WriteLn ('2 ROL 1 = ',_Rol(2,1));
  17. WriteLn ('2 ROL 2 = ',_Rol(2,2));
  18. WriteLn ('2 ROL 3 = ',_Rol(2,3));
  19. WriteLn ('2 ROL 4 = ',_Rol(2,4));
  20. END .

on obtiendra le résultat suivant :

1 ROL 0 = 1
1 ROL 1 = 2
1 ROL 2 = 4
1 ROL 3 = 8
1 ROL 4 = 16
2 ROL 0 = 2
2 ROL 1 = 4
2 ROL 2 = 8
2 ROL 3 = 16
2 ROL 4 = 32

Voir également

Instruction assembleur 80x86 - Instruction RCL
Instruction assembleur 80x86 - Instruction RCR
Instruction assembleur 80x86 - Instruction ROR

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 830
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 415
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 211.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 334 à 341.


Assembleur 80x86

ROR
INTEL 8088+ Rotate Right

Syntaxe

ROR opérandecible,nombredebits

Description

Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans le bit le plus à gauche libéré.

Algorithme

temp ← max ( compteur, 31 )
SI temp = 1 ALORS
OF ← highbit ( destination ) <> highbit ( destination décalage à droite )
SINON
OF ← ?
FIN SI
BOUCLE FAIRE TANT QUE temp <> 0
x ← valeur ∩ 1
valeur ← valeur décalage à droite de 1
highbit ( valeur ) ← x
temp ← temp - 1
BOUCLE FIN DE TANT QUE
CF ← highbit ( valeur )
destination ← valeur

Mnémonique

Instruction | Opcode | Description
ROR reg/mem8, 1 | D0h /1 | Cette instruction effectue une rotation de 8 bits d'un opérande registre ou mémoire 8 bits d'un seul bit vers la droite.
ROR reg/mem8, CL | D2h /1 | Cette instruction effectue une rotation de 8 bits d'un opérande registre ou mémoire 8 bits avec le nombre de bits spécifié par le registre CL vers la droite.
ROR reg/mem8, imm8 | C0h /1 ib | Cette instruction effectue une rotation de 8 bits d'un opérande registre ou mémoire 8 bits avec le nombre de bits spécifié par la valeur immédiate vers la droite.
ROR reg/mem16, 1 | D1h /1 | Cette instruction effectue une rotation de 16 bits d'un opérande registre ou mémoire 16 bits d'un seul bit vers la droite.
ROR reg/mem16, CL | D3h /1 | Cette instruction effectue une rotation de 16 bits d'un opérande registre ou mémoire 16 bits avec le nombre de bits spécifié par le registre CL vers la droite.
ROR reg/mem16, imm8 | C1h /1 ib | Cette instruction effectue une rotation de 16 bits d'un opérande registre ou mémoire 16 bits avec le nombre de bits spécifié par la valeur immédiate vers la droite.
ROR reg/mem32, 1 | D1h /1 | Cette instruction effectue une rotation de 32 bits d'un opérande registre ou mémoire 32 bits d'un seul bit vers la droite.
ROR reg/mem32, CL | D3h /1 | Cette instruction effectue une rotation de 32 bits d'un opérande registre ou mémoire 32 bits avec le nombre de bits spécifié par le registre CL vers la droite.
ROR reg/mem32, imm8 | C1h /1 ib | Cette instruction effectue une rotation de 32 bits d'un opérande registre ou mémoire 32 bits avec le nombre de bits spécifié par la valeur immédiate vers la droite.
ROR reg/mem64, 1 | D1h /1 | Cette instruction effectue une rotation de 64 bits d'un opérande registre ou mémoire 64 bits d'un seul bit vers la droite.
ROR reg/mem64, CL | D3h /1 | Cette instruction effectue une rotation de 64 bits d'un opérande registre ou mémoire 64 bits avec le nombre de bits spécifié par le registre CL vers la droite.
ROR reg/mem64, imm8 | C1h /1 ib | Cette instruction effectue une rotation de 64 bits d'un opérande registre ou mémoire 64 bits avec le nombre de bits spécifié par la valeur immédiate vers la droite.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Voici un exemple en Turbo Pascal montrant l'utilisation de cette instruction :

  1. Program RorSamples;
  3. Function _Ror(Value: Integer ;_Shift: Byte ): Integer ;Assembler; ASM
  4. MOV AX,Value
  5. MOV CL,_Shift
  6. ROR AX,CL
  7. END;
  9. BEGIN
  10. WriteLn ('16 ROR 0 = ',_Ror(16,0));
  11. WriteLn ('16 ROR 1 = ',_Ror(16,1));
  12. WriteLn ('16 ROR 2 = ',_Ror(16,2));
  13. WriteLn ('16 ROR 3 = ',_Ror(16,3));
  14. WriteLn ('16 ROR 4 = ',_Ror(16,4));
  15. WriteLn ('16 ROR 0 = ',_Ror(32,0));
  16. WriteLn ('32 ROR 1 = ',_Ror(32,1));
  17. WriteLn ('32 ROR 2 = ',_Ror(32,2));
  18. WriteLn ('32 ROR 3 = ',_Ror(32,3));
  19. WriteLn ('32 ROR 4 = ',_Ror(32,4));
  20. WriteLn ('32 ROR 4 = ',_Ror(32,4));
  21. END .

on obtiendra le résultat suivant :

16 ROR 0 = 16
16 ROR 1 = 8
16 ROR 2 = 4
16 ROR 3 = 2
16 ROR 4 = 1
16 ROR 0 = 32
32 ROR 1 = 16
32 ROR 2 = 8
32 ROR 3 = 4
32 ROR 4 = 2
32 ROR 4 = 2

Voir également

Instruction assembleur 80x86 - Instruction RCL
Instruction assembleur 80x86 - Instruction RCR
Instruction assembleur 80x86 - Instruction ROL

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 830
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 415
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 213.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 334 à 341.


Assembleur 80x86

SAL
INTEL 8088+ Shift Arithmetic Left

Syntaxe

SAL opérandecible,nombredebits

Paramètres

Nom | Description
opérandecible | Ce paramètre permet d'indiquer une expression de type entier subissant le «décalage de bits vers la gauche»
nombredebits | Ce paramètre permet d'indiquer le décalage de bit vers la gauche à effectuer

Description

Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF).

Algorithme

temp ← compteur ∩ 001Fh
BOUCLE FAIRE TANT QUE temp1 = 0
CF ← highorder ( destination )
destination ← destination décalage à gauche de 1
temp ← temp - 1
BOUCLE FIN DE FAIRE
SI count = 1 ALORS
OF ← highorder ( destination ) ≠ CF
SINON
OF ← ?
FIN SI

Mnémonique

Instruction | Opcode | Description
SAL reg/mem8, 1 | D0h /4 | Cette instruction effectue un décalage d'un seul bit vers la gauche d'un opérande registre ou mémoire 8 bits.
SAL reg/mem8, CL | D2h /4 | Cette instruction effectue un décalage du nombre de bits spécifié par le registre CL vers la gauche d'un opérande registre ou mémoire 8 bits.
SAL reg/mem8, imm8 | C0h /4 ib | Cette instruction effectue un décalage du nombre de bits spécifié par la valeur immédiate vers la gauche de 8 bits d'un opérande registre ou mémoire 8 bits.
SAL reg/mem16, 1 | D1h /4 | Cette instruction effectue un décalage d'un seul bit vers la gauche d'un opérande registre ou mémoire 16 bits.
SAL reg/mem16, CL | D3h /4 | Cette instruction effectue un décalage du nombre de bits spécifié par le registre CL vers la gauche d'un opérande registre ou mémoire 16 bits.
SAL reg/mem16, imm8 | C1h /4 ib | Cette instruction effectue un décalage du nombre de bits spécifié par la valeur immédiate vers la gauche de 8 bits d'un opérande registre ou mémoire 16 bits.
SAL reg/mem32, 1 | D1h /4 | Cette instruction effectue un décalage d'un seul bit vers la gauche d'un opérande registre ou mémoire 32 bits.
SAL reg/mem32, CL | D3h /4 | Cette instruction effectue un décalage du nombre de bits spécifié par le registre CL vers la gauche d'un opérande registre ou mémoire 32 bits.
SAL reg/mem32, imm8 | C1h /4 ib | Cette instruction effectue un décalage du nombre de bits spécifié par la valeur immédiate vers la gauche de 8 bits d'un opérande registre ou mémoire 32 bits.
SAL reg/mem64, 1 | D1h /4 | Cette instruction effectue un décalage d'un seul bit vers la gauche d'un opérande registre ou mémoire 64 bits.
SAL reg/mem64, CL | D3h /4 | Cette instruction effectue un décalage du nombre de bits spécifié par le registre CL vers la gauche de 64 bits d'un opérande registre ou mémoire 64 bits.
SAL reg/mem64, imm8 | C1h /4 ib | Cette instruction effectue un décalage du nombre de bits spécifié par la valeur immédiate vers la gauche de 8 bits d'un opérande registre ou mémoire 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Voici un exemple en Turbo Pascal montrant l'utilisation de cette instruction :

  1. Program SalSamples;
  3. Function _Sal(Value: Integer ;_Shift: Byte ): Integer ;Assembler; ASM
  4. MOV AX,Value
  5. MOV CL,_Shift
  6. SAL AX,CL
  7. END;
  9. BEGIN
  10. WriteLn ('1 SAL 0 = ',_Sal(1,0));
  11. WriteLn ('1 SAL 1 = ',_Sal(1,1));
  12. WriteLn ('1 SAL 2 = ',_Sal(1,2));
  13. WriteLn ('1 SAL 3 = ',_Sal(1,3));
  14. WriteLn ('1 SAL 4 = ',_Sal(1,4));
  15. WriteLn ('2 SAL 0 = ',_Sal(2,0));
  16. WriteLn ('2 SAL 1 = ',_Sal(2,1));
  17. WriteLn ('2 SAL 2 = ',_Sal(2,2));
  18. WriteLn ('2 SAL 3 = ',_Sal(2,3));
  19. WriteLn ('2 SAL 4 = ',_Sal(2,4));
  20. END .

on obtiendra le résultat suivant :

1 SAL 0 = 1
1 SAL 1 = 2
1 SAL 2 = 4
1 SAL 3 = 8
1 SAL 4 = 16
2 SAL 0 = 2
2 SAL 1 = 4
2 SAL 2 = 8
2 SAL 3 = 16
2 SAL 4 = 32

Voir également

Instruction assembleur 80x86 - Instruction SAR
Instruction assembleur 80x86 - Instruction SHR
Instruction assembleur 80x86 - Instruction SHLD
Instruction assembleur 80x86 - Instruction SHRD

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 831
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 415
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 216.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 400 à 408.


Assembleur 80x86

SAR
INTEL 8088+ Shift Arithmetic Right

Syntaxe

SAR opérandecible,nombredebits

Paramètres

Nom | Description
opérandecible | Ce paramètre permet d'indiquer une expression de type entier subissant le «décalage de bits vers la droite»
nombredebits | Ce paramètre permet d'indiquer le décalage de bit vers la droite à effectuer

Description

Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF).

Algorithme

temp ← compteur ∩ 001Fh
BOUCLE FAIRE TANT temp <> 0
x ← highorder ( destination )
CF ← destination ∩ 1
destination ← destination décalage à droite de 1
highorder ( destination ) ← x
temp ← temp - 1
BOUCLE FIN DE FAIRE
SI compteur = 1 ALORS
OF ← 0
SINON
OF ← ?
FIN SI

Mnémonique

Instruction | Opcode | Description
SAR reg/mem8, 1 | D0h /7 | Cette instruction effectue une décalage d'un seul bit vers la droite de 8 bits d'un opérande registre ou mémoire 8 bits.
SAR reg/mem8, CL | D2h /7 | Cette instruction effectue une décalage du nombre de bits spécifié par le registre CL vers la droite de 8 bits d'un opérande registre ou mémoire 8 bits.
SAR reg/mem8, imm8 | C0h /7 ib | Cette instruction effectue une décalage du nombre de bits spécifié par la valeur immédiate vers la droite de 8 bits d'un opérande registre ou mémoire 8 bits.
SAR reg/mem16, 1 | D1h /7 | Cette instruction effectue une décalage d'un seul bit vers la droite de 16 bits d'un opérande registre ou mémoire 16 bits.
SAR reg/mem16, CL | D3h /7 | Cette instruction effectue une décalage du nombre de bits spécifié par le registre CL vers la droite de 16 bits d'un opérande registre ou mémoire 16 bits.
SAR reg/mem16, imm8 | C1h /7 ib | Cette instruction effectue une décalage du nombre de bits spécifié par la valeur immédiate vers la droite de 16 bits d'un opérande registre ou mémoire 16 bits.
SAR reg/mem32, 1 | D1h /7 | Cette instruction effectue une décalage d'un seul bit vers la droite de 32 bits d'un opérande registre ou mémoire 32 bits.
SAR reg/mem32, CL | D3h /7 | Cette instruction effectue une décalage du nombre de bits spécifié par le registre CL vers la droite de 32 bits d'un opérande registre ou mémoire 32 bits.
SAR reg/mem32, imm8 | C1h /7 ib | Cette instruction effectue une décalage du nombre de bits spécifié par la valeur immédiate vers la droite de 32 bits d'un opérande registre ou mémoire 32 bits.
SAR reg/mem64, 1 | D1h /7 | Cette instruction effectue une décalage d'un seul bit vers la droite de 64 bits d'un opérande registre ou mémoire 64 bits.
SAR reg/mem64, CL | D3h /7 | Cette instruction effectue une décalage du nombre de bits spécifié par le registre CL vers la droite de 64 bits d'un opérande registre ou mémoire 64 bits.
SAR reg/mem64, imm8 | C1h /7 ib | Cette instruction effectue une décalage du nombre de bits spécifié par la valeur immédiate vers la droite de 64 bits d'un opérande registre ou mémoire 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Voici un exemple en Turbo Pascal montrant l'utilisation de cette instruction :

  1. Program SarSamples;
  3. Function _Sar(Value: Integer ;_Shift: Byte ): Integer ;Assembler; ASM
  4. MOV AX,Value
  5. MOV CL,_Shift
  6. SAR AX,CL
  7. END;
  9. BEGIN
  10. WriteLn ('16 SAR 0 = ',_Sar(16,0));
  11. WriteLn ('16 SAR 1 = ',_Sar(16,1));
  12. WriteLn ('16 SAR 2 = ',_Sar(16,2));
  13. WriteLn ('16 SAR 3 = ',_Sar(16,3));
  14. WriteLn ('16 SAR 4 = ',_Sar(16,4));
  15. WriteLn ('16 SAR 0 = ',_Sar(32,0));
  16. WriteLn ('32 SAR 1 = ',_Sar(32,1));
  17. WriteLn ('32 SAR 2 = ',_Sar(32,2));
  18. WriteLn ('32 SAR 3 = ',_Sar(32,3));
  19. WriteLn ('32 SAR 4 = ',_Sar(32,4));
  20. WriteLn ('32 SAR 4 = ',_Sar(32,4));
  21. END .

on obtiendra le résultat suivant :

16 SAR 0 = 16
16 SAR 1 = 8
16 SAR 2 = 4
16 SAR 3 = 2
16 SAR 4 = 1
16 SAR 0 = 32
32 SAR 1 = 16
32 SAR 2 = 8
32 SAR 3 = 4
32 SAR 4 = 2
32 SAR 4 = 2

Voir également

Instruction assembleur 80x86 - Instruction SAL
Instruction assembleur 80x86 - Instruction SHL
Instruction assembleur 80x86 - Instruction SHR
Instruction assembleur 80x86 - Instruction SHLD
Instruction assembleur 80x86 - Instruction SHRD

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 831
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 416
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 219.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 400 à 408.


Assembleur 80x86

SHL
INTEL 8088+ Shift Left

Syntaxe

SHL opérandecible,nombredebits

Paramètres

Nom | Description
opérandecible | Ce paramètre permet d'indiquer une expression de type entier subissant le «décalage de bits vers la gauche»
nombredebits | Ce paramètre permet d'indiquer le décalage de bit vers la gauche à effectuer

Description

Cette instruction permet d'effectuer une rotation des bits vers la gauche en réinsérant le bit dans l'indicateur de retenue (CF).

Algorithme

temp ← compteur ∩ 001Fh
POUR FAIRE TANT QUE temp1 = 0
CF ← highorder ( destination )
destination ← destination décalage à gauche de 1
temp ← temp - 1
POUR FIN DE FAIRE
SI count = 1 ALORS
OF ← highorder ( destination ) <> CF
SINON
OF ← ?
FIN SI

Mnémonique

Instruction | Opcode | Description
SHL reg/mem8, 1 | D0h /4 | Cette instruction effectue une décalage d'un seul bit vers la gauche de 8 bits d'un opérande registre ou mémoire 8 bits.
SHL reg/mem8, CL | D2h /4 | Cette instruction effectue une décalage du nombre de bits spécifié par le registre CL vers la gauche de 8 bits d'un opérande registre ou mémoire 8 bits.
SHL reg/mem8, imm8 | C0h /4 ib | Cette instruction effectue une décalage du nombre de bits spécifié par la valeur immédiate vers la gauche de 8 bits d'un opérande registre ou mémoire 8 bits.
SHL reg/mem16, 1 | D1h /4 | Cette instruction effectue une décalage d'un seul bit vers la gauche de 16 bits d'un opérande registre ou mémoire 16 bits.
SHL reg/mem16, CL | D3h /4 | Cette instruction effectue une décalage du nombre de bits spécifié par le registre CL vers la gauche de 16 bits d'un opérande registre ou mémoire 16 bits.
SHL reg/mem16, imm8 | C1h /4 ib | Cette instruction effectue une décalage du nombre de bits spécifié par la valeur immédiate vers la gauche de 16 bits d'un opérande registre ou mémoire 16 bits.
SHL reg/mem32, 1 | D1h /4 | Cette instruction effectue une décalage d'un seul bit vers la gauche de 32 bits d'un opérande registre ou mémoire 32 bits.
SHL reg/mem32, CL | D3h /4 | Cette instruction effectue une décalage du nombre de bits spécifié par le registre CL vers la gauche de 32 bits d'un opérande registre ou mémoire 32 bits.
SHL reg/mem32, imm8 | C1h /4 ib | Cette instruction effectue une décalage du nombre de bits spécifié par la valeur immédiate vers la gauche de 32 bits d'un opérande registre ou mémoire 32 bits.
SHL reg/mem64, 1 | D1h /4 | Cette instruction effectue une décalage d'un seul bit vers la gauche de 64 bits d'un opérande registre ou mémoire 64 bits.
SHL reg/mem64, CL | D3h /4 | Cette instruction effectue une décalage du nombre de bits spécifié par le registre CL vers la gauche de 64 bits d'un opérande registre ou mémoire 64 bits.
SHL reg/mem64, imm8 | C1h /4 ib | Cette instruction effectue une décalage du nombre de bits spécifié par la valeur immédiate vers la gauche de 64 bits d'un opérande registre ou mémoire 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Voici un exemple en Turbo Pascal montrant l'utilisation de cette instruction :

  1. Program ShlSamples;
  3. Function _Shl(Value: Integer ;_Shift: Byte ): Integer ;Assembler; ASM
  4. MOV AX,Value
  5. MOV CL,_Shift
  6. SHL AX,CL
  7. END;
  9. BEGIN
  10. WriteLn ('1 SHL 0 = ',_Shl(1,0));
  11. WriteLn ('1 SHL 1 = ',_Shl(1,1));
  12. WriteLn ('1 SHL 2 = ',_Shl(1,2));
  13. WriteLn ('1 SHL 3 = ',_Shl(1,3));
  14. WriteLn ('1 SHL 4 = ',_Shl(1,4));
  15. WriteLn ('2 SHL 0 = ',_Shl(2,0));
  16. WriteLn ('2 SHL 1 = ',_Shl(2,1));
  17. WriteLn ('2 SHL 2 = ',_Shl(2,2));
  18. WriteLn ('2 SHL 3 = ',_Shl(2,3));
  19. WriteLn ('2 SHL 4 = ',_Shl(2,4));
  20. END .

on obtiendra le résultat suivant :

1 SHL 0 = 1
1 SHL 1 = 2
1 SHL 2 = 4
1 SHL 3 = 8
1 SHL 4 = 16
2 SHL 0 = 2
2 SHL 1 = 4
2 SHL 2 = 8
2 SHL 3 = 16
2 SHL 4 = 32

Voir également

Instruction assembleur 80x86 - Instruction SAR
Instruction assembleur 80x86 - Instruction SHR
Instruction assembleur 80x86 - Instruction SHLD
Instruction assembleur 80x86 - Instruction SHRD

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 836
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 415
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 216.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 400 à 408.


Assembleur 80x86

SHR
INTEL 8088+ Shift Right

Syntaxe

SHR opérandecible,nombredebits

Paramètres

Nom | Description
opérandecible | Ce paramètre permet d'indiquer une expression de type entier subissant le «décalage de bits vers la droite»
nombredebits | Ce paramètre permet d'indiquer le décalage de bit vers la droite à effectuer

Description

Cette instruction permet d'effectuer une rotation des bits vers la droite en réinsérant le bit dans l'indicateur de retenue (CF).

Remarque

  • Optimisation : Il est préférable d'utiliser l'instruction SHR plutôt que DIV si vous effectuer des divisions par 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536,... de nombre naturel.

Algorithme

temp ← compteur ∩ 001Fh
BOUCLE FAIRE TANT temp <> 0
x ← highorder ( destination )
CF ← destination ∩ 1
destination ← destination décalage à droite de 1
highorder ( destination ) ← x
temp ← temp - 1
BOUCLE FIN DE FAIRE
SI compteur = 1 ALORS
OF ← 0
SINON
OF ← ?
FIN SI

Mnémonique

Instruction | Opcode | Description
SHR reg/mem8, 1 | D0h /5 | Cette instruction effectue un décalage d'un seul bit vers la droite d'un opérande registre ou mémoire 8 bits.
SHR reg/mem8, CL | D2h /5 | Cette instruction effectue un décalage du nombre de bits spécifié par le registre CL vers la gauche d'un opérande registre ou mémoire 8 bits.
SHR reg/mem8, imm8 | C0h /5 ib | Cette instruction effectue un décalage du nombre de bits spécifié par la valeur immédiate vers la gauche de 8 bits d'un opérande registre ou mémoire 8 bits.
SHR reg/mem16, 1 | D1h /5 | Cette instruction effectue un décalage d'un seul bit vers la droite d'un opérande registre ou mémoire 16 bits.
SHR reg/mem16, CL | D3h /5 | Cette instruction effectue un décalage du nombre de bits spécifié par le registre CL vers la gauche d'un opérande registre ou mémoire 16 bits.
SHR reg/mem16, imm8 | C1h /5 ib | Cette instruction effectue un décalage du nombre de bits spécifié par la valeur immédiate vers la gauche de 8 bits d'un opérande registre ou mémoire 16 bits.
SHR reg/mem32, 1 | D1h /5 | Cette instruction effectue un décalage d'un seul bit vers la droite d'un opérande registre ou mémoire 32 bits.
SHR reg/mem32, CL | D3h /5 | Cette instruction effectue un décalage du nombre de bits spécifié par le registre CL vers la gauche d'un opérande registre ou mémoire 32 bits.
SHR reg/mem32, imm8 | C1h /5 ib | Cette instruction effectue un décalage du nombre de bits spécifié par la valeur immédiate vers la gauche de 8 bits d'un opérande registre ou mémoire 32 bits.
SHR reg/mem64, 1 | D1h /5 | Cette instruction effectue un décalage d'un seul bit vers la droite d'un opérande registre ou mémoire 64 bits.
SHR reg/mem64, CL | D3h /5 | Cette instruction effectue un décalage du nombre de bits spécifié par le registre CL vers la gauche d'un opérande registre ou mémoire 64 bits.
SHR reg/mem64, imm8 | C1h /5 ib | Cette instruction effectue un décalage du nombre de bits spécifié par la valeur immédiate vers la gauche de 8 bits d'un opérande registre ou mémoire 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Voici un exemple en Turbo Pascal montrant l'utilisation de cette instruction :

  1. Program ShrSamples;
  3. Function _Shr(Value: Integer ;_Shift: Byte ): Integer ;Assembler; ASM
  4. MOV AX,Value
  5. MOV CL,_Shift
  6. SHR AX,CL
  7. END;
  9. BEGIN
  10. WriteLn ('16 SHR 0 = ',_Shr(16,0));
  11. WriteLn ('16 SHR 1 = ',_Shr(16,1));
  12. WriteLn ('16 SHR 2 = ',_Shr(16,2));
  13. WriteLn ('16 SHR 3 = ',_Shr(16,3));
  14. WriteLn ('16 SHR 4 = ',_Shr(16,4));
  15. WriteLn ('16 SHR 0 = ',_Shr(32,0));
  16. WriteLn ('32 SHR 1 = ',_Shr(32,1));
  17. WriteLn ('32 SHR 2 = ',_Shr(32,2));
  18. WriteLn ('32 SHR 3 = ',_Shr(32,3));
  19. WriteLn ('32 SHR 4 = ',_Shr(32,4));
  20. WriteLn ('32 SHR 4 = ',_Shr(32,4));
  21. END .

on obtiendra le résultat suivant :

16 SHR 0 = 16
16 SHR 1 = 8
16 SHR 2 = 4
16 SHR 3 = 2
16 SHR 4 = 1
16 SHR 0 = 32
32 SHR 1 = 16
32 SHR 2 = 8
32 SHR 3 = 4
32 SHR 4 = 2
32 SHR 4 = 2

Voir également

Instruction assembleur 80x86 - Instruction SHL
Instruction assembleur 80x86 - Instruction SAL
Instruction assembleur 80x86 - Instruction SAR
Instruction assembleur 80x86 - Instruction SHLD
Instruction assembleur 80x86 - Instruction SHRD

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 836
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 417
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 231.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 400 à 408.


Voici les instructions assembleur classés par catégorie de drapeaux :

Instruction | Description | CPU/MPU
BT | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue. | INTEL 80386+
BTC | Cette instruction transfère une Opérande vers l'indicateur de retenue le bits spécifié et inverser la valeur du bit correspondant. | INTEL 80386+
BTR | Cette instruction permet de transférer l'Opérande vers l'indicateur de retenue le bits spécifié puis met le bits correspondant de l'Opérande à 0. | INTEL 80386+
BTS | Cette instruction permet de transférer une Opérande vers l'indicateur de retenue le bits spécifié puis ensuite met le bits correspondant dans Opérande à 1. | INTEL 80386+
CLC | Cette instruction permet de mettre l'indicateur d'état de retenu CF à 0. | INTEL 8088+
CLD | Cette instruction met l'indicateur d'état DF à 0. | INTEL 8088+
CLI | Cette instruction met l'indicateur d'état IF à 0. | INTEL 8088+
CLTS | Cette instruction permet de mettre à 0 le drapeau de l'indicateur de tâche (Task-Switch) du registre CR0. | INTEL 80286+
CMC | Cette instruction offre la possibilité d'inverser la valeur de l'indicateur de retenue. Si ce dernier vaut 1, elle le met à 0 et inversement. | INTEL 8088+
LAHF | Cette instruction permet de transférer les bits d'indicateurs du registre d'état vers le registre AH. | INTEL 8086+
POPF | Cette instruction permet de désempiler de la pile le registre 16 bits de drapeau contenant les indicateurs d'état. | INTEL 8086+
POPFD | Cette instruction permet de désempiler de la pile le registre 32 bits de drapeau contenant les indicateurs d'état. | INTEL 80386+
PUSHF | Cette instruction permet d'empiler respectivement le registre 16 bits de drapeau des indicateurs d'état dans la pile. | INTEL 8086+
PUSHFD | Cette instruction permet d'empiler respectivement le registre 32 bits de drapeau des indicateurs d'état dans la pile. | INTEL 80386+
SAHF | Cette instruction permet de copier les bits du registre AH dans l'octet de poids faible dans le registre des drapeaux (les indicateurs d'état). | INTEL 8088+
STC | Cette instruction permet de fixer l'indicateur de retenue (CF) à la valeur 1. | INTEL 8088+
STD | Cette instruction permet de fixer l'indicateur de direction (DF) à la valeur 1. | INTEL 8088+
STI | Cette instruction permet de fixer l'indicateur d'interruption (IF) à la valeur 1. | INTEL 8088+

Dernière mise à jour : Vendredi, le 4 mars 2016


Assembleur 80x86

BT
INTEL 80386+ Bit Test

Syntaxe

BT Opérande Source 1, Opérande Source 2

Description

Cette instruction permet de transférer de l'Opérande Source 1 vers l'indicateur de retenue, le bit spécifié par l'Opérande Source 2. Les opérandes utilisés peuvent être soit 16 ou 32 bits.

Algorithme

drapeau CF ← BIT [ Opérande Source 1, Opérande Source 2 ]

Remarque

    Processeur INTEL: Quand vous faites des accès en bits dans la mémoire, le microprocesseur fabriquer par le constructeur INTEL effectue des accès en mémoire d'adressage sous la forme suivante:

    Adresse ← Segment + ( 4 x ( Bit d'offset ÷ 32 ) )

    Tandis que dans le cas d'une opérande de taille de 32 bits, ou lorsque vous faîtes des accès mémoire de 2 octets (16 bits), il utilise plutôt la forme suivante:

    Adresse ← Segment + ( 2 x ( Bit d'offset ÷ 16 ) )

    Également, lorsqu'il y a 1 octets, il faut appliquer l'opération en tenant compte du 8 bits:

    Adresse ← Segment + ( 1 x ( Bit d'offset ÷ 8 ) )

    Il y a donc au proportionnalité de la division en fonction de la dimension de l'accès en mémoire.

Mnémonique

Instruction | Opcode | Description
BT reg/mem16, reg16 | 0Fh A3h /r | Copie la valeur de sélection de bit dans le drapeau de retenu
BT reg/mem32, reg32 | 0Fh A3h /r | Copie la valeur de sélection de bit dans le drapeau de retenu
BT reg/mem64, reg64 | 0Fh A3h /r | Copie la valeur de sélection de bit dans le drapeau de retenu
BT reg/mem16, imm8 | 0Fh BAh /4 ib | Copie la valeur de sélection de bit dans le drapeau de retenu
BT reg/mem32, imm8 | 0Fh BAh /4 ib | Copie la valeur de sélection de bit dans le drapeau de retenu
BT reg/mem64, imm8 | 0Fh BAh /4 ib | Copie la valeur de sélection de bit dans le drapeau de retenu

Cycles d'horloge

Instruction | Opcode | 8086 | 8088 | 80186 | 80286 | 80386 | i486 | Pentium | Cx486SLC | Cx486DX | IBM 486BL3X | UMC U5S
BT reg16, imm8 | 0Fh BAh /4 ib |  |  |  |  | 3 | 3 | ? | ? | ? | ? | ?
BT mem16, imm8 | 0Fh BAh /4 ib |  |  |  |  | 12 | 6 | ? | ? | ? | ? | ?
BT reg16, reg16 | 0Fh A3h /r |  |  |  |  | 3 | 3 | ? | ? | ? | ? | ?
BT mem16, reg16 | 0Fh A3h /r |  |  |  |  | 12 | 12 | ? | ? | ? | ? | ?

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction BTC
Instruction assembleur 80x86 - Instruction BTR
Instruction assembleur 80x86 - Instruction BTS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 804
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 68 à 69.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 156 à 158.


Assembleur 80x86

BTC
INTEL 80386+ Bit Test and Complement

Syntaxe

BTC Opérande Source 1, Opérande Source 2

Description

Cette instruction offre la possibilité de transférer tout d'abord de l'Opérande Source 1 vers l'indicateur de retenue le bits spécifié par l'Opérande Source 2 puis d'ensuite inverser la valeur du bit correspondant dans l'Opérande Source 1. Les opérandes utilisés peuvent être soit sur 16 ou 32 bits. Il est possible d'associer 2 registres, un registre à un emplacement mémoire, un registre ou un emplacement mémoire à un registre ou à une valeur immédiate.

Algorithme

drapeau CF ← BIT [ Opérande Source 1, Opérande Source 2 ]
BIT [ Opérande Source 1, Opérande Source 2 ] ← Pas BIT [ Opérande Source 1, Opérande Source 2 ]

Remarque

    Processeur INTEL: Quand vous faites des accès en bits dans la mémoire, le microprocesseur fabriquer par le constructeur INTEL effectue des accès en mémoire d'adressage sous la forme suivante:

    Adresse ← Segment + ( 4 x ( Bit d'offset ÷ 32 ) )

    Tandis que dans le cas d'une opérande de taille de 32 bits, ou lorsque vous faîtes des accès mémoire de 2 octets (16 bits), il utilise plutôt la forme suivante:

    Adresse ← Segment + ( 2 x ( Bit d'offset ÷ 16 ) )

    Également, lorsqu'il y a 1 octets, il faut appliquer l'opération en tenant compte du 8 bits:

    Adresse ← Segment + ( 1 x ( Bit d'offset ÷ 8 ) )

    Il y a donc au proportionnalité de la division en fonction de la dimension de l'accès en mémoire.

Mnémonique

Instruction | Opcode | Description
BTC reg/mem16, reg16 | 0Fh BBh /r | Copie la valeur du bit de sélection dans le drapeau de retenu et complémente le bit de sélection.
BTC reg/mem32, reg32 | 0Fh BBh /r | Copie la valeur du bit de sélection dans le drapeau de retenu et complémente le bit de sélection.
BTC reg/mem64, reg64 | 0Fh BBh /r | Copie la valeur du bit de sélection dans le drapeau de retenu et complémente le bit de sélection.
BTC reg/mem16, imm8 | 0Fh BAh /7 ib | Copie la valeur du bit de sélection dans le drapeau de retenu et complémente le bit de sélection.
BTC reg/mem32, imm8 | 0Fh BAh /7 ib | Copie la valeur du bit de sélection dans le drapeau de retenu et complémente le bit de sélection.
BTC reg/mem64, imm8 | 0Fh BAh /7 ib | Copie la valeur du bit de sélection dans le drapeau de retenu et complémente le bit de sélection.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction BT
Instruction assembleur 80x86 - Instruction BTR
Instruction assembleur 80x86 - Instruction BTS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 805
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 70 à 71.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 159 à 161.


Assembleur 80x86

BTR
INTEL 80386+ Bit Test and Reset

Syntaxe

BTR Opérande Source 1, Opérande Source 2

Description

Cette instruction permet de transférer tout d'abord de l'Opérande Source 1 vers l'indicateur de retenue le bits spécifié par l'Opérande Source 2 puis met le bits correspondant de l'Opérande Source 1 à 0. Les opérandes utilisés peuvent être soit sur 16 ou 32 bits.

Algorithme

drapeau CF ← BIT [ Opérande Source 1, Opérande Source 2 ]
BIT [ Opérande Source 1, Opérande Source 2 ] ← 0

Remarque

    Processeur INTEL: Quand vous faites des accès en bits dans la mémoire, le microprocesseur fabriquer par le constructeur INTEL effectue des accès en mémoire d'adressage sous la forme suivante:

    Adresse ← Segment + ( 4 x ( Bit d'offset ¸ 32 ) )

    Tandis que dans le cas d'une opérande de taille de 32 bits, ou lorsque vous faîtes des accès mémoire de 2 octets (16 bits), il utilise plutôt la forme suivante:

    Adresse ← Segment + ( 2 x ( Bit d'offset ¸ 16 ) )

    Également, lorsqu'il y a 1 octets, il faut appliquer l'opération en tenant compte du 8 bits:

    Adresse ← Segment + ( 1 x ( Bit d'offset ¸ 8 ) )

    Il y a donc au proportionnalité de la division en fonction de la dimension de l'accès en mémoire.

Mnémonique

Instruction | Opcode | Description
BTR reg/mem16, reg16 | 0Fh B3h /r | Copie la valeur du bit de sélection dans le drapeau de retenu et efface le bit de sélection.
BTR reg/mem32, reg32 | 0Fh B3h /r | Copie la valeur du bit de sélection dans le drapeau de retenu et efface le bit de sélection.
BTR reg/mem64, reg64 | 0Fh B3h /r | Copie la valeur du bit de sélection dans le drapeau de retenu et efface le bit de sélection.
BTR reg/mem16, imm8 | 0Fh BAh /6 ib | Copie la valeur du bit de sélection dans le drapeau de retenu et efface le bit de sélection.
BTR reg/mem32, imm8 | 0Fh BAh /6 ib | Copie la valeur du bit de sélection dans le drapeau de retenu et efface le bit de sélection.
BTR reg/mem64, imm8 | 0Fh BAh /6 ib | Copie la valeur du bit de sélection dans le drapeau de retenu et efface le bit de sélection.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction BT
Instruction assembleur 80x86 - Instruction BTC
Instruction assembleur 80x86 - Instruction BTS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 805
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 72.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 162 à 164.


Assembleur 80x86

BTS
INTEL 80386+ Bit Test and Set

Syntaxe

BTS Opérande Source 1, Opérande Source 2

Description

Cette instruction permet de transférer tout d'abord de Opérande Source1 vers l'indicateur de retenue le bits spécifié par Opérande Source 2 puis ensuite met le bits correspondant dans Opérande Source 1 à 1. Les opérandes utilisés peuvent être sur soit 16 ou 32 bits.

Algorithme

drapeau CF ← BIT ( Opérande Source 1, Opérande Source 2 )
BIT ( Opérande Source 1, Opérande Source 2 ) ← 1

Remarque

    Processeur INTEL: Quand vous faites des accès en bits dans la mémoire, le microprocesseur fabriquer par le constructeur INTEL effectue des accès en mémoire d'adressage sous la forme suivante:

    Adresse ← Segment + ( 4 x ( Bit d'offset ¸ 32 ) )

    Tandis que dans le cas d'une opérande de taille de 32 bits, ou lorsque vous faîtes des accès mémoire de 2 octets (16 bits), il utilise plutôt la forme suivante:

    Adresse ← Segment + ( 2 x ( Bit d'offset ¸ 16 ) )

    Également, lorsqu'il y a 1 octets, il faut appliquer l'opération en tenant compte du 8 bits:

    Adresse ← Segment + ( 1 x ( Bit d'offset ¸ 8 ) )

    Il y a donc au proportionnalité de la division en fonction de la dimension de l'accès en mémoire.

Mnémonique

Instruction | Opcode | Description
BTS reg/mem16, reg16 | 0Fh ABh /r | Copie la valeur du bit de sélection dans le drapeau de retenu et fixe le bit de sélection.
BTS reg/mem32, reg32 | 0Fh ABh /r | Copie la valeur du bit de sélection dans le drapeau de retenu et fixe le bit de sélection.
BTS reg/mem64, reg64 | 0Fh ABh /r | Copie la valeur du bit de sélection dans le drapeau de retenu et fixe le bit de sélection.
BTS reg/mem16, imm8 | 0Fh BAh /5 ib | Copie la valeur du bit de sélection dans le drapeau de retenu et fixe le bit de sélection.
BTS reg/mem32, imm8 | 0Fh BAh /5 ib | Copie la valeur du bit de sélection dans le drapeau de retenu et fixe le bit de sélection.
BTS reg/mem64, imm8 | 0Fh BAh /5 ib | Copie la valeur du bit de sélection dans le drapeau de retenu et fixe le bit de sélection.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction BT
Instruction assembleur 80x86 - Instruction BTC
Instruction assembleur 80x86 - Instruction BTR

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 805
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 72 à 73.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 165 à 167.


Assembleur 80x86

CLC
INTEL 8088+ Clear Carry Flag

Syntaxe

CLC

Description

Cette instruction permet de mettre l'indicateur d'état de retenu CF à 0.

Algorithme

drapeau CF ← 0

Remarque

    A titre purement informatif, sachez que ce registre d'état de retenue est toujours égal à 1 lorsqu'une opération génère une retenue arithmétique et qu'il est par conséquent impossible de représenter le résultat qu'avec l'aide des bits disponibles. Dans ce éventualité, l'indicateur de retenue est considéré comme 17ième ou 9ième bit du résultat. C'est surtout dans la perspective des instructions ADC et SBB que le positionnement à 0 de l'indicateur de retenue s'avère utile. Dans les autres cas, l'interruption 21h du système d'exploitation sans servira pour indiquer s'il y a eu une erreur d'exécution, toutefois ce n'est pas une situation relier directement au microprocesseur mais une programmation logiciel.

Mnémonique

Instruction | Opcode | Description
CLC | F8h | Efface le drapeau de retenu (CF) à 0

Exceptions

Aucune

Voir également

Instruction assembleur 80x86 - Instruction STC
Instruction assembleur 80x86 - Instruction CMC

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 807
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 402
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 86.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 189 à 189.


Assembleur 80x86

CLD
INTEL 8088+ Clear Direction Flag

Syntaxe

CLD

Description

Cette instruction met l'indicateur d'état DF à 0. Les opérations sur les chaînes de caractères, tel CMPSB, CMPSD, CMPSQ, CMPSW, LODSB, LODSD, LODSQ, LODSW, MOVSB, MOVSD, MOVSQ, MOVSW, OUTSB, OUTSD, OUTSW, STOSB, STOSD, STOSQ et STOSW par exemple, incrémenteront maintenant les registres SI et DI.

Algorithme

drapeau DF ← 0

Mnémonique

Instruction | Opcode | Description
CLD | FCh | Efface le drapeau de direction (DF) à 0

Exceptions

Aucune

Voir également

Instruction assembleur 80x86 - Instruction CMPS
Instruction assembleur 80x86 - Instruction INS
Instruction assembleur 80x86 - Instruction LODS
Instruction assembleur 80x86 - Instruction MOVS
Instruction assembleur 80x86 - Instruction OUTS
Instruction assembleur 80x86 - Instruction SCAS
Instruction assembleur 80x86 - Instruction STD
Instruction assembleur 80x86 - Instruction STOS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 807
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 402
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 87.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 190 à 190.


Assembleur 80x86

CLI
INTEL 8088+ Clear Interrupt Flag

Syntaxe

CLI

Description

Cette instruction met l'indicateur d'état IF à 0. Après avoir exécuter cette instruction, aucune interruption ne sera admise tant que l'instruction STI n'est pas rencontrée.

Algorithme

drapeau IF ← 0

Mnémonique

Instruction | Opcode | Description
CLI | FAh | Efface le drapeau d'interruption (IF) et le met à 0.

Cycles d'horloge

Instruction | Opcode | 8086 | 8088 | 80186 | 80286 | 80386 | i486 | Pentium | Cx486SLC | Cx486DX | IBM 486BL3X | UMC U5S
CLI | FAh | 2 | ? | ? | 2 | 3 | 5 | 7 | 7 | 7 | ? | ?

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) |  | X |  | Le CPL est supérieur au IOCPL et les extensions du mode virtuel sont désactivés (CR4.VME=0).
 |  |  | X | Le CPL est supérieur au IOCPL et le CPL n'est pas 3 ou l'interruption du mode protégé virtuel n'est pas activé (CR4.PVI=0).

Remarque

    Afin que les choses soit bien claire, sachez que même si ce registre d'état d'interruption est mit à 0, le microprocesseur ne masque pas les interruptions de type NMI (Non masquable Interruption). La commande CLI vise donc à faire en sorte que toutes les interruptions masquables ne soient plus exécutées. Cette interdiction peut être levée à l'aide de la commande STI.

Exemple

Cet exemple, destiné au mode réel, permet de retourner 1 dans le registre AL si la touche «ALT» du clavier est enfoncé ou 0 s'il ne l'est pas :

  1. XOR AX,AX
  2. MOV ES,AX
  3. CLI
  4. MOV AL,ES:[417h]
  5. STI
  6. AND AL,8
  7. JZ @@End
  8. MOV AL,1
  9. @@End:

Voir également

Instruction assembleur 80x86 - Instruction STI

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 807
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 402
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 255.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 193 à 195.


Assembleur 80x86

CLTS
INTEL 80286+ (Mode protégé) CLear Task-Switched flags in CR0

Syntaxe

CLTS

Description

Cette instruction permet d'effacer ou si vous préférez de mettre à 0 le drapeau de l'indicateur de tâche (Task-Switch) du registre CR0.

Algorithme

drapeau TS ← 0

Mnémonique

Instruction | Opcode | Description
CLTS | 0Fh 06h | Efface le drapeau d'échangeur de tâche (TS) du registre CR0

Cycles d'horloge

Instruction | Opcode | 8086 | 8088 | 80186 | 80286 | 80386 | i486 | Pentium | Cx486SLC | Cx486DX | IBM 486BL3X | UMC U5S
CLTS | 0Fh 06h |  |  |  | 2 | 5 | 7 | ? | ? | ? | ? | ?

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#GP(Protection général) |  | X | X | Le CPL ne vaut pas 0.

Voir également

Instruction assembleur 80x86 - Instruction LMSW

Références

Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 196 à 197.


Assembleur 80x86

CMC
INTEL 8088+ Complement Carry Flag

Syntaxe

CMC

Description

Cette instruction offre la possibilité d'inverser la valeur de l'indicateur de retenue. Si ce dernier vaut 1, elle le met à 0 et inversement. On utilise cette instruction surtout dans le cas des additions et des soustractions.

Algorithme

drapeau CF ← PAS drapeau CF

Mnémonique

Instruction | Opcode | Description
CMC | F5h | Complément du drapeau de retenue (CF)

Exceptions

Aucune

Voir également

Instruction assembleur 80x86 - Instruction CLC
Instruction assembleur 80x86 - Instruction STC

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 807
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 90.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 198 à 198.


Assembleur 80x86

LAHF
INTEL 8088+ Load AH in Flags

Syntaxe

LAHF

Description

Cette instruction permet de transférer les bits d'indicateurs du registre d'état vers le registre AH.

Algorithme

AH ← Registre de drapeaux(7..0)

Mnémonique

Instruction | Opcode | Description
LAHF | 9Fh | Charge les drapeaux SF, ZF, AF, PF et CF dans le registre AH

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) |  |  | X | Cette instruction n'est pas supporté en mode 64-bits comme indiquer par le bit 0 du registre ECX par la fonction 8000_0001h de l'instruction CPUID.

Voir également

Langage de programmation - Assembleur 80x86 - Lexique et dictionnaire d'instruction assembleur 80x86 -Instruction SAHF

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 816
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 409
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 142.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 630 à 631.


Assembleur 80x86

POPF
INTEL 8088+ Pop Flags

Syntaxe

POPF

Description

Cette instruction permet de désempiler de la pile le registre 16 bits de drapeau contenant les indicateurs d'état.

Algorithme

Registre de drapeaux ← SS:(E)SP
(E)SP ← (E)SP + 2

Mnémonique

Instruction | Opcode | Description
POPF | 9Dh | Désempile le mot de la pile et la met dans le registres des drapeaux (FLAGS).

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) |  | X |  | Le niveau de privilège d'entrée/sortie est inférieur à 3 et CR4.VME vaut 0.
 |  | X |  | Le niveau de privilège d'entrée/sortie est inférieur à 3 et une opérande est de taille de 32 bits.
 |  | X |  | Le niveau de privilège d'entrée/sortie est inférieur à 3 et les bits EFLAGS.VIP et le nouveau EFLAGS.IF valent 1.
 |  | X |  | Le niveau de privilège d'entrée/sortie est inférieur à 3 et le nouveau EFLAGS.TF vaut 1.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction PUSHF
Instruction assembleur 80x86 - Instruction PUSHFD
Instruction assembleur 80x86 - Instruction PUSHFQ

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 826
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 412
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 234 à 237.
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 190.


Assembleur 80x86

POPFD
INTEL 80386+ Pop Flags Double

Syntaxe

POPFD

Description

Cette instruction permet de désempiler de la pile le registre 32 bits de drapeau contenant les indicateurs d'état.

Algorithme

Registre de drapeaux ← SS:(E)SP
(E)SP ← (E)SP + 4

Mnémonique

Instruction | Opcode | Description
POPFD | 9Dh | Désempile le double mot de la pile et la met dans le registres 32 bits des drapeaux (EFLAGS). Il n'y a pas de préfix en mode 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) |  | X |  | Le niveau de privilège d'entrée/sortie est inférieur à 3 et CR4.VME vaut 0.
 |  | X |  | Le niveau de privilège d'entrée/sortie est inférieur à 3 et une opérande est de taille de 32 bits.
 |  | X |  | Le niveau de privilège d'entrée/sortie est inférieur à 3 et les bits EFLAGS.VIP et le nouveau EFLAGS.IF valent 1.
 |  | X |  | Le niveau de privilège d'entrée/sortie est inférieur à 3 et le nouveau EFLAGS.TF vaut 1.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction PUSHF
Instruction assembleur 80x86 - Instruction PUSHFD
Instruction assembleur 80x86 - Instruction PUSHFQ

Références

Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 234 à 237.


Assembleur 80x86

PUSHF
INTEL 8088+ Push Flags

Syntaxe

PUSHF

Description

Cette instruction permet d'empiler respectivement le registre 16 bits de drapeau des indicateurs d'état dans la pile.

Algorithme

(E)SP ← (E)SP - 2
SS:(E)SP ← Registre de drapeaux (FLAGS)

Mnémonique

Instruction | Opcode | Description
PUSHF | 9Ch | Empile le mot du registre de drapeaux 16 bits (FLAGS) dans la pile.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection générale) |  | X |  | Le niveau de privilège d'entrée/sortie est inférieur à 3 et le VME n'est pas actif ou la taille de l'opérande n'est pas 16 bits.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction POPF
Instruction assembleur 80x86 - Instruction POPFD
Instruction assembleur 80x86 - Instruction POPFQ

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 827
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 413
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 200.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 328 à 330.


Assembleur 80x86

PUSHFD
INTEL 80386+ Push Flags Double

Syntaxe

PUSHFD

Description

Cette instruction permet d'empiler respectivement le registre 32 bits de drapeau des indicateurs d'état dans la pile.

Algorithme

(E)SP ← (E)SP - 4
SS:(E)SP ← Registre de drapeaux (EFLAGS)

Mnémonique

Instruction | Opcode | Description
PUSHFD | 9Ch | Empile le double mot du registre de drapeaux 32 bits (EFLAGS) dans la pile.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection générale) |  | X |  | Le niveau de privilège d'entrée/sortie est inférieur à 3 et le VME n'est pas actif ou la taille de l'opérande n'est pas 16 bits.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction POPF
Instruction assembleur 80x86 - Instruction POPFD
Instruction assembleur 80x86 - Instruction POPFQ

Références

Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 328 à 330.


Assembleur 80x86

SAHF
INTEL 8088+ Store AH Into Flags

Syntaxe

SAHF

Description

Cette instruction permet de copier les bits du registre AH dans l'octet de poids faible dans le registre des drapeaux (les indicateurs d'état).

Algorithme

Registre de drapeaux ← Registre de drapeaux ∩ ¬ 0D5h + ( AH ∩ D5h )

Mnémonique

Instruction | Opcode | Description
SAHF | 9Eh | Copie le drapeau de signe, de zéro, auxiliaire, de parité et de retenue dans le registre AH.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) |  |  | X | Cette instruction n'est pas supporté en mode 64 bits, comme indiqué par le bit 0 du registre ECX de la fonction 8000_00001h de l'instruction CPUID.

Voir également

Instruction assembleur 80x86 - Instruction LAHF

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 831
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 416
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 215.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 398 à 399.


Assembleur 80x86

STC
INTEL 8088+ Set Carry Flag

Syntaxe

STC

Description

Cette instruction permet de fixer l'indicateur de retenue (CF) à la valeur 1.

Algorithme

drapeau CF ← 1

Remarque

    A titre purement informatif, sachez que ce registre d'état de retenue est toujours égal à 1 lorsqu'une opération génère une retenue arithmétique et qu'il est par conséquent impossible de représenter le résultat qu'avec l'aide des bits disponibles. Dans ce éventualité, l'indicateur de retenue est considéré comme 17ième ou 9ième bit du résultat. C'est surtout dans la perspective des instructions ADC et SBB que le positionnement à 0 de l'indicateur de retenue s'avère utile. Dans les autres cas, l'interruption 21h du système d'exploitation sans servira pour indiquer s'il y a eu une erreur d'exécution, toutefois ce n'est pas une situation relier directement au microprocesseur mais une programmation logiciel.

Mnémonique

Instruction | Opcode | Description
STC | F9h | Fixe le registre de drapeau de retenue à 1

Exception

Aucune

Voir également

Instruction assembleur 80x86 - Instruction CLC
Instruction assembleur 80x86 - Instruction CMC

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 836
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 417
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 235.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 461.


Assembleur 80x86

STD
INTEL 8088+ Set Direction Flag

Syntaxe

STD

Description

Cette instruction permet de fixer l'indicateur de direction (DF) à la valeur 1. Les opérations sur les chaînes de caractères, tel CMPSB, CMPSD, CMPSQ, CMPSW, LODSB, LODSD, LODSQ, LODSW, MOVSB, MOVSD, MOVSQ, MOVSW, OUTSB, OUTSD, OUTSW, STOSB, STOSD, STOSQ et STOSW par exemple, incrémenteront maintenant les registres SI et DI.

Algorithme

drapeau DF ← 1

Mnémonique

Instruction | Opcode | Description
STD | F9h | Fixe le registre de drapeau de direction à 1

Exception

Aucune

Voir également

Instruction assembleur 80x86 - Instruction CLD
Instruction assembleur 80x86 - Instruction INS
Instruction assembleur 80x86 - Instruction LODS
Instruction assembleur 80x86 - Instruction MOVS
Instruction assembleur 80x86 - Instruction OUTS
Instruction assembleur 80x86 - Instruction SCAS
Instruction assembleur 80x86 - Instruction STOS
Instruction assembleur 80x86 - Instruction CMPS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 836
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 417
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 236.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 462.


Assembleur 80x86

STI
INTEL 8088+ Set Interrupt Flag

Syntaxe

STI

Description

Cette instruction permet de fixer l'indicateur d'interruption (IF) à la valeur 1. Après avoir exécuter cette instruction, aucune interruption ne sera admise tant que l'instruction STI n'est pas rencontrée.

Algorithme

SI CPL <= IOPL ALORS
drapeau IF ← 1
SINON SI (((VIRTUAL_MODE) ET (CR4.VME = 1)) OU ((PROTECTED_MODE) ET (CR4.PVI = 1) ET (CPL = 3))) ALORS
SI RFLAGS.VIP = 1 ALORS
EXCEPTION #GP(0)
FIN SI
RFLAGS.VIF ← 1
SINON
EXCEPTION #GP(0)
FIN SI

Remarque

    Afin que les choses soit bien claire, sachez que même si ce registre d'état d'interruption est mit à 0, le microprocesseur ne masque pas les interruptions de type NMI (Non masquable Interruption). La commande CLI vise donc à faire en sorte que toutes les interruptions masquables ne soient plus exécutées. Cette interdiction peut être levée à l'aide de la commande STI.

Mnémonique

Instruction | Opcode | Description
STI | FBh | Cette instruction permet de fixer l'indicateur d'interruption (IF) à la valeur 1.

Exemple

Cet exemple, en Turbo Pascal, permet de vérifier si la touche «ALT» du clavier est enfoncé :

  1. Program AltPressSamples;
  3. Function IsAltPressed: Boolean ;Assembler; ASM
  4. XOR AX,AX
  5. MOV ES,AX
  6. CLI
  7. MOV AL,ES:[417h]
  8. STI
  9. AND AL,8
  10. JZ @@End
  11. MOV AL,1
  12. @@End:
  13. END;
  15. BEGIN
  16. If (IsAltPressed)Then WriteLn ('Alt enfoncé')
  17. Else WriteLn ('Alt n''est pas enfoncé');
  18. END .

Voir également

Instruction assembleur 80x86 - Instruction CLI

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 836
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 417
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 305.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 463 à 465.


Voici les instructions assembleur classés par catégorie d'opérateurs :

Instruction | Description | CPU/MPU
ADC | Cette instruction additionne 2 quantités numériques sur 8 ou 16 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF (CARRY FLAG), à la somme obtenu. | INTEL 8088+
ADD | Cette instruction additionne 2 quantités numérique sur 8 ou 16 bits. | INTEL 8088+
AND | Cette instruction permet d'effectuer un ET BINAIRE sur les 2 opérandes spécifiés. | INTEL 8088+
DEC | Cette instruction décrément de 1 le registre ou l'adresse mémoire spécifié. | INTEL 8088+
DIV | Cette instruction permet d'effectuer une division non-signée (nombre naturel). | INTEL 8088+
FDIV | Cette instruction offre la possibilité d'effectuer des division de nombre réel de valeur positive. | INTEL MPU 8087+
FDIVP | Cette instruction offre la possibilité d'effectuer des division de nombre réel et place ST(0) dans la pile. | INTEL MPU 8087+
FDIVR | Cette instruction offre la possibilité d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source». | INTEL MPU 8087+
FDIVRP | Cette instruction offre la possibilité d'effectuer des division de nombre réel avec les registres inversés «cible» par «source» et place ST(0) dans la pile. | INTEL MPU 8087+
FIADD | Cette instruction offre l'essentiel possibilité d'ajoute le nombre réel source à cible et enregistre la somme dans cible. | INTEL MPU 8087+
FIDIV | Cette instruction offre la possibilité d'effectuer des division de nombre réel. | INTEL MPU 8087+
FIDIVR | Cette instruction offre la possibilité d'effectuer des division de nombre réel avec les registres inversés «cible» par «source». | INTEL MPU 8087+
FIMUL | Cette instruction permet de multiplier le nombre réel «source» par «cible» et sauvegarde le résultat dans «cible». | INTEL MPU 8087+
FISUB | Cette instruction offre l'essentielle possibilité de soustraire le nombre «source» du registre ST(0). | INTEL MPU 8087+
FISUBR | Cette instruction offre l'essentielle possibilité de soustraire le nombre du registre ST(0) de «source». | INTEL MPU 8087+
FMUL | Cette instruction permet de multiplier le nombre réel de valeur positive «source» par «cible» et sauvegarde le résultat dans «cible». | INTEL MPU 8087+
FMULP | Cette instruction permet de multiplier le nombre réel de valeur positive «source» par «cible» et sauvegarde le résultat dans «cible» et prend ensuite ST(0) dans la pile de registres. | INTEL MPU 8087+
FSUB | Cette instruction permet de soustraire un nombre entier du registre ST(0). | INTEL MPU 8087+
FSUBPP | Cette instruction permet de soustraire un nombre entier du registre ST(0) et copie le registre ST(0) dans la pile de registres. | INTEL MPU 8087+
FSUBR | Cette instruction permet de soustraire le registre ST(0) du nombre entier et place le résultat dans le registre ST(0). | INTEL MPU 8087+
FSUBRP | Cette instruction permet de soustraire le registre ST(0) du nombre entier et place le résultat dans le registre ST(0) et copie le registre ST(0) dans la pile de registres. | INTEL MPU 8087+
IDIV | Cette instruction permet d'effectuer une division signée (nombre entier). | INTEL 8086+
IMUL | Cette instruction permet d'effectuer une multiplication signée (nombre entier). | INTEL 8086+
INC | Cette instruction permet d'incrémenter un registre ou un emplacement mémoire. | INTEL 8086+
MUL | Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). | INTEL 8086+
NEG | Cette instruction permet d'effectuer le complément à 2 d'une opérande. | INTEL 8086+
NOT | Cette instruction permet d'inverser la valeur de chacun des bits d'une opérande. | INTEL 8086+
OR | Cette instruction permet d'effectuer un OU BINAIRE sur les 2 opérandes spécifiés. | INTEL 8086+
SBB | Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande. | INTEL 8088+
SUB | Cette instruction permet de soustraire une valeur à une opérande. | INTEL 8088+
XOR | Cette instruction permet d'effectuer un OU exclusif BINAIRE sur les 2 opérandes spécifiés. | INTEL 8086+

Dernière mise à jour : Vendredi, le 4 mars 2016


Assembleur 80x86

ADC
INTEL 8088+ arithmetic Add with Carry

Syntaxe

ADC Opérande Cible,Opérande Source

Paramètres

Nom | Description
Opérande Cible | Ce paramètre permet d'indiquer l'opérande recevant le résultat
Opérande Source | Ce paramètre permet d'indiquer l'opérande à ajouter au résultat

Description

Cette instruction, des plus indispensable, additionne 2 quantités numériques sur 8, 16, 32 ou 64 bits et ajoute ensuite la valeur de l'indicateur de retenue, lequel est contenu dans le drapeau CF (CARRY FLAG), à la somme obtenu. Le résultat pourra naturellement être placé en mémoire ou dans un registre. Cette opération tient donc compte de la retenue éventuelle ainsi que de l'addition des 16 bits de poids faible pour continuer l'addition des 16 bits de poids fort.

Algorithme

Opérande Cible ← Opérande Cible + Quantité Source + drapeau CF

Mnémonique

Instruction | Opcode | Description
ADC AL, imm8 | 14h ib | Ajout immédiate de 8 bits à AL + CF
ADC AX, imm16 | 15h iw | Ajout immédiate de 16 bits à AX + CF
ADC EAX, imm32 | 15h id | Ajout immédiate de 32 bits à EAX + CF
ADC RAX, imm32 | 15h id | Ajout immédiate de 32 bits à RAX + CF
ADC reg/mem8, imm8 | 80h /2 ib | Ajout immédiate de 8 bits à registre/mémoire + CF
ADC reg/mem16, imm16 | 81h /2 iw | Ajout immédiate de 16 bits à registre/mémoire 16 bits + CF
ADC reg/mem32, imm32 | 81h /2 id | Ajout immédiate de 32 bits à registre/mémoire 32 bits + CF
ADC reg/mem64, imm32 | 81h /2 id | Ajout immédiate de 32 bits entier à registre/mémoire 64 bits + CF
ADC reg/mem16, imm8 | 83h /2 ib | Ajout immédiate de 8 bits entier à registre/mémoire 16 bits + CF
ADC reg/mem32, imm8 | 83h /2 ib | Ajout immédiate de 8 bits entier à registre/mémoire 16 bits + CF
ADC reg/mem64, imm8 | 83h /2 ib | Ajout immédiate de 8 bits entier à registre/mémoire 64 bits + CF
ADC reg/mem8, reg8 | 10h /r | Ajout registre de 8 bits à registre/mémoire 8 bits + CF
ADC reg/mem16, reg16 | 11h /r | Ajout registre de 16 bits à registre/mémoire 16 bits + CF
ADC reg/mem32, reg32 | 11h /r | Ajout registre de 32 bits à registre/mémoire 32 bits + CF
ADC reg/mem64, reg64 | 11h /r | Ajout registre de 64 bits à registre/mémoire 64 bits + CF
ADC reg8, reg/mem8 | 12h /r | Ajout registre de 8 bits à registre/mémoire 8 bits + CF
ADC reg16, reg/mem16 | 13h /r | Ajout registre de 16 bits à registre/mémoire 16 bits + CF
ADC reg32, reg/mem32 | 13h /r | Ajout registre de 32 bits à registre/mémoire 32 bits + CF
ADC reg64, reg/mem64 | 13h /r | Ajout registre de 64 bits à registre/mémoire 64 bits + CF

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Cette exemple permet d'effectuer l'addition de la retenue d'une addition du registre AL sur le registre AH :

  1. MOV AX,0001h
  2. ADD AL,0FFh
  3. ADC AH,00h

Ce programme retournera donc la valeur 0100h dans le registre AX.

Voir également

Instruction assembleur 80x86 - Instruction ADD
Instruction assembleur 80x86 - Instruction SBB
Instruction assembleur 80x86 - Instruction SUB

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 802
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 126, 401
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 57 à 58.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 75 à 78.


Assembleur 80x86

ADD
INTEL 8088+ arithmetic ADDition

Syntaxe

ADD Opérande Cible, Opérande Source

Paramètres

Nom | Description
Opérande Cible | Ce paramètre permet d'indiquer l'opérande recevant le résultat
Opérande Source | Ce paramètre permet d'indiquer l'opérande à ajouter au résultat

Description

Cette instruction additionne 2 quantités numérique sur 8, 16, 32 ou 64 bits. La somme pourra être placé soit en mémoire ou encore dans un registre.

Remarque

  • Il n'est pas possible de mélanger des tailles différentes (8, 16, 32, 64 bits) de registres de cellule mémoire avec cette instruction. Si vos besoins sont de ce type, vous devrez soit les transférées dans un autre registre à l'aide d'une instruction MOVSX ou MOVZX, effectuer votre addition par tranche (ADC) et on tronquer votre valeur.

Algorithme

Opérande Cible ← Opérande Cible + Quantité Source
drapeau CF ← retenue

Mnémonique

Instruction | Opcode | Description
ADD AL, imm8 | 04h ib | Ajout immédiate de 8 bits à AL
ADD AX, imm16 | 05h iw | Ajout immédiate de 16 bits à AX
ADD EAX, imm32 | 05h id | Ajout immédiate de 32 bits à EAX
ADD RAX, imm32 | 05h id | Ajout d'un entier immédiate de 32 bits à RAX
ADD reg/mem8, imm8 | 80h /0 ib | Ajout immédiate de 8 bits à registre/mémoire 8 bits
ADD reg/mem16, imm16 | 81h /0 iw | Ajout immédiate de 16 bits à registre/mémoire 16 bits
ADD reg/mem32, imm32 | 81h /0 id | Ajout immédiate de 32 bits à registre/mémoire 32 bits
ADD reg/mem64, imm32 | 81h /0 id | Ajout entier immédiate de 32 bits à registre/mémoire 64 bits
ADD reg/mem16, imm8 | 83h /0 ib | Ajout entier immédiate de 8 bits à registre/mémoire 16 bits
ADD reg/mem32, imm8 | 83h /0 ib | Ajout entier immédiate de 8 bits à registre/mémoire 32 bits
ADD reg/mem64, imm8 | 83h /0 ib | Ajout entier immédiate de 8 bits à registre/mémoire 64 bits
ADD reg/mem8, reg8 | 00h /r | Ajout registre de 8 bits à registre/mémoire 8 bits
ADD reg/mem16, reg16 | 01h /r | Ajout registre de 16 bits à registre/mémoire 16 bits
ADD reg/mem32, reg32 | 01h /r | Ajout registre de 32 bits à registre/mémoire 32 bits
ADD reg/mem64, reg64 | 01h /r | Ajout registre de 64 bits à registre/mémoire 64 bits
ADD reg8, reg/mem8 | 02h /r | Ajout registre de 8 bits à registre/mémoire 8 bits
ADD reg16, reg/mem16 | 03h /r | Ajout registre de 16 bits à registre/mémoire 16 bits
ADD reg32, reg/mem32 | 03h /r | Ajout registre de 32 bits à registre/mémoire 32 bits
ADD reg64, reg/mem64 | 03h /r | Ajout registre de 64 bits à registre/mémoire 64 bits

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemples

Cet exemple permet d'ajouter la valeur 7 au registre AX :

  1. MOV AX,0008h
  2. ADD AX,0007h

Ce programme retournera donc la valeur 000Fh dans le registre AX.

Voici un exemple en Turbo Pascal 7 montrant une utilisation de cette instruction :

  1. Program AsmAdd;
  3. Var a,b,c,c_: Integer ;
  5. Function Add(X,Y: Integer ): Integer ;Assembler; ASM
  6. MOV AX,X
  7. ADD AX,Y
  8. END;
  10. BEGIN
  11. a := 1;
  12. b := 2;
  13. c := 3;
  14. c_ := -3;
  15. WriteLn ('0 + 0 : ',Add(0,0));
  16. WriteLn ('0 + 1 : ',Add(0,1));
  17. WriteLn ('1 + 1 : ',Add(1,1));
  18. WriteLn ('1 + 2 : ',Add(1,2));
  19. WriteLn ('a + b : ',Add(a,b));
  20. WriteLn ('a + b + c : ',Add(Add(a,b),c));
  21. WriteLn ('a + b + c_ : ',Add(Add(a,b),c_));
  22. WriteLn ('c + c_ : ',Add(c,c_));
  23. WriteLn ('a + b + 20 : ',Add(Add(a,b),20));
  24. END .

on obtiendra le résultat suivant :

0 + 0 : 0
0 + 1 : 1
1 + 1 : 2
1 + 2 : 3
a + b : 3
a + b + c : 6
a + b + c_ : 0
c + c_ : 0
a + b + 20 : 23

Voir également

Instruction assembleur 80x86 - Instruction ADC
Instruction assembleur 80x86 - Instruction SBB
Instruction assembleur 80x86 - Instruction SUB

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 803
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 401
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 59 à 60.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 79 à 81.


Assembleur 80x86

AND
INTEL 8088+ AND binary

Syntaxe

AND Opérande Cible, Opérande Source

Paramètres

Nom | Description
Opérande Cible | Ce paramètre permet d'indiquer l'opérande reçevant le résultat
Opérande Source | Ce paramètre permet d'indiquer l'opérande effectuant le masque binaire sur le résultat

Description

L'instruction AND effectue un ET BINAIRE sur les 2 opérandes spécifiés, le calcul est placé dans la première opérande, c'est-à-dire l'Opérande Cible. Rappelons qu'un ET BINAIRE donne le résultat 1 si les 2 opérandes sont 1 et donne 0 dans les autres cas et cela sur chacun des bits de l'opérande.

Remarques

  • Si vous souhaitez effectuer cette opération sur des nombres réels, il peut être préférable d'utiliser l'instruction «ANDPD» laquelle a été développé dans cette optique.

    De façon concrète, on utilise cette instruction entre autre, afin d'isolé un bit dans un mot afin d'en déterminer sa valeur ou afin de déterminé si un nombre est impaire ou non (AND @Result,1). Voir Langage de programmation - C - Mathématique - Odd (Impaire ou paire)

    Optimisation : On devrait utiliser l'instruction «AND» plutôt qu'un modulo à partir d'un DIV lorsque le nombre est une puissance 2, car il utilise beaucoup moins de cycle d'horloge qu'un DIV; ainsi, il faudra alors appliquer AND avec une comme première opérande le numérateur et comme deuxième opérande le dénominateur - 1.

Algorithme

Opérande Cible ← Opérande Cible ∩ Opérande Source
drapeau CF ← 0
drapeau OF ← 0

Mnémonique

Instruction | Opcode | Description
AND AL, imm8 | 24h ib | Et binaire sur le contenu du registre AL avec une valeur immédiate 8 bits et met le résultat dans AL
AND AX, imm16 | 25h iw | Et binaire sur le contenu du registre AX avec une valeur immédiate 16 bits et met le résultat dans AX
AND EAX, imm32 | 25h iw | Et binaire sur le contenu du registre EAX avec une valeur immédiate 32 bits et met le résultat dans EAX
AND RAX, imm32 | 25h id | Et binaire sur le contenu du registre RAX avec une valeur entière immédiate 32 bits et met le résultat dans RAX
AND reg/mem8, imm8 | 80h /4 ib | Et binaire sur le contenu du registre/mémoire 8 bits avec une valeur immédiate 8 bits
AND reg/mem16, imm16 | 81h /4 iw | Et binaire sur le contenu du registre/mémoire 16 bits avec une valeur immédiate 16 bits
AND reg/mem32, imm32 | 81h /4 id | Et binaire sur le contenu du registre/mémoire 32 bits avec une valeur immédiate 32 bits
AND reg/mem64, imm32 | 81h /4 id | Et binaire sur le contenu du registre/mémoire 64 bits avec une valeur entière immédiate 32 bits
AND reg/mem16, imm8 | 83h /4 ib | Et binaire sur le contenu du registre/mémoire 16 bits avec une valeur entière immédiate 8 bits
AND reg/mem32, imm8 | 83h /4 ib | Et binaire sur le contenu du registre/mémoire 32 bits avec une valeur entière immédiate 8 bits
AND reg/mem64, imm8 | 83h /4 ib | Et binaire sur le contenu du registre/mémoire 64 bits avec une valeur entière immédiate 8 bits
AND reg/mem8, reg8 | 20h /r | Et binaire sur le contenu du registre/mémoire 8 bits avec un registre 8 bits
AND reg/mem16, reg16 | 21h /r | Et binaire sur le contenu du registre/mémoire 16 bits avec un registre 16 bits
AND reg/mem32, reg32 | 21h /r | Et binaire sur le contenu du registre/mémoire 32 bits avec un registre 32 bits
AND reg/mem64, reg64 | 21h /r | Et binaire sur le contenu du registre/mémoire 64 bits avec un registre 64 bits
AND reg8, reg/mem8 | 22h /r | Et binaire sur le contenu du registre 8 bits avec un registre/mémoire 8 bits
AND reg16, reg/mem16 | 23h /r | Et binaire sur le contenu du registre 16 bits avec un registre/mémoire 16 bits
AND reg32, reg/mem32 | 23h /r | Et binaire sur le contenu du registre 32 bits avec un registre/mémoire 32 bits
AND reg64, reg/mem64 | 23h /r | Et binaire sur le contenu du registre 64 bits avec un registre/mémoire 64 bits

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Cet exemple permet de vérifier si un nombre est impaire :

  1. MOV AX,5
  2. CALL IsOdd
  3. CMP AL,1
  4. JE @Impaire
  5. CMP AL,0
  6. JE @Paire
  7. ...
  8. Proc IsOdd
  9. AND AX,1
  10. End Proc

Voir également

Instruction assembleur 80x86 - Instruction OR
Instruction assembleur 80x86 - Instruction NOT
Instruction assembleur 80x86 - Instruction NEG
Instruction assembleur 80x86 - Instruction TEST
Instruction assembleur 80x86 - Instruction XOR
Articles - Table de vérité

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 803
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 401
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 61 à 62.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 119 à 121.


Assembleur 80x86

DEC
INTEL 8088+ Decrement

Syntaxe

DEC opérande

Description

Cette instruction est un quelque sorte un raccourci de l'instruction SUB, en effet celle-ci décrément de 1 le registre ou l'adresse mémoire spécifié, le résultat obtenu est donc identique à celui d'un SUB avec 1 comme 2ième opérande.

Algorithme

opérande ← opérande - 1

Mnémonique

Instruction | Opcode | Description
DEC reg/mem8 | FEh /1 | Décrémente de 1 le contenu d'un emplacement de registre ou mémoire 8 bits
DEC reg/mem16 | FFh /1 | Décrémente de 1 le contenu d'un emplacement de registre ou mémoire 16 bits
DEC reg/mem32 | FFh /1 | Décrémente de 1 le contenu d'un emplacement de registre ou mémoire 32 bits
DEC reg/mem64 | FFh /1 | Décrémente de 1 le contenu d'un emplacement de registre ou mémoire 64 bits
DEC reg16 | (48h + rw) | Décrémente de 1 le contenu d'un registre 16 bits
DEC reg32 | (48h +rd) | Décrémente de 1 le contenu d'un registre 32 bits

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction INC
Instruction assembleur 80x86 - Instruction SUB

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 810
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 404
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 107 à 108.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 355 à 357.


Assembleur 80x86

DIV
INTEL 8088+ Division

Syntaxe

DIV Opérande

Description

L'instruction DIV permet d'effectuer une division non-signée (nombre naturel). Le dividende est implicite; il est ajuster en fonction de la taille du diviseur. Le restant est toujours plus petit que le diviseur. Le type de diviseur détermine quel registre l'instruction utilisera :

Taille | Dividende | Diviseur | Quotient | Restant
Octet | AX | Opérande | AL | AH
Mot | DX:AX | Opérande | AX | DX
Double mot | EDX:EAX | Opérande | EAX | EDX

Remarque

  • Optimisation : On devrait utiliser l'instruction «AND» plutôt qu'un modulo à partir d'un DIV lorsque le nombre est une puissance 2, car il utilise beaucoup moins de cycle d'horloge qu'un DIV; ainsi, il faudra alors appliquer AND avec une comme première opérande le numérateur et comme deuxième opérande le dénominateur - 1.

Algorithme

SI Opérande = 0 ALORS
Interruption 0
SINON
SI Opérande 8 bits ALORS
AL ← AX ÷ Opérande
AH ← AX MOD Opérande
FIN SI
SI Opérande 16 bits ALORS
AX ← ( ( DX x 65536 ) + AX ) ÷ Opérande
DX ← ( ( DX x 65536 ) + AX ) MOD Opérande
FIN SI
SI Opérande 32 bits ALORS
EAX ← ( ( EDX x 65536 x 65536 ) + EAX ) ÷ Opérande
EDX ← ( ( EDX x 65536 x 65536 ) + EAX ) MOD Opérande
FIN SI
FIN SI

Mnémonique

Instruction | Opcode | Description
DIV reg/mem8 | F6h /6 | Division naturel de AX par le contenu d'un emplacement mémoire ou registre 8 bits et entrepose le quotient dans AL et restant dans AH.
DIV reg/mem16 | F7h /6 | Division naturel de DX:AX par le contenu d'un emplacement mémoire ou registre 16 bits et entrepose le quotient dans AX et restant dans DX.
DIV reg/mem32 | F7h /6 | Division naturel de EDX:EAX par le contenu d'un emplacement mémoire ou registre 32 bits et entrepose le quotient dans EAX et restant dans EDX.
DIV reg/mem64 | F7h /6 | Division naturel de RDX:RAX par le contenu d'un emplacement mémoire ou registre 64 bits et entrepose le quotient dans RAX et restant dans RDX.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#DE(Division par zéro) | X | X | X | L'opérande de diviseur vaut 0.
 | X | X | X | Le quotient est trop large pour le registre désigné.
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Voici quelques exemples typiques de l'utilisation de cet opérateur :

  1. .MODEL small
  2. .STACK 100h
  3. .DATA
  4. Message1 DB 'div(-81,9) = ','$'
  5. Message2 DB 'div(15,3) = ','$'
  6. Message3 DB 'div(16,3) = ','$'
  7. Message4 DB 'div(17,3) = ','$'
  8. Message5 DB 'div(18,3) = ','$'
  9. Message6 DB 'div(19,3) = ','$'
  10. Message7 DB 'div(0,1) = ','$'
  11. CRLF DB 13,10,'$'
  12. .CODE
  13. PrintDigit PROC NEAR
  14. OR AX,AX
  15. JNS Positif
  16. PUSH AX
  17. MOV AH,02h
  18. MOV DL,'-'
  19. INT 21h
  20. POP AX
  21. NEG AX
  22. Positif:
  23. MOV BX,10
  24. XOR CX,CX
  25. NextDigit:
  26. XOR DX,DX
  27. DIV BX
  28. PUSH DX
  29. INC CX
  30. OR AX,AX
  31. JNZ NextDigit
  32. PrintOneDigit:
  33. POP AX
  34. ADD AL,48
  35. MOV DL,AL
  36. MOV AH,02h
  37. INT 21h
  38. LOOP PrintOneDigit
  39. RET
  40. ENDP
  42. .startup
  44. ; div(-81,9)
  45. MOV AX,@data
  46. MOV DS,AX
  47. MOV AH,9
  48. MOV DX,OFFSET Message1
  49. INT 21h
  50. MOV AL,81
  51. XOR AH,AH
  52. NEG AH
  53. MOV CX,9
  54. DIV CL
  55. NEG AX
  56. CALL PrintDigit
  57. MOV AH,9
  58. MOV DX,OFFSET CRLF
  59. INT 21h
  61. ; div(15,3)
  62. MOV AX,@data
  63. MOV DS,AX
  64. MOV AH,9
  65. MOV DX,OFFSET Message2
  66. INT 21h
  67. MOV AX,15
  68. XOR DX,DX
  69. MOV CX,3
  70. DIV CX
  71. CALL PrintDigit
  72. MOV AH,9
  73. MOV DX,OFFSET CRLF
  74. INT 21h
  76. ; div(16,3)
  77. MOV AX,@data
  78. MOV DS,AX
  79. MOV AH,9
  80. MOV DX,OFFSET Message3
  81. INT 21h
  82. MOV AX,16
  83. XOR DX,DX
  84. MOV CX,3
  85. DIV CX
  86. CALL PrintDigit
  87. MOV AH,9
  88. MOV DX,OFFSET CRLF
  89. INT 21h
  91. ; div(17,3)
  92. MOV AX,@data
  93. MOV DS,AX
  94. MOV AH,9
  95. MOV DX,OFFSET Message4
  96. INT 21h
  97. MOV AX,17
  98. XOR DX,DX
  99. MOV CX,3
  100. DIV CX
  101. CALL PrintDigit
  102. MOV AH,9
  103. MOV DX,OFFSET CRLF
  104. INT 21h
  106. ; div(18,3)
  107. MOV AX,@data
  108. MOV DS,AX
  109. MOV AH,9
  110. MOV DX,OFFSET Message5
  111. INT 21h
  112. MOV AX,18
  113. XOR DX,DX
  114. MOV CX,3
  115. DIV CX
  116. CALL PrintDigit
  117. MOV AH,9
  118. MOV DX,OFFSET CRLF
  119. INT 21h
  121. ; div(19,3)
  122. MOV AX,@data
  123. MOV DS,AX
  124. MOV AH,9
  125. MOV DX,OFFSET Message6
  126. INT 21h
  127. MOV AX,19
  128. XOR DX,DX
  129. MOV CX,3
  130. DIV CX
  131. CALL PrintDigit
  132. MOV AH,9
  133. MOV DX,OFFSET CRLF
  134. INT 21h
  136. ; div(0,1)
  137. MOV AX,@data
  138. MOV DS,AX
  139. MOV AH,9
  140. MOV DX,OFFSET Message7
  141. INT 21h
  142. MOV AX,0
  143. XOR DX,DX
  144. MOV CX,1
  145. DIV CX
  146. CALL PrintDigit
  147. MOV AH,9
  148. MOV DX,OFFSET CRLF
  149. INT 21h
  152. MOV AX,4C00h
  153. INT 21h
  154. END

on obtiendra le résultat suivant :

div(-81,9) = -9
div(15,3) = 5
div(16,3) = 5
div(17,3) = 5
div(18,3) = 6
div(19,3) = 6
div(0,1) = 0

Voir également

Instruction assembleur 80x86 - Instruction MUL
Instruction assembleur 80x86 - Instruction IDIV

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 810
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 404
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 109.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 358 à 360.


Assembleur 80x86

FDIV
INTEL MPU 8087+ Float Division

Syntaxe

FDIV source, cible

Description

Cette instruction offre la possibilité d'effectuer des divisions de nombre réel de valeur positive source par cible et enregistrer le résultat dans cible. Si cible n'est pas spécifié, le registre mathématique ST(0) est inutilisé. Si source et cible ne sont pas défini, le couple de registre mathématique ST(1) et ST(0) sont utilisés.

Algorithme

source ← source ÷ cible

Mnémonique

Instruction | Opcode | Description
FDIV mem32 | D8h /6 | Cette instruction permet d'effectuer des divisions de nombre réel de valeur positive source par cible et enregistrer le résultat dans cible.
FDIV mem64 | DCh /6 | Cette instruction permet d'effectuer des divisions de nombre réel de valeur positive source par cible et enregistrer le résultat dans cible.
FDIV fpureg | D8h (F0h+r) | Cette instruction permet d'effectuer des divisions de nombre réel de valeur positive source par cible et enregistrer le résultat dans cible.
FDIV ST0,fpureg | D8h (F0h+r) | Cette instruction permet d'effectuer des divisions de nombre réel de valeur positive source par cible et enregistrer le résultat dans cible.
FDIV TO fpureg | DCh (F8h+r) | Cette instruction permet d'effectuer des divisions de nombre réel de valeur positive source par cible et enregistrer le résultat dans cible.
FDIV fpureg,ST0 | DCh (F8h+r) | Cette instruction permet d'effectuer des divisions de nombre réel de valeur positive source par cible et enregistrer le résultat dans cible.

Voir également

Langage de programmation - Assembleur 80x86 - MPU : Coprocesseur mathématique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 843
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 422 à 424.


Assembleur 80x86

FDIVP
INTEL MPU 8087+ Float Division & Position

Syntaxe

FDIVP source, cible

Description

Cette instruction offre la possibilité d'effectuer des division de nombre réel et place ST(0) dans la pile.

Algorithme

source ← source ÷ cible
POP ST

Mnémonique

Instruction | Opcode | Description
FDIVP fpureg | DEh (F8h+r) | Cette instruction permet d'effectuer des division de nombre réel et place ST(0) dans la pile.
FDIVP fpureg,ST0 | DEh (F8h+r) | Cette instruction permet d'effectuer des division de nombre réel et place ST(0) dans la pile.

Voir également

Langage de programmation - Assembleur 80x86 - MPU : Coprocesseur mathématique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 843
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 422 à 424.


Assembleur 80x86

FDIVR
INTEL MPU 8087+ Float Division Reverse

Syntaxe

FDIVR cible, source

Description

Cette instruction offre la possibilité d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».

Algorithme

source ← source ÷ cible

Mnémonique

Instruction | Opcode | Description
FDIVR mem32 | D8h /7 | Cette instruction permet d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».
FDIVR mem64 | DCh /7 | Cette instruction permet d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».
FDIVR fpureg | D8h (F8h+r) | Cette instruction permet d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».
FDIVR ST0,fpureg | D8h (F8h+r) | Cette instruction permet d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».
FDIVR TO fpureg | DCh (F0h+r) | Cette instruction permet d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».
FDIVR fpureg,ST0 | DCh (F0h+r) | Cette instruction permet d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».

Voir également

Langage de programmation - Assembleur 80x86 - MPU : Coprocesseur mathématique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 843
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 425 à 428.


Assembleur 80x86

FDIVRP
INTEL MPU 8087+ Float Division Reverse & Position

Syntaxe

FDIVRP cible, source

Description

Cette instruction offre la possibilité d'effectuer des divisions de nombre réel avec les registres inversés «cible» par «source» et place ST(0) dans la pile.

Algorithme

source ← source ÷ cible
POP ST

Mnémonique

Instruction | Opcode | Description
FDIVRP fpureg | DEh (F0h+r) | Cette instruction permet d'effectuer des divisions de nombre réel avec les registres inversés «cible» par «source» et place ST(0) dans la pile.
FDIVRP fpureg,ST0 | DEh (F0h+r) | Cette instruction permet d'effectuer des divisions de nombre réel avec les registres inversés «cible» par «source» et place ST(0) dans la pile.
FDIVRP | DEh F1h | Cette instruction permet d'effectuer des division de nombre réel de valeur positive avec les registres inversés «cible» par «source».

Voir également

Langage de programmation - Assembleur 80x86 - MPU : Coprocesseur mathématique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 844
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 425 à 428.


Assembleur 80x86

FIMUL
INTEL MPU 8087+ Float Integer Multplication

Syntaxe

FIMUL source,cible

Description

Cette instruction permet de multiplier le nombre réel «source» par «cible» et sauvegarde le résultat dans «cible». Si la «cible» n'est pas définit, le registre ST(0) est utilisé. Si «source» et «cible» ne sont pas définit, les registres ST(1) et ST(0) sont utilisés.

Algorithme

source ← source x cible

Mnémonique

Instruction | Opcode | Description
FIMUL mem16 | DEh /1 | Cette instruction permet de multiplier le nombre réel «source» par «cible» et sauvegarde le résultat dans «cible». Si la «cible» n'est pas définit, le registre ST(0) est utilisé. Si «source» et «cible» ne sont pas définit, les registres ST(1) et ST(0) sont utilisés.
FIMUL mem32 | DAh /1 | Cette instruction permet de multiplier le nombre réel «source» par «cible» et sauvegarde le résultat dans «cible». Si la «cible» n'est pas définit, le registre ST(0) est utilisé. Si «source» et «cible» ne sont pas définit, les registres ST(1) et ST(0) sont utilisés.

Voir également

Langage de programmation - Assembleur 80x86 - MPU : Coprocesseur mathématique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 845
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 455 à 459.


Assembleur 80x86

FISUB
INTEL MPU 8087+ Float Integer Subtract

Syntaxe

FISUB source

Description

Cette instruction offre l'essentielle possibilité de soustraire le nombre «source» du registre ST(0).

Algorithme

ST ← ST - source

Mnémonique

Instruction | Opcode | Description
FISUB mem16 | DEh /4 | Cette instruction permet de soustraire le nombre «source» 16 bits du registre ST(0).
FISUB mem32 | DAh /4 | Cette instruction permet de soustraire le nombre «source» 32 bits du registre ST(0).

Voir également

Langage de programmation - Assembleur 80x86 - MPU : Coprocesseur mathématique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 845
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 503 à 506.


Assembleur 80x86

FISUBR
INTEL MPU 8087+ Float Integer Subtract Reverse

Syntaxe

FISUBR source

Description

Cette instruction offre l'essentielle possibilité de soustraire le nombre du registre ST(0) de «source».

Algorithme

source ← source - ST

Mnémonique

Instruction | Opcode | Description
FISUBR mem16 | DEh /5 | Cette instruction permet de soustraire le nombre du registre ST(0) de «source» 16 bits.
FISUBR mem32 | DAh /5 | Cette instruction permet de soustraire le nombre du registre ST(0) de «source» 32 bits.

Voir également

Langage de programmation - Assembleur 80x86 - MPU : Coprocesseur mathématique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 846
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 507 à 510.


Assembleur 80x86

FMUL
INTEL MPU 8087+ Float MULtiplication

Syntaxe

FMUL source,cible

Description

Cette instruction permet de multiplier le nombre réel de valeur positive «source» par «cible» et sauvegarde le résultat dans «cible». Si la «cible» n'est pas définit, le registre ST(0) est utilisé. Si «source» et «cible» ne sont pas définit, les registres ST(1) et ST(0) sont utilisés.

Algorithme

source ← source x cible

Mnémonique

Instruction | Opcode | Description
FMUL mem32 | D8h /1 | Cette instruction permet de multiplier le nombre réel de valeur positive «source» 32 bits par «cible» et sauvegarde le résultat dans «cible».
FMUL mem64 | DCh /1 | Cette instruction permet de multiplier le nombre réel de valeur positive «source» 64 bits par «cible» et sauvegarde le résultat dans «cible».
FMUL fpureg | D8h (C8h+r) | Cette instruction permet de multiplier le nombre réel de valeur positive «source» par «cible» et sauvegarde le résultat dans «cible».
FMUL ST0,fpureg | D8h (C8h+r) | Cette instruction permet de multiplier le nombre réel de valeur positive «source» par «cible» et sauvegarde le résultat dans «cible».
FMUL TO fpureg | DCh (C8h+r) | Cette instruction permet de multiplier le nombre réel de valeur positive «source» par «cible» et sauvegarde le résultat dans «cible».
FMUL fpureg,ST0 | DCh (C8h+r) | Cette instruction permet de multiplier le nombre réel de valeur positive «source» par «cible» et sauvegarde le résultat dans «cible».

Voir également

Langage de programmation - Assembleur 80x86 - MPU : Coprocesseur mathématique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 847
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 455 à 459.


Assembleur 80x86

FMULP
INTEL MPU 8087+ Float MULtiplication in Pointer

Syntaxe

FMULP source,cible

Description

Cette instruction permet de multiplier le nombre réel de valeur positive «source» par «cible» et sauvegarde le résultat dans «cible» et prend ensuite ST(0) dans la pile de registres. Si «source» et «cible» ne sont pas définit, les registres ST(1) et ST(0) sont utilisés.

Algorithme

source ← source x cible
POP ST(0)

Mnémonique

Instruction | Opcode | Description
FMULP fpureg | DEh (C8h+r) | Cette instruction permet de multiplier le nombre réel de valeur positive «source» par «cible» et sauvegarde le résultat dans «cible» et prend ensuite ST(0) dans la pile de registres.
FMULP fpureg,ST0 | DEh (C8h+r) | Cette instruction permet de multiplier le nombre réel de valeur positive «source» par «cible» et sauvegarde le résultat dans «cible» et prend ensuite ST(0) dans la pile de registres.

Voir également

Langage de programmation - Assembleur 80x86 - MPU : Coprocesseur mathématique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 847
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 455 à 459.


Assembleur 80x86

FSUB
INTEL MPU 8087+ Float Subtract

Syntaxe

FSUB source

Description

Cette instruction permet de soustraire un nombre entier du registre ST(0).

Algorithme

ST ← ST - source

Mnémonique

Instruction | Opcode | Description
FSUB mem32 | D8h /4 | Cette instruction permet de soustraire un nombre entier du registre ST(0).
FSUB mem64 | DCh /4 | Cette instruction permet de soustraire un nombre entier du registre ST(0).
FSUB fpureg | D8h (E0h+r) | Cette instruction permet de soustraire un nombre entier du registre ST(0).
FSUB ST0,fpureg | D8h (E0h+r) | Cette instruction permet de soustraire un nombre entier du registre ST(0).
FSUB TO fpureg | DCh (E8h+r) | Cette instruction permet de soustraire un nombre entier du registre ST(0).
FSUB fpureg,ST0 | DCh (E8h+r) | Cette instruction permet de soustraire un nombre entier du registre ST(0).

Voir également

Langage de programmation - Assembleur 80x86 - MPU : Coprocesseur mathématique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 851
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 503 à 506.


Assembleur 80x86

FSUBPP
INTEL MPU 8087+

Syntaxe

FSUBPP source

Description

Cette instruction permet de soustraire un nombre entier du registre ST(0) et copie le registre ST(0) dans la pile de registres.

Remarque

    L'utilisation de cette instruction est déconseillée, il est préférable d'utiliser plutôt «FSUBP» car cette instruction est très peu supporté par les compilateurs.

Voir également

Langage de programmation - Assembleur 80x86 - MPU : Coprocesseur mathématique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 851


Assembleur 80x86

FSUBR
INTEL MPU 8087+

Syntaxe

FSUBR source

Description

Cette instruction permet de soustraire le registre ST(0) du nombre entier et place le résultat dans le registre ST(0).

Algorithme

ST ← source - ST

Mnémonique

Instruction | Opcode | Description
FSUBR mem32 | D8h /5 | Cette instruction permet de soustraire le registre ST(0) du nombre entier et place le résultat dans le registre ST(0).
FSUBR mem64 | DCh /5 | Cette instruction permet de soustraire le registre ST(0) du nombre entier et place le résultat dans le registre ST(0).
FSUBR fpureg | D8h (E8h+r) | Cette instruction permet de soustraire le registre ST(0) du nombre entier et place le résultat dans le registre ST(0).
FSUBR ST0,fpureg | D8h (E8h+r) | Cette instruction permet de soustraire le registre ST(0) du nombre entier et place le résultat dans le registre ST(0).
FSUBR TO fpureg | DCh (E0h+r) | Cette instruction permet de soustraire le registre ST(0) du nombre entier et place le résultat dans le registre ST(0).
FSUBR fpureg,ST0 | DCh (E0h+r) | Cette instruction permet de soustraire le registre ST(0) du nombre entier et place le résultat dans le registre ST(0).

Voir également

Langage de programmation - Assembleur 80x86 - MPU : Coprocesseur mathématique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 851
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 507 à 510.


Assembleur 80x86

FSUBRP
INTEL MPU 8087+

Syntaxe

FSUBRP source

Description

Cette instruction permet de soustraire le registre ST(0) du nombre entier et place le résultat dans le registre ST(0) et copie le registre ST(0) dans la pile de registres.

Algorithme

ST ← source - ST
Désempile le registre de pile

Mnémonique

Instruction | Opcode | Description
FSUBRP fpureg | DEh (E0h+r) | Cette instruction permet de soustraire le registre ST(0) du nombre entier et place le résultat dans le registre ST(0) et copie le registre ST(0) dans la pile de registres.
FSUBRP fpureg,ST0 | DEh (E0h+r) | Cette instruction permet de soustraire le registre ST(0) du nombre entier et place le résultat dans le registre ST(0) et copie le registre ST(0) dans la pile de registres.

Voir également

Langage de programmation - Assembleur 80x86 - MPU : Coprocesseur mathématique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 851
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 507 à 510.


Assembleur 80x86

IDIV
INTEL 8088+ Division entière

Syntaxe

IDIV Opérande

Description

Cette instruction permet d'effectuer une division signée (nombre entier). Le dividende est implicite; il est ajuster en fonction de la taille du diviseur. Le restant est toujours plus petit que le diviseur. Le type de diviseur détermine quel registre l'instruction utilisera:

Taille | Dividende | Diviseur | Quotient | Restant
Octet | AX | Opérande | AL | AH
Mot | DX:AX | Opérande | AX | DX
Double mot | EDX:EAX | Opérande | EAX | EDX

Remarques

  • Optimisation : On devrait utiliser l'instruction «AND» plutôt qu'un modulo à partir d'un IDIV lorsque le nombre est une puissance 2, car il utilise beaucoup moins de cycle d'horloge qu'un IDIV; ainsi, il faudra alors appliquer AND avec une comme première opérande le numérateur et comme deuxième opérande le dénominateur - 1.

    Si vous effectuer des divisions de nombre naturel, vous devriez plutôt envisager d'utiliser les instructions «SHR» ou «DIV» car elles sont plus efficaces.

Algorithme

SI Opérande = 0 ALORS
Interruption 0
SINON
SI Opérande 8 bits ALORS
AL ← AX ÷ Opérande
AH ← AX MOD Opérande
FIN SI
SI Opérande 16 bits ALORS
AX ← ( ( DX x 65536 ) + AX ) ÷ Opérande
DX ← ( ( DX x 65536 ) + AX ) MOD Opérande
FIN SI
SI Opérande 32 bits ALORS
EAX ← ( ( EDX x 65536 x 65536 ) + EAX ) ÷ Opérande
EDX ← ( ( EDX x 65536 x 65536 ) + EAX ) MOD Opérande
FIN SI
FIN SI

Mnémonique

Instruction | Opcode | Description
IDIV reg/mem8 | F6h /7 | Division entière de AX par le contenu d'un emplacement mémoire ou registre 8 bits et entrepose le quotient dans AL et restant dans AH.
IDIV reg/mem16 | F7h /7 | Division entière de DX:AX par le contenu d'un emplacement mémoire ou registre 16 bits et entrepose le quotient dans AX et restant dans DX.
IDIV reg/mem32 | F7h /7 | Division entière de EDX:EAX par le contenu d'un emplacement mémoire ou registre 32 bits et entrepose le quotient dans EAX et restant dans EDX.
IDIV reg/mem64 | F7h /7 | Division entière de RDX:RAX par le contenu d'un emplacement mémoire ou registre 64 bits et entrepose le quotient dans RAX et restant dans RDX.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#DE(Division par zéro) | X | X | X | L'opérande de diviseur vaut 0.
 | X | X | X | Le quotient est trop large pour le registre désigné.
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Voici quelques exemples typiques de l'utilisation de cet opérateur :

  1. .MODEL small
  2. .STACK 100h
  3. .DATA
  4. Message1 DB 'idiv(-81,9) = ','$'
  5. Message2 DB 'idiv(15,3) = ','$'
  6. Message3 DB 'idiv(16,3) = ','$'
  7. Message4 DB 'idiv(17,3) = ','$'
  8. Message5 DB 'idiv(18,3) = ','$'
  9. Message6 DB 'idiv(19,3) = ','$'
  10. Message7 DB 'idiv(0,1) = ','$'
  11. CRLF DB 13,10,'$'
  12. .CODE
  13. PrintDigit PROC NEAR
  14. OR AX,AX
  15. JNS Positif
  16. PUSH AX
  17. MOV AH,02h
  18. MOV DL,'-'
  19. INT 21h
  20. POP AX
  21. NEG AX
  22. Positif:
  23. MOV BX,10
  24. XOR CX,CX
  25. NextDigit:
  26. XOR DX,DX
  27. DIV BX
  28. PUSH DX
  29. INC CX
  30. OR AX,AX
  31. JNZ NextDigit
  32. PrintOneDigit:
  33. POP AX
  34. ADD AL,48
  35. MOV DL,AL
  36. MOV AH,02h
  37. INT 21h
  38. LOOP PrintOneDigit
  39. RET
  40. ENDP
  42. .startup
  44. ; idiv(-81,9)
  45. MOV AX,@data
  46. MOV DS,AX
  47. MOV AH,9
  48. MOV DX,OFFSET Message1
  49. INT 21h
  50. MOV AX,81
  51. XOR DX,DX
  52. MOV CX,9
  53. IDIV CX
  54. NEG AX
  55. CALL PrintDigit
  56. MOV AH,9
  57. MOV DX,OFFSET CRLF
  58. INT 21h
  60. ; idiv(15,3)
  61. MOV AX,@data
  62. MOV DS,AX
  63. MOV AH,9
  64. MOV DX,OFFSET Message2
  65. INT 21h
  66. MOV AX,15
  67. XOR DX,DX
  68. MOV CX,3
  69. IDIV CX
  70. CALL PrintDigit
  71. MOV AH,9
  72. MOV DX,OFFSET CRLF
  73. INT 21h
  75. ; idiv(16,3)
  76. MOV AX,@data
  77. MOV DS,AX
  78. MOV AH,9
  79. MOV DX,OFFSET Message3
  80. INT 21h
  81. MOV AX,16
  82. XOR DX,DX
  83. MOV CX,3
  84. iDIV CX
  85. CALL PrintDigit
  86. MOV AH,9
  87. MOV DX,OFFSET CRLF
  88. INT 21h
  90. ; idiv(17,3)
  91. MOV AX,@data
  92. MOV DS,AX
  93. MOV AH,9
  94. MOV DX,OFFSET Message4
  95. INT 21h
  96. MOV AX,17
  97. XOR DX,DX
  98. MOV CX,3
  99. IDIV CX
  100. CALL PrintDigit
  101. MOV AH,9
  102. MOV DX,OFFSET CRLF
  103. INT 21h
  105. ; idiv(18,3)
  106. MOV AX,@data
  107. MOV DS,AX
  108. MOV AH,9
  109. MOV DX,OFFSET Message5
  110. INT 21h
  111. MOV AX,18
  112. XOR DX,DX
  113. MOV CX,3
  114. IDIV CX
  115. CALL PrintDigit
  116. MOV AH,9
  117. MOV DX,OFFSET CRLF
  118. INT 21h
  120. ; idiv(19,3)
  121. MOV AX,@data
  122. MOV DS,AX
  123. MOV AH,9
  124. MOV DX,OFFSET Message6
  125. INT 21h
  126. MOV AX,19
  127. XOR DX,DX
  128. MOV CX,3
  129. IDIV CX
  130. CALL PrintDigit
  131. MOV AH,9
  132. MOV DX,OFFSET CRLF
  133. INT 21h
  135. ; idiv(0,1)
  136. MOV AX,@data
  137. MOV DS,AX
  138. MOV AH,9
  139. MOV DX,OFFSET Message7
  140. INT 21h
  141. MOV AX,0
  142. XOR DX,DX
  143. MOV CX,1
  144. IDIV CX
  145. CALL PrintDigit
  146. MOV AH,9
  147. MOV DX,OFFSET CRLF
  148. INT 21h
  151. MOV AX,4C00h
  152. INT 21h
  153. END

on obtiendra le résultat suivant :

div(-81,9) = -9
div(15,3) = 5
div(16,3) = 5
div(17,3) = 5
div(18,3) = 6
div(19,3) = 6
div(0,1) = 0

Voir également

Instruction assembleur 80x86 - Instruction IMUL
Instruction assembleur 80x86 - Instruction DIV

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 811
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 404
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 113 à 114.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 559 à 562.


Assembleur 80x86

IMUL
INTEL 8088+ Multiplication entière

Syntaxe

IMUL Opérande | INTEL 8088+
IMUL dest, src | INTEL 80286+
IMUL dest, src, imm | INTEL 80386+

Description

Cette instruction permet d'effectuer une multiplication signée (nombre entier). Le multiplicateur est implicite; il est ajuster en fonction de la taille de la base. Le produit est toujours plus grand que le multiplicateur. Le type de multiplication détermine quel registre l'instruction utilisera :

Taille | Base | Multiplicateur | Résultat
Octet | AL | Opérande | AX
Mot | AX | Opérande | DX:AX
Double mot | EAX | Opérande | EDX:EAX

Algorithme

SI Nombre d'opérande = 1 ALORS
SI Taille de l'opérande en bits = 8 ALORS
AX ← AL x Opérande
SI (AH = 00h) OU (AH = FFh) ALORS
CF ← 0
OF ← 0
SINON
CF ← 1
OF ← 1
FIN SI
SINON SI Taille de l'opérande en bits = 16 ALORS
DX:AX ← AX x Opérande
SI (DX = 0000h) OU (DX = FFFFh) ALORS
CF ← 0
OF ← 0
SINON
CF ← 1
OF ← 1
FIN SI
SINON
EDX:EAX ← EAX x Opérande
SI ((EDX = 00000000h) OU (EDX = FFFFFFFFh)) ALORS
CF ← 0
OF ← 0
SINON
CF ← 1
OF ← 1
FIN SI
FIN SI
SINON SI Nombre d'opérande = 2 ALORS
temp ← dest x src
dest ← dest x src
SI temp = dest ALORS
CF ← 1
OF ← 1
SINON
CF ← 0
OF ← 0
FIN SI
SINON
temp ← dest x src
dest ← dest x src
SI temp = dest ALORS
CF ← 1
OF ← 1
SINON
CF ← 0
OF ← 0
FIN SI
FIN SI
FIN SI

Mnémonique

Instruction | Opcode | Description
IMUL reg/mem8 | F6h /5 | Multiplie le contenu du registre AL avec une opérande mémoire ou registre de 8 bits et met le résultat entier dans le registre AX.
IMUL reg/mem16 | F7h /5 | Multiplie le contenu du registre AX avec une opérande mémoire ou registre de 16 bits et met le résultat entier dans le registre DX:AX.
IMUL reg/mem32 | F7h /5 | Multiplie le contenu du registre EAX avec une opérande mémoire ou registre de 32 bits et met le résultat entier dans le registre EDX:EAX.
IMUL reg/mem64 | F7h /5 | Multiplie le contenu du registre RAX avec une opérande mémoire ou registre de 64 bits et met le résultat entier dans le registre RDX:RAX.
IMUL reg16, reg/mem16 | 0Fh AFh /r | Multiplie le contenu d'un registre de destination 16 bits avec une opérande mémoire ou registre de 16 bits et met le résultat entier dans le registre de destination 16 bits.
IMUL reg32, reg/mem32 | 0Fh AFh /r | Multiplie le contenu d'un registre de destination 32 bits avec une opérande mémoire ou registre de 32 bits et met le résultat entier dans le registre de destination 32 bits.
IMUL reg64, reg/mem64 | 0Fh AFh /r | Multiplie le contenu d'un registre de destination 64 bits avec une opérande mémoire ou registre de 64 bits et met le résultat entier dans le registre de destination 64 bits.
IMUL reg16, reg/mem16, imm8 | 6Bh /r ib | Multiplie le contenu d'une opérande mémoire ou registre de 16 bits par une valeur entière immédiate de 8 bits et met le résultat entier dans le registre 16 bits.
IMUL reg32, reg/mem32, imm8 | 6Bh /r ib | Multiplie le contenu d'une opérande mémoire ou registre de 32 bits par une valeur entière immédiate de 8 bits et met le résultat entier dans le registre 32 bits.
IMUL reg64, reg/mem64, imm8 | 6Bh /r ib | Multiplie le contenu d'une opérande mémoire ou registre de 64 bits par une valeur entière immédiate de 8 bits et met le résultat entier dans le registre 64 bits.
IMUL reg16, reg/mem16,imm16 | 69h /r iw | Multiplie le contenu d'une opérande mémoire ou registre de 16 bits par une valeur entière immédiate de 16 bits et met le résultat entier dans le registre 16 bits.
IMUL reg32, reg/mem32,imm32 | 69h /r id | Multiplie le contenu d'une opérande mémoire ou registre de 32 bits par une valeur entière immédiate de 32 bits et met le résultat entier dans le registre 32 bits.
IMUL reg64, reg/mem64,imm32 | 69h /r id | Multiplie le contenu d'une opérande mémoire ou registre de 64 bits par une valeur entière immédiate de 32 bits et met le résultat entier dans le registre 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique

Exemple

Voici un exemple en Turbo Pascal montrant une utilisation de cet instruction :

  1. Program AsmIMul;
  2.
  3. Var a,b,c,c_:Integer;
  4.
  5. Function IMul(X,Y:Integer):LongInt;Assembler;ASM
  6.  MOV AX,X
  7.  IMUL Y
  8. END;
  9.
  10. BEGIN
  11.  a := 1;
  12.  b := 2;
  13.  c := 3;
  14.  c_ := -3;
  15.  WriteLn('0 * 0 : ',IMul(0,0));
  16.  WriteLn('0 * 1 : ',IMul(0,1));
  17.  WriteLn('1 * 1 : ',IMul(1,1));
  18.  WriteLn('1 * 2 : ',IMul(1,2));
  19.  WriteLn('a * b : ',IMul(a,b));
  20.  WriteLn('a * b * c : ',IMul(Mul(a,b),c));
  21.  WriteLn('a * b * c_ : ',Integer(IMul(IMul(a,b),c_)));
  22.  WriteLn('c * c_ : ',Integer(IMul(c,c_)));
  23.  WriteLn('a * b * 20 : ',IMul(IMul(a,b),20));
  24. END.

on obtiendra le résultat suivant :

0 * 0 : 0
0 * 1 : 0
1 * 1 : 1
1 * 2 : 2
a * b : 2
a * b * c : 6
a * b * c_ : -6
c * c_ : -9
a * b * 20 : 40

Voir également

Instruction assembleur 80x86 - Instruction IDIV
Instruction assembleur 80x86 - Instruction MUL

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 812
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 405
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 115.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 563 à 567.


Assembleur 80x86

INC
INTEL 8088+ Increment

Syntaxe

INC registre
INC mémoire

Description

Cette instruction permet d'incrémenter un registre ou un emplacement mémoire.

Algorithme

operande ← operande + 1

Mnémonique

Instruction | Opcode | Description
INC reg/mem8 | FEh /0 | Incrémente le contenu d'un emplacement registre ou mémoire de 8 bits de 1.
INC reg/mem16 | FFh /0 | Incrémente le contenu d'un emplacement registre ou mémoire de 16 bits de 1.
INC reg/mem32 | FFh /0 | Incrémente le contenu d'un emplacement registre ou mémoire de 32 bits de 1.
INC reg/mem64 | FFh /0 | Incrémente le contenu d'un emplacement registre ou mémoire de 64 bits de 1.
INC reg16 | 40h +rw | Incrémente le contenu d'un registre 16 bits de 1.
INC reg32 | 40h +rd | Incrémente le contenu d'un registre 32 bits de 1.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction ADD
Instruction assembleur 80x86 - Instruction DEC

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 812
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 405
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 118.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 570 à 572.


Assembleur 80x86

MUL
INTEL 8088+ Multiplication

Syntaxe

MUL Opérande

Description

Cette instruction permet d'effectuer une multiplication non-signée (nombre naturel). Le multiplicateur est implicite; il est ajuster en fonction de la taille de la base. Le produit est toujours plus grand que le multiplicateur. Le type de multiplication détermine quel registre l'instruction utilisera :

Taille | Base | Multiplicateur | Résultat
Octet | AL | Opérande | AX
Mot | AX | Opérande | DX:AX
Double mot | EAX | Opérande | EDX:EAX

Algorithme

SI Nombre d'opérande = 1 ALORS
SI Taille de l'opérande en bits = 8 ALORS
AX ← AL x Opérande
SI (AH = 00h) OU (AH = FFh) ALORS
CF ← 0
OF ← 0
SINON
CF ← 1
OF ← 1
FIN SI
SINON SI Taille de l'opérande en bits = 16 ALORS
DX:AX ← AX x Opérande
SI (DX = 0000h) OU (DX = FFFFh) ALORS
CF ← 0
OF ← 0
SINON
CF ← 1
OF ← 1
FIN SI
SINON
EDX:EAX ← EAX x Opérande
SI ((EDX = 00000000h) OU (EDX = FFFFFFFFh)) ALORS
CF ← 0
OF ← 0
SINON
CF ← 1
OF ← 1
FIN SI
FIN SI
SINON SI Nombre d'opérande = 2 ALORS
temp ← dest x src
dest ← dest x src
SI temp = dest ALORS
CF ← 1
OF ← 1
SINON
CF ← 0
OF ← 0
FIN SI
SINON
temp ← dest x src
dest ← dest x src
SI temp = dest ALORS
CF ← 1
OF ← 1
SINON
CF ← 0
OF ← 0
FIN SI
FIN SI
FIN SI

Mnémonique

Instruction | Opcode | Description
MUL reg/mem8 | F6h /4 | Multiple l'opérande mémoire ou registre 8 bits par le contenu du registre AL et entrepose le résultat dans le registre AX.
MUL reg/mem16 | F7h /4 | Multiple l'opérande mémoire ou registre 16 bits par le contenu du registre AX et entrepose le résultat dans le registre DX:AX.
MUL reg/mem32 | F7h /4 | Multiple l'opérande mémoire ou registre 32 bits par le contenu du registre EAX et entrepose le résultat dans le registre EDX:EAX.
MUL reg/mem64 | F7h /4 | Multiple l'opérande mémoire ou registre 64 bits par le contenu du registre RAX et entrepose le résultat dans le registre RDX:RAX.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Voici un exemple en Turbo Pascal montrant une utilisation de cet instruction :

  1. Program AsmMul;
  3. Var a,b,c,c_: Integer ;
  5. Function Mul(X,Y: Integer ): LongInt ;Assembler; ASM
  6. MOV AX,X
  7. MUL Y
  8. END;
  10. BEGIN
  11. a := 1;
  12. b := 2;
  13. c := 3;
  14. c_ := -3;
  15. WriteLn ('0 * 0 : ',Mul(0,0));
  16. WriteLn ('0 * 1 : ',Mul(0,1));
  17. WriteLn ('1 * 1 : ',Mul(1,1));
  18. WriteLn ('1 * 2 : ',Mul(1,2));
  19. WriteLn ('a * b : ',Mul(a,b));
  20. WriteLn ('a * b * c : ',Mul(Mul(a,b),c));
  21. WriteLn ('a * b * c_ : ', Integer (Mul(Mul(a,b),c_)));
  22. WriteLn ('c * c_ : ', Integer (Mul(c,c_)));
  23. WriteLn ('a * b * 20 : ',Mul(Mul(a,b),20));
  24. END .

on obtiendra le résultat suivant :

0 * 0 : 0
0 * 1 : 0
1 * 1 : 1
1 * 2 : 2
a * b : 2
a * b * c : 6
a * b * c_ : -6
c * c_ : -9
a * b * 20 : 40

Voir également

Instruction assembleur 80x86 - Instruction DIV
Instruction assembleur 80x86 - Instruction IMUL
Langage de programmation - Assembleur et Pascal - Opération Mathématique

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 822
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 411 à 412
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 173.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 824 à 826.


Assembleur 80x86

NEG
INTEL 8088+ Negation

Syntaxe

NEG registre
NEG mémoire

Description

Cette instruction permet d'effectuer le complément à 2 d'une opérande.

Algorithme

SI DEST = 0 ALORS
CF ← 0
SINON
CF ← 1
FIN SI
DEST ← - (DEST)

Mnémonique

Instruction | Opcode | Description
NEG reg/mem8 | F6h /3 | Effectue une négation de compléments de 2 dans une opérande de registre ou mémoire 8 bits.
NEG reg/mem16 | F7h /3 | Effectue une négation de compléments de 2 dans une opérande de registre ou mémoire 16 bits.
NEG reg/mem32 | F7h /3 | Effectue une négation de compléments de 2 dans une opérande de registre ou mémoire 32 bits.
NEG reg/mem64 | F7h /3 | Effectue une négation de compléments de 2 dans une opérande de registre ou mémoire 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Cet exemple permet de montrer l'affectation des nombres par cette instruction :

  1. Program NegSamples;
  3. Function AsmNeg(X: Integer ): Integer ;Assembler; ASM
  4. MOV AX,X
  5. NEG AX
  6. END;
  8. BEGIN
  9. WriteLn ('NEG -1 = ',AsmNeg(-1));
  10. WriteLn ('NEG 0 = ',AsmNeg(0));
  11. WriteLn ('NEG 1 = ',AsmNeg(1));
  12. WriteLn ('NEG 255 = ',AsmNeg(255));
  13. WriteLn ('NEG 32767 = ',AsmNeg(32767));
  14. WriteLn ('NEG TRUE = ',AsmNeg( Integer (TRUE)));
  15. WriteLn ('NEG FALSE = ',AsmNeg( Integer (FALSE)));
  16. END .

on obtiendra le résultat suivant :

NEG -1 = 1
NEG 0 = 0
NEG 1 = -1
NEG 255 = -255
NEG 32767 = -32767
NEG TRUE = -1
NEG FALSE = 0

Voir également

Instruction assembleur 80x86 - Instruction AND
Instruction assembleur 80x86 - Instruction NEG
Instruction assembleur 80x86 - Instruction OR
Instruction assembleur 80x86 - Instruction XOR
Articles - Table de vérité

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 823
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 412
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 175.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 10 à 12.


Assembleur 80x86

NOT
INTEL 8088+ Pas

Syntaxe

NOT registre
NOT mémoire

Description

Cette instruction permet d'inverser la valeur de chacun des bits d'une opérande.

Algorithme

dest ← (¬ dest)

Mnémonique

Instruction | Opcode | Description
NOT reg/mem8 | F6h /2 | Compléments les bits d'une opérande de registre ou mémoire 8 bits.
NOT reg/mem16 | F7h /2 | Compléments les bits d'une opérande de registre ou mémoire 16 bits.
NOT reg/mem32 | F7h /2 | Compléments les bits d'une opérande de registre ou mémoire 32 bits.
NOT reg/mem64 | F7h /2 | Compléments les bits d'une opérande de registre ou mémoire 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Cet exemple permet de montrer l'affectaction des nombres par cette instruction :

  1. Program NotSamples;
  3. Function AsmNot(X: Integer ): Integer ;Assembler; ASM
  4. MOV AX,X
  5. NOT AX
  6. END;
  8. BEGIN
  9. WriteLn ('NOT -1 = ',AsmNot(-1));
  10. WriteLn ('NOT 0 = ',AsmNot(0));
  11. WriteLn ('NOT 1 = ',AsmNot(1));
  12. WriteLn ('NOT 255 = ',AsmNot(255));
  13. WriteLn ('NOT 32767 = ',AsmNot(32767));
  14. WriteLn ('NOT TRUE = ',AsmNot( Integer (TRUE)));
  15. WriteLn ('NOT FALSE = ',AsmNot( Integer (FALSE)));
  16. END .

on obtiendra le résultat suivant :

NOT -1 = 0
NOT 0 = -1
NOT 1 = -2
NOT 255 = -256
NOT 32767 = -32768
NOT TRUE = -2
NOT FALSE = -1

Voir également

Instruction assembleur 80x86 - Instruction AND
Instruction assembleur 80x86 - Instruction NEG
Instruction assembleur 80x86 - Instruction OR
Instruction assembleur 80x86 - Instruction XOR
Articles - Table de vérité

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 823
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 412
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 178.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 15 à 15.


Assembleur 80x86

OR
INTEL 8088+ Or bitwise

Syntaxe

OR Opérande Cible, Opérande Source

Description

L'instruction OR effectue un OU BINAIRE sur les 2 opérandes spécifiés, le calcul est placé dans la première opérande, c'est-à-dire l'Opérande Cible. Rappelons qu'un OU BINAIRE donne le résultat 1 si au moins une des 2 opérandes vaut 1 et donne 0 si les deux bits valent 0.

Algorithme

Opérande Cible ← Opérande Cible U Opérande Source
drapeau CF ← 0
drapeau OF ← 0

Mnémonique

Instruction | Opcode | Description
OR AL, imm8 | 0Ch ib | Effectue un «Ou binaire» du contenu du registre AL avec une valeur immédiate de 8 bits.
OR AX, imm16 | 0Dh iw | Effectue un «Ou binaire» du contenu du registre AX avec une valeur immédiate de 16 bits.
OR EAX, imm32 | 0Dh id | Effectue un «Ou binaire» du contenu du registre EAX avec une valeur immédiate de 32 bits.
OR RAX, imm32 | 0Dh id | Effectue un «Ou binaire» du contenu du registre RAX avec une valeur immédiate de 32 bits.
OR reg/mem8, imm8 | 80h /1 ib | Effectue un «Ou binaire» du contenu d'une opérande mémoire ou registre 8 bits avec une valeur immédiate de 8 bits.
OR reg/mem16, imm16 | 81h /1 iw | Effectue un «Ou binaire» du contenu d'une opérande mémoire ou registre 16 bits avec une valeur immédiate de 16 bits.
OR reg/mem32, imm32 | 81h /1 id | Effectue un «Ou binaire» du contenu d'une opérande mémoire ou registre 32 bits avec une valeur immédiate de 32 bits.
OR reg/mem64, imm32 | 81h /1 id | Effectue un «Ou binaire» du contenu d'une opérande mémoire ou registre 64 bits avec une valeur immédiate entière de 32 bits.
OR reg/mem16, imm8 | 83h /1 ib | Effectue un «Ou binaire» du contenu d'une opérande mémoire ou registre 16 bits avec une valeur immédiate entière de 8 bits.
OR reg/mem32, imm8 | 83h /1 ib | Effectue un «Ou binaire» du contenu d'une opérande mémoire ou registre 32 bits avec une valeur immédiate entière de 8 bits.
OR reg/mem64, imm8 | 83h /1 ib | Effectue un «Ou binaire» du contenu d'une opérande mémoire ou registre 64 bits avec une valeur immédiate entière de 8 bits.
OR reg/mem8, reg8 | 08h /r | Effectue un «Ou binaire» du contenu d'une opérande mémoire ou registre 8 bits avec le contenu d'un registre de 8 bits.
OR reg/mem16, reg16 | 09h /r | Effectue un «Ou binaire» du contenu d'une opérande mémoire ou registre 16 bits avec le contenu d'un registre de 16 bits.
OR reg/mem32, reg32 | 09h /r | Effectue un «Ou binaire» du contenu d'une opérande mémoire ou registre 32 bits avec le contenu d'un registre de 32 bits.
OR reg/mem64, reg64 | 09h /r | Effectue un «Ou binaire» du contenu d'une opérande mémoire ou registre 64 bits avec le contenu d'un registre de 64 bits.
OR reg8, reg/mem8 | 0Ah /r | Effectue un «Ou binaire» du contenu d'un registre de 8 bits avec le contenu d'une opérande mémoire ou registre 8 bits.
OR reg16, reg/mem16 | 0Bh /r | Effectue un «Ou binaire» du contenu d'un registre de 16 bits avec le contenu d'une opérande mémoire ou registre 16 bits.
OR reg32, reg/mem32 | 0Bh /r | Effectue un «Ou binaire» du contenu d'un registre de 32 bits avec le contenu d'une opérande mémoire ou registre 32 bits.
OR reg64, reg/mem64 | 0Bh /r | Effectue un «Ou binaire» du contenu d'un registre de 64 bits avec le contenu d'une opérande mémoire ou registre 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Cet exemple permet de vérifier si AX vaut 0. Cette technique de programmation à l'apparence un peu étrange, est pourtant très commune chez les professionnels de l'assembleur, car il consomme moins d'octets en mémoire, que l'utilisation de l'instruction «CMP AX,0» :

  1. OR AX,AX
  2. JE @axvautzero
  3. ; AX ne vaut pas 0
  4. ; ...
  5. @axvautzero
  6. ; AX vaut 0
  7. ; ...

Voir également

Instruction assembleur 80x86 - Instruction AND
Instruction assembleur 80x86 - Instruction NEG
Instruction assembleur 80x86 - Instruction NOT
Instruction assembleur 80x86 - Instruction XOR
Articles - Table de vérité

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 823
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 412
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 179.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 16 à 19.


Assembleur 80x86

SBB
INTEL 8088+ Subtraction With Borrow

Syntaxe

SBB opérandecible,opérandesource

Paramètres

Nom | Description
opérandecible | Ce paramètre permet d'indiquer l'opérande de base sur lequel l'opération sera effectué.
opérandesource | Ce paramètre permet d'indiquer la quantité à soustraire

Description

Cette instruction permet de soustraire avec l'indicateur de retenue (CF) une valeur à une opérande.

Algorithme

opérandecible ← opérandecible - (opérandesource + CF)

Mnémonique

Instruction | Opcode | Description
SBB AL, imm8 | 1Ch ib | Soustrait une valeur immédiate de 8 bits du registre AL avec la retenue.
SBB AX, imm16 | 1Dh iw | Soustrait une valeur immédiate de 16 bits du registre AX avec la retenue.
SBB EAX, imm32 | 1Dh id | Soustrait une valeur immédiate de 32 bits du registre EAX avec la retenue.
SBB RAX, imm32 | 1Dh id | Soustrait une valeur entière immédiate de 32 bits du registre RAX avec la retenue.
SBB reg/mem8, imm8 | 80h /3 ib | Soustrait une valeur immédiate de 8 bits d'un emplacement registre ou mémoire de 8 bits avec la retenue.
SBB reg/mem16, imm16 | 81h /3 iw | Soustrait une valeur immédiate de 16 bits d'un emplacement registre ou mémoire de 16 bits avec la retenue.
SBB reg/mem32, imm32 | 81h /3 id | Soustrait une valeur immédiate de 32 bits d'un emplacement registre ou mémoire de 32 bits avec la retenue.
SBB reg/mem64, imm32 | 81h /3 id | Soustrait une valeur immédiate de 32 bits d'un emplacement registre ou mémoire de 64 bits avec la retenue.
SBB reg/mem16, imm8 | 83h /3 ib | Soustrait une valeur immédiate de 8 bits d'un emplacement registre ou mémoire de 16 bits avec la retenue.
SBB reg/mem32, imm8 | 83h /3 ib | Soustrait une valeur entière immédiate de 8 bits d'un emplacement registre ou mémoire de 32 bits avec la retenue.
SBB reg/mem64, imm8 | 83h /3 ib | Soustrait une valeur entière immédiate de 8 bits d'un emplacement registre ou mémoire de 64 bits avec la retenue.
SBB reg/mem8, reg8 | 18h /r | Soustrait un registre de 8 bits d'un emplacement registre ou mémoire de 8 bits avec la retenue.
SBB reg/mem16, reg16 | 19h /r | Soustrait un registre de 16 bits d'un emplacement registre ou mémoire de 16 bits avec la retenue.
SBB reg/mem32, reg32 | 19h /r | Soustrait un registre de 32 bits d'un emplacement registre ou mémoire de 32 bits avec la retenue.
SBB reg/mem64, reg64 | 19h /r | Soustrait un registre de 32 bits d'un emplacement registre ou mémoire de 32 bits avec la retenue.
SBB reg8, reg/mem8 | 1Ah /r | Soustrait un emplacement registre ou mémoire de 8 bits avec la retenue d'un registre de 8 bits.
SBB reg16, reg/mem16 | 1Bh /r | Soustrait un emplacement registre ou mémoire de 16 bits avec la retenue d'un registre de 16 bits.
SBB reg32, reg/mem32 | 1Bh /r | Soustrait un emplacement registre ou mémoire de 32 bits avec la retenue d'un registre de 32 bits.
SBB reg64, reg/mem64 | 1Bh /r | Soustrait un emplacement registre ou mémoire de 32 bits avec la retenue d'un registre de 32 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Voici un exemple, en Turbo Pascal, permettant d'effectuer une soustraction d'un nombre 16 bits par tranche de 8 bits en utilisant l'instruction «SBB» :

  1. Program SBBSamples;
  3. Var _AX: Word ;
  5. BEGIN
  6. ASM
  7. MOV AX,00FEh
  8. SBB AL,0FFh
  9. SBB AH,00h
  10. MOV _AX,AX
  11. END;
  12. WriteLn (_AX);
  13. END .

on obtiendra le résultat suivant :

65535

Voir également

Instruction assembleur 80x86 - Instruction SUB
Instruction assembleur 80x86 - Instruction ADD
Instruction assembleur 80x86 - Instruction ADC

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 832
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 416
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 221.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 409 à 412.


Assembleur 80x86

SUB
INTEL 8088+ Arithmetic Substraction Unsigned

Syntaxe

SUB opérandecible,opérandesource

Paramètres

Nom | Description
opérandecible | Ce paramètre permet d'indiquer l'opérande de base sur lequel l'opération sera effectué.
opérandesource | Ce paramètre permet d'indiquer la quantité à soustraire

Description

Cette instruction permet de soustraire une valeur à une opérande.

Algorithme

opérandecible ← opérandecible - opérandesource

Mnémonique

Instruction | Opcode | Description
SUB AL, imm8 | 2Ch ib | Soustrait une valeur immédiate de 8 bits du registre AL et entrepose le résultat dans le registre AL.
SUB AX, imm16 | 2Dh iw | Soustrait une valeur immédiate de 16 bits du registre AX et entrepose le résultat dans le registre AX.
SUB EAX, imm32 | 2Dh id | Soustrait une valeur immédiate de 32 bits du registre EAX et entrepose le résultat dans le registre EAX.
SUB RAX, imm32 | 2Dh id | Soustrait une valeur entière immédiate de 32 bits du registre RAX et entrepose le résultat dans le registre RAX.
SUB reg/mem8, imm8 | 80h /5 ib | Soustrait une valeur entière immédiate de 8 bits de l'emplacement registre ou mémoire de 8 bits.
SUB reg/mem16, imm16 | 81h /5 iw | Soustrait une valeur entière immédiate de 16 bits de l'emplacement registre ou mémoire de 16 bits.
SUB reg/mem32, imm32 | 81h /5 id | Soustrait une valeur entière immédiate de 32 bits de l'emplacement registre ou mémoire de 32 bits.
SUB reg/mem64, imm32 | 81h /5 id | Soustrait une valeur entière immédiate de 64 bits de l'emplacement registre ou mémoire de 32 bits.
SUB reg/mem16, imm8 | 83h /5 ib | Soustrait une valeur entière immédiate de 16 bits de l'emplacement registre ou mémoire de 8 bits.
SUB reg/mem32, imm8 | 83h /5 ib | Soustrait une valeur entière immédiate de 32 bits de l'emplacement registre ou mémoire de 8 bits.
SUB reg/mem64, imm8 | 83h /5 ib | Soustrait une valeur entière immédiate de 64 bits de l'emplacement registre ou mémoire de 8 bits.
SUB reg/mem8, reg8 | 28h /r | Soustrait un registre de 8 bits de l'emplacement registre ou mémoire de 8 bits.
SUB reg/mem16, reg16 | 29h /r | Soustrait un registre de 16 bits de l'emplacement registre ou mémoire de 16 bits.
SUB reg/mem32, reg32 | 29h /r | Soustrait un registre de 32 bits de l'emplacement registre ou mémoire de 32 bits.
SUB reg/mem64, reg64 | 29h /r | Soustrait un registre de 64 bits de l'emplacement registre ou mémoire de 64 bits.
SUB reg8, reg/mem8 | 2Ah /r | Soustrait de l'opérande d'emplacement registre ou mémoire de 8 bits d'un registre de 8 bits.
SUB reg16, reg/mem16 | 2Bh /r | Soustrait de l'opérande d'emplacement registre ou mémoire de 16 bits d'un registre de 16 bits.
SUB reg32, reg/mem32 | 2Bh /r | Soustrait de l'opérande d'emplacement registre ou mémoire de 32 bits d'un registre de 32 bits.
SUB reg64, reg/mem64 | 2Bh /r | Soustrait de l'opérande d'emplacement registre ou mémoire de 64 bits d'un registre de 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Voici un exemple en Turbo Pascal montrant une utilisation de cet instruction :

  1. Program AsmSub;
  3. Var a,b,c,c_: Integer ;
  5. Function Sub(X,Y: Integer ): Integer ;Assembler; ASM
  6. MOV AX,X
  7. SUB AX,Y
  8. END;
  10. BEGIN
  11. a := 1;
  12. b := 2;
  13. c := 3;
  14. c_ := -3;
  15. WriteLn ('0 - 0 : ',Sub(0,0));
  16. WriteLn ('0 - 1 : ',Sub(0,1));
  17. WriteLn ('1 - 1 : ',Sub(1,1));
  18. WriteLn ('1 - 2 : ',Sub(1,2));
  19. WriteLn ('a - b : ',Sub(a,b));
  20. WriteLn ('a - b - c : ',Sub(Sub(a,b),c));
  21. WriteLn ('a - b - c_ : ',Sub(Sub(a,b),c_));
  22. WriteLn ('c - c_ : ',Sub(c,c_));
  23. WriteLn ('a - b - 20 : ',Sub(Sub(a,b),20));
  24. END .

on obtiendra le résultat suivant :

0 - 0 : 0
0 - 1 : -1
1 - 1 : 0
1 - 2 : -1
a - b : -1
a - b - c : -4
a - b - c_ : 2
c - c_ : 6
a - b - 20 : -21

Voir également

Instruction assembleur 80x86 - Instruction ADC
Instruction assembleur 80x86 - Instruction ADD
Instruction assembleur 80x86 - Instruction SBB

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 838
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 418
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 239.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 476 à 478.


Assembleur 80x86

XOR
INTEL 8088+ binary eXclusive OR

Syntaxe

XOR OpérandeCible, OpérandeSource

Description

L'instruction XOR effectue un OU exclusif BINAIRE sur les 2 opérandes spécifiés, le calcul est placé dans la première opérande, c'est-à-dire l'Opérande Cible. Rappelons qu'un OU exclusif BINAIRE donne le résultat 1 si une des 2 opérandes vaut 1 et donne 0 si les deux bits valent 0 ou 1.

Algorithme

OpérandeCible ← OpérandeCible XOR OpérandeSource

Mnémonique

Instruction | Opcode | Description
XOR AL, imm8 | 34h ib | Effectue un «Ou exclusif binaire» du contenu du registre AL avec une valeur immédiate de 8 bits.
XOR AX, imm16 | 35h iw | Effectue un «Ou exclusif binaire» du contenu du registre AX avec une valeur immédiate de 16 bits.
XOR EAX, imm32 | 35h id | Effectue un «Ou exclusif binaire» du contenu du registre EAX avec une valeur immédiate de 32 bits.
XOR RAX, imm32 | 35h id | Effectue un «Ou exclusif binaire» du contenu du registre RAX avec une valeur immédiate de 32 bits.
XOR reg/mem8, imm8 | 80h /6 ib | Effectue un «Ou exclusif binaire» du contenu d'une opérande mémoire ou registre 8 bits avec une valeur immédiate de 8 bits.
XOR reg/mem16, imm16 | 81h /6 iw | Effectue un «Ou exclusif binaire» du contenu d'une opérande mémoire ou registre 16 bits avec une valeur immédiate de 16 bits.
XOR reg/mem32, imm32 | 81h /6 id | Effectue un «Ou exclusif binaire» du contenu d'une opérande mémoire ou registre 32 bits avec une valeur immédiate de 32 bits.
XOR reg/mem64, imm32 | 81h /6 id | Effectue un «Ou exclusif binaire» du contenu d'une opérande mémoire ou registre 64 bits avec une valeur immédiate de 32 bits.
XOR reg/mem16, imm8 | 83h /6 ib | Effectue un «Ou exclusif binaire» du contenu d'une opérande mémoire ou registre 16 bits avec une valeur immédiate de 8 bits.
XOR reg/mem32, imm8 | 83h /6 ib | Effectue un «Ou exclusif binaire» du contenu d'une opérande mémoire ou registre 32 bits avec une valeur immédiate de 8 bits.
XOR reg/mem64, imm8 | 83h /6 ib | Effectue un «Ou exclusif binaire» du contenu d'une opérande mémoire ou registre 64 bits avec une valeur immédiate de 8 bits.
XOR reg/mem8, reg8 | 30h /r | Effectue un «Ou exclusif binaire» du contenu d'une opérande mémoire ou registre 8 bits avec le contenu d'un registre de 8 bits.
XOR reg/mem16, reg16 | 31h /r | Effectue un «Ou exclusif binaire» du contenu d'une opérande mémoire ou registre 16 bits avec le contenu d'un registre de 16 bits.
XOR reg/mem32, reg32 | 31h /r | Effectue un «Ou exclusif binaire» du contenu d'une opérande mémoire ou registre 32 bits avec le contenu d'un registre de 32 bits.
XOR reg/mem64, reg64 | 31h /r | Effectue un «Ou exclusif binaire» du contenu d'une opérande mémoire ou registre 64 bits avec le contenu d'un registre de 64 bits.
XOR reg8, reg/mem8 | 32h /r | Effectue un «Ou exclusif binaire» du contenu d'un registre de 8 bits avec le contenu d'une opérande mémoire ou registre 8 bits.
XOR reg16, reg/mem16 | 33h /r | Effectue un «Ou exclusif binaire» du contenu d'un registre de 16 bits avec le contenu d'une opérande mémoire ou registre 16 bits.
XOR reg32, reg/mem32 | 33h /r | Effectue un «Ou exclusif binaire» du contenu d'un registre de 32 bits avec le contenu d'une opérande mémoire ou registre 32 bits.
XOR reg64, reg/mem64 | 33h /r | Effectue un «Ou exclusif binaire» du contenu d'un registre de 64 bits avec le contenu d'une opérande mémoire ou registre 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemples

Cet exemple permet de mettre la valeur 0 dans le registre EAX (EAX = 0). Cette technique utilise moins d'octets que l'instruction «MOV EAX,0», cependant il modifie l'état du registre des drapeaux, il faut donc l'utiliser avec astuce lors d'optimisation de code :

  1. XOR EAX,EAX

Voici un exemple permettant d'échanger les valeurs des registres AX et BX à l'aide de l'opérateur XOR :

  1. .MODEL small
  2.    .STACK 100h
  3.    .DATA
  4. Message1       DB 'Valeur de AX = ','$'
  5. Message2       DB ', Valeur de BX = ','$'
  6. CRLF           DB 13,10,'$'
  7.    .CODE
  8. PrintDigit PROC NEAR
  9.     OR  AX,AX
  10.     JNS Positif
  11.     PUSH AX
  12.      MOV AH,02h
  13.      MOV DL,'-'
  14.      INT 21h
  15.     POP AX
  16.     NEG AX
  17. Positif:
  18.     MOV BX,10
  19.     XOR CX,CX
  20. NextDigit:
  21.     XOR DX,DX
  22.     DIV BX
  23.     PUSH DX
  24.      INC CX
  25.      OR  AX,AX
  26.      JNZ NextDigit
  27. PrintOneDigit:
  28.     POP AX
  29.     ADD AL,48
  30.     MOV DL,AL
  31.     MOV AH,02h
  32.     INT 21h
  33.     LOOP PrintOneDigit
  34.     RET
  35. ENDP
  36.
  37. Exchange PROC NEAR
  38.     XOR AX,BX
  39.     XOR BX,AX
  40.     XOR AX,BX
  41.     RET
  42. ENDP
  43.
  44.     .startup
  45.     MOV  AX,@data
  46.     MOV  DS,AX
  47.     MOV  AH,9
  48.     MOV  DX,OFFSET Message1
  49.     INT  21h
  50.     MOV  AX,-1234
  51.     MOV  BX,76
  52.     CALL Exchange
  53.     PUSH BX
  54.      CALL PrintDigit
  55.      MOV  AX,@data
  56.      MOV  DS,AX
  57.      MOV  AH,9
  58.      MOV  DX,OFFSET Message2
  59.      INT  21h
  60.     POP AX
  61.     CALL PrintDigit
  62.     MOV  AH,9
  63.     MOV  DX,OFFSET CRLF
  64.     INT  21h
  65.     MOV  AX,4C00h
  66.     INT  21h
  67.     END

on obtiendra le résultat suivant :

Valeur de AX = 76, Valeur de BX = -1234

Voir également

Instruction assembleur 80x86 - Instruction OR
Instruction assembleur 80x86 - Instruction AND
Instruction assembleur 80x86 - Instruction NOT
Instruction assembleur 80x86 - Instruction NEG
Langage de programmation - Turbo Pascal - Référence de procédures et fonctions - XOR
Articles - Table de vérité

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 839
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 419
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 248.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 547 à 549.


Voici les instructions assembleur classés par catégorie de saut conditionnel :

Instruction | Description | CPU/MPU
BOUND | Cette instruction permet de vérifier la validité pouvant exister entre avec un tableau et son indexation. | INTEL 80186+
INTO | Cette instruction permet d'exécuter l'interruption numéro 4 si le drapeau de débordement (OF) est fixé sur 1. | INTEL 8086+
Jump if | Ces instructions permettent d'effectuer d'effectuer un branchement conditionnel à emplacement mémoire spécifié. | INTEL 8086+

Dernière mise à jour : Vendredi, le 4 mars 2016


Assembleur 80x86

BOUND
INTEL 80186+ check array index against BOUNDs

Syntaxe

BOUND registre, mémoire

Description

Cette instruction, ayant fait sont apparition sur un processeur méconnue du public, offre la possibilité professionnel de vérifier la validité pouvant exister entre avec un tableau et son indexation.

Algorithme

SI ( Source De Gauche < [Source De Droite] ) U ( Source De Gauche > [ Source De Droite + Taille Opérande ÷ 8 ] ) ALORS
Interruption 5
FIN SI

Mnémonique

Instruction | Opcode | Description
BOUND reg16, mem16&mem16 | 62h /r | Test avec un index de tableau 16 bits spécifié deux valeurs 16 bits (Invalide en mode 64 bits)
BOUND reg32, mem32&mem32 | 62h /r | Test avec un index de tableau 32 bits spécifié deux valeurs 32 bits (Invalide en mode 64 bits)

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#BR(Débordement de rang) | X | X | X | La limite du rang est dépassé.
#UD(Opcode invalide) | X | X | X | La source de l'opérande est un registre
 |  |  | X | Cette instruction est exécuté en mode 64-bits
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction INT
Instruction assembleur 80x86 - Instruction INTO

Références

Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 145 à 147.


Assembleur 80x86

INTO
INTEL 8086+ Interrupt Overflow

Syntaxe

INTO

Description

Cette instruction permet d'exécuter l'interruption numéro 4 si le drapeau de débordement (OF) est fixé sur 1. Parcontre, si le drapeau de débordement (OF) est égal à 0, l'exécution se poursuit tout simplement à l'instruction suivante.

Algorithme

SI OF = 1 ALORS
SP ← SP - 2
Les drapeaux sont préservé
SP ← SP - 2
CS est préservé
SP ← SP - 2
IP est préservé
CS ← Donnée à la position mémoire 12h
IP ← Donnée à la position mémoire 10h
FIN SI

Mnémonique

Instruction | Opcode | Description
INTO | CEh | Appel une exception de débordement si le drapeau de débordement vaut 1. Invalide en mode 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#OF(Débordement) | X | X | X | Cette instruction est exécuté avec OF fixé à 1.
#UD(Opcode invalide) |  |  | X | Cette instruction est exécuté en mode 64-bits

Voir également

Instruction assembleur 80x86 - Instruction INT
Instruction assembleur 80x86 - Instruction BOUND

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 814
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 129.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 581 à 595.


Voici les instructions assembleur classés par catégorie de saut inconditionnel :

Instruction | Description | CPU/MPU
CALL | Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse d'appel avant de continuer. | INTEL 8088+
INT | Cette instruction permet d'exécuter l'interruption avec le numéro spécifié. | INTEL 8086+
JMP | Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié. | INTEL 8086+
RET | Cette instruction permet de quitter une procédure. | INTEL 8086+
RETF | Cette instruction permet de quitter une procédure ayant lieu avec un appel long (FAR CALL). | INTEL 8086+
RETN | Cette instruction permet de quitter une procédure ayant lieu avec un appel court (NEAR CALL). | INTEL 8086+

Dernière mise à jour : Vendredi, le 4 mars 2016


Assembleur 80x86

CALL
INTEL 8088+ CALL

Syntaxe

CALL adresse

Description

Cette instruction force le microprocesseur à exécuter les instructions du sous-programme indiqué par l'adresse d'appel avant de continuer. Dès que la routine est terminé, l'exécution reprendra son cours à l'instruction suivant le CALL.

Algorithme

Appel long | Appel court
PUSH CS PUSH IP CS:IP ← Destination | PUSH IP IP ← Destination

Mnémonique

Instruction | Opcode | Description
CALL rel16off | E8h iw | Appel court avec une destination spécifié par une adresse 16 bits
CALL rel32off | E8h id | Appel court avec une destination spécifié par une adresse 32 bits
CALL reg/mem16 | FFh /2 | Appel court avec une destination spécifié par un registre/mémoire 16 bits
CALL reg/mem32 | FFh /2 | Appel court avec une destination spécifié par un registre/mémoire 32 bits. Il n'y a pas de préfixe pour l'encoder en mode 64 bits.
CALL reg/mem64 | FFh /2 | Appel court avec une destination spécifié par un registre/mémoire 64 bits
CALL FAR pntr16:16 | 9Ah cd | Appel long direct, avec un destination spécifié par un pointeur long. Invalide en mode 64 bits.
CALL FAR pntr16:32 | 9Ah cp | Appel long direct, avec un destination spécifié par un pointeur long. Invalide en mode 64 bits.
CALL FAR mem16:16 | FFh /3 | Appel long indirect, avec un destination spécifié par un pointeur long en mémoire.
CALL FAR mem16:32 | FFh /3 | Appel long indirect, avec un destination spécifié par un pointeur long en mémoire.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 | X | X | X | L'opérande de destination dépasse la limite du segment de code ou n'est pas canonique.
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#GP(Sélecteur) |  |  | X | Le sélecteur de segment de code de destination est un sélecteur nulle.
 |  |  | X | Un code, d'un appel de pont, de tâche de pont, ou un descripteur TSS dépasse la limite du descripteur de table.
 |  |  | X | Un sélecteur de segment de bit TI est fixer mais le sélecteur LDT est un sélecteur nulle.
 |  |  | X | Le descripteur de segment spécifié par l'instruction n'est pas un segment de code, une tâche de pont, un appel de pont, ou un TSS disponible en mode legacy, ou un segment de code n'étant en mode 64 bits ou un appel de pont 64 bits dans un mode long.
 |  |  | X | Le RPL de sélecteur de segment de code spécifié est non-conforme à une instruction plus grande que le CPL, ou le DPL n'est pas égale au CPL.
 |  |  | X | Le DPL du descripteur de segment de code spécifié est conforme au instruction plus grande que le CPL.
 |  |  | X | Le DPL de l'appel de pont, de tâche de pont, ou le descripteur TSS spécifié par l'instruction est inférieur au CPL ou RPL.
 |  |  | X | Le descripteur de segment spécifié par l'appel de pont ou la tâche de pont est un sélecteur nulle.
 |  |  | X | Le descripteur de segment spécifié par l'appel de pont n'est pas en segment de code en mode legacy pi n'est pas un segment de code 64 bits dans le mode long.
 |  |  | X | Le DPL du du descripteur de segment spécifié par l'appel de pont est plus grand que le CPL.
 |  |  | X | L'appel d'un pont 64 bits avec des bits d'attribues étendues n'est pas à 0.
 |  |  | X | Le TSS du descripteur est présent dans le LDT.
#NP(Segment non présent) |  |  | X | L'accès au segment de code, appel d'un pont, tâche de pont, ou TSS n'est pas présent.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique, et n'est pas l'échange de pile spécifié.
#SS(Sélecteur) |  |  | X | Après l'échange de pile, un accès mémoire dépasse la limite de segment de pile ou est non-canonique.
 |  |  | X | Après l'échange de pile, le registre SS n'est pas chargé avec un sélecteur de segment non-nulle et le segment est marqué comme non-présent.
#TS(Sélecteur TSS invalide) |  |  | X | Lors d'une partie de l'échange entre la pile, la destination du segment de la pile ou du registre RSP dans le TSS est en dehors des limites TSS.
 |  |  | X | Lors d'une partie de l'échange entre la pile, la destination du segment de la pile ou du registre RSP dans le TSS est dans un sélecteur nulle.
 |  |  | X | Lors d'une partie de l'échange entre la pile, la destination du sélecteur de pile du bit TI est fixé, mais le sélecteur LDT n'est pas un sélecteur nulle.
 |  |  | X | Lors d'une partie de l'échange entre la pile, la destination du sélecteur de segment de pile dans le TSS est en dehors des limites de la table du descripteur GDT ou LDT.
 |  |  | X | Lors d'une partie de l'échange entre la pile, la destination du sélecteur de segment de pile dans le TSS contient un RPL n'est pas égale au DPL.
 |  |  | X | Lors d'une partie de l'échange entre la pile, la destination du sélecteur de segment de pile dans le TSS contient un DPL n'est pas égale au CPL du sélecteur de segment de code.
 |  |  | X | Lors d'une partie de l'échange entre la pile, la destination du sélecteur de segment de pile dans le TSS n'est pas dans un segment écrivable.
#UD(Opcode invalide) | X | X | X | L'appel long indirect avec le Opcode (FFh /3) est un opérande de registre.
 |  |  | X | L'appel long direct avec le Opcode (9Ah) est effectué en mode 64 bits.

Remarque

  • Si vous programmez avec des microprocesseurs ARM, il faut plutôt utiliser l'instruction «BL» à la place de «CALL».

Exemple

Voici un exemple en Turbo Pascal montrant l'utilisation de cette instruction :

  1. Program AsmCallSamples;
  3. Var _AX: Word ;
  5. BEGIN
  6. ASM
  7. CALL @SetValue
  8. JMP @End
  9. MOV AX,0002h
  10. @SetValue:
  11. MOV AX,0001h
  12. RETN
  13. @End:
  14. MOV _AX,AX
  15. END;
  16. WriteLn ('AX = ',_AX);
  17. END .

on obtiendra le résultat suivant :

AX = 1

Voir également

Instruction assembleur 80x86 - Instruction RET
Instruction assembleur 80x86 - Instruction RETF
Instruction assembleur 80x86 - Instruction RETN

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 806
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 401
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 76 à 83.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 168 à 185.


Assembleur 80x86

INT
INTEL 8088+ Interrupt

Syntaxe

INT numéro

Paramètres

Nom | Description
numéro | Ce paramètre permet d'indiquer le numéro d'interruption, soit un nombre situé entre 0 et 255 en décimal ou 00h et FFh en hexadécimal.

Description

Cette instruction permet d'exécuter l'interruption avec le numéro spécifié.

Algorithme

drapeaux préservé
SP ← SP - 2
drapeau IF ← 0
drapeau TF ← 0
CS préservé
SP ← SP - 2
IP préservé
CS ← Donnée à l'adresse mémoire (numéro x 4 + 2)
IP ← Donnée à l'adresse mémoire (numéro x 4)

Mnémonique

Instruction | Opcode | Description
INT 03h | CCh | Cette instruction permet d'exécuter l'interruption avec le numéro 03h.
INT imm8 | CDh ib | Appel une routine de service d'interruption spécifié par le vecteur imm8.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#TS(Sélecteur) |  | X | X | Une partie de l'échangeur de pile, la destination du sélecteur de segment de pile ou le registre (R)SP dans le TSS est en dehors des limites du TSS.
 |  | X | X | Une partie de l'échangeur de pile, la destination du sélecteur de segment de pile ou le registre (R)SP dans le TSS a sélecteur nulle.
 |  | X | X | Une partie de l'échangeur de pile, la destination du sélecteur du bit TS est fixé, mais le sélecteur LDT a un sélecteur nulle.
 |  | X | X | Une partie de l'échangeur de pile, la destination du sélecteur du TSS est en dehors des limites des tables de descripteur GDT ou LDT.
 |  | X | X | Une partie de l'échangeur de pile, la destination du sélecteur du TSS contient un RPL n'étant pas égale au DPL.
 |  | X | X | Une partie de l'échangeur de pile, la destination du sélecteur du TSS contient un DPL n'étant pas égale au CPL du sélecteur de code segment.
 |  | X | X | Une partie de l'échangeur de pile, la destination du sélecteur du TSS n'est pas dans un segment écrivable.
#NP(Segment non présent) |  | X | X | L'accès au segment de code, le pont d'interruption, le pont de la trappe, le pont de la tâche ou le TSS ne sont pas présent.
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#SS(Sélecteur) |  | X | X | Après un échange de pile, une adresse mémoire dépasse les limites du segment de pile ou est non-canonique.
 |  | X | X | Après un échange de pile, le registre SS est chargé dans un sélecteur de segment non-nulle et le segment est marqué comme non présent.
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 | X | X | X | La destination de déplacement dépasse la limite du segment de code ou n'est pas canonique.
 |  | X |  | Le IOPL est inférieur à 3 et le CR4.VME vaut 0.
 |  | X |  | Le IOPL est inférieur à 3, le CR4.VME vaut 1 et le bit correspondant à la redirection de la cartographie d'interruption VME vaut 1.
#GP(Sélecteur) | X | X | X | Le vecteur d'interruption est en dehors des limites du IDT.
 |  | X | X | Le descripteur d'IDT n'est pas une interruption, une trappe ou une tâche de pont dans un mode «legacy» ou n'est pas une interruption 64 bits ou un pont de trappe pour un mode «long».
 |  | X | X | Le DPL de l'interruption, de la trappe, du descripteur de pont de tâche est inférieur au CPL.
 |  | X | X | Le sélecteur de segment spécifié par l'interruption ou la trappe du pont est un bit TI fixé, mais le sélecteur LDT a un sélecteur nulle.
 |  | X | X | Le sélecteur de segment spécifié par l'interruption ou la trappe du pont dépasse la limite de la table de descripteur ou a un sélecteur nulle.
 |  | X | X | Le descripteur de segment spécifié par l'interruption ou le pont de la trappe n'est pas un segment de code dans un mode «legacy», ou un segment de code 64 bits dans un mode «long».
 |  |  | X | Le segment de DPL spécifié par l'interruption ou le pont de la trappe est supérieur au CPL.
 |  | X |  | Le segment de DPL spécifié par l'interruption ou le pont ne pointe pas sur 0 ou est dans un segment conforme.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

L'exemple suivant permet d'afficher un message «Bonjour» sur la console du système d'exploitation DOS :

  1. Message DB 'Bonjour$'
  2. ; Place des instructions ici
  3. MOV AH,09h
  4. MOV DX,Offset Message
  5. INT 21h

On obtiendra le résultat suivant :

Bonjour

Voir également

Liste des interruptions
Instruction assembleur 80x86 - Instruction INTO
Instruction assembleur 80x86 - Instruction IRET

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 814
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 405
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 122 à 128.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 581 à 595.


Assembleur 80x86

JMP
INTEL 8086+ Jump

Syntaxe

JMP destination

Paramètres

Nom | Description
destination | Ce paramètre permet d'indiquer l'emplacement ou doit être poursuivi l'exécution.

Description

Cette instruction permet d'effectuer un branchement à un emplacement mémoire spécifié.

Algorithme

SI near jump ALORS
SI saut relatif court ALORS
tempEIP ← EIP + destination
SINON
tempEIP ← destination
FIN SI
SI tempEIP est en dehors des limites du code segment ALORS
EXCEPTION #GP(0)
FIN SI
SI taille de l'opérande = 32 bits ALORS
EIP ← tempEIP
SINON
EIP ← tempEIP ∩ 0000FFFFh
FIN SI
FIN SI
SI saut long ET (PE = 0 OU (PE = 1 ET VM = 1)) ALORS * Adresse réel ou mode virtuel 8086
tempEIP ← destination(offset)
SI tempEIP est en dehors des limites du code de segment ALORS
EXCEPTION #GP(0)
FIN SI
CS ← destination(Sélecteur de segment)
SI taille de l'opérande = 32 bits ALORS
EIP ← tempEIP
SINON
EIP ← tempEIP ∩ 0000FFFFh
FIN SI
FIN SI
SI far jump ET (PE = 1 ET VM = 0) ALORS * Mode protégé, pas mode virtuel 8086
SI l'adresse effective dans les segments CS, DS, ES, FS, GS ou SS est illégale OU sélecteur de segment dans une destination d'opérande nulle ALORS
EXCEPTION #GP(0)
FIN SI
SI index de sélecteur de segment n'est pas dans la limite de descripteur de table ALORS
EXCEPTION #GP(nouveau sélecteur)
FIN SI
Lecture du type et de l'accès correct du descripteur de segment
SI type de segment n'est pas conforme OU code de segment non conforme, appel le pont, tâche du pont, ou TSS ALORS
EXCEPTION #GP(sélecteur de segment)
FIN SI
Type de dépendance et accès correct
ALLER A CONFORMING-CODE-SEGMENT
ALLER A NONCONFORMING-CODE-SEGMENT
ALLER A CALL-GATE
ALLER A TASK-GATE
ALLER A TASK-STATE-SEGMENT
SINON
EXCEPTION #GP(Sélecteur de segment)
FIN SI

CONFORMING-CODE-SEGMENT:
SI DPL > CPL ALORS
EXCEPTION #GP(Sélecteur de segment)
FIN SI
SI segment pas présent ALORS
EXCEPTION #NP(Sélecteur de segment)
FIN SI
tempEIP ← destination(Offset)
SI Taille de l'opérande = 16 bits ALORS
tempEIP ← tempEIP ∩ 0000FFFFh
FIN SI
SI tempEIP n'est pas dans la limite du code segment ALORS
EXCEPTION #GP(0)
FIN SI
CS ← destination(Sélecteur de segment)
CS(RPL) ← CPL
EIP ← tempEIP
FIN

NONCONFORMING-CODE-SEGMENT:
SI (RPL > CPL) OU (DPL = CPL) ALORS
EXCEPTION #GP(Sélecteur de code segment)
FIN SI
SI segment n'est pas présent ALORS
EXCEPTION #NP(Sélecteur de segment)
FIN SI
SI pointeur d'instruction est en dehors des limites du segment ALORS
EXCEPTION #GP(0)
FIN SI
tempEIP ← destination(offset)
SI taille de l'opérande = 16 bits ALORS
tempEIP ← tempEIP ∩ 0000FFFFh
FIN SI
SI tempEIP n'est pas dans les limites du code segment ALORS
EXCEPTION #GP(0)
FIN SI
CS ← destination(Sélecteur de segment)
CS(RPL) ← CPL
EIP ← tempEIP
FIN

CALL-GATE:
SI appel de pont DPL < CPL OU appel de pont DPL < appel de pont de sélecteur de segment RPL ALORS
EXCEPTION #GP(sélecteur d'appel de pont)
FIN SI
SI appel d'un pont non présent ALORS
EXCEPTION #NP(Sélecteur d'appel de pont)
FIN SI
SI appel d'un pont du sélecteur de code segment est nulle ALORS
EXCEPTION #GP(0)
FIN SI
SI appel d'un pont d'index de sélecteur de code de segment est en dehors des limites du descripteur de table ALORS
EXCEPTION #GP(sélecteur de code segment)
FIN SI
Lecture du descripteur de code segment
SI descripteur de code segment n'est pas indiquer dans le code segment OU descripteur de code segment est conforme et DPL > CPL OU decripteur de segment de code n'est pas conforme ET DPL = CPL ALORS
EXCEPTION #GP(Sélecteur de code segment)
FIN SI
SI code segment n'est pas présent ALORS
EXCEPTION #NP(sélecteur de code segment)
FIN SI
SI pointeur d'instruction n'est pas dans les limites du code segment ALORS
EXCEPTION #GP(0)
FIN SI
tempEIP ← destination(offset)
SI Taille du pont = 16 bits ALORS
tempEIP ← tempEIP ∩ 0000FFFFh
FIN SI
SI tempEIP n'est pas dans les limites du code segment ALORS
EXCEPTION #GP(0)
FIN SI
CS ← destination(Sélecteur de segment)
CS(RPL) ← CPL
EIP ← tempEIP
FIN

TASK-GATE:
SI tâche du pont DPL < CPL OU tâche du pont DPL < sélecteur de segment du pont de tâche RPL ALORS
EXCEPTION #GP(Sélecteur de tâche du pont)
FIN SI
SI pont de tâche n'est pas présent ALORS
EXCEPTION #NP(Sélecteur de pont)
FIN SI
Lecteur du sélecteur de segment TSS dans le descripteur de pont de tâche
SI bit de sélecteur de segment TSS local/global est fixer à local OU index n'est dans les limites du GDT OU que le descripteur TSS specifié est occupé ALORS
EXCEPTION #GP(Sélecteur TSS)
FIN SI
SI TSS n'est pas présent ALORS
EXCEPTION #NP(Sélecteur TSS)
FIN SI
SWITCH-TASKS à TSS
SI EIP n'est dans les limites de code de segment ALORS
EXCEPTION #GP(0)
FIN SI
FIN

TASK-STATE-SEGMENT:
SI TSS DPL < CPL OU TSS DPL < sélecteur de segment TSS RPL OU descripteur TSS indique que le TSS n'est pas disponible ALORS
EXCEPTION #GP(Sélecteur TSS)
FIN SI
SI TSS n'est pas présent ALORS
EXCEPTION #NP(Sélecteur TSS)
FIN SI
SWITCH-TASKS à TSS
SI EIP n'est pas dans les limites de code segment ALORS
EXCEPTION #GP(0)
FIN SI
FIN

Mnémonique

Instruction | Opcode | Description
JMP rel8off | EBh cb | Saut court à la destination spécifié par un déplacement signé de 8 bits
JMP rel16off | E9h cw | Saut court à la destination spécifié par un déplacement signé de 16 bits
JMP rel32off | E9h cd | Saut court à la destination spécifié par un déplacement signé de 32 bits
JMP reg/mem16 | FFh /4 | Saut court à la destination spécifié par un le registre/mémoire 16 bits
JMP reg/mem32 | FFh /4 | Saut court à la destination spécifié par un le registre/mémoire 32 bits
JMP reg/mem64 | FFh /4 | Saut court à la destination spécifié par un le registre/mémoire 64 bits
JMP FAR pntr16:16 | EAh cd | Saut long direct avec la destination spécifié par un long pointeur contenu dans l'instruction. Cette instruction est invalide en mode 64 bits.
JMP FAR pntr16:32 | EAh cp | Saut long direct avec la destination spécifié par un long pointeur contenu dans l'instruction. Cette instruction est invalide en mode 64 bits.
JMP FAR mem16:16 | FFh /5 | Saut long indirect avec la destination spécifié par un long pointeur contenu en mémoire. Cette instruction est invalide en mode 64 bits.
JMP FAR mem16:32 | FFh /5 | Saut long indirect avec la destination spécifié par un long pointeur contenu en mémoire. Cette instruction est invalide en mode 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) | X | X | X | Cette instruction est exécuté en mode 64-bits avec un code un opcode indirect JMP (FFh /5) dans un opérande de registre.
 |  |  | X | Cette instruction est exécuté en mode 64-bits avec un code un opcode direct JMP (EAh)
#SS(Pile non-canonique) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#NP(Sélecteur) |  |  | X | L'accès au segment de code, au pont d'appel, un pont de tâche, ou a un TSS non présent.
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#GP(Sélecteur) |  |  | X | La destination de sélecteur de segment de code est un sélecteur nulle.
 |  |  | X | Un code, un pont d'appel, une tâche de pont, ou un descripteur TSS dépasse la limite de descripteur de table.
 |  |  | X | Un sélecteur de segment de bit TI est fixé, mais le sélecteur LDT est un sélecteur nulle.
 |  |  | X | Le descripteur de segment spécifié par l'instruction n'est pas un segment de code, une tâche de pont, un pont d'appel, ou un TSS disponible dans le mode «legacy», ou n'est pas un segment de code 64 bits ou un appel 64 bits long d'un pont dans le mode «long».
 |  |  | X | Le RPL d'un sélecteur de segment de code non-conforme spécifié par l'instruction est supérieur au CPL, ou le DPL n'est pas égale au CPL.
 |  |  | X | Le DPL du descripteur de segment de code spécifié est conforme quand l'instruction est supérieur au CPL.
 |  |  | X | Le DPL est un pont d'appel, une tâche de pont, un descripteur TSS spécifié quand l'instruction est inférieur au CPL ou au RPL.
 |  |  | X | Le sélecteur de segment spécifié par le pont d'appel ou le pont de tâche est un sélecteur nulle.
 |  |  | X | Le descripteur de segment spécifié par l'appel de pont n'est pas un segment de code en mode «legacy» ou segment de code 64 bits dans un mode «long».
 |  |  | X | Le DPL du descripteur de segment spécifié par le pont d'appel est supérieur au CPL et dans un segment conforme.
 |  |  | X | Le DPL du descripteur de segment spécifié par le pont d'appel n'est pas égale au CPL et il n'est pas dans un segment conforme.
 |  |  | X | L'attribut étendue du pont d'appel 64 bits n'est pas à 0.
 |  |  | X | Le descripteur TSS n'est pas un LDT.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Cet exemple permet d'effectuer un saut à partir d'un tableau d'adresse :

  1. .MODEL small
  2. .STACK 100h
  3. .DATA
  4. .CODE
  5. CheckVideoCard PROC NEAR
  6. MOV AX,1A00h
  7. INT 10h
  8. CMP AL,1Ah
  9. JNE @@Default
  10. @@RePass:
  11. AND BX,000Fh
  12. SHL BX,1
  13. JMP Word Ptr CS:[Offset @PS2Jmp+BX]
  14. @PS2Jmp:
  15. DW Offset @@NoEGAExist ; 0h
  16. DW Offset @@Default ; 1h
  17. DW Offset @@Default ; 2h
  18. DW Offset @@Default ; 3h
  19. DW Offset @@EgaDefault ; 4h
  20. DW Offset @@EgaDefault ; 5h
  21. DW Offset @@PGA ; 6h
  22. DW Offset @@VGAPS2 ; 7h
  23. DW Offset @@VGAPS2 ; 8h
  24. DW Offset @@Default ; 9h
  25. DW Offset @@MCGADigitalColor ; Ah
  26. DW Offset @@MCGAAnalogMono ; Bh
  27. DW Offset @@MCGAPS2 ; Ch
  28. DW Offset @@Default ; Dh
  29. DW Offset @@Default ; Eh
  30. DW Offset @@Default ; Fh
  31. @@Default:
  32. ; ...
  33. JMP @@SetCardNExit
  34. @@NoPCJunior:
  35. ; ...
  36. JMP @@SetCardNExit
  37. @@EgaDefault:
  38. ; ...
  39. JMP @@SetCardNExit
  40. @@PGA:
  41. ; ...
  42. JMP @@SetCardNExit
  43. @@VGAPS2:
  44. ; ...
  45. JMP @@SetCardNExit
  46. @@NoEGAExist:
  47. ; ...
  48. JMP @@SetCardNExit
  49. @@MCGADigitalColor:
  50. ; ...
  51. JMP @@SetCardNExit
  52. @@MCGAAnalogMono:
  53. ; ...
  54. JMP @@SetCardNExit
  55. @@MCGAPS2:
  56. ; ...
  57. @@SetCardNExit:
  58. RET
  59. ENDP
  61. .startup
  62. ; ...
  63. INT 21h
  64. MOV AX,4C00h
  65. INT 21h
  66. END

Voici un exemple, en Turbo Pascal 7, permettant d'afficher un message en utilisant le segment de code pour entreposer les données et sauter la partie du code étant en faite des données :

  1. Program AsmJmp;
  3. BEGIN
  4. ASM
  5. JMP @End
  6. @MessageBonjour:
  7. DB 'Mon message...$'
  8. @End:
  9. PUSH DS
  10. PUSH CS
  11. POP DS
  12. MOV AH,9
  13. MOV DX,OFFSET @MessageBonjour
  14. INT 21h
  15. POP DS
  16. END;
  17. END .

Voir également

Langage de programmation - Instruction assembleur 80x86 - Instruction Jump if (JA, JB, JC, JCX, JE,...)
Langage de programmation - Assembleur 8080 et 8085 - Référence des instructions 8080 et 8085 - JMP
Langage de programmation - SAS/JMP

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 816
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 135.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 619 à 629.


Assembleur 80x86

RET
INTEL 8088+ Return

Syntaxe

RET
RET immédiat

Description

Cette instruction permet de quitter une procédure. Ainsi, elle indique au microprocesseur qu'il doit désempiler la valeur du pointeur d'instructions contenu dans la pile et la copier dans les registres CS:IP pour une procédure de type FAR ou dans le registre IP pour une procédure de type NEAR. Ensuite, l'exécution du code se poursuit à l'instruction suivant l'instruction «CALL».

Algorithme

SI instruction = RETN ALORS
SI opérande de taille = 32 bits ALORS
SI les 12 octets du haut de la pile sont en dehors de la limite de la pile ALORS
EXCEPTION #SS(0)
FIN SI
EIP ← Pop()
SINON
SI les 6 octets du haut de la pile sont en dehors de la limite de la pile ALORS
EXCEPTION #SS(0)
FIN SI
tempEIP ← Pop()
tempEIP ← tempEIP ∩ 0000FFFFh
SI tempEIP n'est pas dans limite du segment de code ALORS
EXCEPTION #GP(0)
FIN SI
EIP ← tempEIP
FIN SI
SI instruction a une opérande immédiate ALORS
SI taille de l'adresse de la pile = 32 bits ALORS
ESP ← ESP + SRC
SINON
SP ← SP + SRC
FIN SI
FIN SI
FIN SI

SI ((PE = 0) OU (PE = 1 ET VM = 1)) ET instruction RETF ALORS
SI taille de l'opérande = 32 bits ALORS
SI les 12 octets du haut de la pile sont en dehors de la limite de la pile ALORS
EXCEPTION #SS(0)
FIN SI
EIP ← Pop()
CS ← Pop()
SINON
SI les 6 octets du haut de la pile sont en dehors de la limite de la pile ALORS
EXCEPTION #SS(0)
FIN SI
tempEIP ← Pop()
tempEIP ← tempEIP ∩ 0000FFFFh
SI tempEIP n'est pas dans limite du segment de code ALORS
EXCEPTION #GP(0)
FIN SI
EIP ← tempEIP
CS ← Pop()
FIN SI
SI instruction a une opérande immédiate ALORS
SP ← SP + (SRC ∩ FFFFh)
FIN SI
FIN SI

SI (PE = 1 ET VM = 0) ET instruction RETF ALORS
SI taille de l'opérande = 32 bits ALORS
SI le deuxième double mot de la pile est en dehors de la limite de la pile ALORS
EXCEPTION #SS(0)
FIN SI
FIN SI
SI sélecteur de code de retour est nulle ALORS
EXCEPTION GP(0)
FIN SI
SI adresse du sélecteur de retour de code segment est en dehors des limites de la table de descripteur ALORS
EXCEPTION GP(selecteur)
FIN SI
Demande le descripteur avec le point du sélecteur de segment de code de retour du descripteur de table
SI descripteur de retour de code segment n'est pas un code segment ALORS
EXCEPTION #GP(selecteur)
FIN SI
SI selecteur de retour de segment de code RPL < CPL ALORS
EXCEPTION #GP(Sélecteur)
FIN SI
SI descripteur retour de code de segment retour est conforme ET retour de segment de code DPL > sélecteur de retour de segment de code RPL ALORS
EXCEPTION #GP(Sélecteur)
FIN SI
SI descripteur de retour segment de code n'est pas présent ALORS
EXCEPTION #NP(Sélecteur)
FIN SI
SI sélecteur de retour de segment de code RPL > CPL ALORS
ALLER A RETURN-OUTER-PRIVILEGE-LEVEL
SINON
ALLER A RETURN-TO-SAME-PRIVILEGE-LEVEL
FIN SI
FIN SI

RETURN-SAME-PRIVILEGE-LEVEL:
SI l'instruction de pointeur n'est pas à l'intérieur de la limite de segment de code ALORS
EXCEPTION #GP(0)
FIN SI
SI taille de l'opérande = 32 bits ALORS
EIP ← Pop()
CS ← Pop()
ESP ← ESP + SRC
SINON
EIP ← Pop()
EIP ← EIP ∩ 0000FFFFh
CS ← Pop()
ESP ← ESP + SRC
FIN SI

RETURN-OUTER-PRIVILEGE-LEVEL:
SI (16 + SRC) octets du haut de la pile sont en dehors de la limite de la pile ET taille de l'opérande = 32 bits OU (8 + SRC) octets du haut de la pile sont en dehors de la limite de la pile ET taille de l'opérande = 16 ALORS
EXCEPTION #SS(0)
FIN SI
Lecture du sélecteur de retour de segment
SI sélecteur de segment de pile n'est pas nulle ALORS
EXCEPTION #GP(0)
FIN SI
SI index de retour du sélecteur de segment n'est pas dans les limites du descripteur de table ALORS
EXCEPTION #GP(selector)
FIN SI
Lecture du descripteur de segment pointant sur le retour de sélecteur de segment
SI sélecteur de segment de pile RPL <> RPL du retour de sélecteur de segment de code OU segment de pile n'est pas dans une segment de données écrivable OU descripteur de segment de pile DPL <> RPL de retour de sélecteur de segment de code ALORS
EXCEPTION #GP(Séelecteur)
FIN SI
SI segment de pile n'est pas présent ALORS
EXCEPTION #SS(Sélecteur de segment de pile)
FIN SI
SI pointeur de retourn d'instruction n'est pas dans la limite de segment de code ALORS
EXCEPTION #GP(0)
FIN SI
CPL ← Retour du sélecteur de segment de code du RPL
SI taille de l'opérande = 32 bits ALORS
EIP ← Pop()
CS ← Pop()
CS(RPL) ← CPL
ESP ← ESP + SRC
tempESP ← Pop()
tempSS ← Pop()
ESP ← tempESP
SS ← tempSS
SINON
EIP ← Pop()
EIP ← EIP ∩ 0000FFFFh
CS ← Pop()
CS(RPL) ← CPL
ESP ← ESP + SRC
tempESP ← Pop()
tempSS ← Pop()
ESP ← tempESP
SS ← tempSS
FIN SI
BOUCLE POUR chaque registre de segment (ES, FS, GS et DS) FAIRE
SI registre de segment pointe sur des données ou segment de code est non-conforme ET CPL > descripteur de segment DPL ALORS
Sélecteur de segment ← 0
FIN SI
FIN BOUCLE POUR
BOUCLE POUR chaque registre de segment ES, FS, GS et DS FAIRE
SI index de sélecteur de segment est en dehors de la limite du descripteur de table OU descripteur de segment indique que le segment n'est pas dans des données OU lecteur de segment de code si le segment de données OU segment de code non-conforme ET descripteur de segment DPL < CPL OU RPL du sélecteur de segment de code ALORS
Sélecteur de egistre de segment ← Sélecteur nulle
FIN SI
FIN BOUCLE POUR
ESP ← ESP + SRC

Mnémonique

Instruction | Opcode | Description
RET | C3h | Retour d'un appel de procédure court.
RET imm16 | C2h iw | Retour d'un appel de procédure court et spécifie le nombre d'octets à retirer de la pile.
RET | CBh | Retour d'un appel de procédure long.
RET imm16 | CAh iw | Retour d'un appel de procédure long et spécifie le nombre d'octets à retirer de la pile.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
#NP(Sélecteur) |  |  | X | Le retour de segment de code est marqué non présent.
#SS(Sélecteur) | X | X | X | Le registre SS est chargé avec un sélecteur non-nulle et le segment est marqué non présent.
#GP(Sélecteur) |  |  | X | Le sélecteur de code de retour est un sélecteur nulle.
 |  |  | X | Le sélecteur de retour de pile et de mode de retour n'est pas un mode 64 bits ou CPL vaut 3.
 |  |  | X | Le code de retour ou le descripteur de pile dépasse la limite du descripteur de table.
 |  |  | X | Le code de retour ou le bit TI du sélecteur de pile est fixé mais le sélecteur LDT n'est pas un sélecteur nulle.
 |  |  | X | Le descripteur de segment pour le code retour n'est pas un segment de code.
 |  |  | X | Le RPL du sélecteur du retour de segment de code est inférieur au CPL.
 |  |  | X | Le retour du segment de code n'est pas conforme et le sélecteur de segment DPL n'est pas égale au RPL du sélecteur de segment de code.
 |  |  | X | Le retour du segment de code est conforme et le sélecteur de segment DPL est supérieur au RPL du sélecteur de segment de code.
 |  |  | X | Le descripteur de segment pour le retour de pile n'est pas dans segment de données écrivable.
 |  |  | X | Le descripteur de segment de pile DPL n'est pas égale au RPL du sélecteur de retour de segment de code.
 |  |  | X | Le sélecteur de segment de pile RPL n'est pas égale au RPL du retour de sélecteur de segment de code.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 830
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 414
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 207.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 366 à 376.


Assembleur 80x86

RETF
INTEL 8088+ Return Far

Syntaxe

RETF
RETF immédiat

Description

Cette instruction permet de quitter une procédure ayant lieu avec un appel long (FAR CALL). Ainsi, elle indique au microprocesseur qu'il doit désempiler la valeur du pointeur d'instructions contenu dans la pile et la copier dans les registres CS:IP. Ensuite, l'exécution du code se poursuit à l'instruction suivant l'instruction «CALL».

Algorithme

SI ((PE = 0) OU (PE = 1 ET VM = 1)) ALORS
SI taille de l'opérande = 32 bits ALORS
SI les 12 octets du haut de la pile sont en dehors de la limite de la pile ALORS
EXCEPTION #SS(0)
FIN SI
EIP ← Pop()
CS ← Pop()
SINON
SI les 6 octets du haut de la pile sont en dehors de la limite de la pile ALORS
EXCEPTION #SS(0)
FIN SI
tempEIP ← Pop()
tempEIP ← tempEIP ∩ 0000FFFFh
SI tempEIP n'est pas dans limite du segment de code ALORS
EXCEPTION #GP(0)
FIN SI
EIP ← tempEIP
CS ← Pop()
FIN SI
SI instruction a une opérande immédiate ALORS
SP ← SP + (SRC ∩ FFFFh)
FIN SI
FIN SI

SI (PE = 1 ET VM = 0) ALORS
SI taille de l'opérande = 32 bits ALORS
SI le deuxième double mot de la pile est en dehors de la limite de la pile ALORS
EXCEPTION #SS(0)
FIN SI
FIN SI
SI sélecteur de code de retour est nulle ALORS
EXCEPTION GP(0)
FIN SI
SI adresse du sélecteur de retour de code segment est en dehors des limites de la table de descripteur ALORS
EXCEPTION GP(selecteur)
FIN SI
Demande le descripteur avec le point du sélecteur de segment de code de retour du descripteur de table
SI descripteur de retour de code segment n'est pas un code segment ALORS
EXCEPTION #GP(selecteur)
FIN SI
SI selecteur de retour de segment de code RPL < CPL ALORS
EXCEPTION #GP(Sélecteur)
FIN SI
SI descripteur retour de code de segment retour est conforme ET retour de segment de code DPL > sélecteur de retour de segment de code RPL ALORS
EXCEPTION #GP(Sélecteur)
FIN SI
SI descripteur de retour segment de code n'est pas présent ALORS
EXCEPTION #NP(Sélecteur)
FIN SI
SI sélecteur de retour de segment de code RPL > CPL ALORS
ALLER A RETURN-OUTER-PRIVILEGE-LEVEL
SINON
ALLER A RETURN-TO-SAME-PRIVILEGE-LEVEL
FIN SI
FIN SI

RETURN-SAME-PRIVILEGE-LEVEL:
SI l'instruction de pointeur n'est pas à l'intérieur de la limite de segment de code ALORS
EXCEPTION #GP(0)
FIN SI
SI taille de l'opérande = 32 bits ALORS
EIP ← Pop()
CS ← Pop()
ESP ← ESP + SRC
SINON
EIP ← Pop()
EIP ← EIP ∩ 0000FFFFh
CS ← Pop()
ESP ← ESP + SRC
FIN SI

RETURN-OUTER-PRIVILEGE-LEVEL:
SI (16 + SRC) octets du haut de la pile sont en dehors de la limite de la pile ET taille de l'opérande = 32 bits OU (8 + SRC) octets du haut de la pile sont en dehors de la limite de la pile ET taille de l'opérande = 16 ALORS
EXCEPTION #SS(0)
FIN SI
Lecture du sélecteur de retour de segment
SI sélecteur de segment de pile n'est pas nulle ALORS
EXCEPTION #GP(0)
FIN SI
SI index de retour du sélecteur de segment n'est pas dans les limites du descripteur de table ALORS
EXCEPTION #GP(selector)
FIN SI
Lecture du descripteur de segment pointant sur le retour de sélecteur de segment
SI sélecteur de segment de pile RPL <> RPL du retour de sélecteur de segment de code OU segment de pile n'est pas dans une segment de données écrivable OU descripteur de segment de pile DPL <> RPL de retour de sélecteur de segment de code ALORS
EXCEPTION #GP(Séelecteur)
FIN SI
SI segment de pile n'est pas présent ALORS
EXCEPTION #SS(Sélecteur de segment de pile)
FIN SI
SI pointeur de retourn d'instruction n'est pas dans la limite de segment de code ALORS
EXCEPTION #GP(0)
FIN SI
CPL ← Retour du sélecteur de segment de code du RPL
SI taille de l'opérande = 32 bits ALORS
EIP ← Pop()
CS ← Pop()
CS(RPL) ← CPL
ESP ← ESP + SRC
tempESP ← Pop()
tempSS ← Pop()
ESP ← tempESP
SS ← tempSS
SINON
EIP ← Pop()
EIP ← EIP ∩ 0000FFFFh
CS ← Pop()
CS(RPL) ← CPL
ESP ← ESP + SRC
tempESP ← Pop()
tempSS ← Pop()
ESP ← tempESP
SS ← tempSS
FIN SI
BOUCLE POUR chaque registre de segment (ES, FS, GS et DS) FAIRE
SI registre de segment pointe sur des données ou segment de code est non-conforme ET CPL > descripteur de segment DPL ALORS
Sélecteur de segment ← 0
FIN SI
FIN BOUCLE POUR
BOUCLE POUR chaque registre de segment ES, FS, GS et DS FAIRE
SI index de sélecteur de segment est en dehors de la limite du descripteur de table OU descripteur de segment indique que le segment n'est pas dans des données OU lecteur de segment de code si le segment de données OU segment de code non-conforme ET descripteur de segment DPL < CPL OU RPL du sélecteur de segment de code ALORS
Sélecteur de egistre de segment ← Sélecteur nulle
FIN SI
FIN BOUCLE POUR
ESP ← ESP + SRC

Mnémonique

Instruction | Opcode | Description
RETF | CBh | Retour d'un appel de procédure long.
RETF imm16 | CAh iw | Retour d'un appel de procédure long et spécifie le nombre d'octets à retirer de la pile.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#NP(Sélecteur) |  |  | X | Le retour de segment de code est marqué non présent.
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#SS(Sélecteur) | X | X | X | Le registre SS est chargé avec un sélecteur non-nulle et le segment est marqué non présent.
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
#GP(Sélecteur) |  |  | X | Le sélecteur de code de retour est un sélecteur nulle.
 |  |  | X | Le sélecteur de retour de pile et de mode de retour n'est pas un mode 64 bits ou CPL vaut 3.
 |  |  | X | Le code de retour ou le descripteur de pile dépasse la limite du descripteur de table.
 |  |  | X | Le code de retour ou le bit TI du sélecteur de pile est fixé mais le sélecteur LDT n'est pas un sélecteur nulle.
 |  |  | X | Le descripteur de segment pour le code retour n'est pas un segment de code.
 |  |  | X | Le RPL du sélecteur du retour de segment de code est inférieur au CPL.
 |  |  | X | Le retour du segment de code n'est pas conforme et le sélecteur de segment DPL n'est pas égale au RPL du sélecteur de segment de code.
 |  |  | X | Le retour du segment de code est conforme et le sélecteur de segment DPL est supérieur au RPL du sélecteur de segment de code.
 |  |  | X | Le descripteur de segment pour le retour de pile n'est pas dans segment de données écrivable.
 |  |  | X | Le descripteur de segment de pile DPL n'est pas égale au RPL du sélecteur de retour de segment de code.
 |  |  | X | Le sélecteur de segment de pile RPL n'est pas égale au RPL du retour de sélecteur de segment de code.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction CALL
Instruction assembleur 80x86 - Instruction RET


Assembleur 80x86

RETN
INTEL 8088+ Return Near

Syntaxe

RETN
RETN immédiat

Description

Cette instruction permet de quitter une procédure. Ainsi, elle indique au microprocesseur qu'il doit désempiler la valeur du pointeur d'instructions contenu dans la pile et la copie dans le registre IP. Ensuite, l'exécution du code se poursuit à l'instruction suivant l'instruction «CALL».

Algorithme

SI opérande de taille = 32 bits ALORS
SI les 12 octets du haut de la pile sont en dehors de la limite de la pile ALORS
EXCEPTION #SS(0)
FIN SI
EIP ← Pop()
SINON
SI les 6 octets du haut de la pile sont en dehors de la limite de la pile ALORS
EXCEPTION #SS(0)
FIN SI
tempEIP ← Pop()
tempEIP ← tempEIP ∩ 0000FFFFh
SI tempEIP n'est pas dans limite du segment de code ALORS
EXCEPTION #GP(0)
FIN SI
EIP ← tempEIP
FIN SI
SI instruction a une opérande immédiate ALORS
SI taille de l'adresse de la pile = 32 bits ALORS
ESP ← ESP + SRC
SINON
SP ← SP + SRC
FIN SI
FIN SI

Mnémonique

Instruction | Opcode | Description
RETN | C3h | Retour d'un appel de procédure court.
RETN imm16 | C2h iw | Retour d'un appel de procédure court et spécifie le nombre d'octets à retirer de la pile.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Voici un exemple en Turbo Pascal montrant l'utilisation de cette instruction :

  1. Program RetNCallSamples;
  3. Var _AX: Word ;
  5. BEGIN
  6. ASM
  7. CALL @SetValue
  8. JMP @End
  9. MOV AX,0002h
  10. @SetValue:
  11. MOV AX,0001h
  12. CALL @Next
  13. CALL @Next
  14. CALL @Next
  15. RETN
  16. @Next:
  17. INC AX
  18. RETN
  19. @End:
  20. MOV _AX,AX
  21. END;
  22. WriteLn ('AX = ',_AX);
  23. END .

on obtiendra le résultat suivant :

AX = 4

Voir également

Instruction assembleur 80x86 - Instruction CALL
Instruction assembleur 80x86 - Instruction RET


Voici les instructions assembleur classés par catégorie de transferts de données :

Instruction | Description | CPU/MPU
LDS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment DS et dans un registre d'offset spécifié. | INTEL 8086+
LEA | Cette instruction permet de copier l'offset d'une adresse de mémoire contenu dans un registre spécifié. | INTEL 8086+
LES | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment ES et dans un registre d'offset spécifié. | INTEL 8086+
LFS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment FS et dans un registre d'offset spécifié. | INTEL 80386+
LGS | Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment GS et dans un registre d'offset spécifié. | INTEL 80386+
LODS | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction. | INTEL 8086+
LODSB | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 1 en fonction de l'état du drapeau de direction. | INTEL 8086+
LODSD | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
LODSW | Cette instruction permet de copier un élément de l'adresse DS:SI dans le registre accumulateur et incrémente/décrémente le registre SI de 2 en fonction de l'état du drapeau de direction. | INTEL 8086+
MOV | Cette instruction permet de copier opérande source dans une opérande destinataire. | INTEL 8086+
MOVS | Cette instruction permet de copier un élément de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI en fonction de la taille de l'opérande source et de l'état du drapeau de direction. | INTEL 8086+
MOVSB | Cette instruction permet de copier un octet de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 1 en fonction de l'état du drapeau de direction. | INTEL 8086+
MOVSD | Cette instruction permet de copier un double mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
MOVSW | Cette instruction permet de copier un mot de l'adresse DS:SI dans l'adresse ES:DI et incrémente/décrémente les registres DI et SI de 2 en fonction de l'état du drapeau de direction. | INTEL 8086+
STOS | Cette instruction permet de copier un octet, un mot ou un double mot dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI en fonction de la taille de l'opérande cible et de l'état du drapeau de direction. | INTEL 8086+
STOSB | Cette instruction permet de copier le registre AL dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 1 en fonction de l'état du drapeau de direction. | INTEL 8086+
STOSD | Cette instruction permet de copier le registre EAX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 4 en fonction de l'état du drapeau de direction. | INTEL 80386+
STOSW | Cette instruction permet de copier le registre AX dans la cellule mémoire à l'adresse ES:[DI] et incrémente/décrémente le registre DI de 2 en fonction de l'état du drapeau de direction. | INTEL 8086+
XCHG | Cette instruction permet d'échanger la valeur de deux opérandes. | INTEL 8088+
XLAT | Cette instruction permet de remplacer le contenu du registre AL par un octet de la «tablesource». | INTEL 8088+

Dernière mise à jour : Vendredi, le 4 mars 2016


Assembleur 80x86

LDS
INTEL 8088+ Load in DS

Syntaxe

LDS opérande_cible,opérande_source

Description

Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment DS et dans un registre d'offset spécifié.

Algorithme

Registre d'offset ← Source
Registre de segment DS ← Source + 2

Mnémonique

Instruction | Opcode | Description
LDS reg16, mem16:16 | C5h /r | Charge le DS:reg16 avec un pointeur long dans la mémoire. Invalide en mode 64 bits.
LDS reg32, mem16:32 | C5h /r | Charge le DS:reg32 avec un pointeur long dans la mémoire. Invalide en mode 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) | X | X | X | L'opérande source est un registre.
 |  |  | X | Cette instruction est exécuté en mode 64-bits.
#NP(Sélecteur) |  |  | X | Le registre DS, ES, FS ou GS est chargé avec un sélecteur de segment non-nulle et le segment est marqué comme non présent.
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#SS(Sélecteur) | X | X | X | Le registre SS est chargé avec un sélecteur de segment non-nulle et le segment est marqué comme non présent.
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#GP(Sélecteur) | X | X | X | Un registre de segment est chargé, mais le descripteur de segment dépasse la limite du descripteur de la table.
 | X | X | X | Un registre de segment est chargé et le bit TI de sélecteur de segment est fixé, mais le sélecteur LDT est un sélecteur nulle.
 | X | X | X | Le registre SS est chargé avec un sélecteur de segment nulle dans un mode 64-bits ou avec CPL = 3.
 | X | X | X | Le registre SS est chargé avec un sélecteur de segment RPL et le descripteur de segment DPL n'est pas égale au CPL.
 | X | X | X | Le registre SS est chargé et le pointeur de segment n'est pas dans un segment de données écrivable.
 | X | X | X | Le registre DS, ES, FS ou GS n'est pas chargé et le segment pointe sur des données ou un segment de code non-conforme, mais le RPL ou CPL est supérieur au DPL.
 | X | X | X | Le registre DS, ES, FS ou GS n'est pas chargé et le segment pointe sur des données ou un segment de code en lecture.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 817
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 409
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 143.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 642 à 646.


Assembleur 80x86

LEA
INTEL 8088+ Load Effective Address

Syntaxe

LEA opérande_cible,opérande_source

Description

Cette instruction permet d'incrémenter un registre ou un emplacement mémoire.

Algorithme

Destination ← Adresse (source)

Mnémonique

Instruction | Opcode | Description
LEA reg16, mem | 8Dh /r | Entrepose l'adresse effective dans un registre 16 bits.
LEA reg32, mem | 8Dh /r | Entrepose l'adresse effective dans un registre 32 bits.
LEA reg64, mem | 8Dh /r | Entrepose l'adresse effective dans un registre 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) | X | X | X | L'opérande source est un registre.

Voir également

Instruction assembleur 80x86 - Instruction MOV

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 817
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 409
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 145.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 647 à 651.


Assembleur 80x86

LES
INTEL 8088+ Load in ES

Syntaxe

LES opérande_cible,opérande_source

Description

Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment ES et dans un registre d'offset spécifié.

Algorithme

Registre d'offset ← Source
Registre de segment ES ← Source + 2

Mnémonique

Instruction | Opcode | Description
LES reg16, mem16:16 | C4h /r | Charge le ES:reg16 avec un pointeur long dans la mémoire. Invalide en mode 64 bits.
LES reg32, mem16:32 | C4h /r | Charge le ES:reg32 avec un pointeur long dans la mémoire. Invalide en mode 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) | X | X | X | L'opérande source est un registre.
 |  |  | X | Cette instruction est exécuté en mode 64-bits.
#NP(Sélecteur) |  |  | X | Le registre DS, ES, FS ou GS est chargé avec un sélecteur de segment non-nulle et le segment est marqué comme non présent.
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#SS(Sélecteur) | X | X | X | Le registre SS est chargé avec un sélecteur de segment non-nulle et le segment est marqué comme non présent.
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#GP(Sélecteur) | X | X | X | Un registre de segment est chargé, mais le descripteur de segment dépasse la limite du descripteur de la table.
 | X | X | X | Un registre de segment est chargé et le bit TI de sélecteur de segment est fixé, mais le sélecteur LDT est un sélecteur nulle.
 | X | X | X | Le registre SS est chargé avec un sélecteur de segment nulle dans un mode 64-bits ou avec CPL = 3.
 | X | X | X | Le registre SS est chargé avec un sélecteur de segment RPL et le descripteur de segment DPL n'est pas égale au CPL.
 | X | X | X | Le registre SS est chargé et le pointeur de segment n'est pas dans un segment de données écrivable.
 | X | X | X | Le registre DS, ES, FS ou GS n'est pas chargé et le segment pointe sur des données ou un segment de code non-conforme, mais le RPL ou CPL est supérieur au DPL.
 | X | X | X | Le registre DS, ES, FS ou GS n'est pas chargé et le segment pointe sur des données ou un segment de code en lecture.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Cette exemple permet de retourner dans la paire de registres DX:AX, l'heure de l'horloge étant incrémenté à tous les 18,2 par seconde. Pour se faire il utilise une méthode d'accès directe à la mémoire et prend soit de ne pas être interrompu par un IRQ. L'astuce de l'utilisation de cette instruction consiste au fait qu'il utilise une seule instruction pour un chargé double mot de 32 bits (l'instruction LES) plutôt que deux instructions MOV beaucoup plus longue en cycle d'horloge et en consommation d'octets :

  1. PUSH 0
  2. POP ES
  3. XOR AX,AX
  4. MOV ES,AX
  5. CLI
  6. LES AX,ES:[$46C]
  7. STI
  8. MOV DX,ES

Cette routine est utilisé dans le coeur de la bibliothèque «RLL» de l'application «MonsterBook» par soucis de performance lorsqu'on tant de faire jouer des «.MOD» en arrière plan en même temps que le «MonsterBook» fonctionne.

Voir également

Instruction assembleur 80x86 - Instruction LDS
Instruction assembleur 80x86 - Instruction LFS
Instruction assembleur 80x86 - Instruction LGS
Instruction assembleur 80x86 - Instruction LSS

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 817
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 410
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 143.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 642 à 646.


Assembleur 80x86

LFS
INTEL 80386+ Load in FS

Syntaxe

LFS opérande_cible,opérande_source

Description

Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment FS et dans un registre d'offset spécifié.

Algorithme

Registre d'offset ← Source
Registre de segment FS ← Source + 2

Mnémonique

Instruction | Opcode | Description
LFS reg16, mem16:16 | 0Fh B4h /r | Charge le FS:reg16 avec un pointeur long dans la mémoire. Invalide en mode 64 bits.
LFS reg32, mem16:32 | 0Fh B4h /r | Charge le FS:reg32 avec un pointeur long dans la mémoire. Invalide en mode 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) | X | X | X | L'opérande source est un registre.
 |  |  | X | Cette instruction est exécuté en mode 64-bits.
#NP(Sélecteur) |  |  | X | Le registre DS, ES, FS ou GS est chargé avec un sélecteur de segment non-nulle et le segment est marqué comme non présent.
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#SS(Sélecteur) | X | X | X | Le registre SS est chargé avec un sélecteur de segment non-nulle et le segment est marqué comme non présent.
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#GP(Sélecteur) | X | X | X | Un registre de segment est chargé, mais le descripteur de segment dépasse la limite du descripteur de la table.
 | X | X | X | Un registre de segment est chargé et le bit TI de sélecteur de segment est fixé, mais le sélecteur LDT est un sélecteur nulle.
 | X | X | X | Le registre SS est chargé avec un sélecteur de segment nulle dans un mode 64-bits ou avec CPL = 3.
 | X | X | X | Le registre SS est chargé avec un sélecteur de segment RPL et le descripteur de segment DPL n'est pas égale au CPL.
 | X | X | X | Le registre SS est chargé et le pointeur de segment n'est pas dans un segment de données écrivable.
 | X | X | X | Le registre DS, ES, FS ou GS n'est pas chargé et le segment pointe sur des données ou un segment de code non-conforme, mais le RPL ou CPL est supérieur au DPL.
 | X | X | X | Le registre DS, ES, FS ou GS n'est pas chargé et le segment pointe sur des données ou un segment de code en lecture.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Références

Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 642 à 646.


Assembleur 80x86

LGS
INTEL 80386+ Load in GS

Syntaxe

LGS opérande_cible,opérande_source

Description

Cette instruction permet de copier une adresse de mémoire contenu sur 32 bits dans la paire de registre de segment FS et dans un registre d'offset spécifié.

Algorithme

Registre d'offset ← Source
Registre de segment GS ← Source + 2

Mnémonique

Instruction | Opcode | Description
LGS reg16, mem16:16 | 0Fh B5h /r | Charge le GS:reg16 avec un pointeur long dans la mémoire. Invalide en mode 64 bits.
LGS reg32, mem16:32 | 0Fh B5h /r | Charge le GS:reg32 avec un pointeur long dans la mémoire. Invalide en mode 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) | X | X | X | L'opérande source est un registre.
 |  |  | X | Cette instruction est exécuté en mode 64-bits.
#NP(Sélecteur) |  |  | X | Le registre DS, ES, FS ou GS est chargé avec un sélecteur de segment non-nulle et le segment est marqué comme non présent.
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#SS(Sélecteur) | X | X | X | Le registre SS est chargé avec un sélecteur de segment non-nulle et le segment est marqué comme non présent.
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#GP(Sélecteur) | X | X | X | Un registre de segment est chargé, mais le descripteur de segment dépasse la limite du descripteur de la table.
 | X | X | X | Un registre de segment est chargé et le bit TI de sélecteur de segment est fixé, mais le sélecteur LDT est un sélecteur nulle.
 | X | X | X | Le registre SS est chargé avec un sélecteur de segment nulle dans un mode 64-bits ou avec CPL = 3.
 | X | X | X | Le registre SS est chargé avec un sélecteur de segment RPL et le descripteur de segment DPL n'est pas égale au CPL.
 | X | X | X | Le registre SS est chargé et le pointeur de segment n'est pas dans un segment de données écrivable.
 | X | X | X | Le registre DS, ES, FS ou GS n'est pas chargé et le segment pointe sur des données ou un segment de code non-conforme, mais le RPL ou CPL est supérieur au DPL.
 | X | X | X | Le registre DS, ES, FS ou GS n'est pas chargé et le segment pointe sur des données ou un segment de code en lecture.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Références

Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 642 à 646.


Assembleur 80x86

MOV
INTEL 8088+ MOVe

Syntaxe

MOV opérandecible,opérandesource

Description

Cette instruction permet de copier opérande source dans une opérande destinataire.

Algorithme

opérandecible ← opérandesource

Mnémonique

Instruction | Opcode | Description
MOV reg/mem8, reg8 | 88h /r | Copie le contenu du registre 8 bits dans l'opérande de registre ou mémoire 8 bits.
MOV reg/mem16, reg16 | 89h /r | Copie le contenu du registre 16 bits dans l'opérande de registre ou mémoire 16 bits.
MOV reg/mem32, reg32 | 89h /r | Copie le contenu du registre 32 bits dans l'opérande de registre ou mémoire 32 bits.
MOV reg/mem64, reg64 | 89h /r | Copie le contenu du registre 64 bits dans l'opérande de registre ou mémoire 64 bits.
MOV reg8, reg/mem8 | 8Ah /r | Copie le contenu de l'opérande de registre ou mémoire 8 bits dans le registre 8 bits.
MOV reg16, reg/mem16 | 8Bh /r | Copie le contenu de l'opérande de registre ou mémoire 16 bits dans le registre 16 bits.
MOV reg32, reg/mem32 | 8Bh /r | Copie le contenu de l'opérande de registre ou mémoire 32 bits dans le registre 32 bits.
MOV reg64, reg/mem64 | 8Bh /r | Copie le contenu de l'opérande de registre ou mémoire 64 bits dans le registre 64 bits.
MOV reg16/32/64/mem16,segReg | 8Ch /r | Copie le contenu du registre de segment dans l'opérande de registre ou mémoire 16, 32 ou 64 bits.
MOV segReg, reg/mem16 | 8Eh /r | Copie le contenu de l'opérande de registre ou mémoire 16 bits dans le registre de segment.
MOV AL,[yyxxh] | A0h xxh yyh | Copie le contenu de l'opérande de l'adresse mémoire 8 bits dans le registre AL.
MOV AX, [yyxxh] | A1h xxh yyh | Copie le contenu de l'opérande de l'adresse mémoire 16 bits dans le registre AX.
MOV EAX, moffset32 | A1h dw | Copie le contenu de l'opérande de l'adresse mémoire 32 bits dans le registre EAX.
MOV RAX, moffset64 | A1h dw | Copie le contenu de l'opérande de l'adresse mémoire 64 bits dans le registre RAX.
MOV moffset8, AL | A2h dw | Copie le registre AL dans l'opérande de l'adresse mémoire 8 bits.
MOV moffset16, AX | A3h dw | Copie le registre AX dans l'opérande de l'adresse mémoire 16 bits.
MOV moffset32, EAX | A3h dw | Copie le registre EAX dans l'opérande de l'adresse mémoire 32 bits.
MOV moffset64, RAX | A3h dw | Copie le registre RAX dans l'opérande de l'adresse mémoire 64 bits.
MOV reg8, imm8 | (B0h+rb) ib | Copie une valeur immédiate de 8 bits dans un registre 8 bits.
MOV reg16, imm16 | (B8h+rw) iw | Copie une valeur immédiate de 16 bits dans un registre 16 bits.
MOV reg32, imm32 | (B8h+rd) id | Copie une valeur immédiate de 32 bits dans un registre 32 bits.
MOV reg64, imm64 | (B8h+rq) iq | Copie une valeur immédiate de 64 bits dans un registre 64 bits.
MOV reg/mem8, imm8 | C6h /0 ib | Copie une valeur immédiate 8 bits dans une opérande de registre ou mémoire 8 bits.
MOV reg/mem16, imm16 | C7h /0 iw | Copie une valeur immédiate 16 bits dans une opérande de registre ou mémoire 16 bits.
MOV reg/mem32, imm32 | C7h /0 id | Copie une valeur immédiate 32 bits dans une opérande de registre ou mémoire 32 bits.
MOV reg/mem64, imm32 | C7h /0 id | Copie une valeur immédiate 32 bits dans une opérande de registre ou mémoire 64 bits.
MOV CRn, reg32 | 0Fh 22h /r | Copie un registre 32 bits dans un registre CRn.
MOV CRn, reg64 | 0Fh 22h /r | Copie un registre 64 bits dans un registre CRn.
MOV reg32, CRn | 0Fh 20h /r | Copie un registre CRn dans un registre 32 bits.
MOV reg64, CRn | 0Fh 20h /r | Copie un registre CRn dans un registre 64 bits.
MOV CR8, reg32 | F0h 0Fh 22h/r | Copie un registre 32 bits dans le registre CR8.
MOV CR8, reg64 | F0h 0Fh 22h/r | Copie un registre 64 bits dans le registre CR8.
MOV reg32, CR8 | F0h 0Fh 20h/r | Copie un registre CR8 dans le registre 32 bits.
MOV reg64, CR8 | F0h 0Fh 20h/r | Copie un registre CR8 dans le registre 64 bits.
MOV reg32, DRn | 0Fh 21h /r | Copie un registre DRn dans le registre 32 bits.
MOV reg64, DRn | 0Fh 21h /r | Copie un registre DRn dans le registre 64 bits.
MOV DRn, reg32 | 0Fh 23h /r | Copie un registre 32 bits dans le registre DRn.
MOV DRn, reg64 | 0Fh 23h /r | Copie un registre 64 bits dans le registre DRn.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé
#DB(Déboguage) |  | X | X | Un registre de déboguage est référencé quand une détection générale du bit GD du registre DR7 est fixé.
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
 |  | X | X | Le CPL ne vaut pas 0.
 |  |  | X | La valeur 1 est écrite dans n'importe quel des 32 bits haut du registre DR6 ou DR7 en mode 64 bits.
 | X |  | X | Une tentative de fixer le CR0.PG = 1 et le CR0.PE = 0.
 | X |  | X | Une tentative de fixer le CR0.CD = 0 et le CR0.NW = 1.
 | X |  | X | Bits réservé à 1 dans le pointeur de la table de page de répertoire (utilise le mode «legacy» d'adresse physique étendue) et l'instruction modifie le registre CR0, CR3 ou CR4.
 | X |  | X | Une tentative d'écrire 1 dans n'importe quel bit réservé du registre CR0, CR3, CR4 ou CR8.
 | X |  | X | Une tentative de fixé le CR0.PG en mode long est activé (EFER.LME = 1), mais l'adresse d'extensions de page est désactivé (CR4.PAE = 0).
 |  |  | X | Une tentative d'effacer le CR4.PAE en mode «long» est activé (EFER.LMA = 1).
#GP(Sélecteur) |  |  | X | Un registre de segment est chargé, mais le descripteur de segment dépasse la limite de la table du descripteur.
 |  |  | X | Un registre de segment est chargé et le bit TI de sélecteur de segment est fixé, mais le sélecteur LDT est un sélecteur nulle.
 |  |  | X | Le registre SS est chargé avec un sélecteur de segment nulle dans un mode non 64 bits ou avec CPL = 3.
 |  |  | X | Le registre SS est chargé et le sélecteur de segment RPL et le descripteur de segment DPL n'est pas égale au CPL.
 |  |  | X | Le registre SS est chargé et le segment pointe dans un segment de données non écrivable.
 |  |  | X | Le registre DS, ES, FS ou GS est chargé et le segment pointe sur des données ou un segment de code non-conforme, mais le RPL ou CPL est supérieur au DPL.
 |  |  | X | Le registre DS, ES, FS ou GS est chargé et le segment ne pointe pas sur un segment de données ou un segment de code en lecture.
#NP(Sélecteur) |  |  | X | Le registre DS, ES, FS ou GS n'est pas chargé avec une valeur non-nulle.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#SS(Sélecteur) | X | X | X | Le registre SS est chargé avec un sélecteur non-nulle et le segment est marqué non présent.
#UD(Opcode invalide) |  |  | X | Une tentative de chargement dans le registre CS.
 |  | X | X | Le registre DR4 ou DR5 est référencé quand le bit d'extensions de déboguage (DE) du registre CR4 est fixé.
 |  |  | X | Un registre de déboguage illégale (DR8 à DR15) est référencé.
#UD(Instruction invalide) | X | X | X | Un registre de contrôle illégale est référencé (CR1, CR6 à CR7, CR8 à CR15).
 | X | X | X | L'utilisation d'un préfixe de verrou LOCK en lecture du registre CR8 n'est pas supporté, comme indiqué par le bit 4 du registre ECX de la fonction 8000_0001h de l'instruction CPUID.

Exemple

Voici quelques exemples typiques de l'utilisation de cette instruction :

  1. .MODEL small
  2. .STACK 100h
  3. .DATA
  4. Message1 DB 'MOV AX,15 = ','$'
  5. Message2 DB 'MOV BX,16 = ','$'
  6. CRLF DB 13,10,'$'
  7. .CODE
  8. PrintDigit PROC NEAR
  9. OR AX,AX
  10. JNS Positif
  11. PUSH AX
  12. MOV AH,02h
  13. MOV DL,'-'
  14. INT 21h
  15. POP AX
  16. NEG AX
  17. Positif:
  18. MOV BX,10
  19. XOR CX,CX
  20. NextDigit:
  21. XOR DX,DX
  22. DIV BX
  23. PUSH DX
  24. INC CX
  25. OR AX,AX
  26. JNZ NextDigit
  27. PrintOneDigit:
  28. POP AX
  29. ADD AL,48
  30. MOV DL,AL
  31. MOV AH,02h
  32. INT 21h
  33. LOOP PrintOneDigit
  34. RET
  35. ENDP
  37. .startup
  38. MOV AX,@data
  39. MOV DS,AX
  40. MOV AH,9
  41. MOV DX,OFFSET Message1
  42. INT 21h
  43. MOV AX,15
  44. CALL PrintDigit
  45. MOV AH,9
  46. MOV DX,OFFSET CRLF
  47. INT 21h
  49. MOV AX,@data
  50. MOV DS,AX
  51. MOV AH,9
  52. MOV DX,OFFSET Message2
  53. INT 21h
  54. MOV BX,16
  55. XCHG AX,BX
  56. CALL PrintDigit
  57. MOV AH,9
  58. MOV DX,OFFSET CRLF
  59. INT 21h
  61. MOV AX,4C00h
  62. INT 21h
  63. END

on obtiendra le résultat suivant :

MOV AX,15 = 15
MOV BX,16 = 16

Voir également

Instruction assembleur 80x86 - Instruction CLTS
Instruction assembleur 80x86 - Instruction LMSW
Instruction assembleur 80x86 - Instruction MOVD
Instruction assembleur 80x86 - Instruction MOVSX
Instruction assembleur 80x86 - Instruction MOVZX
Instruction assembleur 80x86 - Instruction MOVSXD
Instruction assembleur 80x86 - Instruction MOVS
Instruction assembleur 80x86 - Instruction SMSW

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 820
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 411
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 156.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M, Edition Intel, Mars 2010, Publication No. 253666-034US, page 713 à 724.


Assembleur 80x86

XCHG
INTEL 8088+ Exchange

Syntaxe

XCHG opérandecible1,opérandecible2

Description

Cette instruction permet d'échanger la valeur de deux opérandes.

Algorithme

temp ← opérandecible1
opérandecible1 ← opérandecible2
opérandecible2 ← temp

Mnémonique

Instruction | Opcode | Description
XCHG AX, reg16 | 90h +rw | Échange le contenu du registre AX avec le contenu d'un registre 16 bits.
XCHG reg16, AX | 90h +rw | Échange le contenu du registre 16 bits avec le contenu du registre AX.
XCHG EAX, reg32 | 90h +rd | Échange le contenu du registre EAX avec le contenu d'un registre 32 bits.
XCHG reg32, EAX | 90h +rd | Échange le contenu du registre 32 bits avec le contenu du registre EAX.
XCHG RAX, reg64 | 90h +rq | Échange le contenu du registre RAX avec le contenu d'un registre 64 bits.
XCHG reg/mem8, reg8 | 86h /r | Échange le contenu d'une opérande registre ou mémoire 8 bits avec le contenu d'un registre 8 bits.
XCHG reg8, reg/mem8 | 86h /r | Échange le contenu d'un registre 8 bits avec le contenu d'une opérande registre ou mémoire 8 bits.
XCHG reg/mem16, reg16 | 87h /r | Échange le contenu d'une opérande registre ou mémoire 16 bits avec le contenu d'un registre 16 bits.
XCHG reg16, reg/mem16 | 87h /r | Échange le contenu d'un registre 16 bits avec le contenu d'une opérande registre ou mémoire 16 bits.
XCHG reg/mem32, reg32 | 87h /r | Échange le contenu d'une opérande registre ou mémoire 32 bits avec le contenu d'un registre 32 bits.
XCHG reg32, reg/mem32 | 87h /r | Échange le contenu d'un registre 32 bits avec le contenu d'une opérande registre ou mémoire 32 bits.
XCHG reg/mem64, reg64 | 87h /r | Échange le contenu d'une opérande registre ou mémoire 64 bits avec le contenu d'un registre 64 bits.
XCHG reg64, reg/mem64 | 87h /r | Échange le contenu d'un registre 64 bits avec le contenu d'une opérande registre ou mémoire 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction BSWAP
Instruction assembleur 80x86 - Instruction XADD

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 839
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 418
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 245.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 538 à 541.


Assembleur 80x86

XLAT
INTEL 8088+ Translate By Table Lookup

Syntaxe

XLAT tablesource

Description

Cette instruction permet de remplacer le contenu du registre AL par un octet de la «tablesource».

Algorithme

AL ← DS:BX+AL

Mnémonique

Instruction | Opcode | Description
XLAT mem8 | D7h | Fixe le contenu avec le DS:[(R)BX+AL]

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 839
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 245.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 544 à 546.


Voici les instructions assembleur classés par catégorie d'utilisation de la pile :

Instruction | Description | CPU/MPU
POP | Cette instruction permet de désempiler de la pile un mot ou un double mot et la met dans une opérande. | INTEL 8086+
POPA | Cette instruction permet de désempiler de la pile respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX. | INTEL 80286+
POPAD | Cette instruction permet de désempiler de la pile respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX. | INTEL 80386+
POPF | Cette instruction permet de désempiler de la pile le registre 16 bits de drapeau contenant les indicateurs d'état. | INTEL 8086+
POPFD | Cette instruction permet de désempiler de la pile le registre 32 bits de drapeau contenant les indicateurs d'état. | INTEL 80386+
PUSH | Cette instruction permet d'empiler un mot ou un double mot dans la pile. | INTEL 8086+
PUSHA | Cette instruction permet d'empiler respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX dans la pile. | INTEL 80286+
PUSHAD | Cette instruction permet d'empiler respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX dans la pile. | INTEL 80386+
PUSHF | Cette instruction permet d'empiler respectivement le registre 16 bits de drapeau des indicateurs d'état dans la pile. | INTEL 8086+
PUSHFD | Cette instruction permet d'empiler respectivement le registre 32 bits de drapeau des indicateurs d'état dans la pile. | INTEL 80386+

Dernière mise à jour : Vendredi, le 4 mars 2016


Assembleur 80x86

POP
INTEL 8088+ Pop Value Of Stack

Syntaxe

POP opérande

Description

Cette instruction permet de désempiler de la pile un mot, un double mot ou un quadruple mot et la met dans une opérande.

Algorithme

SI taille de l'adresse de pile = 32 bits ALORS
SI taille de opérande = 32 bits ALORS
opérande ← SS:ESP
ESP ← ESP + 4
SINON
opérande ← SS:ESP
ESP ← ESP + 2
FIN SI
SINON
SI taille de l'opérande = 16 bits ALORS
opérande ← SS:SP
SP ← SP + 2
SINON
opérande ← SS:SP
SP ← SP + 4
FIN SI
FIN SI

Mnémonique

Instruction | Opcode | Description
POP reg/mem16 | 8Fh /0 | Désempile du sommet de la pile une valeur et la met dans un emplacement mémoire ou registre 16 bits.
POP reg/mem32 | 8Fh /0 | Désempile du sommet de la pile une valeur et la met dans un emplacement mémoire ou registre 32 bits. Il n'y a pas de préfix en mode 64 bits.
POP reg/mem64 | 8Fh /0 | Désempile du sommet de la pile une valeur et la met dans un emplacement mémoire ou registre 64 bits.
POP reg16 | 58h +rw | Désempile du sommet de la pile une valeur et la met dans le registre 16 bits.
POP reg32 | 58h +rd | Désempile du sommet de la pile une valeur et la met dans un registre 32 bits. Il n'y a pas de préfix en mode 64 bits.
POP reg64 | 58h +rq | Désempile du sommet de la pile une valeur et la met dans un registre 64 bits.
POP DS | 1Fh | Désempile du sommet de la pile une valeur et la met dans le registre DS. Invalide en mode 64 bits.
POP ES | 07h | Désempile du sommet de la pile une valeur et la met dans le registre ES. Invalide en mode 64 bits.
POP SS | 17h | Désempile du sommet de la pile une valeur et la met dans le registre SS. Invalide en mode 64 bits.
POP FS | 0Fh A1h | Désempile du sommet de la pile une valeur et la met dans le registre FS.
POP GS | 0Fh A9h | Désempile du sommet de la pile une valeur et la met dans le registre GS.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) |  |  | X | Les instructions «POP DS», «POP ES» ou «POP SS» sont exécutés en mode 64 bits.
#NP(Sélecteur) |  |  | X | Les registres DS, ES, FS ou GS sont chargés dans un sélecteur de segment non-nulle et le segment est marqué non présent.
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#SS(Sélecteur) | X | X | X | Le registre SS est chargé avec un sélecteur non-nulle et le segment est marqué non présent.
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | L'opérande de destination n'est pas dans un segment non écrivable
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#GP(Sélecteur) |  |  | X | Un registre de segment est chargé, mais le descripteur de segment dépasse la limite de la table du descripteur.
 |  |  | X | Un registre de segment est chargé et le bit TI de sélecteur de segment est fixé, mais le sélecteur LDT est un sélecteur nulle.
 |  |  | X | Le registre SS est chargé avec un sélecteur de segment nulle dans un mode non 64 bits ou avec CPL = 3.
 |  |  | X | Le registre SS est chargé et le sélecteur de segment RPL et le descripteur de segment DPL n'est pas égale au CPL.
 |  |  | X | Le registre SS est chargé et le segment pointe dans un segment de données non écrivable.
 |  |  | X | Le registre DS, ES, FS ou GS est chargé et le segment pointe sur des données ou un segment de code non-conforme, mais le RPL ou CPL est supérieur au DPL.
 |  |  | X | Le registre DS, ES, FS ou GS est chargé et le segment ne pointe pas sur un segment de données ou un segment de code en lecture.
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Voici un exemple en Turbo Pascal 7 montrant une utilisation de cette instruction :

  1. Program AsmPopSamples;
  3. Var _AX: Word ;
  5. BEGIN
  6. ASM
  7. MOV AX,4
  8. MOV BX,7
  9. PUSH AX
  10. PUSH BX
  11. POP AX
  12. POP BX
  13. PUSH AX
  14. MOV AX,3
  15. MOV BX,AX
  16. POP AX
  17. ADD AX,BX
  18. MOV _AX,AX
  19. END;
  20. WriteLn ('AX = ',_AX);
  21. END .

on obtiendra le résultat suivant :

AX = 10

Voir également

Instruction assembleur 80x86 - Instruction PUSH

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 825
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 412
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 222 à 228.
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 185 à 186.


Assembleur 80x86

POPA
INTEL 80286+ Pop All General Registers

Syntaxe

POPA

Description

Cette instruction permet de désempiler de la pile respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX.

Algorithme

DI ← SS:SP
SP ← SP + 2
SI ← SS:SP
SP ← SP + 2
BP ← SS:SP
SP ← SP + 2
* Ne depile jamais le SP
SP ← SP + 2
BX ← SS:SP
SP ← SP + 2
DX ← SS:SP
SP ← SP + 2
CX ← SS:SP
SP ← SP + 2
AX ← SS:SP
SP ← SP + 2

Mnémonique

Instruction | Opcode | Description
POPA | 61h | Désempile les registres DI, SI, BP, SP, BX, DX, CX et AX. Invalide en mode 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) |  |  | X | Cette instructions est exécuté en mode 64 bits.
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction PUSHA
Instruction assembleur 80x86 - Instruction PUSHAD

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 826
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 229 à 231.
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 187.


Assembleur 80x86

POPAD
INTEL 80386+ Pop All General Registers Double

Syntaxe

POPAD

Description

Cette instruction permet de désempiler de la pile respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX.

Algorithme

EDI ← SS:(E)SP
(E)SP ← (E)SP + 2
ESI ← SS:(E)SP
(E)SP ← (E)SP + 2
EBP ← SS:(E)SP
(E)SP ← (E)SP + 2
* Ne depile jamais le ESP
(E)SP ← (E)SP + 2
EBX ← SS:(E)SP
(E)SP ← (E)SP + 2
EDX ← SS:(E)SP
(E)SP ← (E)SP + 2
ECX ← SS:(E)SP
(E)SP ← (E)SP + 2
EAX ← SS:(E)SP
(E)SP ← (E)SP + 2

Mnémonique

Instruction | Opcode | Description
POPAD | 61h | Désempile les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX. Invalide en mode 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) |  |  | X | Cette instructions est exécuté en mode 64 bits.
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction PUSHA
Instruction assembleur 80x86 - Instruction PUSHAD

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 826
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 229 à 231.
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 187.


Assembleur 80x86

PUSH
INTEL 8088+ Push Value Onto Stack

Syntaxe

PUSH opérande

Description

Cette instruction permet d'empiler un mot, un double mot ou quadruple mot dans la pile.

Algorithme

SI taille de l'adresse = 32 bits ALORS
SI taille de l'opérande = 32 bits ALORS
ESP ← ESP - 4
SS:ESP ← opérande
SINON
ESP ← ESP - 2
SS:ESP ← opérande
FIN SI
SINON
SI taille de l'opérande = 16 bits ALORS
SP ← SP - 2
SS:SP ← opérande
SINON
SP ← SP - 4
SS:SP ← opérande
FIN SI
FIN SI

Mnémonique

Instruction | Opcode | Description
PUSH reg/mem16 | FFh /6 | Empile le contenu d'une opérande registre ou mémoire 16 bits dans la pile.
PUSH reg/mem32 | FFh /6 | Empile le contenu d'une opérande registre ou mémoire 32 bits dans la pile. Il n'y a pas de préfixe en mode 64 bits.
PUSH reg/mem64 | FFh /6 | Empile le contenu d'une opérande registre ou mémoire 64 bits dans la pile.
PUSH reg16 | 50h +rw | Empile le contenu d'un registre 16 bits dans la pile.
PUSH reg32 | 50h +rd | Empile le contenu d'un registre 32 bits dans la pile. Il n'y a pas de préfixe en mode 64 bits.
PUSH reg64 | 50h +rq | Empile le contenu d'un registre 64 bits dans la pile.
PUSH imm8 | 6Ah ib | Empile le contenu d'une valeur immédiate 8 bits dans la pile.
PUSH imm16 | 68h iw | Empile le contenu d'une valeur immédiate 16 bits dans la pile.
PUSH imm32 | 68h id | Empile le contenu d'une valeur immédiate 32 bits dans la pile. Il n'y a pas de préfixe en mode 64 bits.
PUSH imm64 | 68h id | Empile le contenu d'une valeur immédiate 32 bits dans la pile. Il n'y a pas de préfixe en mode 64 bits.
PUSH CS | 0Eh | Empile le contenu du registre CS dans la pile. Invalide en mode 64 bits.
PUSH DS | 1Eh | Empile le contenu du registre DS dans la pile. Invalide en mode 64 bits.
PUSH ES | 06h | Empile le contenu du registre ES dans la pile. Invalide en mode 64 bits.
PUSH FS | 0Fh A0h | Empile le contenu du registre FS dans la pile.
PUSH GS | 0Fh A8h | Empile le contenu du registre GS dans la pile.
PUSH SS | 16h | Empile le contenu du registre SS dans la pile. Invalide en mode 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) |  |  | X | Les instructions «PUSH CS», «PUSH DS», «PUSH ES» ou «PUSH SS» sont exécutés en mode 64 bits.
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#GP(Protection général) | X | X | X | Une adresse mémoire dépasse la limite du segment de données ou n'est pas canonique
 |  |  | X | Un segment de données nulle est utilisé comme référence mémoire
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Exemple

Voici un exemple en Turbo Pascal 7 montrant une utilisation de cette instruction :

  1. Program AsmPushSamples;
  3. Var _AX: Word ;
  5. BEGIN
  6. ASM
  7. MOV AX,4
  8. MOV BX,7
  9. PUSH AX
  10. MOV AX,3
  11. MOV BX,AX
  12. POP AX
  13. ADD AX,BX
  14. MOV _AX,AX
  15. END;
  16. WriteLn ('AX = ',_AX);
  17. END .

on obtiendra le résultat suivant :

AX = 7

Voir également

Instruction assembleur 80x86 - Instruction POP

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 826
Assembleur Facile, Philippe Mercier, 1990, ISBN: 2-501-01176-7, page 413
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 197.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 321 à 325.


Assembleur 80x86

PUSHA
INTEL 80286+ Push All General Registers

Syntaxe

PUSHA

Description

Cette instruction permet d'empiler respectivement les registres DI, SI, BP, SP, BX, DX, CX et AX dans la pile.

Algorithme

temp ← ESP
(E)SP ← (E)SP - 2
SS:(E)SP ← AX
(E)SP ← (E)SP - 2
SS:(E)SP ← CX
(E)SP ← (E)SP - 2
SS:(E)SP ← DX
(E)SP ← (E)SP - 2
SS:(E)SP ← BX
(E)SP ← (E)SP - 2
SS:(E)SP ← temp
(E)SP ← (E)SP - 2
SS:(E)SP ← BP
(E)SP ← (E)SP - 2
SS:(E)SP ← SI
(E)SP ← (E)SP - 2
SS:(E)SP ← DI

Mnémonique

Instruction | Opcode | Description
PUSHA | 60h | Empile le contenu des registres AX, CX, DX, BX, SP avant l'appel de cette instruction, BP, SI et DI dans la pile. Invalide en mode 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) |  |  | X | Cette instruction est exécuté en mode 64 bits.
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction POPA
Instruction assembleur 80x86 - Instruction POPAD

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 827
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 199.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 326 à 327.


Assembleur 80x86

PUSHAD
INTEL 80386+ Push All General Registers Double

Syntaxe

PUSHAD

Description

Cette instruction permet d'empiler respectivement les registres EDI, ESI, EBP, ESP, EBX, EDX, ECX et EAX dans la pile.

Algorithme

temp ← ESP
(E)SP ← (E)SP - 2
SS:(E)SP ← EAX
(E)SP ← (E)SP - 2
SS:(E)SP ← ECX
(E)SP ← (E)SP - 2
SS:(E)SP ← EDX
(E)SP ← (E)SP - 2
SS:(E)SP ← EBX
(E)SP ← (E)SP - 2
SS:(E)SP ← temp
(E)SP ← (E)SP - 2
SS:(E)SP ← EBP
(E)SP ← (E)SP - 2
SS:(E)SP ← ESI
(E)SP ← (E)SP - 2
SS:(E)SP ← EDI

Mnémonique

Instruction | Opcode | Description
PUSHAD | 60h | Empile le contenu des registres EAX, ECX, EDX, EBX, ESP avant l'appel de cette instruction, EBP, ESI et EDI dans la pile. Invalide en mode 64 bits.

Exceptions

Message | Mode réel | Virtuel 8086 | Mode protégé | Description
#UD(Opcode invalide) |  |  | X | Cette instruction est exécuté en mode 64 bits.
#SS(Pile) | X | X | X | Une adresse mémoire dépasse la limite du segment de pile ou n'est pas canonique
#PF(Faute de page) |  | X | X | Une faute de page résultat de l'exécution de l'instruction
#AC(Vérifie l'alignement) |  | X | X | Un désalignement de la référence mémoire est effectué quand une vérification d'alignement est activé

Voir également

Instruction assembleur 80x86 - Instruction POPA
Instruction assembleur 80x86 - Instruction POPAD

Références

Le livre d'Or PC, Martin Althaus, 1992, ISBN: 2-7361-0934-1, page 827
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Edition Advanced Micro Devices, Revision 3.14, September 2007, Publication No. 24594, page 199.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z, Edition Intel, Mars 2010, Publication No. 253667-034US, page 326 à 327.


INC - Increment by 1 FE /0 INC r

INC - Increment by 1
FE /0 INC r/m8 Increment r/m byte by 1
FF /0 INC r/m16 Increment r/m word by 1
FF /0 INC r/m32 Increment r/m doubleword by 1
40+ rw INC r16 Increment word register by 1
40+ rd INC r32 Increment doubleword register by 1

Description
Adds 1 to the destination operand, while preserving the state of the CF flag. The destination operand can be a register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag. (Use a ADD instruction with an immediate operand of 1 to perform an increment operation that does updates the CF flag.)

Operands Bytes Clocks
r8 2 1 UV
r16 1 1 UV
r32 1 1 UV
mem 2+d(0,2) 3 UV

Flags
The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.


PUSHF/PUSHFD - Push EFLAGS Regis

PUSHF/PUSHFD - Push EFLAGS Register onto the Stack
9C PUSHF Push lower 16 bits of EFLAGS
9C PUSHFD Push EFLAGS

Description
Decrements the stack pointer by 4 (if the current operand-size attribute is 32) and pushes the entire contents of the EFLAGS register onto the stack, or decrements the stack pointer by 2 (if the operand-size attribute is 16) and pushes the lower 16 bits of the EFLAGS register (that is, the FLAGS register) onto the stack. (These instructions reverse the operation of the POPF/POPFD instructions.) When copying the entire EFLAGS register to the stack, the VM and RF flags (bits 16 and 17) are not copied; instead, the values for these flags are cleared in the EFLAGS image stored on the stack. See the section titled "EFLAGS Register" in Chapter 3 of the Intel Architecture Software Developer's Manual, Volume 1, for information about the EFLAGS registers.

The PUSHF (push flags) and PUSHFD (push flags double) mnemonics reference the same opcode. The PUSHF instruction is intended for use when the operand-size attribute is 16 and the PUSHFD instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when PUSHF is used and to 32 when PUSHFD is used. Others may treat these mnemonics as synonyms (PUSHF/PUSHFD) and use the current setting of the operand-size attribute to determine the size of values to be pushed from the stack, regardless of the mnemonic used.

When in virtual-8086 mode and the I/O privilege level (IOPL) is less than 3, the PUSHF/PUSHFD instruction causes a general protection exception (#GP).

In the real-address mode, if the ESP or SP register is 1, 3, or 5 when the PUSHA/PUSHAD instruction is executed, the processor shuts down due to a lack of stack space. No exception is generated to indicate this condition.

Variations Bytes Clocks
pushf 1 9 NP
pushfd 1 9 NP

Protected Mode
pushf 1 3 NP
pushfd 1 3 NP

Flags
None.


ROR - Rotate Bits Right Usage

ROR - Rotate Bits Right

Usage: ROR dest, count

Description
See RCLCW50O

Operands Bytes Clocks
reg, 1 2 1 PU
mem, 1 2+d(0,2) 3 PU
reg, cl 2 4 NP
mem, cl 2+d(0,2) 4 NP
reg, imm 3 1 PU
mem, imm 3+d(0,2) 3 PU*

* = not pairable if there is a displacement and immediate

RDMSR - Read from Model Specific Register
0F 32 RDMSR Load MSR specified by ECX into EDX:EAX

Description
Loads the contents of a 64-bit model specific register (MSR) specified in the ECX register into registers EDX:EAX. The EDX register is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. If less than 64 bits are implemented in the MSR being read, the values returned to EDX:EAX in unimplemented bit locations are undefined.

This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) will be generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a general protection exception.

The MSRs control functions for testability, execution tracing, performance-monitoring and machine check errors. Appendix B, Model-Specific Registers (MSRs), in the Intel Architecture Software Developer's Manual, Volume 3, lists all the MSRs that can be read with this instruction and their addresses.

The CPUID instruction should be used to determine whether MSRs are supported (EDX[5]=1) before using this instruction.

Operands Bytes Clocks
2 20-24 NP

Flags
None.


FADD, FADDP: Floating-Point Addition

fadd  mem32
fadd  mem64
fadd  fpureg
fadd  fpureg,st0
fadd  st0,fpureg
faddp fpureg
faddo st0,fpureg

FADD, given one operand, adds the operand to ST0 and stores the result back in ST0. If the operand has the TO modifier, the result is stored in the register given rather than in ST0.

FADDP performs the same function as FADD TO, but pops the register stack after storing the result.

The given two-operand forms are synonyms for the one-operand forms.


A.69. FUCOMxx: Floating-Point Unordered Compare

FUCOM fpureg ; DD E0+r [386,FPU]

FUCOM ST0,fpureg ; DD E0+r [386,FPU]

FUCOMP fpureg ; DD E8+r [386,FPU]

FUCOMP ST0,fpureg ; DD E8+r [386,FPU]

FUCOMPP ; DA E9 [386,FPU]

FUCOMI fpureg ; DB E8+r [P6,FPU]

FUCOMI ST0,fpureg ; DB E8+r [P6,FPU]

FUCOMIP fpureg ; DF E8+r [P6,FPU]

FUCOMIP ST0,fpureg ; DF E8+r [P6,FPU]

FUCOM compares ST0 with the given operand, and sets the FPU flags accordingly. ST0 is treated as the left-hand side of the comparison, so that the carry flag is set (for a `less-than' result) if ST0 is less than the given operand.

FUCOMP does the same as FUCOM, but pops the register stack afterwards. FUCOMPP compares ST0 with ST1 and then pops the register stack twice.

FUCOMI and FUCOMIP work like the corresponding forms of FUCOM and FUCOMP, but write their results directly to the CPU flags register rather than the FPU status word, so they can be immediately followed by conditional jump or conditional move instructions.

The FUCOM instructions differ from the FCOM instructions (section A.35) only in the way they handle quiet NaNs: FUCOM will handle them silently and set the condition code flags to an `unordered' result, whereas FCOM will generate an exception.


MOVD: Move 32 Bits

movd r/mm32,mmxreg
movd mmxreg,r/mm32

The MOVD instruction moves 32 bits from a memory or 32 bit register into an MMX register or moves from an MMX register to a 32 bit register or memory.


PADDSIW: MMX Packed Addition to Implicit Destination

paddsiw r/m64,mmxreg

PADDSIW, specific to the Cyrix extensions to the MMX instruction set, performs the same function as PADDSW, except that the result is not placed in the register specified by the first operand, but instead in the register whose number differs from the first operand only in the last bit.

So PADDSIW MM2,MM0 would put the result in MM1, but PADDSIW MM2,MM1 would put the result in MM0.


Key to Instruction Flags

Given along with each instruction in this appendix is a set of flags, denoting the type of the instruction. The types are as follows:

8086, 186, 286, 386, 486, PENT and P6 denote the lowest processor type that supports the instruction. Most instructions run on all processors above the given type; those that do not are documented. The Pentium II contains no additional instructions beyond the P6 (Pentium Pro); from the point of view of its instruction set, it can be thought of as a P6 with MMX capability.

CYRIX indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set.

FPU indicates that the instruction is a floating-point one, and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above).

MMX indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II.

PRIV indicates that the instruction is a protected-mode management instruction. Many of these may only be used in protected mode, or only at privilege level zero.

UNDOC indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine.


Key to Opcode Descriptions

This section provides the key to various short forms where opcodes are defined throughout this help file.

All opcodes and mnemonics should be in lower case e.g. movl %ecx,%eax but for clarity these are sometimes displayed in upper case, e.g MOVL %ECX,%EAX.

Generally mnemonics will have registers and or memory specifies attached

e.g. add reg16,r/m16

This means that the instruction can operate from a 16 bit register (reg16) and either another 16 bit register (r/) or a 16 bit memory location (m16).

Another example is

and imm16,r/m16

The instruction use a 16 bit immediate value (imm16) and either a 16 bit register or a 16 bit memory location.

Other examples;

reg8r/m8     8 bit reg, 8 bit memory location
reg16,r/m16  16 bit reg, 16 bit reg /16 bit memory location
reg32,r/m32  32 bit reg, 32 bit reg / 32 bit memory location
r/m8,reg8    8 bit reg / 8 bit memory location, 8 bit reg
imm32,r/m32  32 bit immediate value, 32 bit reg / 0r memory location
imm16,ax     16 bit immediate value, 16 bit reg


Key to Operand Specifications

Key to Operands

The instruction descriptions in this document specify their operands using the following notation:

Registers: reg8 denotes an 8-bit general purpose register

reg16 denotes a 16-bit general purpose register

reg32 denotes a 32-bit general purpose register.

fpureg denotes one of the eight FPU stack registers

mmxreg denotes one of the eight 64-bit MMX registers

segreg denotes a segment register

In addition, some registers for example, al, dx, ecx may be specified explicitly.

Immediate operands: imm denotes a generic immediate operand. imm8, imm16 and imm32 are used when the operand is intended to be a specific size. For some of these instructions, one needs to explicitly add a specified: for example, addl for a long, addw for a word and addb for a byte.

Memory references: mem denotes a generic memory reference; mem8, mem16, mem32, mem64 and mem80 are used when the operand needs to be a specific size.

Restricted memory references: one form of the mov instruction allows a memory address to be specified without allowing the normal range of register combinations and effective address processing. This is denoted by memoffs8, memoffs16 and memoffs32.

Register or memory choices: many instructions can accept either a register or a memory reference as an operand. r/m8 is a shorthand for reg8/mem8; similarly r/m16 and r/m32.

r/m64 is MMX-related, and is a shorthand for mmxreg/mem64.